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path: root/drivers/usb/dwc2/core.h
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* Revert "usb: dwc2: gadget: fix TX FIFO size and address initialization"John Youn2016-10-18
| | | | | | | | | | | | | | | | | | | This reverts commit aa381a7259c3 ("usb: dwc2: gadget: fix TX FIFO size and address initialization"). The original commit removed the FIFO size programming per endpoint. The DPTXFSIZn register is also used for DIEPTXFn and the SIZE field is r/w in dedicated fifo mode. So it isn't appropriate to simply remove this initialization as it might break existing behavior. Also, some cores might not have enough fifo space to handle the programming method used in the reverted patch, resulting in fifo initialization failure. Signed-off-by: John Youn <johnyoun@synopsys.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* Merge tag 'usb-for-v4.9' of ↵Greg Kroah-Hartman2016-09-14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next Felipe writes: usb: patches for v4.9 merge window This time around we have 92 non-merge commits. Most of the changes are in drivers/usb/gadget (40.3%) with drivers/usb/gadget/function being the most active directory (27.2%). As for UDC drivers, only dwc3 (26.5%) and dwc2 (12.7%) have really been active. The most important changes for dwc3 are better support for scatterlist and, again, throughput improvements. While on dwc2 got some minor stability fixes related to soft reset and FIFO usage. Felipe Tonello has done some good work fixing up our f_midi gadget and Tal Shorer has implemented a nice API change for our ULPI bus. Apart from these, we have our usual set of non-critical fixes, spelling fixes, build warning fixes, etc.
| * usb: dwc2: Add delay to core soft resetJohn Youn2016-09-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a delay to the core soft reset function to account for the IDDIG debounce filter. If the current mode is host, either due to the force mode bit being set (which persists after core reset) or the connector id pin, a core soft reset will temporarily reset the mode to device and a delay from the IDDIG debounce filter will occur before going back to host mode. Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc2: gadget: fix TX FIFO size and address initializationRobert Baldyga2016-08-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to DWC2 documentation, DPTxFSize field of DPTXFSIZn register is read only, which means that software cannot change FIFO size. Register description says: "The value of this register is the Largest Device Mode Periodic Tx Data FIFO Depth (parameter OTG_TX_DPERIO_DFIFO_DEPTH_n), as specified during coreConsultant configuration." That means, that we have to setup only FIFO start addresses (DPTxFStAddr), taking into account reset values of DPTxFSize. Initialize FIFO start addresses properly and remove unneeded core related to incorrect FIFO size initialization. Signed-off-by: Robert Baldyga <r.baldyga@samsung.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* | usb: dwc2: Add reset control to dwc2Dinh Nguyen2016-08-22
|/ | | | | | | | | | Allow for platforms that have a reset controller driver in place to bring the USB IP out of reset. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: John Youn <johnyoun@synopsys.com> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: gadget: Final fixes for BDMA ISOCVardan Mikayelyan2016-06-21
| | | | | | | | | | | | | | | | | | | | | | | Done fixes and tested hsotg gadget's BDMA mode. Tested Control, Bulk, Isoc, Inter transfers. Added code for isoc transfers, removed unusable code, done minor fixes. Affected functions and IRQ handlers: - dwc2_hsotg_start_req(), - dwc2_hsotg_ep_enable(), - dwc2_hsotg_ep_queue(), - dwc2_hsotg_handle_outdone(), - GINTSTS_GOUTNAKEFF handler, Removed 'has_correct_parity' flag from 'dwc2_hsotg_ep' struct. Before this patch series, to set the data pid the DWC2 gadget driver was toggling the even/odd until it match, then were leaving it set. But now I have added mechanism to set pid and excluded all code where this flag was set. Tested-by: John Keeping <john@metanate.com> Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: gadget: Corrected interval calculationVardan Mikayelyan2016-06-21
| | | | | | | | | | Calculate the interval according to the USB 2.0 specification section 9.6.6. Tested-by: John Keeping <john@metanate.com> Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: gadget: Add dwc2_gadget_incr_frame_num()Vardan Mikayelyan2016-06-21
| | | | | | | | | | | | | | Increases and checks targeted frame number of current ep if overrun happened, sets flag and masks with DSTS_SOFFN_LIMIT Added following fields to struct dwc2_hsotg_ep -target_frame: Targeted frame num to setup next ISOC transfer -frame_overrun: Indicates SOF number overrun in DSTS Tested-by: John Keeping <john@metanate.com> Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: fix regression on big-endian PowerPC/ARM systemsArnd Bergmann2016-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A patch that went into Linux-4.4 to fix big-endian mode on a Lantiq MIPS system unfortunately broke big-endian operation on PowerPC APM82181 as reported by Christian Lamparter, and likely other systems. It actually introduced multiple issues: - it broke big-endian ARM kernels: any machine that was working correctly with a little-endian kernel is no longer using byteswaps on big-endian kernels, which clearly breaks them. - On PowerPC the same thing must be true: if it was working before, using big-endian kernels is now broken. Unlike ARM, 32-bit PowerPC usually uses big-endian kernels, so they are likely all broken. - The barrier for dwc2_writel is on the wrong side of the __raw_writel(), so the MMIO no longer synchronizes with DMA operations. - On architectures that require specific CPU instructions for MMIO access, using the __raw_ variant may turn this into a pointer dereference that does not have the same effect as the readl/writel. This patch is a simple revert for all architectures other than MIPS, in the hope that we can more easily backport it to fix the regression on PowerPC and ARM systems without breaking the Lantiq system again. We should follow this up with a more elaborate change to add runtime detection of endianness, to make sure it also works on all other combinations of architectures and implementations of the usb-dwc2 device. That patch however will be fairly large and not appropriate for backports to stable kernels. Felipe suggested a different approach, using an endianness switching register to always put the device into LE mode, but unfortunately the dwc2 hardware does not provide a generic way to do that. Also, I see no practical way of addressing the problem more generally by patching architecture specific code on MIPS. Fixes: 95c8bc360944 ("usb: dwc2: Use platform endianness when accessing registers") Acked-by: John Youn <johnyoun@synopsys.com> Tested-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Move host-specific core functions into hcd.cJohn Youn2016-03-04
| | | | | | | | | | | Move host core initialization and host channel routines into hcd.c. This allows these functions to only be compiled in host-enabled driver configurations (DRD or host-only). Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: Move register save and restore functionsJohn Youn2016-03-04
| | | | | | | | | | Move the register save and restore functions into the host and gadget specific files. Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: host: Totally redo the microframe schedulerDouglas Anderson2016-03-04
| | | | | | | | | | | | | | | | | | | | | | This totally reimplements the microframe scheduler in dwc2 to attempt to handle periodic splits properly. The old code didn't even try, so this was a significant effort since periodic splits are one of the most complicated things in USB. I've attempted to keep the old "don't use the microframe" schduler around for now, but not sure it's needed. It has also only been lightly tested. I think it's pretty certain that this scheduler isn't perfect and might have some bugs, but it seems much better than what was there before. With this change my stressful USB test (USB webcam + USB audio + some keyboards) crackles less. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: host: Add dwc2_hcd_get_future_frame_number() callDouglas Anderson2016-03-04
| | | | | | | | | | | | | | | | | | | | | As we start getting more exact about our scheduling it's becoming more and more important to know exactly how far through the current frame we are. This lets us make decisions about whether there's still time left to start a new transaction in the current frame. We'll add dwc2_hcd_get_future_frame_number() which will tell you what the frame number will be a certain number of microseconds (us) from now. We can use this information to help decide if there's enough time left in the frame for a transaction that will take a certain duration. This is expected to be used by a future change ("usb: dwc2: host: Properly set even/odd frame"). Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: host: Add scheduler logging for missed SOFsDouglas Anderson2016-03-04
| | | | | | | | | | | | | | We'll use the new "scheduler verbose debugging" macro to log missed SOFs. This is fast enough (assuming you configure it to use the ftrace buffer) that we can do it without worrying about the speed hit. The overhead hit if the scheduler tracing is set to "no_printk" should be near zero. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: host: Add scheduler tracingDouglas Anderson2016-03-04
| | | | | | | | | | | | | | | | In preparation for future changes to the scheduler let's add some tracing that makes it easy for us to see what's happening. By default this tracing will be off. By changing "core.h" you can easily trace to ftrace, the console, or nowhere. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: host: fix split transfer schedule sequenceDouglas Anderson2016-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We're supposed to keep outstanding splits in order. Keep track of a list of the order of splits and process channel interrupts in that order. Without this change and the following setup: * Rockchip rk3288 Chromebook, using port ff540000 -> Pluggable 7-port Hub with Charging (powered) -> Microsoft Wireless Keyboard 2000 in port 1. -> Das Keyboard in port 2. ...I find that I get dropped keys on the Microsoft keyboard (I'm sure there are other combinations that fail, but this documents my test). Specifically I've been typing "hahahahahahaha" on the keyboard and often see keys dropped or repeated. After this change the above setup works properly. This patch is based on a previous patch proposed by Yunzhi Li ("usb: dwc2: hcd: fix periodic transfer schedule sequence") Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: Improve handling of host and device hwparamsJohn Youn2015-12-22
| | | | | | | | | | | Adds separate functions to get the host and device specific hardware parameters. The functions check whether the parameters need to be read at all, depending on dr_mode, and forces the mode only if necessary. This saves some delays during probe. This also adds two device mode parameters that will be used by the gadget. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: Add functions to set and clear force modeJohn Youn2015-12-22
| | | | | | | | | | | | | | Added functions to set force mode for host and device. These functions will check the current mode and only force if needed thus avoiding unnecessary force mode delays. However clearing the mode is currently done unconditionally and with the delay in place. This is needed during the connector ID status change interrupt in order to ensure that the mode has changed properly. This preserves the old behavior only for this case. The warning comment about this is moved into the clear mode condition. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: Move mode querying functions into core.hJohn Youn2015-12-22
| | | | | | | | | | These functions should go in core.h where they can be called from core, device, or host. Signed-off-by: John Youn <johnyoun@synopsys.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: Add functions to check the HW OTG configJohn Youn2015-12-22
| | | | | | | | | | Added functions to query the GHWCFG2.OTG_MODE. This tells us whether the controller hardware is configured for OTG, device-only, or host-only. Signed-off-by: John Youn <johnyoun@synopsys.com> Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: Add dwc2_core_reset()John Youn2015-12-22
| | | | | | | | | dwc2_core_reset() was previously renamed to dwc2_core_reset_and_dr_force_mode(). Now add back dwc2_core_reset() which performs only a basic core reset without forcing the mode. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: Rename dwc2_core_reset()John Youn2015-12-22
| | | | | | | | | | Renamed dwc2_core_reset() to dwc2_core_reset_and_force_dr_mode(). This describes what it is doing more accurately. This is in preparation of introducing a plain dwc2_core_reset() function that only performs the reset and doesn't force the mode. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: Avoid double-reset at boot timeDouglas Anderson2015-12-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In (usb: dwc2: reset dwc2 core before dwc2_get_hwparams()) we added an extra reset to the probe path for the dwc2 USB controllers. This allowed proper detection of parameters even if the firmware had already used the USB part. Unfortunately, this extra reset is quite slow and is affecting boot speed. We can avoid the double-reset by skipping the extra reset that would happen just after the one we added. Logic that explains why this is safe: * As of the CL mentioned above, we now always call dwc2_core_reset() in dwc2_driver_probe() before dwc2_hcd_init(). * The only caller of dwc2_hcd_init() is dwc2_driver_probe(), so we're guaranteed that dwc2_core_reset() was called before dwc2_hdc_init(). * dwc2_hdc_init() is the only caller that passes an irq other than -1 to dwc2_core_init(). Thus if dwc2_core_init() is called with an irq other than -1 we're guaranteed that dwc2_core_reset was called before dwc2_core_init(). ...this allows us to remove the dwc2_core_reset() in dwc2_core_init() if irq is not < 0. Note that since "irq" wasn't used in the function dwc2_core_init() anyway and since select_phy was always set at exactly the same times we could avoid the reset, we remove "irq" and rename "select_phy" to "initial_setup" and adjust the callers accordingly. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: reset dwc2 core before dwc2_get_hwparams()Yunzhi Li2015-12-22
| | | | | | | | | | | | | | | | | We initiate dwc2 usb controller in BIOS, dwc2_core_reset() should be called before dwc2_get_hwparams() to reset core registers to default value. Without this the FIFO setting might be incorrect because calculating FIFO size need power-on value of GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers. This patch could avoid warnning massage like in rk3288 platform: [ 2.074764] dwc2 ff580000.usb: 256 invalid for host_perio_tx_fifo_size. Check HW configuration. Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: host: Fix missing device insertionsDouglas Anderson2015-12-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If you've got your interrupt signals bouncing a bit as you insert your USB device, you might end up in a state when the device is connected but the driver doesn't know it. Specifically, the observed order is: 1. hardware sees connect 2. hardware sees disconnect 3. hardware sees connect 4. dwc2_port_intr() - clears connect interrupt 5. dwc2_handle_common_intr() - calls dwc2_hcd_disconnect() Now you'll be stuck with the cable plugged in and no further interrupts coming in but the driver will think we're disconnected. We'll fix this by checking for the missing connect interrupt and re-connecting after the disconnect is posted. We don't skip the disconnect because if there is a transitory disconnect we really want to de-enumerate and re-enumerate. Notes: 1. As part of this change we add a "force" parameter to dwc2_hcd_disconnect() so that when we're unloading the module we avoid the new behavior. The need for this was pointed out by John Youn. 2. The bit of code needed at the end of dwc2_hcd_disconnect() is exactly the same bit of code from dwc2_port_intr(). To avoid duplication, we refactor that code out into a new function dwc2_hcd_connect(). Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: John Youn <johnyoun@synopsys.com> Tested-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: host: use kmem cache to allocate descriptorsGregory Herrero2015-12-15
| | | | | | | | | | | Kmem caches help to get correct boundary for descriptor buffers which need to be 512 bytes aligned for dwc2 controller. Two kmem caches are needed for generic descriptors and for hs isochronous descriptors which doesn't have same size. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: host: avoid usage of dma_alloc_coherent with irqs disabledGregory Herrero2015-12-15
| | | | | | | | | | Use Streaming DMA mappings to handle cache coherency of frame list and descriptor list. Cache are always flushed before controller access it or before cpu access it. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: host: enable descriptor dma for fs devicesMian Yousaf Kaukab2015-12-15
| | | | | | | | | | | | | | As descriptor dma mode does not support split transfers, it can't be enabled for high speed devices. Add a core parameter to enable it for full speed devices. Ensure frame list and descriptor list are correctly freed during disconnect. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: refactor common low-level hw code to platform.cMarek Szyprowski2015-10-14
| | | | | | | | | | | | | | | | | | DWC2 module on some platforms needs three additional hardware resources: phy controller, clock and power supply. All of them must be enabled/activated to properly initialize and operate. This was initially handled in s3c-hsotg driver, which has been converted to 'gadget' part of dwc2 driver. Unfortunately, not all of this code got moved to common platform code, what resulted in accessing DWC2 registers without enabling low-level hardware resources. This fails for example on Exynos SoCs. This patch moves all the code for managing those resources to common platform.c file and provides convenient wrappers for controlling them. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: John Youn <johnyoun@synopsys.com> Tested-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: remove no longer needed init_mutexMarek Szyprowski2015-10-14
| | | | | | | | | | | | | | init_mutex is a leftover from the time, when s3c-hsotg driver did not implement proper pull up/down control and emulated it by enabling enabling/disabling usb phy. Proper pull up/down control has been added by commit 5b9451f8c4fbaf0549139755fb45ff2b57975b7f ("usb: dwc2: gadget: use soft-disconnect udc feature in pullup() method"), so init_muxtex can be removed now to avoid potential deadlocks with other locks. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: John Youn <johnyoun@synopsys.com> Tested-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: gadget: parity fix in isochronous modeRoman Bacik2015-10-02
| | | | | | | | | | | | | | | | USB OTG driver in isochronous mode has to set the parity of the receiving microframe. The parity is set to even by default. This causes problems for an audio gadget, if the host starts transmitting on odd microframes. This fix uses Incomplete Periodic Transfer interrupt to toggle between even and odd parity until the Transfer Complete interrupt is received. Signed-off-by: Roman Bacik <rbacik@broadcom.com> Reviewed-by: Abhinav Ratna <aratna@broadcom.com> Reviewed-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: gadget: only reset core after addressed stateMian Yousaf Kaukab2015-10-01
| | | | | | | | | | | | | | There is a 200ms guard period to avoid unnecessary resets of the dwc2 ip. This delay sometimes prove to be too large when usbcv is run with an ehci host. dwc2 only needs to be reset after addressed state. Change the logic to reset ip after addressed state. Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Tested-by: Robert Baldyga <r.baldyga@samsung.com> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com> Tested-by: John Youn <johnyoun@synopsys.com> Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: host: add flag to reflect bus stateGregory Herrero2015-10-01
| | | | | | | | | | | | | lx_state must be used to reflect controller power state only and not bus state. Thus add a flag to track state during bus suspend. Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Tested-by: Robert Baldyga <r.baldyga@samsung.com> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com> Tested-by: John Youn <johnyoun@synopsys.com> Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: Use platform endianness when accessing registersAntti Seppälä2015-09-27
| | | | | | | | | | | | | | | | | | | | | | | This patch switches calls to readl/writel to their dwc2_readl/dwc2_writel equivalents which preserve platform endianness. This patch is necessary to access dwc2 registers correctly on big-endian systems such as the mips based SoCs made by Lantiq. Then dwc2 can be used to replace ifx-hcd driver for Lantiq platforms found e.g. in OpenWrt. The patch was autogenerated with the following commands: $EDITOR core.h sed -i "s/\<readl\>/dwc2_readl/g" *.c hcd.h hw.h sed -i "s/\<writel\>/dwc2_writel/g" *.c hcd.h hw.h Some files were then hand-edited to fix checkpatch.pl warnings about too long lines. Signed-off-by: Antti Seppälä <a.seppala@gmail.com> Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: rename all s3c_* to dwc2_*Felipe Balbi2015-09-27
| | | | | | | | | | this driver has long ago became dwc2.ko with both peripheral and host roles, there's no point in keeping the old function names. Acked-by: John Youn <johnyoun@synopsys.com> Tested-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: embed storage for reg backup in struct dwc2_hsotgMian Yousaf Kaukab2015-07-06
| | | | | | | | | | | | | | | Register backup function can be called from atomic context. Instead of using atomic memory pool, embed backup storage space in struct dwc2_hsotg. Also add a valid flag in each struct as NULL pointer can't be used as the content validity check any more. Acked-by: John Youn <johnyoun@synopsys.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: add hibernation core parameterGregory Herrero2015-04-29
| | | | | | | | | | dwc2 may not be able to exit from hibernation if the hardware does not provide a way to detect resume signalling in this state. Thus, add the possibility to disable hibernation feature. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: set parameter values in probe functionMian Yousaf Kaukab2015-04-29
| | | | | | | | | So the parameters can be used in both host and gadget modes. Also consolidate param functions in the core.h Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: add external_id_pin_ctl core parameterGregory Herrero2015-04-29
| | | | | | | | | | | | | | This is required due to an Intel specific hardware issue. Where id- pin setup causes glitches on the interrupt line when CONIDSTSCHG interrupt is enabled. Specify external_id_pin_ctl when an external driver (for example phy) can handle id change, so that CONIDSTSCHG interrupt can be disabled from the controller. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: implement hibernation during bus suspend/resumeGregory Herrero2015-04-29
| | | | | | | | | | | | | Allow controller to enter in hibernation during usb bus suspend and inform both phy and gadget about the suspended state. While in hibernation, the controller can't detect the resume condition. An external mechanism must call usb_phy_set_suspend on resume. Exit hibernation when controller gets the resume interrupt and inform only gadget driver about it. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: add controller hibernation supportGregory Herrero2015-04-29
| | | | | | | | | | When suspending usb bus, phy driver may disable controller power. In this case, registers need to be saved on suspend and restored on resume. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: debugfs: add support for complete register dumpMian Yousaf Kaukab2015-04-29
| | | | | | | | | Dump all registers to take a complete snapshot of dwc2 state. Code is inspired by dwc3/debugfs.c Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: move debugfs code to a separate fileMian Yousaf Kaukab2015-04-29
| | | | | | | | | | | Prepare to add more debug code. Moreover, don't save dentry * for each file in struct dwc2_hsotg as clean up is done with debugfs_remove_recursive(). s3c_hsotg_delete_debug() is removed altogether for the same reason. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: rework initialization of host and gadget in dual-role modeMarek Szyprowski2015-03-12
| | | | | | | | | | If device is configured to work only in HOST or DEVICE mode, there is no point in initializing both subdrivers. This patch also fixes resource leakage if host subdriver fails to initialize. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: gadget: add reset flag in init functionGregory Herrero2015-01-30
| | | | | | | | | | | | | | Add a flag to request physical reset of the controller when s3c_hsotg_core_init_disconnected is called. During the usb reset, controller must not be fully reconfigured and resetted. Else this leads to shorter chirp-k duration during enumeration. Tested-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: gadget: add unaligned buffers supportMian Yousaf Kaukab2015-01-30
| | | | | | | | | | When using DMA, dwc2 requires buffers to be 4 bytes aligned. Use bounce buffers if they are not. Tested-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: gadget: add TEST_MODE feature supportGregory Herrero2015-01-30
| | | | | | | | | | | | Handle SET_FEATURE TEST_MODE request sent by the host. Slightly rework FEATURE request handling to allow parsing other request types than Endpoint. Also add a debugfs to change test mode value from user space. Tested-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: gadget: rename sent_zlp to send_zlpMian Yousaf Kaukab2015-01-12
| | | | | | | | | | This flag is set before sending the zlp. So use present tense instead of the past tense. Tested-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: gadget: manage ep0 state in softwareMian Yousaf Kaukab2015-01-12
| | | | | | | | | | | | | | Manage ep0 state in software to add handling of status OUT stage. Just toggling hsotg->setup in s3c_hsotg_handle_outdone leaves it in wrong state in 2-stage control transfers. Moreover, ensure that for setup-packet s3c_hsotg_handle_outdone is called either from SetupDone or OutDone but not both. Dwc2 ip v3.00a generates both SetupDone and OutDone on setup packets. Tested-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: gadget: remove unused members from hsotg_reqMian Yousaf Kaukab2015-01-12
| | | | | | | | | These members are only occupying space. Tested-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-06 17:21:00 -0400