aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/nouveau/include/nvkm
Commit message (Collapse)AuthorAge
* drm/nouveau: Revert "bus: remove cpu_coherent flag"Karol Herbst2016-09-22
| | | | | | | | | | | | | This reverts commit aff51175cdbf345740ec9203eff88e772af88059. The commit caused fence timeouts within nvc0_screen_destroy and most likely other places as well. The most obvious effect is, that userspace processes take minutes to actually quit. Signed-off-by: Karol Herbst <karolherbst@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bus: remove cpu_coherent flagAlexandre Courbot2016-07-13
| | | | | | | | | | | | | | | This flag's only remaining function is to ignore the uncached flag for BOs on coherent architectures. However the reason for allocating an object uncache on a non-coherent architecture (namely because the cost of doing explicit flushes/ invalidations is higher than the benefit of caching the data because accesses are few and far between) should also apply on architectures for which coherency is maintained implicitly. Thus allocate coherent objects as uncached on all architectures. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ce/gp104: initial supportBen Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/gp104: initial supportBen Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fb/gp104: initial supportBen Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gp100: initial supportBen Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ce/gp100: initial supportBen Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gp100: initial supportBen Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/gp100: initial supportBen Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ltc/gp100: initial supportBen Skeggs2016-07-13
| | | | | | | | Due to the GPU preventing us from touching NV_PLTCG_LTCS_LTSS_CBC_BASE, we cannot provide CBC/ZBC support without signed PMU firmware to handle the task for us... Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fb/gp100: initial supportBen Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci/gp100: initial supportBen Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc/gp100: initial supportBen Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: recognise GP100 chipsetBen Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: increase maximum nvenc instances to 3Ben Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: increase maximum ce instances to 6Ben Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fb/gf100-: allow selection of an alternate big page sizeBen Skeggs2016-07-13
| | | | | | | | | | | | | GFxxx/GM1xx support the selection of 64/128KiB big pages globally. GM2xx supports the same, as well as another mode where the page size can be selected per-instance. We default to 128KiB pages (With per-instance for GM200, but the current code selects 128KiB there already) as the MMU code isn't currently able to handle otherwise. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios: pointers beyond end of first image need special handlingBen Skeggs2016-07-13
| | | | | | | | | Makes common the code that was previously used by the PMU table parsing, as it appears other tables need this too. Not much of an idea what this is all about... Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios: guard against out-of-bounds accesses to imageBen Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/volt: save the voltage range we are able to setKarol Herbst2016-07-13
| | | | | | | | | | We shouldn't set voltages below the min or above the max voltage the gpu is able to set, so save the range for future lookups. Signed-off-by: Karol Herbst <karolherbst@gmail.de> Reviewed-by: Martin Peres <martin.peres@free.fr> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/tegra: fetch gpu_speedo_idAlexandre Courbot2016-07-13
| | | | | | | | The GPU speedo ID is required to select the right clk/volt parameters on GM20B. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot: use nvkm_mc_enable/disable()Ben Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot: use nvkm_mc_intr_mask/unmask()Ben Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc: support for temporarily masking interrupts from a specific ↵Ben Skeggs2016-07-13
| | | | | | device Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc: expose device enable/disable separately, as well as resetBen Skeggs2016-07-13
| | | | | | | | | | There are cases where subdevs need to perform additonal actions around the master reset, so we want to expost the operations separately. This commit also adds a flag to the NV_PMC_ENABLE bitfield definitions which allow skipping the automatic reset() called from core/subdev.c. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc: take nvkm_device as argument to public functionsBen Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/top: add function to lookup interrupt mask for a given deviceBen Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/top: take nvkm_device as argument to public functionsBen Skeggs2016-07-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: swap the order of imem/fbBen Skeggs2016-06-01
| | | | | | Fixes a use-after-free reported by valgrind and KASAN. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios/disp: fix handling of "match any protocol" entriesBen Skeggs2016-06-01
| | | | | | | As it turns out, a value of 0xff means "any protocol" and not "VGA". Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Cc: stable@vger.kernel.org
* drm/nouveau/fb/gm200: setup mmu debug buffer registers at init()Ben Skeggs2016-05-20
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fb/gf100-: allocate mmu debug buffersBen Skeggs2016-05-20
| | | | | | | Later chipsets require setting this up both in FB and GR, so let's just move the allocation to FB. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: remove pmc_enable argument from subdev ctorBen Skeggs2016-05-20
| | | | | | These are now specified directly in the MC subdev. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc/nv11: define reset masks + intr cleanupBen Skeggs2016-05-20
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc/nv17: define reset masks + intr cleanupBen Skeggs2016-05-20
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc/g84: define reset masks + intr cleanupBen Skeggs2016-05-20
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc/gt215: define reset masks + intr cleanupBen Skeggs2016-05-20
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc/gk104: define reset masks + intr cleanupBen Skeggs2016-05-20
| | | | | | Engine fields have been removed, as they're specified by PTOP. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc: add helper function to handle device resetBen Skeggs2016-05-20
| | | | | | | This will be later extended to handle PTOP-specified reset masks as well as the hardcoded ones. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/top/gk104: initial implementationBen Skeggs2016-05-20
| | | | | | Ported from the code currently in engine/fifo/gk104.c. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/top: initial implementationBen Skeggs2016-05-20
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: add top plumbingBen Skeggs2016-05-20
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/iccsense: split sensor into own structKarol Herbst2016-05-20
| | | | | | | | v2: add list_del call, reword error message Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/iccsense: convert to linked listKarol Herbst2016-05-20
| | | | | | | | v2: add list_del calls Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/iccsense: remove read functionKarol Herbst2016-05-20
| | | | | | Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/devinit/gf100: make devinit on resume saferAlexandre Courbot2016-05-20
| | | | | | | | | | | | | | | | | | In case of successful suspend, devinit will have to be run and this is the behavior currently hardcoded. However, as FD bug 94725 suggests, there might be cases where runtime suspend leaves the GPU powered, and in such cases devinit should not be run on resume. On GF100+ we have a reliable way to know whether we need to run devinit. Use it instead of blindly trusting the flag set by nvkm_devinit_fini(). The code around the NvForcePost also needs to be slightly reworked in order to keep working. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Suggested-by: Dave Airlie <airlied@redhat.com> Suggested-by: Karol Herbst <nouveau@karolherbst.de> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/tegra: acquire and enable reference clock if neededAlexandre Courbot2016-04-06
| | | | | | | | GM20B requires an extra clock compared to GK20A. Add that information into the platform data and acquire and enable this clock if necessary. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/clk/gm20b: add basic driverAlexandre Courbot2016-03-13
| | | | | | | Add a basic clock driver that reuses the GK20A logic. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/volt: add GM20B driverAlexandre Courbot2016-03-13
| | | | | | | Add basic GM20B volt driver that reuses the GK20A logic. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ce/gm107: expose MaxwellDmaCopyABen Skeggs2016-03-13
| | | | | | The HW accepts KeplerDmaCopyA and MaxwellDmaCopyA classes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-10 00:03:53 -0400