| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | clk: sunxi: display: Add per-clock flags | Maxime Ripard | 2016-06-10 |
| | | | | | | | | | | | | | | | | | The TCON channel 0 clock that is the parent clock of our pixel clock is expected to change its rate depending on the resolution we want to output in our display engine. However, since it's only a mux, the only way it can do that is by changing its parents rate. Allow to give flags in our display clocks description, and add the CLK_SET_RATE_PARENT flag for the TCON channel 0 flag. Fixes: a3b4956ee6d9 ("clk: sunxi: display: Add per-clock flags") Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> | ||
| * | clk: sunxi: Add display and TCON0 clocks driver | Maxime Ripard | 2016-05-12 |
| The A10 SoCs and its relatives has a special clock controller to drive the display engines (both frontend and backend), that have a lot in common with the clock to drive the first TCON channel. Add a driver to support both. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> [sboyd@codeaurora.org: Silence variable sized array warning] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> | |||
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index : litmus-rt-edfsc.git | |
| LITMUS^RT with the EDF-SC plugin for Real-Time Systems journal paper | Zelin Tong |
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