| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | clk: sunxi: mod1 clock should modify it's parent | Andrea Venturi | 2016-04-21 |
| | | | | | | | | add CLK_SET_RATE_PARENT to modify the rate on clk upstream Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> | ||
| * | clk: sunxi: mod1 clock support | Emilio López | 2015-10-21 |
| The module 1 type of clocks consist of a gate and a mux and are used on the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or SPDIF. This commit adds support for them on the sunxi clock driver. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> | |||
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index : litmus-rt-edfsc.git | |
| LITMUS^RT with the EDF-SC plugin for Real-Time Systems journal paper | Zelin Tong |
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