| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | clk: iproc: Split off dig_filter | Jon Mason | 2015-10-21 |
| | | | | | | | | | | | The PLL loop filter/gain can be located in a separate register on some SoCs. Split these off into a separate variable, so that an offset can be added if necessary. Also, make the necessary modifications to the Cygnus and NSP drivers for this change. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> | ||
| * | clk: nsp: add clock support for Broadcom Northstar Plus SoC | Jon Mason | 2015-10-21 |
| The Broadcom Northstar Plus SoC is architected under the iProc architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all derived from an onboard crystal. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> | |||
 |
index : litmus-rt-edfsc.git | |
| LITMUS^RT with the EDF-SC plugin for Real-Time Systems journal paper | Zelin Tong |
| aboutsummaryrefslogtreecommitdiffstats |