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* xtensa: xtfpga: group platform_* functions togetherMax Filippov2016-09-20
| | | | | | | Group platform_* functions together and turn two separate #ifdef/#ifndef blocks into single #ifdef/#else. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: rearrange CCOUNT calibrationMax Filippov2016-09-20
| | | | | | | | | | | | | | | DT-enabled kernel should have a CPU node connected to a clock. This clock is the CCOUNT clock. Use old platform_calibrate_ccount call as a fallback when CPU node cannot be found or has no clock and in non-DT-enabled configurations. Drop no longer needed code that updates CPU clock-frequency property in the DT; drop DT-related code from the platform_calibrate_ccount too. Move of_clk_init to the top of time_init, so that clocks are initialized before CCOUNT calibration is attempted. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: xtfpga: use clock provider, don't update DTMax Filippov2016-09-20
| | | | | | | | | | | Instead of querying hardcoded FPGA frequency register and then updating clock-frequency property in specificly named DT nodes in machine setup code register a clock provider that returns fixed-rate clock, configured by register specified in DT. This way we have less magic/hardcoded names and use more existing common clock framework code. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Tested-by: Guenter Roeck <linux@roeck-us.net>
* xtensa: extract common CPU reset code into separate functionMax Filippov2016-09-12
| | | | | | | | platform_restart implementatations do the same thing to reset CPU. Don't duplicate that code, move it to a function and call it from platform_restart. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: xtfpga: fix ethernet controller endiannessMax Filippov2016-03-11
| | | | | | | | Ethernet controller is attached to XTFPGA boards as native endian device, mark it as such in DTS and pass correct endianness in platform data. This makes network functional on big-endian CPUs. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: xtfpga: fix serial port register width and endiannessMax Filippov2016-03-11
| | | | | | | | | Serial port is attached to XTFPGA boards as native endian device, mark it as such in DTS and pass correct endianness in platform data. Set register width in DTS to 4, this way it matches the platform data and works correctly on big-endian CPUs. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: xtfpga: fix integer overflow in TASK_SIZEMax Filippov2015-11-02
| | | | | | | | | | | This fixes the following warning when default memory region crosses 0x80000000: arch/xtensa/include/asm/processor.h:40:47: warning: integer overflow in expression [-Woverflow] #define TASK_SIZE (PLATFORM_DEFAULT_MEM_START + PLATFORM_DEFAULT_MEM_SIZE) ^ Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: fixes for configs without loop optionMax Filippov2015-11-02
| | | | | | | | | | | | | | | | Build-time fixes: - make lbeg/lend/lcount save/restore conditional on kernel entry; - don't clear lcount in platform_restart functions unconditionally. Run-time fixes: - use correct end of range register in __endla paired with __loopt, not the unused temporary register. This fixes .bss zero-initialization. Update comments in asmmacro.h; - don't clobber a10 in the usercopy that leads to access to unmapped memory. Cc: <stable@vger.kernel.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* Merge tag 'xtensa-for-next-20150413' of ↵Chris Zankel2015-04-14
|\ | | | | | | | | | | | | | | | | | | | | | | git://github.com/jcmvbkbc/linux-xtensa into for_next Xtensa improvements for 4.1: - fix locking issues in ISS network driver; - document PIC and MX interrupt distributor device tree bindings; - add CY7C67300 USB controller support to XTFPGA. Signed-off-by: Chris Zankel <chris@zankel.net>
| * xtensa: xtfpga: add CY7C67300 USB controller supportMax Filippov2015-04-13
| | | | | | | | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* | xtensa: xtfpga: fix hardware lockup caused by LCD driverMax Filippov2015-02-26
|/ | | | | | | | | | | | LCD driver is always built for the XTFPGA platform, but its base address is not configurable, and is wrong for ML605/KC705. Its initialization locks up KC705 board hardware. Make the whole driver optional, and its base address and bus width configurable. Implement 4-bit bus access method. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: make PLATFORM_DEFAULT_MEM parameters configurableMax Filippov2014-10-21
| | | | | | This allows using xtfpga platform with both MMU and noMMU cores. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: xtfpga: set ethoc clock frequencyMax Filippov2014-02-21
| | | | | | | Connect xtfpga board ethernet MAC to the clock in the DTS. Set up MAC base frequency in the platform data in case of build w/o CONFIG_OF. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: xtfpga: use common clock frameworkMax Filippov2014-02-21
| | | | | | | With this change the board needs to set up single clock object, users of this clock will get correct frequency automatically. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: xtfpga: fix definitions of platform devicesMax Filippov2014-01-14
| | | | | | | | Remove __initdata attribute, as the devices may be used after init sections are freed. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: standardize devicetree cpu compatible stringsBaruch Siach2014-01-14
| | | | | | | | | | | The recommended compatible string format, according to the ePAPR v1.1 standard, is "manufacturer,model". Change the xtensa cpu compatible strings to "cdns,xtensa-cpu". Also, change the boards compatible strings in a similar way. The pic compatible string will be dealt with in a separate patch. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: add SMP supportMax Filippov2014-01-14
| | | | | | | | | This is largely based on SMP code from the xtensa-2.6.29-smp tree by Piet Delaney, Marc Gauthier, Joe Taylor, Christian Zankel (and possibly other Tensilica folks). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: remove NO_IRQ definitionsMax Filippov2014-01-14
| | | | | | | | These definitions (-1) were correct when used as a hardware IRQ number, but are incorrect as a mapped IRQ number. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: cleanup ccount frequency trackingBaruch Siach2013-07-08
| | | | | | | Remove unused nsec_per_ccount, and rename ccount_per_jiffy to ccount_preq. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: xtfpga: fix section mismatchBaruch Siach2013-06-05
| | | | | | | | | | platform_calibrate_ccount() calls update_clock_frequency() which is in .init section. However, platform_calibrate_ccount() itself is only called from .init (i.e., time_init()). Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: fix ibreakenable register updateMax Filippov2013-05-09
| | | | | | | | | | | | Only set the register when there is at least one ibreak register, otherwise the build fails: arch/xtensa/kernel/head.S:105: Error: invalid register 'ibreakenable' for 'wsr' instruction arch/xtensa/platforms/iss/setup.c:67: Error: invalid register 'ibreakenable' for 'wsr' instruction Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: rename prom_update_property to of_update_propertyMax Filippov2013-02-23
| | | | | | | | This rename happened in 79d1c71 powerpc+of: Rename the drivers/of prom_* functions to of_*. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: set the correct ethernet address for xtfpgaChris Zankel2012-12-19
| | | | | | | The last byte of the mac address is determined by a DIP switch, so update the OF property with that address. Signed-off-by: Chris Zankel <chris@zankel.net>
* Use for_each_compatible_node() macro.Wei Yongjun2012-12-19
| | | | | | Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: add support for the XTFPGA boardsMax Filippov2012-12-19
The Avnet LX60/LX110/LX200 board is an FPGA board that can be configured with an Xtensa processor and an OpenCores Ethernet device. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
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