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path: root/arch/arm/boot/dts/bcm958625k.dts
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* ARM: dts: NSP: Specify RAM amount for BCM958625K boardJon Mason2016-08-08
| | | | | | | Add 2GB of memory starting at physical offset 0x6000_0000. Signed-off-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: NSP: Add AMAC entriesJon Mason2016-08-08
| | | | | | | | Add Device Tree entries for the Ethernet devices (AMAC) present on the Broadcom Northstar Plus SoCs. Signed-off-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: nsp: Add sata device tree entryYendapally Reddy Dhananjaya Reddy2016-06-16
| | | | | | | | Add sata support to the Northstar Plus SoC device tree. Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Tejun Heo <tj@kernel.org>
* ARM: dts: enable pinctrl for Broadcom NSPYendapally Reddy Dhananjaya Reddy2015-12-06
| | | | | | | This enables the pinctrl support for Broadcom NSP SoC Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yrdreddy@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: NSP: Add NAND Support to DTJon Mason2015-11-16
| | | | | | | | | Add NAND support to the device tree for the Broadcom Northstar Plus SoC. Since no driver changes are needed to enable this hardware, only the device tree changes are required to make this functional. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: NSP: Add PCI supportJon Mason2015-11-16
| | | | | | | | | Add PCI support to the Northstar Plus SoC. This uses the existing pcie-iproc driver. So, all that is needed is device tree entries in the DTS. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: NSP: add minimal Northstar Plus device treeJon Mason2015-09-14
Add a very minimalistic set of Northstar Plus Device Tree files which describes the SoC and the BCM958625 implementation. The perpherials described are: ARM Cortex A9 CPU 2 8250 UARTs ARM GIC PL310 L2 Cache ARM A9 Global timer Signed-off-by: Kapil Hali <kapilh@broadcom.com> Signed-off-by: Jon Mason <jonmason@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>