aboutsummaryrefslogtreecommitdiffstats
path: root/sound/soc/rockchip
diff options
context:
space:
mode:
Diffstat (limited to 'sound/soc/rockchip')
-rw-r--r--sound/soc/rockchip/Kconfig12
-rw-r--r--sound/soc/rockchip/Makefile4
-rw-r--r--sound/soc/rockchip/rockchip_i2s.c530
-rw-r--r--sound/soc/rockchip/rockchip_i2s.h223
4 files changed, 769 insertions, 0 deletions
diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig
new file mode 100644
index 000000000000..c196a466eef6
--- /dev/null
+++ b/sound/soc/rockchip/Kconfig
@@ -0,0 +1,12 @@
1config SND_SOC_ROCKCHIP
2 tristate "ASoC support for Rockchip"
3 depends on COMPILE_TEST || ARCH_ROCKCHIP
4 select SND_SOC_GENERIC_DMAENGINE_PCM
5 select SND_ROCKCHIP_I2S
6 help
7 Say Y or M if you want to add support for codecs attached to
8 the Rockchip SoCs' Audio interfaces. You will also need to
9 select the audio interfaces to support below.
10
11config SND_ROCKCHIP_I2S
12 tristate
diff --git a/sound/soc/rockchip/Makefile b/sound/soc/rockchip/Makefile
new file mode 100644
index 000000000000..1006418e1394
--- /dev/null
+++ b/sound/soc/rockchip/Makefile
@@ -0,0 +1,4 @@
1# ROCKCHIP Platform Support
2snd-soc-i2s-objs := rockchip_i2s.o
3
4obj-$(CONFIG_SND_ROCKCHIP_I2S) += snd-soc-i2s.o
diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c
new file mode 100644
index 000000000000..af1d8eb94f04
--- /dev/null
+++ b/sound/soc/rockchip/rockchip_i2s.c
@@ -0,0 +1,530 @@
1/* sound/soc/rockchip/rockchip_i2s.c
2 *
3 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
4 *
5 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
6 * Author: Jianqun <jay.xu@rock-chips.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/delay.h>
14#include <linux/of_gpio.h>
15#include <linux/clk.h>
16#include <linux/pm_runtime.h>
17#include <linux/regmap.h>
18#include <sound/pcm_params.h>
19#include <sound/dmaengine_pcm.h>
20
21#include "rockchip_i2s.h"
22
23#define DRV_NAME "rockchip-i2s"
24
25struct rk_i2s_dev {
26 struct device *dev;
27
28 struct clk *hclk;
29 struct clk *mclk;
30
31 struct snd_dmaengine_dai_dma_data capture_dma_data;
32 struct snd_dmaengine_dai_dma_data playback_dma_data;
33
34 struct regmap *regmap;
35
36/*
37 * Used to indicate the tx/rx status.
38 * I2S controller hopes to start the tx and rx together,
39 * also to stop them when they are both try to stop.
40*/
41 bool tx_start;
42 bool rx_start;
43};
44
45static int i2s_runtime_suspend(struct device *dev)
46{
47 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
48
49 clk_disable_unprepare(i2s->mclk);
50
51 return 0;
52}
53
54static int i2s_runtime_resume(struct device *dev)
55{
56 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
57 int ret;
58
59 ret = clk_prepare_enable(i2s->mclk);
60 if (ret) {
61 dev_err(i2s->dev, "clock enable failed %d\n", ret);
62 return ret;
63 }
64
65 return 0;
66}
67
68static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
69{
70 return snd_soc_dai_get_drvdata(dai);
71}
72
73static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
74{
75 unsigned int val = 0;
76 int retry = 10;
77
78 if (on) {
79 regmap_update_bits(i2s->regmap, I2S_DMACR,
80 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
81
82 regmap_update_bits(i2s->regmap, I2S_XFER,
83 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
84 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
85
86 i2s->tx_start = true;
87 } else {
88 i2s->tx_start = false;
89
90 regmap_update_bits(i2s->regmap, I2S_DMACR,
91 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
92
93 if (!i2s->rx_start) {
94 regmap_update_bits(i2s->regmap, I2S_XFER,
95 I2S_XFER_TXS_START |
96 I2S_XFER_RXS_START,
97 I2S_XFER_TXS_STOP |
98 I2S_XFER_RXS_STOP);
99
100 regmap_update_bits(i2s->regmap, I2S_CLR,
101 I2S_CLR_TXC | I2S_CLR_TXC,
102 I2S_CLR_TXC | I2S_CLR_TXC);
103
104 regmap_read(i2s->regmap, I2S_CLR, &val);
105
106 /* Should wait for clear operation to finish */
107 while (val) {
108 regmap_read(i2s->regmap, I2S_CLR, &val);
109 retry--;
110 if (!retry)
111 dev_warn(i2s->dev, "fail to clear\n");
112 }
113 }
114 }
115}
116
117static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
118{
119 unsigned int val = 0;
120 int retry = 10;
121
122 if (on) {
123 regmap_update_bits(i2s->regmap, I2S_DMACR,
124 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
125
126 regmap_update_bits(i2s->regmap, I2S_XFER,
127 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
128 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
129
130 i2s->rx_start = true;
131 } else {
132 i2s->rx_start = false;
133
134 regmap_update_bits(i2s->regmap, I2S_DMACR,
135 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
136
137 if (!i2s->tx_start) {
138 regmap_update_bits(i2s->regmap, I2S_XFER,
139 I2S_XFER_TXS_START |
140 I2S_XFER_RXS_START,
141 I2S_XFER_TXS_STOP |
142 I2S_XFER_RXS_STOP);
143
144 regmap_update_bits(i2s->regmap, I2S_CLR,
145 I2S_CLR_TXC | I2S_CLR_TXC,
146 I2S_CLR_TXC | I2S_CLR_TXC);
147
148 regmap_read(i2s->regmap, I2S_CLR, &val);
149
150 /* Should wait for clear operation to finish */
151 while (val) {
152 regmap_read(i2s->regmap, I2S_CLR, &val);
153 retry--;
154 if (!retry)
155 dev_warn(i2s->dev, "fail to clear\n");
156 }
157 }
158 }
159}
160
161static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
162 unsigned int fmt)
163{
164 struct rk_i2s_dev *i2s = to_info(cpu_dai);
165 unsigned int mask = 0, val = 0;
166
167 mask = I2S_CKR_MSS_SLAVE;
168 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
169 case SND_SOC_DAIFMT_CBS_CFS:
170 val = I2S_CKR_MSS_SLAVE;
171 break;
172 case SND_SOC_DAIFMT_CBM_CFM:
173 val = I2S_CKR_MSS_MASTER;
174 break;
175 default:
176 return -EINVAL;
177 }
178
179 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
180
181 mask = I2S_TXCR_IBM_MASK;
182 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
183 case SND_SOC_DAIFMT_RIGHT_J:
184 val = I2S_TXCR_IBM_RSJM;
185 break;
186 case SND_SOC_DAIFMT_LEFT_J:
187 val = I2S_TXCR_IBM_LSJM;
188 break;
189 case SND_SOC_DAIFMT_I2S:
190 val = I2S_TXCR_IBM_NORMAL;
191 break;
192 default:
193 return -EINVAL;
194 }
195
196 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
197
198 mask = I2S_RXCR_IBM_MASK;
199 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
200 case SND_SOC_DAIFMT_RIGHT_J:
201 val = I2S_RXCR_IBM_RSJM;
202 break;
203 case SND_SOC_DAIFMT_LEFT_J:
204 val = I2S_RXCR_IBM_LSJM;
205 break;
206 case SND_SOC_DAIFMT_I2S:
207 val = I2S_RXCR_IBM_NORMAL;
208 break;
209 default:
210 return -EINVAL;
211 }
212
213 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
214
215 return 0;
216}
217
218static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
219 struct snd_pcm_hw_params *params,
220 struct snd_soc_dai *dai)
221{
222 struct rk_i2s_dev *i2s = to_info(dai);
223 unsigned int val = 0;
224
225 switch (params_format(params)) {
226 case SNDRV_PCM_FORMAT_S8:
227 val |= I2S_TXCR_VDW(8);
228 break;
229 case SNDRV_PCM_FORMAT_S16_LE:
230 val |= I2S_TXCR_VDW(16);
231 break;
232 case SNDRV_PCM_FORMAT_S20_3LE:
233 val |= I2S_TXCR_VDW(20);
234 break;
235 case SNDRV_PCM_FORMAT_S24_LE:
236 val |= I2S_TXCR_VDW(24);
237 break;
238 default:
239 return -EINVAL;
240 }
241
242 regmap_update_bits(i2s->regmap, I2S_TXCR, I2S_TXCR_VDW_MASK, val);
243 regmap_update_bits(i2s->regmap, I2S_RXCR, I2S_RXCR_VDW_MASK, val);
244
245 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
246 dai->playback_dma_data = &i2s->playback_dma_data;
247 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
248 I2S_DMACR_TDL(1) | I2S_DMACR_TDE_ENABLE);
249 } else {
250 dai->capture_dma_data = &i2s->capture_dma_data;
251 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
252 I2S_DMACR_RDL(1) | I2S_DMACR_RDE_ENABLE);
253 }
254
255 return 0;
256}
257
258static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
259 int cmd, struct snd_soc_dai *dai)
260{
261 struct rk_i2s_dev *i2s = to_info(dai);
262 int ret = 0;
263
264 switch (cmd) {
265 case SNDRV_PCM_TRIGGER_START:
266 case SNDRV_PCM_TRIGGER_RESUME:
267 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
268 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
269 rockchip_snd_rxctrl(i2s, 1);
270 else
271 rockchip_snd_txctrl(i2s, 1);
272 break;
273 case SNDRV_PCM_TRIGGER_SUSPEND:
274 case SNDRV_PCM_TRIGGER_STOP:
275 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
276 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
277 rockchip_snd_rxctrl(i2s, 0);
278 else
279 rockchip_snd_txctrl(i2s, 0);
280 break;
281 default:
282 ret = -EINVAL;
283 break;
284 }
285
286 return ret;
287}
288
289static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
290 unsigned int freq, int dir)
291{
292 struct rk_i2s_dev *i2s = to_info(cpu_dai);
293 int ret;
294
295 ret = clk_set_rate(i2s->mclk, freq);
296 if (ret)
297 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
298
299 return ret;
300}
301
302static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
303 .hw_params = rockchip_i2s_hw_params,
304 .set_sysclk = rockchip_i2s_set_sysclk,
305 .set_fmt = rockchip_i2s_set_fmt,
306 .trigger = rockchip_i2s_trigger,
307};
308
309static struct snd_soc_dai_driver rockchip_i2s_dai = {
310 .playback = {
311 .channels_min = 2,
312 .channels_max = 8,
313 .rates = SNDRV_PCM_RATE_8000_192000,
314 .formats = (SNDRV_PCM_FMTBIT_S8 |
315 SNDRV_PCM_FMTBIT_S16_LE |
316 SNDRV_PCM_FMTBIT_S20_3LE |
317 SNDRV_PCM_FMTBIT_S24_LE),
318 },
319 .capture = {
320 .channels_min = 2,
321 .channels_max = 2,
322 .rates = SNDRV_PCM_RATE_8000_192000,
323 .formats = (SNDRV_PCM_FMTBIT_S8 |
324 SNDRV_PCM_FMTBIT_S16_LE |
325 SNDRV_PCM_FMTBIT_S20_3LE |
326 SNDRV_PCM_FMTBIT_S24_LE),
327 },
328 .ops = &rockchip_i2s_dai_ops,
329};
330
331static const struct snd_soc_component_driver rockchip_i2s_component = {
332 .name = DRV_NAME,
333};
334
335static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
336{
337 switch (reg) {
338 case I2S_TXCR:
339 case I2S_RXCR:
340 case I2S_CKR:
341 case I2S_DMACR:
342 case I2S_INTCR:
343 case I2S_XFER:
344 case I2S_CLR:
345 case I2S_TXDR:
346 return true;
347 default:
348 return false;
349 }
350}
351
352static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
353{
354 switch (reg) {
355 case I2S_TXCR:
356 case I2S_RXCR:
357 case I2S_CKR:
358 case I2S_DMACR:
359 case I2S_INTCR:
360 case I2S_XFER:
361 case I2S_CLR:
362 case I2S_RXDR:
363 return true;
364 default:
365 return false;
366 }
367}
368
369static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
370{
371 switch (reg) {
372 case I2S_FIFOLR:
373 case I2S_INTSR:
374 return true;
375 default:
376 return false;
377 }
378}
379
380static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
381{
382 switch (reg) {
383 case I2S_FIFOLR:
384 return true;
385 default:
386 return false;
387 }
388}
389
390static const struct regmap_config rockchip_i2s_regmap_config = {
391 .reg_bits = 32,
392 .reg_stride = 4,
393 .val_bits = 32,
394 .max_register = I2S_RXDR,
395 .writeable_reg = rockchip_i2s_wr_reg,
396 .readable_reg = rockchip_i2s_rd_reg,
397 .volatile_reg = rockchip_i2s_volatile_reg,
398 .precious_reg = rockchip_i2s_precious_reg,
399 .cache_type = REGCACHE_FLAT,
400};
401
402static int rockchip_i2s_probe(struct platform_device *pdev)
403{
404 struct rk_i2s_dev *i2s;
405 struct resource *res;
406 void __iomem *regs;
407 int ret;
408
409 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
410 if (!i2s) {
411 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
412 return -ENOMEM;
413 }
414
415 /* try to prepare related clocks */
416 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
417 if (IS_ERR(i2s->hclk)) {
418 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
419 return PTR_ERR(i2s->hclk);
420 }
421
422 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
423 if (IS_ERR(i2s->mclk)) {
424 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
425 return PTR_ERR(i2s->mclk);
426 }
427
428 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
429 regs = devm_ioremap_resource(&pdev->dev, res);
430 if (IS_ERR(regs)) {
431 dev_err(&pdev->dev, "No memory resource\n");
432 return PTR_ERR(regs);
433 }
434
435 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
436 &rockchip_i2s_regmap_config);
437 if (IS_ERR(i2s->regmap)) {
438 dev_err(&pdev->dev,
439 "Failed to initialise managed register map\n");
440 return PTR_ERR(i2s->regmap);
441 }
442
443 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
444 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
445 i2s->playback_dma_data.maxburst = 16;
446
447 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
448 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
449 i2s->capture_dma_data.maxburst = 16;
450
451 i2s->dev = &pdev->dev;
452 dev_set_drvdata(&pdev->dev, i2s);
453
454 pm_runtime_enable(&pdev->dev);
455 if (!pm_runtime_enabled(&pdev->dev)) {
456 ret = i2s_runtime_resume(&pdev->dev);
457 if (ret)
458 goto err_pm_disable;
459 }
460
461 ret = devm_snd_soc_register_component(&pdev->dev,
462 &rockchip_i2s_component,
463 &rockchip_i2s_dai, 1);
464 if (ret) {
465 dev_err(&pdev->dev, "Could not register DAI\n");
466 goto err_suspend;
467 }
468
469 ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
470 if (ret) {
471 dev_err(&pdev->dev, "Could not register PCM\n");
472 goto err_pcm_register;
473 }
474
475 return 0;
476
477err_pcm_register:
478 snd_dmaengine_pcm_unregister(&pdev->dev);
479err_suspend:
480 if (!pm_runtime_status_suspended(&pdev->dev))
481 i2s_runtime_suspend(&pdev->dev);
482err_pm_disable:
483 pm_runtime_disable(&pdev->dev);
484
485 return ret;
486}
487
488static int rockchip_i2s_remove(struct platform_device *pdev)
489{
490 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
491
492 pm_runtime_disable(&pdev->dev);
493 if (!pm_runtime_status_suspended(&pdev->dev))
494 i2s_runtime_suspend(&pdev->dev);
495
496 clk_disable_unprepare(i2s->mclk);
497 clk_disable_unprepare(i2s->hclk);
498 snd_dmaengine_pcm_unregister(&pdev->dev);
499 snd_soc_unregister_component(&pdev->dev);
500
501 return 0;
502}
503
504static const struct of_device_id rockchip_i2s_match[] = {
505 { .compatible = "rockchip,rk3066-i2s", },
506 {},
507};
508
509static const struct dev_pm_ops rockchip_i2s_pm_ops = {
510 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
511 NULL)
512};
513
514static struct platform_driver rockchip_i2s_driver = {
515 .probe = rockchip_i2s_probe,
516 .remove = rockchip_i2s_remove,
517 .driver = {
518 .name = DRV_NAME,
519 .owner = THIS_MODULE,
520 .of_match_table = of_match_ptr(rockchip_i2s_match),
521 .pm = &rockchip_i2s_pm_ops,
522 },
523};
524module_platform_driver(rockchip_i2s_driver);
525
526MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
527MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
528MODULE_LICENSE("GPL v2");
529MODULE_ALIAS("platform:" DRV_NAME);
530MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
diff --git a/sound/soc/rockchip/rockchip_i2s.h b/sound/soc/rockchip/rockchip_i2s.h
new file mode 100644
index 000000000000..89a5d8bc6ee7
--- /dev/null
+++ b/sound/soc/rockchip/rockchip_i2s.h
@@ -0,0 +1,223 @@
1/*
2 * sound/soc/rockchip/rockchip_i2s.h
3 *
4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
5 *
6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
7 * Author: Jianqun xu <jay.xu@rock-chips.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef _ROCKCHIP_IIS_H
15#define _ROCKCHIP_IIS_H
16
17/*
18 * TXCR
19 * transmit operation control register
20*/
21#define I2S_TXCR_RCNT_SHIFT 17
22#define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT)
23#define I2S_TXCR_CSR_SHIFT 15
24#define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT)
25#define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT)
26#define I2S_TXCR_HWT BIT(14)
27#define I2S_TXCR_SJM_SHIFT 12
28#define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT)
29#define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT)
30#define I2S_TXCR_FBM_SHIFT 11
31#define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT)
32#define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT)
33#define I2S_TXCR_IBM_SHIFT 9
34#define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT)
35#define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT)
36#define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT)
37#define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT)
38#define I2S_TXCR_PBM_SHIFT 7
39#define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT)
40#define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT)
41#define I2S_TXCR_TFS_SHIFT 5
42#define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
43#define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
44#define I2S_TXCR_VDW_SHIFT 0
45#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
46#define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
47
48/*
49 * RXCR
50 * receive operation control register
51*/
52#define I2S_RXCR_HWT BIT(14)
53#define I2S_RXCR_SJM_SHIFT 12
54#define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT)
55#define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT)
56#define I2S_RXCR_FBM_SHIFT 11
57#define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT)
58#define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT)
59#define I2S_RXCR_IBM_SHIFT 9
60#define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT)
61#define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT)
62#define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT)
63#define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT)
64#define I2S_RXCR_PBM_SHIFT 7
65#define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT)
66#define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT)
67#define I2S_RXCR_TFS_SHIFT 5
68#define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
69#define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
70#define I2S_RXCR_VDW_SHIFT 0
71#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
72#define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
73
74/*
75 * CKR
76 * clock generation register
77*/
78#define I2S_CKR_MSS_SHIFT 27
79#define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT)
80#define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT)
81#define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT)
82#define I2S_CKR_CKP_SHIFT 26
83#define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT)
84#define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT)
85#define I2S_CKR_RLP_SHIFT 25
86#define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT)
87#define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT)
88#define I2S_CKR_TLP_SHIFT 24
89#define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT)
90#define I2S_CKR_TLP_OPPSITE (1 << I2S_CKR_TLP_SHIFT)
91#define I2S_CKR_MDIV_SHIFT 16
92#define I2S_CKR_MDIV(x) ((x - 1) << I2S_CKR_MDIV_SHIFT)
93#define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT)
94#define I2S_CKR_RSD_SHIFT 8
95#define I2S_CKR_RSD(x) ((x - 1) << I2S_CKR_RSD_SHIFT)
96#define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT)
97#define I2S_CKR_TSD_SHIFT 0
98#define I2S_CKR_TSD(x) ((x - 1) << I2S_CKR_TSD_SHIFT)
99#define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT)
100
101/*
102 * FIFOLR
103 * FIFO level register
104*/
105#define I2S_FIFOLR_RFL_SHIFT 24
106#define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT)
107#define I2S_FIFOLR_TFL3_SHIFT 18
108#define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT)
109#define I2S_FIFOLR_TFL2_SHIFT 12
110#define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT)
111#define I2S_FIFOLR_TFL1_SHIFT 6
112#define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT)
113#define I2S_FIFOLR_TFL0_SHIFT 0
114#define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT)
115
116/*
117 * DMACR
118 * DMA control register
119*/
120#define I2S_DMACR_RDE_SHIFT 24
121#define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT)
122#define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT)
123#define I2S_DMACR_RDL_SHIFT 16
124#define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT)
125#define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT)
126#define I2S_DMACR_TDE_SHIFT 8
127#define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT)
128#define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT)
129#define I2S_DMACR_TDL_SHIFT 0
130#define I2S_DMACR_TDL(x) ((x - 1) << I2S_DMACR_TDL_SHIFT)
131#define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT)
132
133/*
134 * INTCR
135 * interrupt control register
136*/
137#define I2S_INTCR_RFT_SHIFT 20
138#define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT)
139#define I2S_INTCR_RXOIC BIT(18)
140#define I2S_INTCR_RXOIE_SHIFT 17
141#define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT)
142#define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT)
143#define I2S_INTCR_RXFIE_SHIFT 16
144#define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT)
145#define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT)
146#define I2S_INTCR_TFT_SHIFT 4
147#define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT)
148#define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT)
149#define I2S_INTCR_TXUIC BIT(2)
150#define I2S_INTCR_TXUIE_SHIFT 1
151#define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT)
152#define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT)
153
154/*
155 * INTSR
156 * interrupt status register
157*/
158#define I2S_INTSR_TXEIE_SHIFT 0
159#define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTSR_TXEIE_SHIFT)
160#define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTSR_TXEIE_SHIFT)
161#define I2S_INTSR_RXOI_SHIFT 17
162#define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT)
163#define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT)
164#define I2S_INTSR_RXFI_SHIFT 16
165#define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT)
166#define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT)
167#define I2S_INTSR_TXUI_SHIFT 1
168#define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT)
169#define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT)
170#define I2S_INTSR_TXEI_SHIFT 0
171#define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT)
172#define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT)
173
174/*
175 * XFER
176 * Transfer start register
177*/
178#define I2S_XFER_RXS_SHIFT 1
179#define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT)
180#define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT)
181#define I2S_XFER_TXS_SHIFT 0
182#define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT)
183#define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT)
184
185/*
186 * CLR
187 * clear SCLK domain logic register
188*/
189#define I2S_CLR_RXC BIT(1)
190#define I2S_CLR_TXC BIT(0)
191
192/*
193 * TXDR
194 * Transimt FIFO data register, write only.
195*/
196#define I2S_TXDR_MASK (0xff)
197
198/*
199 * RXDR
200 * Receive FIFO data register, write only.
201*/
202#define I2S_RXDR_MASK (0xff)
203
204/* Clock divider id */
205enum {
206 ROCKCHIP_DIV_MCLK = 0,
207 ROCKCHIP_DIV_BCLK,
208};
209
210/* I2S REGS */
211#define I2S_TXCR (0x0000)
212#define I2S_RXCR (0x0004)
213#define I2S_CKR (0x0008)
214#define I2S_FIFOLR (0x000c)
215#define I2S_DMACR (0x0010)
216#define I2S_INTCR (0x0014)
217#define I2S_INTSR (0x0018)
218#define I2S_XFER (0x001c)
219#define I2S_CLR (0x0020)
220#define I2S_TXDR (0x0024)
221#define I2S_RXDR (0x0028)
222
223#endif /* _ROCKCHIP_IIS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 17:46:02 -0500