51 files changed, 871 insertions, 234 deletions

diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index c57e064666e4..7f1c0f00db9b 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -192,6 +192,7 @@ header-y += in_route.h
 header-y += sock_diag.h
 header-y += inet_diag.h
 header-y += unix_diag.h
+header-y += packet_diag.h
 header-y += inotify.h
 header-y += input.h
 header-y += ioctl.h
@@ -359,6 +360,7 @@ header-y += sysctl.h
 header-y += sysinfo.h
 header-y += taskstats.h
 header-y += tcp.h
+header-y += tcp_metrics.h
 header-y += telephony.h
 header-y += termios.h
 header-y += time.h
diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h
index d323a4b4143c..6ba45d2b99db 100644
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
@@ -100,6 +100,7 @@
 #define  BCMA_CC_CHIPST_4706_SFLASH_TYPE        BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
 #define  BCMA_CC_CHIPST_4706_MIPS_BENDIAN       BIT(3) /* 0: little, 1: big endian */
 #define  BCMA_CC_CHIPST_4706_PCIE1_DISABLE      BIT(5) /* PCIE1 enable strap pin */
+#define  BCMA_CC_CHIPST_5357_NAND_BOOT          BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
 #define BCMA_CC_JCMD                    0x0030          /* Rev >= 10 only */
 #define  BCMA_CC_JCMD_START             0x80000000
 #define  BCMA_CC_JCMD_BUSY              0x80000000
@@ -266,6 +267,29 @@
 #define  BCMA_CC_SROM_CONTROL_SIZE_16K  0x00000004
 #define  BCMA_CC_SROM_CONTROL_SIZE_SHIFT        1
 #define  BCMA_CC_SROM_CONTROL_PRESENT   0x00000001
+/* Block 0x140 - 0x190 registers are chipset specific */
+#define BCMA_CC_4706_FLASHSCFG          0x18C           /* Flash struct configuration */
+#define  BCMA_CC_4706_FLASHSCFG_MASK    0x000000ff
+#define  BCMA_CC_4706_FLASHSCFG_SF1     0x00000001      /* 2nd serial flash present */
+#define  BCMA_CC_4706_FLASHSCFG_PF1     0x00000002      /* 2nd parallel flash present */
+#define  BCMA_CC_4706_FLASHSCFG_SF1_TYPE        0x00000004      /* 2nd serial flash type : 0 : ST, 1 : Atmel */
+#define  BCMA_CC_4706_FLASHSCFG_NF1     0x00000008      /* 2nd NAND flash present */
+#define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK      0x000000f0
+#define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB       0x00000010      /* 4MB */
+#define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB       0x00000020      /* 8MB */
+#define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB      0x00000030      /* 16MB */
+#define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB      0x00000040      /* 32MB */
+#define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB      0x00000050      /* 64MB */
+#define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB     0x00000060      /* 128MB */
+#define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB     0x00000070      /* 256MB */
+/* NAND flash registers for BCM4706 (corerev = 31) */
+#define BCMA_CC_NFLASH_CTL              0x01A0
+#define  BCMA_CC_NFLASH_CTL_ERR         0x08000000
+#define BCMA_CC_NFLASH_CONF             0x01A4
+#define BCMA_CC_NFLASH_COL_ADDR         0x01A8
+#define BCMA_CC_NFLASH_ROW_ADDR         0x01AC
+#define BCMA_CC_NFLASH_DATA             0x01B0
+#define BCMA_CC_NFLASH_WAITCNT0         0x01B4
 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
 #define BCMA_CC_HW_WORKAROUND           0x01E4 /* Hardware workaround (rev >= 20) */
 #define BCMA_CC_UART0_DATA              0x0300
@@ -325,6 +349,60 @@
 #define BCMA_CC_PLLCTL_ADDR             0x0660
 #define BCMA_CC_PLLCTL_DATA             0x0664
 #define BCMA_CC_SPROM                   0x0800 /* SPROM beginning */
+/* NAND flash MLC controller registers (corerev >= 38) */
+#define BCMA_CC_NAND_REVISION           0x0C00
+#define BCMA_CC_NAND_CMD_START          0x0C04
+#define BCMA_CC_NAND_CMD_ADDR_X         0x0C08
+#define BCMA_CC_NAND_CMD_ADDR           0x0C0C
+#define BCMA_CC_NAND_CMD_END_ADDR       0x0C10
+#define BCMA_CC_NAND_CS_NAND_SELECT     0x0C14
+#define BCMA_CC_NAND_CS_NAND_XOR        0x0C18
+#define BCMA_CC_NAND_SPARE_RD0          0x0C20
+#define BCMA_CC_NAND_SPARE_RD4          0x0C24
+#define BCMA_CC_NAND_SPARE_RD8          0x0C28
+#define BCMA_CC_NAND_SPARE_RD12         0x0C2C
+#define BCMA_CC_NAND_SPARE_WR0          0x0C30
+#define BCMA_CC_NAND_SPARE_WR4          0x0C34
+#define BCMA_CC_NAND_SPARE_WR8          0x0C38
+#define BCMA_CC_NAND_SPARE_WR12         0x0C3C
+#define BCMA_CC_NAND_ACC_CONTROL        0x0C40
+#define BCMA_CC_NAND_CONFIG             0x0C48
+#define BCMA_CC_NAND_TIMING_1           0x0C50
+#define BCMA_CC_NAND_TIMING_2           0x0C54
+#define BCMA_CC_NAND_SEMAPHORE          0x0C58
+#define BCMA_CC_NAND_DEVID              0x0C60
+#define BCMA_CC_NAND_DEVID_X            0x0C64
+#define BCMA_CC_NAND_BLOCK_LOCK_STATUS  0x0C68
+#define BCMA_CC_NAND_INTFC_STATUS       0x0C6C
+#define BCMA_CC_NAND_ECC_CORR_ADDR_X    0x0C70
+#define BCMA_CC_NAND_ECC_CORR_ADDR      0x0C74
+#define BCMA_CC_NAND_ECC_UNC_ADDR_X     0x0C78
+#define BCMA_CC_NAND_ECC_UNC_ADDR       0x0C7C
+#define BCMA_CC_NAND_READ_ERROR_COUNT   0x0C80
+#define BCMA_CC_NAND_CORR_STAT_THRESHOLD        0x0C84
+#define BCMA_CC_NAND_READ_ADDR_X        0x0C90
+#define BCMA_CC_NAND_READ_ADDR          0x0C94
+#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X        0x0C98
+#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR  0x0C9C
+#define BCMA_CC_NAND_COPY_BACK_ADDR_X   0x0CA0
+#define BCMA_CC_NAND_COPY_BACK_ADDR     0x0CA4
+#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
+#define BCMA_CC_NAND_BLOCK_ERASE_ADDR   0x0CAC
+#define BCMA_CC_NAND_INV_READ_ADDR_X    0x0CB0
+#define BCMA_CC_NAND_INV_READ_ADDR      0x0CB4
+#define BCMA_CC_NAND_BLK_WR_PROTECT     0x0CC0
+#define BCMA_CC_NAND_ACC_CONTROL_CS1    0x0CD0
+#define BCMA_CC_NAND_CONFIG_CS1         0x0CD4
+#define BCMA_CC_NAND_TIMING_1_CS1       0x0CD8
+#define BCMA_CC_NAND_TIMING_2_CS1       0x0CDC
+#define BCMA_CC_NAND_SPARE_RD16         0x0D30
+#define BCMA_CC_NAND_SPARE_RD20         0x0D34
+#define BCMA_CC_NAND_SPARE_RD24         0x0D38