3 files changed, 36 insertions, 1 deletions

diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 9299222d680d..223be696df27 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -263,7 +263,8 @@ void omap2_clk_legacy_provider_init(int index, void __iomem *mem);
 int omap3430_dt_clk_init(void);
 int omap3630_dt_clk_init(void);
 int am35xx_dt_clk_init(void);
-int ti81xx_dt_clk_init(void);
+int dm814x_dt_clk_init(void);
+int dm816x_dt_clk_init(void);
 int omap4xxx_dt_clk_init(void);
 int omap5xxx_dt_clk_init(void);
 int dra7xx_dt_clk_init(void);
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index d16f4c82c568..558a485d03ab 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -435,4 +435,12 @@
 #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS                 (0x1 << 1)
 #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK                 (0x1 << 1)
 
+/* For imx6ul iomux gpr register field define */
+#define IMX6UL_GPR1_ENET1_CLK_DIR               (0x1 << 17)
+#define IMX6UL_GPR1_ENET2_CLK_DIR               (0x1 << 18)
+#define IMX6UL_GPR1_ENET1_CLK_OUTPUT            (0x1 << 17)
+#define IMX6UL_GPR1_ENET2_CLK_OUTPUT            (0x1 << 18)
+#define IMX6UL_GPR1_ENET_CLK_DIR                (0x3 << 17)
+#define IMX6UL_GPR1_ENET_CLK_OUTPUT             (0x3 << 17)
+
 #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
new file mode 100644
index 000000000000..a5714e93fb34
--- /dev/null
+++ b/include/linux/soc/mediatek/infracfg.h
@@ -0,0 +1,26 @@
+#ifndef __SOC_MEDIATEK_INFRACFG_H
+#define __SOC_MEDIATEK_INFRACFG_H
+
+#define MT8173_TOP_AXI_PROT_EN_MCI_M2           BIT(0)
+#define MT8173_TOP_AXI_PROT_EN_MM_M0            BIT(1)
+#define MT8173_TOP_AXI_PROT_EN_MM_M1            BIT(2)
+#define MT8173_TOP_AXI_PROT_EN_MMAPB_S          BIT(6)
+#define MT8173_TOP_AXI_PROT_EN_L2C_M2           BIT(9)
+#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI         BIT(11)
+#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD         BIT(12)
+#define MT8173_TOP_AXI_PROT_EN_CCI_M2           BIT(13)
+#define MT8173_TOP_AXI_PROT_EN_MFG_S            BIT(14)
+#define MT8173_TOP_AXI_PROT_EN_PERI_M0          BIT(15)
+#define MT8173_TOP_AXI_PROT_EN_PERI_M1          BIT(16)
+#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS         BIT(17)
+#define MT8173_TOP_AXI_PROT_EN_CQ_DMA           BIT(18)
+#define MT8173_TOP_AXI_PROT_EN_GCPU             BIT(19)
+#define MT8173_TOP_AXI_PROT_EN_IOMMU            BIT(20)
+#define MT8173_TOP_AXI_PROT_EN_MFG_M0           BIT(21)
+#define MT8173_TOP_AXI_PROT_EN_MFG_M1           BIT(22)
+#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT    BIT(23)
+
+int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask);
+int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask);
+
+#endif /* __SOC_MEDIATEK_INFRACFG_H */