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-rw-r--r--include/linux/mfd/88pm860x.h3
-rw-r--r--include/linux/mfd/abx500/ab5500.h (renamed from include/linux/mfd/ab5500/ab5500.h)0
-rw-r--r--include/linux/mfd/abx500/ab8500-gpadc.h (renamed from include/linux/mfd/ab8500/gpadc.h)0
-rw-r--r--include/linux/mfd/abx500/ab8500-gpio.h (renamed from include/linux/mfd/ab8500/gpio.h)0
-rw-r--r--include/linux/mfd/abx500/ab8500-sysctrl.h (renamed from include/linux/mfd/ab8500/sysctrl.h)0
-rw-r--r--include/linux/mfd/abx500/ab8500.h (renamed from include/linux/mfd/ab8500.h)0
-rw-r--r--include/linux/mfd/da9052/da9052.h131
-rw-r--r--include/linux/mfd/da9052/pdata.h40
-rw-r--r--include/linux/mfd/da9052/reg.h749
-rw-r--r--include/linux/mfd/max8925.h9
-rw-r--r--include/linux/mfd/max8997.h83
-rw-r--r--include/linux/mfd/mc13xxx.h9
-rw-r--r--include/linux/mfd/mcp.h7
-rw-r--r--include/linux/mfd/s5m87xx/s5m-core.h373
-rw-r--r--include/linux/mfd/s5m87xx/s5m-pmic.h100
-rw-r--r--include/linux/mfd/s5m87xx/s5m-rtc.h84
-rw-r--r--include/linux/mfd/stmpe.h16
-rw-r--r--include/linux/mfd/tps65910.h30
-rw-r--r--include/linux/mfd/ucb1x00.h5
-rw-r--r--include/linux/mfd/wm8994/core.h7
-rw-r--r--include/linux/mfd/wm8994/pdata.h31
-rw-r--r--include/linux/mfd/wm8994/registers.h112
22 files changed, 1772 insertions, 17 deletions
diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h
index 63b4fb8e3b6f..92be3476c9f5 100644
--- a/include/linux/mfd/88pm860x.h
+++ b/include/linux/mfd/88pm860x.h
@@ -297,10 +297,11 @@ enum {
297 297
298struct pm860x_chip { 298struct pm860x_chip {
299 struct device *dev; 299 struct device *dev;
300 struct mutex io_lock;
301 struct mutex irq_lock; 300 struct mutex irq_lock;
302 struct i2c_client *client; 301 struct i2c_client *client;
303 struct i2c_client *companion; /* companion chip client */ 302 struct i2c_client *companion; /* companion chip client */
303 struct regmap *regmap;
304 struct regmap *regmap_companion;
304 305
305 int buck3_double; /* DVC ramp slope double */ 306 int buck3_double; /* DVC ramp slope double */
306 unsigned short companion_addr; 307 unsigned short companion_addr;
diff --git a/include/linux/mfd/ab5500/ab5500.h b/include/linux/mfd/abx500/ab5500.h
index a720051ae933..a720051ae933 100644
--- a/include/linux/mfd/ab5500/ab5500.h
+++ b/include/linux/mfd/abx500/ab5500.h
diff --git a/include/linux/mfd/ab8500/gpadc.h b/include/linux/mfd/abx500/ab8500-gpadc.h
index 252966769d93..252966769d93 100644
--- a/include/linux/mfd/ab8500/gpadc.h
+++ b/include/linux/mfd/abx500/ab8500-gpadc.h
diff --git a/include/linux/mfd/ab8500/gpio.h b/include/linux/mfd/abx500/ab8500-gpio.h
index 488a8c920a29..488a8c920a29 100644
--- a/include/linux/mfd/ab8500/gpio.h
+++ b/include/linux/mfd/abx500/ab8500-gpio.h
diff --git a/include/linux/mfd/ab8500/sysctrl.h b/include/linux/mfd/abx500/ab8500-sysctrl.h
index 10da0291f8f8..10da0291f8f8 100644
--- a/include/linux/mfd/ab8500/sysctrl.h
+++ b/include/linux/mfd/abx500/ab8500-sysctrl.h
diff --git a/include/linux/mfd/ab8500.h b/include/linux/mfd/abx500/ab8500.h
index 838c6b487cc5..838c6b487cc5 100644
--- a/include/linux/mfd/ab8500.h
+++ b/include/linux/mfd/abx500/ab8500.h
diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h
new file mode 100644
index 000000000000..5702d1be13b4
--- /dev/null
+++ b/include/linux/mfd/da9052/da9052.h
@@ -0,0 +1,131 @@
1/*
2 * da9052 declarations for DA9052 PMICs.
3 *
4 * Copyright(c) 2011 Dialog Semiconductor Ltd.
5 *
6 * Author: David Dajun Chen <dchen@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24#ifndef __MFD_DA9052_DA9052_H
25#define __MFD_DA9052_DA9052_H
26
27#include <linux/interrupt.h>
28#include <linux/regmap.h>
29#include <linux/slab.h>
30#include <linux/completion.h>
31#include <linux/list.h>
32#include <linux/mfd/core.h>
33
34#include <linux/mfd/da9052/reg.h>
35
36#define DA9052_IRQ_DCIN 0
37#define DA9052_IRQ_VBUS 1
38#define DA9052_IRQ_DCINREM 2
39#define DA9052_IRQ_VBUSREM 3
40#define DA9052_IRQ_VDDLOW 4
41#define DA9052_IRQ_ALARM 5
42#define DA9052_IRQ_SEQRDY 6
43#define DA9052_IRQ_COMP1V2 7
44#define DA9052_IRQ_NONKEY 8
45#define DA9052_IRQ_IDFLOAT 9
46#define DA9052_IRQ_IDGND 10
47#define DA9052_IRQ_CHGEND 11
48#define DA9052_IRQ_TBAT 12
49#define DA9052_IRQ_ADC_EOM 13
50#define DA9052_IRQ_PENDOWN 14
51#define DA9052_IRQ_TSIREADY 15
52#define DA9052_IRQ_GPI0 16
53#define DA9052_IRQ_GPI1 17
54#define DA9052_IRQ_GPI2 18
55#define DA9052_IRQ_GPI3 19
56#define DA9052_IRQ_GPI4 20
57#define DA9052_IRQ_GPI5 21
58#define DA9052_IRQ_GPI6 22
59#define DA9052_IRQ_GPI7 23
60#define DA9052_IRQ_GPI8 24
61#define DA9052_IRQ_GPI9 25
62#define DA9052_IRQ_GPI10 26
63#define DA9052_IRQ_GPI11 27
64#define DA9052_IRQ_GPI12 28
65#define DA9052_IRQ_GPI13 29
66#define DA9052_IRQ_GPI14 30
67#define DA9052_IRQ_GPI15 31
68
69enum da9052_chip_id {
70 DA9052,
71 DA9053_AA,
72 DA9053_BA,
73 DA9053_BB,
74};
75
76struct da9052_pdata;
77
78struct da9052 {
79 struct mutex io_lock;
80
81 struct device *dev;
82 struct regmap *regmap;
83
84 int irq_base;
85 u8 chip_id;
86
87 int chip_irq;
88};
89
90/* Device I/O API */
91static inline int da9052_reg_read(struct da9052 *da9052, unsigned char reg)
92{
93 int val, ret;
94
95 ret = regmap_read(da9052->regmap, reg, &val);
96 if (ret < 0)
97 return ret;
98 return val;
99}
100
101static inline int da9052_reg_write(struct da9052 *da9052, unsigned char reg,
102 unsigned char val)
103{
104 return regmap_write(da9052->regmap, reg, val);
105}
106
107static inline int da9052_group_read(struct da9052 *da9052, unsigned char reg,
108 unsigned reg_cnt, unsigned char *val)
109{
110 return regmap_bulk_read(da9052->regmap, reg, val, reg_cnt);
111}
112
113static inline int da9052_group_write(struct da9052 *da9052, unsigned char reg,
114 unsigned reg_cnt, unsigned char *val)
115{
116 return regmap_raw_write(da9052->regmap, reg, val, reg_cnt);
117}
118
119static inline int da9052_reg_update(struct da9052 *da9052, unsigned char reg,
120 unsigned char bit_mask,
121 unsigned char reg_val)
122{
123 return regmap_update_bits(da9052->regmap, reg, bit_mask, reg_val);
124}
125
126int da9052_device_init(struct da9052 *da9052, u8 chip_id);
127void da9052_device_exit(struct da9052 *da9052);
128
129extern struct regmap_config da9052_regmap_config;
130
131#endif /* __MFD_DA9052_DA9052_H */
diff --git a/include/linux/mfd/da9052/pdata.h b/include/linux/mfd/da9052/pdata.h
new file mode 100644
index 000000000000..62c5c3c2992e
--- /dev/null
+++ b/include/linux/mfd/da9052/pdata.h
@@ -0,0 +1,40 @@
1/*
2 * Platform data declarations for DA9052 PMICs.
3 *
4 * Copyright(c) 2011 Dialog Semiconductor Ltd.
5 *
6 * Author: David Dajun Chen <dchen@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24#ifndef __MFD_DA9052_PDATA_H__
25#define __MFD_DA9052_PDATA_H__
26
27#define DA9052_MAX_REGULATORS 14
28
29struct da9052;
30
31struct da9052_pdata {
32 struct led_platform_data *pled;
33 int (*init) (struct da9052 *da9052);
34 int irq_base;
35 int gpio_base;
36 int use_for_apm;
37 struct regulator_init_data *regulators[DA9052_MAX_REGULATORS];
38};
39
40#endif
diff --git a/include/linux/mfd/da9052/reg.h b/include/linux/mfd/da9052/reg.h
new file mode 100644
index 000000000000..b97f7309d7f6
--- /dev/null
+++ b/include/linux/mfd/da9052/reg.h
@@ -0,0 +1,749 @@
1/*
2 * Register declarations for DA9052 PMICs.
3 *
4 * Copyright(c) 2011 Dialog Semiconductor Ltd.
5 *
6 * Author: David Dajun Chen <dchen@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24#ifndef __LINUX_MFD_DA9052_REG_H
25#define __LINUX_MFD_DA9052_REG_H
26
27/* PAGE REGISTERS */
28#define DA9052_PAGE0_CON_REG 0
29#define DA9052_PAGE1_CON_REG 128
30
31/* STATUS REGISTERS */
32#define DA9052_STATUS_A_REG 1
33#define DA9052_STATUS_B_REG 2
34#define DA9052_STATUS_C_REG 3
35#define DA9052_STATUS_D_REG 4
36
37/* EVENT REGISTERS */
38#define DA9052_EVENT_A_REG 5
39#define DA9052_EVENT_B_REG 6
40#define DA9052_EVENT_C_REG 7
41#define DA9052_EVENT_D_REG 8
42#define DA9052_FAULTLOG_REG 9
43
44/* IRQ REGISTERS */
45#define DA9052_IRQ_MASK_A_REG 10
46#define DA9052_IRQ_MASK_B_REG 11
47#define DA9052_IRQ_MASK_C_REG 12
48#define DA9052_IRQ_MASK_D_REG 13
49
50/* CONTROL REGISTERS */
51#define DA9052_CONTROL_A_REG 14
52#define DA9052_CONTROL_B_REG 15
53#define DA9052_CONTROL_C_REG 16
54#define DA9052_CONTROL_D_REG 17
55
56#define DA9052_PDDIS_REG 18
57#define DA9052_INTERFACE_REG 19
58#define DA9052_RESET_REG 20
59
60/* GPIO REGISTERS */
61#define DA9052_GPIO_0_1_REG 21
62#define DA9052_GPIO_2_3_REG 22
63#define DA9052_GPIO_4_5_REG 23
64#define DA9052_GPIO_6_7_REG 24
65#define DA9052_GPIO_14_15_REG 28
66
67/* POWER SEQUENCER CONTROL REGISTERS */
68#define DA9052_ID_0_1_REG 29
69#define DA9052_ID_2_3_REG 30
70#define DA9052_ID_4_5_REG 31
71#define DA9052_ID_6_7_REG 32
72#define DA9052_ID_8_9_REG 33
73#define DA9052_ID_10_11_REG 34
74#define DA9052_ID_12_13_REG 35
75#define DA9052_ID_14_15_REG 36
76#define DA9052_ID_16_17_REG 37
77#define DA9052_ID_18_19_REG 38
78#define DA9052_ID_20_21_REG 39
79#define DA9052_SEQ_STATUS_REG 40
80#define DA9052_SEQ_A_REG 41
81#define DA9052_SEQ_B_REG 42
82#define DA9052_SEQ_TIMER_REG 43
83
84/* LDO AND BUCK REGISTERS */
85#define DA9052_BUCKA_REG 44
86#define DA9052_BUCKB_REG 45
87#define DA9052_BUCKCORE_REG 46
88#define DA9052_BUCKPRO_REG 47
89#define DA9052_BUCKMEM_REG 48
90#define DA9052_BUCKPERI_REG 49
91#define DA9052_LDO1_REG 50
92#define DA9052_LDO2_REG 51
93#define DA9052_LDO3_REG 52
94#define DA9052_LDO4_REG 53
95#define DA9052_LDO5_REG 54
96#define DA9052_LDO6_REG 55
97#define DA9052_LDO7_REG 56
98#define DA9052_LDO8_REG 57
99#define DA9052_LDO9_REG 58
100#define DA9052_LDO10_REG 59
101#define DA9052_SUPPLY_REG 60
102#define DA9052_PULLDOWN_REG 61
103#define DA9052_CHGBUCK_REG 62
104#define DA9052_WAITCONT_REG 63
105#define DA9052_ISET_REG 64
106#define DA9052_BATCHG_REG 65
107
108/* BATTERY CONTROL REGISTRS */
109#define DA9052_CHG_CONT_REG 66
110#define DA9052_INPUT_CONT_REG 67
111#define DA9052_CHG_TIME_REG 68
112#define DA9052_BBAT_CONT_REG 69
113
114/* LED CONTROL REGISTERS */
115#define DA9052_BOOST_REG 70
116#define DA9052_LED_CONT_REG 71
117#define DA9052_LEDMIN123_REG 72
118#define DA9052_LED1_CONF_REG 73
119#define DA9052_LED2_CONF_REG 74
120#define DA9052_LED3_CONF_REG 75
121#define DA9052_LED1CONT_REG 76
122#define DA9052_LED2CONT_REG 77
123#define DA9052_LED3CONT_REG 78
124#define DA9052_LED_CONT_4_REG 79
125#define DA9052_LED_CONT_5_REG 80
126
127/* ADC CONTROL REGISTERS */
128#define DA9052_ADC_MAN_REG 81
129#define DA9052_ADC_CONT_REG 82
130#define DA9052_ADC_RES_L_REG 83
131#define DA9052_ADC_RES_H_REG 84
132#define DA9052_VDD_RES_REG 85
133#define DA9052_VDD_MON_REG 86
134
135#define DA9052_ICHG_AV_REG 87
136#define DA9052_ICHG_THD_REG 88
137#define DA9052_ICHG_END_REG 89
138#define DA9052_TBAT_RES_REG 90
139#define DA9052_TBAT_HIGHP_REG 91
140#define DA9052_TBAT_HIGHN_REG 92
141#define DA9052_TBAT_LOW_REG 93
142#define DA9052_T_OFFSET_REG 94
143
144#define DA9052_ADCIN4_RES_REG 95
145#define DA9052_AUTO4_HIGH_REG 96
146#define DA9052_AUTO4_LOW_REG 97
147#define DA9052_ADCIN5_RES_REG 98
148#define DA9052_AUTO5_HIGH_REG 99
149#define DA9052_AUTO5_LOW_REG 100
150#define DA9052_ADCIN6_RES_REG 101
151#define DA9052_AUTO6_HIGH_REG 102
152#define DA9052_AUTO6_LOW_REG 103
153
154#define DA9052_TJUNC_RES_REG 104
155
156/* TSI CONTROL REGISTERS */
157#define DA9052_TSI_CONT_A_REG 105
158#define DA9052_TSI_CONT_B_REG 106
159#define DA9052_TSI_X_MSB_REG 107
160#define DA9052_TSI_Y_MSB_REG 108
161#define DA9052_TSI_LSB_REG 109
162#define DA9052_TSI_Z_MSB_REG 110
163
164/* RTC COUNT REGISTERS */
165#define DA9052_COUNT_S_REG 111
166#define DA9052_COUNT_MI_REG 112
167#define DA9052_COUNT_H_REG 113
168#define DA9052_COUNT_D_REG 114
169#define DA9052_COUNT_MO_REG 115
170#define DA9052_COUNT_Y_REG 116
171
172/* RTC CONTROL REGISTERS */
173#define DA9052_ALARM_MI_REG 117
174#define DA9052_ALARM_H_REG 118
175#define DA9052_ALARM_D_REG 119
176#define DA9052_ALARM_MO_REG 120
177#define DA9052_ALARM_Y_REG 121
178#define DA9052_SECOND_A_REG 122
179#define DA9052_SECOND_B_REG 123
180#define DA9052_SECOND_C_REG 124
181#define DA9052_SECOND_D_REG 125
182
183/* PAGE CONFIGURATION BIT */
184#define DA9052_PAGE_CONF 0X80
185
186/* STATUS REGISTER A BITS */
187#define DA9052_STATUSA_VDATDET 0X80
188#define DA9052_STATUSA_VBUSSEL 0X40
189#define DA9052_STATUSA_DCINSEL 0X20
190#define DA9052_STATUSA_VBUSDET 0X10
191#define DA9052_STATUSA_DCINDET 0X08
192#define DA9052_STATUSA_IDGND 0X04
193#define DA9052_STATUSA_IDFLOAT 0X02
194#define DA9052_STATUSA_NONKEY 0X01
195
196/* STATUS REGISTER B BITS */
197#define DA9052_STATUSB_COMPDET 0X80
198#define DA9052_STATUSB_SEQUENCING 0X40
199#define DA9052_STATUSB_GPFB2 0X20
200#define DA9052_STATUSB_CHGTO 0X10
201#define DA9052_STATUSB_CHGEND 0X08
202#define DA9052_STATUSB_CHGLIM 0X04
203#define DA9052_STATUSB_CHGPRE 0X02
204#define DA9052_STATUSB_CHGATT 0X01
205
206/* STATUS REGISTER C BITS */
207#define DA9052_STATUSC_GPI7 0X80
208#define DA9052_STATUSC_GPI6 0X40
209#define DA9052_STATUSC_GPI5 0X20
210#define DA9052_STATUSC_GPI4 0X10
211#define DA9052_STATUSC_GPI3 0X08
212#define DA9052_STATUSC_GPI2 0X04
213#define DA9052_STATUSC_GPI1 0X02
214#define DA9052_STATUSC_GPI0 0X01
215
216/* STATUS REGISTER D BITS */
217#define DA9052_STATUSD_GPI15 0X80
218#define DA9052_STATUSD_GPI14 0X40
219#define DA9052_STATUSD_GPI13 0X20
220#define DA9052_STATUSD_GPI12 0X10
221#define DA9052_STATUSD_GPI11 0X08
222#define DA9052_STATUSD_GPI10 0X04
223#define DA9052_STATUSD_GPI9 0X02
224#define DA9052_STATUSD_GPI8 0X01
225
226/* EVENT REGISTER A BITS */
227#define DA9052_EVENTA_ECOMP1V2 0X80
228#define DA9052_EVENTA_ESEQRDY 0X40
229#define DA9052_EVENTA_EALRAM 0X20
230#define DA9052_EVENTA_EVDDLOW 0X10
231#define DA9052_EVENTA_EVBUSREM 0X08
232#define DA9052_EVENTA_EDCINREM 0X04
233#define DA9052_EVENTA_EVBUSDET 0X02
234#define DA9052_EVENTA_EDCINDET 0X01
235
236/* EVENT REGISTER B BITS */
237#define DA9052_EVENTB_ETSIREADY 0X80
238#define DA9052_EVENTB_EPENDOWN 0X40
239#define DA9052_EVENTB_EADCEOM 0X20
240#define DA9052_EVENTB_ETBAT 0X10
241#define DA9052_EVENTB_ECHGEND 0X08
242#define DA9052_EVENTB_EIDGND 0X04
243#define DA9052_EVENTB_EIDFLOAT 0X02
244#define DA9052_EVENTB_ENONKEY 0X01
245
246/* EVENT REGISTER C BITS */
247#define DA9052_EVENTC_EGPI7 0X80
248#define DA9052_EVENTC_EGPI6 0X40
249#define DA9052_EVENTC_EGPI5 0X20
250#define DA9052_EVENTC_EGPI4 0X10
251#define DA9052_EVENTC_EGPI3 0X08
252#define DA9052_EVENTC_EGPI2 0X04
253#define DA9052_EVENTC_EGPI1 0X02
254#define DA9052_EVENTC_EGPI0 0X01
255
256/* EVENT REGISTER D BITS */
257#define DA9052_EVENTD_EGPI15 0X80
258#define DA9052_EVENTD_EGPI14 0X40
259#define DA9052_EVENTD_EGPI13 0X20
260#define DA9052_EVENTD_EGPI12 0X10
261#define DA9052_EVENTD_EGPI11 0X08
262#define DA9052_EVENTD_EGPI10 0X04
263#define DA9052_EVENTD_EGPI9 0X02
264#define DA9052_EVENTD_EGPI8 0X01
265
266/* IRQ MASK REGISTERS BITS */
267#define DA9052_M_NONKEY 0X0100
268
269/* TSI EVENT REGISTERS BITS */
270#define DA9052_E_PEN_DOWN 0X4000
271#define DA9052_E_TSI_READY 0X8000
272
273/* FAULT LOG REGISTER BITS */
274#define DA9052_FAULTLOG_WAITSET 0X80
275#define DA9052_FAULTLOG_NSDSET 0X40
276#define DA9052_FAULTLOG_KEYSHUT 0X20
277#define DA9052_FAULTLOG_TEMPOVER 0X08
278#define DA9052_FAULTLOG_VDDSTART 0X04
279#define DA9052_FAULTLOG_VDDFAULT 0X02
280#define DA9052_FAULTLOG_TWDERROR 0X01
281
282/* CONTROL REGISTER A BITS */
283#define DA9052_CONTROLA_GPIV 0X80
284#define DA9052_CONTROLA_PMOTYPE 0X20
285#define DA9052_CONTROLA_PMOV 0X10
286#define DA9052_CONTROLA_PMIV 0X08
287#define DA9052_CONTROLA_PMIFV 0X08
288#define DA9052_CONTROLA_PWR1EN 0X04
289#define DA9052_CONTROLA_PWREN 0X02
290#define DA9052_CONTROLA_SYSEN 0X01
291
292/* CONTROL REGISTER B BITS */
293#define DA9052_CONTROLB_SHUTDOWN 0X80
294#define DA9052_CONTROLB_DEEPSLEEP 0X40
295#define DA9052_CONTROL_B_WRITEMODE 0X20
296#define DA9052_CONTROLB_BBATEN 0X10
297#define DA9052_CONTROLB_OTPREADEN 0X08
298#define DA9052_CONTROLB_AUTOBOOT 0X04
299#define DA9052_CONTROLB_ACTDIODE 0X02
300#define DA9052_CONTROLB_BUCKMERGE 0X01
301
302/* CONTROL REGISTER C BITS */
303#define DA9052_CONTROLC_BLINKDUR 0X80
304#define DA9052_CONTROLC_BLINKFRQ 0X60
305#define DA9052_CONTROLC_DEBOUNCING 0X1C
306#define DA9052_CONTROLC_PMFB2PIN 0X02
307#define DA9052_CONTROLC_PMFB1PIN 0X01
308
309/* CONTROL REGISTER D BITS */
310#define DA9052_CONTROLD_WATCHDOG 0X80
311#define DA9052_CONTROLD_ACCDETEN 0X40
312#define DA9052_CONTROLD_GPI1415SD 0X20
313#define DA9052_CONTROLD_NONKEYSD 0X10
314#define DA9052_CONTROLD_KEEPACTEN 0X08
315#define DA9052_CONTROLD_TWDSCALE 0X07
316
317/* POWER DOWN DISABLE REGISTER BITS */
318#define DA9052_PDDIS_PMCONTPD 0X80
319#define DA9052_PDDIS_OUT32KPD 0X40
320#define DA9052_PDDIS_CHGBBATPD 0X20
321#define DA9052_PDDIS_CHGPD 0X10
322#define DA9052_PDDIS_HS2WIREPD 0X08
323#define DA9052_PDDIS_PMIFPD 0X04
324#define DA9052_PDDIS_GPADCPD 0X02
325#define DA9052_PDDIS_GPIOPD 0X01
326
327/* CONTROL REGISTER D BITS */
328#define DA9052_INTERFACE_IFBASEADDR 0XE0
329#define DA9052_INTERFACE_NCSPOL 0X10
330#define DA9052_INTERFACE_RWPOL 0X08
331#define DA9052_INTERFACE_CPHA 0X04
332#define DA9052_INTERFACE_CPOL 0X02
333#define DA9052_INTERFACE_IFTYPE 0X01
334
335/* CONTROL REGISTER D BITS */
336#define DA9052_RESET_RESETEVENT 0XC0
337#define DA9052_RESET_RESETTIMER 0X3F
338
339/* GPIO REGISTERS */
340/* GPIO CONTROL REGISTER BITS */
341#define DA9052_GPIO_EVEN_PORT_PIN 0X03
342#define DA9052_GPIO_EVEN_PORT_TYPE 0X04
343#define DA9052_GPIO_EVEN_PORT_MODE 0X08
344
345#define DA9052_GPIO_ODD_PORT_PIN 0X30
346#define DA9052_GPIO_ODD_PORT_TYPE 0X40
347#define DA9052_GPIO_ODD_PORT_MODE 0X80
348
349/*POWER SEQUENCER REGISTER BITS */
350/* SEQ CONTROL REGISTER BITS FOR ID 0 AND 1 */
351#define DA9052_ID01_LDO1STEP 0XF0
352#define DA9052_ID01_SYSPRE 0X04
353#define DA9052_ID01_DEFSUPPLY 0X02
354#define DA9052_ID01_NRESMODE 0X01
355
356/* SEQ CONTROL REGISTER BITS FOR ID 2 AND 3 */
357#define DA9052_ID23_LDO3STEP 0XF0
358#define DA9052_ID23_LDO2STEP 0X0F
359
360/* SEQ CONTROL REGISTER BITS FOR ID 4 AND 5 */
361#define DA9052_ID45_LDO5STEP 0XF0
362#define DA9052_ID45_LDO4STEP 0X0F
363
364/* SEQ CONTROL REGISTER BITS FOR ID 6 AND 7 */
365#define DA9052_ID67_LDO7STEP 0XF0
366#define DA9052_ID67_LDO6STEP 0X0F
367
368/* SEQ CONTROL REGISTER BITS FOR ID 8 AND 9 */
369#define DA9052_ID89_LDO9STEP 0XF0
370#define DA9052_ID89_LDO8STEP 0X0F
371
372/* SEQ CONTROL REGISTER BITS FOR ID 10 AND 11 */
373#define DA9052_ID1011_PDDISSTEP 0XF0
374#define DA9052_ID1011_LDO10STEP 0X0F
375
376/* SEQ CONTROL REGISTER BITS FOR ID 12 AND 13 */
377#define DA9052_ID1213_VMEMSWSTEP 0XF0
378#define DA9052_ID1213_VPERISWSTEP 0X0F
379
380/* SEQ CONTROL REGISTER BITS FOR ID 14 AND 15 */
381#define DA9052_ID1415_BUCKPROSTEP 0XF0
382#define DA9052_ID1415_BUCKCORESTEP 0X0F
383
384/* SEQ CONTROL REGISTER BITS FOR ID 16 AND 17 */
385#define DA9052_ID1617_BUCKPERISTEP 0XF0
386#define DA9052_ID1617_BUCKMEMSTEP 0X0F
387
388/* SEQ CONTROL REGISTER BITS FOR ID 18 AND 19 */
389#define DA9052_ID1819_GPRISE2STEP 0XF0
390#define DA9052_ID1819_GPRISE1STEP 0X0F
391
392/* SEQ CONTROL REGISTER BITS FOR ID 20 AND 21 */
393#define DA9052_ID2021_GPFALL2STEP 0XF0
394#define DA9052_ID2021_GPFALL1STEP 0X0F
395
396/* POWER SEQ STATUS REGISTER BITS */
397#define DA9052_SEQSTATUS_SEQPOINTER 0XF0
398#define DA9052_SEQSTATUS_WAITSTEP 0X0F
399
400/* POWER SEQ A REGISTER BITS */
401#define DA9052_SEQA_POWEREND 0XF0
402#define DA9052_SEQA_SYSTEMEND 0X0F
403
404/* POWER SEQ B REGISTER BITS */
405#define DA9052_SEQB_PARTDOWN 0XF0
406#define DA9052_SEQB_MAXCOUNT 0X0F
407
408/* POWER SEQ TIMER REGISTER BITS */
409#define DA9052_SEQTIMER_SEQDUMMY 0XF0
410#define DA9052_SEQTIMER_SEQTIME 0X0F
411
412/*POWER SUPPLY CONTROL REGISTER BITS */
413/* BUCK REGISTER A BITS */
414#define DA9052_BUCKA_BPROILIM 0XC0
415#define DA9052_BUCKA_BPROMODE 0X30
416#define DA9052_BUCKA_BCOREILIM 0X0C
417#define DA9052_BUCKA_BCOREMODE 0X03
418
419/* BUCK REGISTER B BITS */
420#define DA9052_BUCKB_BERIILIM 0XC0
421#define DA9052_BUCKB_BPERIMODE 0X30
422#define DA9052_BUCKB_BMEMILIM 0X0C
423#define DA9052_BUCKB_BMEMMODE 0X03
424
425/* BUCKCORE REGISTER BITS */
426#define DA9052_BUCKCORE_BCORECONF 0X80
427#define DA9052_BUCKCORE_BCOREEN 0X40
428#define DA9052_BUCKCORE_VBCORE 0X3F
429
430/* BUCKPRO REGISTER BITS */
431#define DA9052_BUCKPRO_BPROCONF 0X80
432#define DA9052_BUCKPRO_BPROEN 0X40
433#define DA9052_BUCKPRO_VBPRO 0X3F
434
435/* BUCKMEM REGISTER BITS */
436#define DA9052_BUCKMEM_BMEMCONF 0X80
437#define DA9052_BUCKMEM_BMEMEN 0X40
438#define DA9052_BUCKMEM_VBMEM 0X3F
439
440/* BUCKPERI REGISTER BITS */
441#define DA9052_BUCKPERI_BPERICONF 0X80
442#define DA9052_BUCKPERI_BPERIEN 0X40
443#define DA9052_BUCKPERI_BPERIHS 0X20
444#define DA9052_BUCKPERI_VBPERI 0X1F
445
446/* LDO1 REGISTER BITS */
447#define DA9052_LDO1_LDO1CONF 0X80
448#define DA9052_LDO1_LDO1EN 0X40
449#define DA9052_LDO1_VLDO1 0X1F
450
451/* LDO2 REGISTER BITS */
452#define DA9052_LDO2_LDO2CONF 0X80
453#define DA9052_LDO2_LDO2EN 0X40
454#define DA9052_LDO2_VLDO2 0X3F
455
456/* LDO3 REGISTER BITS */
457#define DA9052_LDO3_LDO3CONF 0X80
458#define DA9052_LDO3_LDO3EN 0X40
459#define DA9052_LDO3_VLDO3 0X3F
460
461/* LDO4 REGISTER BITS */
462#define DA9052_LDO4_LDO4CONF 0X80
463#define DA9052_LDO4_LDO4EN 0X40
464#define DA9052_LDO4_VLDO4 0X3F
465
466/* LDO5 REGISTER BITS */
467#define DA9052_LDO5_LDO5CONF 0X80
468#define DA9052_LDO5_LDO5EN 0X40
469#define DA9052_LDO5_VLDO5 0X3F
470
471/* LDO6 REGISTER BITS */
472#define DA9052_LDO6_LDO6CONF 0X80
473#define DA9052_LDO6_LDO6EN 0X40
474#define DA9052_LDO6_VLDO6 0X3F
475
476/* LDO7 REGISTER BITS */
477#define DA9052_LDO7_LDO7CONF 0X80
478#define DA9052_LDO7_LDO7EN 0X40
479#define DA9052_LDO7_VLDO7 0X3F
480
481/* LDO8 REGISTER BITS */
482#define DA9052_LDO8_LDO8CONF 0X80
483#define DA9052_LDO8_LDO8EN 0X40
484#define DA9052_LDO8_VLDO8 0X3F
485
486/* LDO9 REGISTER BITS */
487#define DA9052_LDO9_LDO9CONF 0X80
488#define DA9052_LDO9_LDO9EN 0X40
489#define DA9052_LDO9_VLDO9 0X3F
490
491/* LDO10 REGISTER BITS */
492#define DA9052_LDO10_LDO10CONF 0X80
493#define DA9052_LDO10_LDO10EN 0X40
494#define DA9052_LDO10_VLDO10 0X3F
495
496/* SUPPLY REGISTER BITS */
497#define DA9052_SUPPLY_VLOCK 0X80
498#define DA9052_SUPPLY_VMEMSWEN 0X40
499#define DA9052_SUPPLY_VPERISWEN 0X20
500#define DA9052_SUPPLY_VLDO3GO 0X10
501#define DA9052_SUPPLY_VLDO2GO 0X08
502#define DA9052_SUPPLY_VBMEMGO 0X04
503#define DA9052_SUPPLY_VBPROGO 0X02
504#define DA9052_SUPPLY_VBCOREGO 0X01
505
506/* PULLDOWN REGISTER BITS */
507#define DA9052_PULLDOWN_LDO5PDDIS 0X20
508#define DA9052_PULLDOWN_LDO2PDDIS 0X10
509#define DA9052_PULLDOWN_LDO1PDDIS 0X08
510#define DA9052_PULLDOWN_MEMPDDIS 0X04
511#define DA9052_PULLDOWN_PROPDDIS 0X02
512#define DA9052_PULLDOWN_COREPDDIS 0X01
513
514/* BAT CHARGER REGISTER BITS */
515/* CHARGER BUCK REGISTER BITS */
516#define DA9052_CHGBUCK_CHGTEMP 0X80
517#define DA9052_CHGBUCK_CHGUSBILIM 0X40
518#define DA9052_CHGBUCK_CHGBUCKLP 0X20
519#define DA9052_CHGBUCK_CHGBUCKEN 0X10
520#define DA9052_CHGBUCK_ISETBUCK 0X0F
521
522/* WAIT COUNTER REGISTER BITS */
523#define DA9052_WAITCONT_WAITDIR 0X80
524#define DA9052_WAITCONT_RTCCLOCK 0X40
525#define DA9052_WAITCONT_WAITMODE 0X20
526#define DA9052_WAITCONT_EN32KOUT 0X10
527#define DA9052_WAITCONT_DELAYTIME 0X0F
528
529/* ISET CONTROL REGISTER BITS */
530#define DA9052_ISET_ISETDCIN 0XF0
531#define DA9052_ISET_ISETVBUS 0X0F
532
533/* BATTERY CHARGER CONTROL REGISTER BITS */
534#define DA9052_BATCHG_ICHGPRE 0XC0
535#define DA9052_BATCHG_ICHGBAT 0X3F
536
537/* CHARGER COUNTER REGISTER BITS */
538#define DA9052_CHG_CONT_VCHG_BAT 0XF8
539#define DA9052_CHG_CONT_TCTR 0X07
540
541/* INPUT CONTROL REGISTER BITS */
542#define DA9052_INPUT_CONT_TCTR_MODE 0X80
543#define DA9052_INPUT_CONT_VBUS_SUSP 0X10
544#define DA9052_INPUT_CONT_DCIN_SUSP 0X08
545
546/* CHARGING TIME REGISTER BITS */
547#define DA9052_CHGTIME_CHGTIME 0XFF
548
549/* BACKUP BATTERY CONTROL REGISTER BITS */
550#define DA9052_BBATCONT_BCHARGERISET 0XF0
551#define DA9052_BBATCONT_BCHARGERVSET 0X0F
552
553/* LED REGISTERS BITS */
554/* LED BOOST REGISTER BITS */
555#define DA9052_BOOST_EBFAULT 0X80
556#define DA9052_BOOST_MBFAULT 0X40
557#define DA9052_BOOST_BOOSTFRQ 0X20
558#define DA9052_BOOST_BOOSTILIM 0X10
559#define DA9052_BOOST_LED3INEN 0X08
560#define DA9052_BOOST_LED2INEN 0X04
561#define DA9052_BOOST_LED1INEN 0X02
562#define DA9052_BOOST_BOOSTEN 0X01
563
564/* LED CONTROL REGISTER BITS */
565#define DA9052_LEDCONT_SELLEDMODE 0X80
566#define DA9052_LEDCONT_LED3ICONT 0X40
567#define DA9052_LEDCONT_LED3RAMP 0X20
568#define DA9052_LEDCONT_LED3EN 0X10
569#define DA9052_LEDCONT_LED2RAMP 0X08
570#define DA9052_LEDCONT_LED2EN 0X04
571#define DA9052_LEDCONT_LED1RAMP 0X02
572#define DA9052_LEDCONT_LED1EN 0X01
573
574/* LEDMIN123 REGISTER BIT */
575#define DA9052_LEDMIN123_LEDMINCURRENT 0XFF
576
577/* LED1CONF REGISTER BIT */
578#define DA9052_LED1CONF_LED1CURRENT 0XFF
579
580/* LED2CONF REGISTER BIT */
581#define DA9052_LED2CONF_LED2CURRENT 0XFF
582
583/* LED3CONF REGISTER BIT */
584#define DA9052_LED3CONF_LED3CURRENT 0XFF
585
586/* LED COUNT REGISTER BIT */
587#define DA9052_LED_CONT_DIM 0X80
588
589/* ADC MAN REGISTERS BITS */
590#define DA9052_ADC_MAN_MAN_CONV 0X10
591#define DA9052_ADC_MAN_MUXSEL_VDDOUT 0X00
592#define DA9052_ADC_MAN_MUXSEL_ICH 0X01
593#define DA9052_ADC_MAN_MUXSEL_TBAT 0X02
594#define DA9052_ADC_MAN_MUXSEL_VBAT 0X03
595#define DA9052_ADC_MAN_MUXSEL_AD4 0X04
596#define DA9052_ADC_MAN_MUXSEL_AD5 0X05
597#define DA9052_ADC_MAN_MUXSEL_AD6 0X06
598#define DA9052_ADC_MAN_MUXSEL_VBBAT 0X09
599
600/* ADC CONTROL REGSISTERS BITS */
601#define DA9052_ADCCONT_COMP1V2EN 0X80
602#define DA9052_ADCCONT_ADCMODE 0X40
603#define DA9052_ADCCONT_TBATISRCEN 0X20
604#define DA9052_ADCCONT_AD4ISRCEN 0X10
605#define DA9052_ADCCONT_AUTOAD6EN 0X08
606#define DA9052_ADCCONT_AUTOAD5EN 0X04
607#define DA9052_ADCCONT_AUTOAD4EN 0X02
608#define DA9052_ADCCONT_AUTOVDDEN 0X01
609
610/* ADC 10 BIT MANUAL CONVERSION RESULT LOW REGISTER */
611#define DA9052_ADC_RES_LSB 0X03
612
613/* ADC 10 BIT MANUAL CONVERSION RESULT HIGH REGISTER */
614#define DA9052_ADCRESH_ADCRESMSB 0XFF
615
616/* VDD RES REGSISTER BIT*/
617#define DA9052_VDDRES_VDDOUTRES 0XFF
618
619/* VDD MON REGSISTER BIT */
620#define DA9052_VDDMON_VDDOUTMON 0XFF
621
622/* ICHG_AV REGSISTER BIT */
623#define DA9052_ICHGAV_ICHGAV 0XFF
624
625/* ICHG_THD REGSISTER BIT */
626#define DA9052_ICHGTHD_ICHGTHD 0XFF
627
628/* ICHG_END REGSISTER BIT */
629#define DA9052_ICHGEND_ICHGEND 0XFF
630
631/* TBAT_RES REGSISTER BIT */
632#define DA9052_TBATRES_TBATRES 0XFF
633
634/* TBAT_HIGHP REGSISTER BIT */
635#define DA9052_TBATHIGHP_TBATHIGHP 0XFF
636
637/* TBAT_HIGHN REGSISTER BIT */
638#define DA9052_TBATHIGHN_TBATHIGHN 0XFF
639
640/* TBAT_LOW REGSISTER BIT */
641#define DA9052_TBATLOW_TBATLOW 0XFF
642
643/* T_OFFSET REGSISTER BIT */
644#define DA9052_TOFFSET_TOFFSET 0XFF
645
646/* ADCIN4_RES REGSISTER BIT */
647#define DA9052_ADCIN4RES_ADCIN4RES 0XFF
648
649/* ADCIN4_HIGH REGSISTER BIT */
650#define DA9052_AUTO4HIGH_AUTO4HIGH 0XFF
651
652/* ADCIN4_LOW REGSISTER BIT */
653#define DA9052_AUTO4LOW_AUTO4LOW 0XFF
654
655/* ADCIN5_RES REGSISTER BIT */
656#define DA9052_ADCIN5RES_ADCIN5RES 0XFF
657
658/* ADCIN5_HIGH REGSISTER BIT */
659#define DA9052_AUTO5HIGH_AUTOHIGH 0XFF
660
661/* ADCIN5_LOW REGSISTER BIT */
662#define DA9052_AUTO5LOW_AUTO5LOW 0XFF
663
664/* ADCIN6_RES REGSISTER BIT */
665#define DA9052_ADCIN6RES_ADCIN6RES 0XFF
666
667/* ADCIN6_HIGH REGSISTER BIT */
668#define DA9052_AUTO6HIGH_AUTO6HIGH 0XFF
669
670/* ADCIN6_LOW REGSISTER BIT */
671#define DA9052_AUTO6LOW_AUTO6LOW 0XFF
672
673/* TJUNC_RES REGSISTER BIT*/
674#define DA9052_TJUNCRES_TJUNCRES 0XFF
675
676/* TSI REGISTER */
677/* TSI CONTROL REGISTER A BITS */
678#define DA9052_TSICONTA_TSIDELAY 0XC0
679#define DA9052_TSICONTA_TSISKIP 0X38
680#define DA9052_TSICONTA_TSIMODE 0X04
681#define DA9052_TSICONTA_PENDETEN 0X02
682#define DA9052_TSICONTA_AUTOTSIEN 0X01
683
684/* TSI CONTROL REGISTER B BITS */
685#define DA9052_TSICONTB_ADCREF 0X80
686#define DA9052_TSICONTB_TSIMAN 0X40
687#define DA9052_TSICONTB_TSIMUX 0X30
688#define DA9052_TSICONTB_TSISEL3 0X08
689#define DA9052_TSICONTB_TSISEL2 0X04
690#define DA9052_TSICONTB_TSISEL1 0X02
691#define DA9052_TSICONTB_TSISEL0 0X01
692
693/* TSI X CO-ORDINATE MSB RESULT REGISTER BITS */
694#define DA9052_TSIXMSB_TSIXM 0XFF
695
696/* TSI Y CO-ORDINATE MSB RESULT REGISTER BITS */
697#define DA9052_TSIYMSB_TSIYM 0XFF
698
699/* TSI CO-ORDINATE LSB RESULT REGISTER BITS */
700#define DA9052_TSILSB_PENDOWN 0X40
701#define DA9052_TSILSB_TSIZL 0X30
702#define DA9052_TSILSB_TSIYL 0X0C
703#define DA9052_TSILSB_TSIXL 0X03
704
705/* TSI Z MEASUREMENT MSB RESULT REGISTER BIT */
706#define DA9052_TSIZMSB_TSIZM 0XFF
707
708/* RTC REGISTER */
709/* RTC TIMER SECONDS REGISTER BITS */
710#define DA9052_COUNTS_MONITOR 0X40
711#define DA9052_RTC_SEC 0X3F
712
713/* RTC TIMER MINUTES REGISTER BIT */
714#define DA9052_RTC_MIN 0X3F
715
716/* RTC TIMER HOUR REGISTER BIT */
717#define DA9052_RTC_HOUR 0X1F
718
719/* RTC TIMER DAYS REGISTER BIT */
720#define DA9052_RTC_DAY 0X1F
721
722/* RTC TIMER MONTHS REGISTER BIT */
723#define DA9052_RTC_MONTH 0X0F
724
725/* RTC TIMER YEARS REGISTER BIT */
726#define DA9052_RTC_YEAR 0X3F
727
728/* RTC ALARM MINUTES REGISTER BITS */
729#define DA9052_ALARMM_I_TICK_TYPE 0X80
730#define DA9052_ALARMMI_ALARMTYPE 0X40
731
732/* RTC ALARM YEARS REGISTER BITS */
733#define DA9052_ALARM_Y_TICK_ON 0X80
734#define DA9052_ALARM_Y_ALARM_ON 0X40
735
736/* RTC SECONDS REGISTER A BITS */
737#define DA9052_SECONDA_SECONDSA 0XFF
738
739/* RTC SECONDS REGISTER B BITS */
740#define DA9052_SECONDB_SECONDSB 0XFF
741
742/* RTC SECONDS REGISTER C BITS */
743#define DA9052_SECONDC_SECONDSC 0XFF
744
745/* RTC SECONDS REGISTER D BITS */
746#define DA9052_SECONDD_SECONDSD 0XFF
747
748#endif
749/* __LINUX_MFD_DA9052_REG_H */
diff --git a/include/linux/mfd/max8925.h b/include/linux/mfd/max8925.h
index 5259dfe8c585..15b2392a56fb 100644
--- a/include/linux/mfd/max8925.h
+++ b/include/linux/mfd/max8925.h
@@ -167,9 +167,6 @@ enum {
167 MAX8925_IRQ_VCHG_DC_OVP, 167 MAX8925_IRQ_VCHG_DC_OVP,
168 MAX8925_IRQ_VCHG_DC_F, 168 MAX8925_IRQ_VCHG_DC_F,
169 MAX8925_IRQ_VCHG_DC_R, 169 MAX8925_IRQ_VCHG_DC_R,
170 MAX8925_IRQ_VCHG_USB_OVP,
171 MAX8925_IRQ_VCHG_USB_F,
172 MAX8925_IRQ_VCHG_USB_R,
173 MAX8925_IRQ_VCHG_THM_OK_R, 170 MAX8925_IRQ_VCHG_THM_OK_R,
174 MAX8925_IRQ_VCHG_THM_OK_F, 171 MAX8925_IRQ_VCHG_THM_OK_F,
175 MAX8925_IRQ_VCHG_SYSLOW_F, 172 MAX8925_IRQ_VCHG_SYSLOW_F,
@@ -206,6 +203,8 @@ struct max8925_chip {
206 int irq_base; 203 int irq_base;
207 int core_irq; 204 int core_irq;
208 int tsc_irq; 205 int tsc_irq;
206
207 unsigned int wakeup_flag;
209}; 208};
210 209
211struct max8925_backlight_pdata { 210struct max8925_backlight_pdata {
@@ -223,6 +222,10 @@ struct max8925_power_pdata {
223 unsigned batt_detect:1; 222 unsigned batt_detect:1;
224 unsigned topoff_threshold:2; 223 unsigned topoff_threshold:2;
225 unsigned fast_charge:3; /* charge current */ 224 unsigned fast_charge:3; /* charge current */
225 unsigned no_temp_support:1; /* set if no temperature detect */
226 unsigned no_insert_detect:1; /* set if no ac insert detect */
227 char **supplied_to;
228 int num_supplicants;
226}; 229};
227 230
228/* 231/*
diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
index 0bbd13dbe336..fff590521e50 100644
--- a/include/linux/mfd/max8997.h
+++ b/include/linux/mfd/max8997.h
@@ -77,6 +77,82 @@ struct max8997_regulator_data {
77 struct regulator_init_data *initdata; 77 struct regulator_init_data *initdata;
78}; 78};
79 79
80enum max8997_muic_usb_type {
81 MAX8997_USB_HOST,
82 MAX8997_USB_DEVICE,
83};
84
85enum max8997_muic_charger_type {
86 MAX8997_CHARGER_TYPE_NONE = 0,
87 MAX8997_CHARGER_TYPE_USB,
88 MAX8997_CHARGER_TYPE_DOWNSTREAM_PORT,
89 MAX8997_CHARGER_TYPE_DEDICATED_CHG,
90 MAX8997_CHARGER_TYPE_500MA,
91 MAX8997_CHARGER_TYPE_1A,
92 MAX8997_CHARGER_TYPE_DEAD_BATTERY = 7,
93};
94
95struct max8997_muic_reg_data {
96 u8 addr;
97 u8 data;
98};
99
100/**
101 * struct max8997_muic_platform_data
102 * @usb_callback: callback function for USB
103 * inform callee of USB type (HOST or DEVICE)
104 * and attached state(true or false)
105 * @charger_callback: callback function for charger
106 * inform callee of charger_type
107 * and attached state(true or false)
108 * @deskdock_callback: callback function for desk dock
109 * inform callee of attached state(true or false)
110 * @cardock_callback: callback function for car dock
111 * inform callee of attached state(true or false)
112 * @mhl_callback: callback function for MHL (Mobile High-definition Link)
113 * inform callee of attached state(true or false)
114 * @uart_callback: callback function for JIG UART
115 * inform callee of attached state(true or false)
116 * @init_data: array of max8997_muic_reg_data
117 * used for initializing registers of MAX8997 MUIC device
118 * @num_init_data: array size of init_data
119 */
120struct max8997_muic_platform_data {
121 void (*usb_callback)(enum max8997_muic_usb_type usb_type,
122 bool attached);
123 void (*charger_callback)(bool attached,
124 enum max8997_muic_charger_type charger_type);
125 void (*deskdock_callback) (bool attached);
126 void (*cardock_callback) (bool attached);
127 void (*mhl_callback) (bool attached);
128 void (*uart_callback) (bool attached);
129
130 struct max8997_muic_reg_data *init_data;
131 int num_init_data;
132};
133
134enum max8997_led_mode {
135 MAX8997_NONE,
136 MAX8997_FLASH_MODE,
137 MAX8997_MOVIE_MODE,
138 MAX8997_FLASH_PIN_CONTROL_MODE,
139 MAX8997_MOVIE_PIN_CONTROL_MODE,
140};
141
142/**
143 * struct max8997_led_platform_data
144 * The number of LED devices for MAX8997 is two
145 * @mode: LED mode for each LED device
146 * @brightness: initial brightness for each LED device
147 * range:
148 * [0 - 31]: MAX8997_FLASH_MODE and MAX8997_FLASH_PIN_CONTROL_MODE
149 * [0 - 15]: MAX8997_MOVIE_MODE and MAX8997_MOVIE_PIN_CONTROL_MODE
150 */
151struct max8997_led_platform_data {
152 enum max8997_led_mode mode[2];
153 u8 brightness[2];
154};
155
80struct max8997_platform_data { 156struct max8997_platform_data {
81 /* IRQ */ 157 /* IRQ */
82 int irq_base; 158 int irq_base;
@@ -113,10 +189,13 @@ struct max8997_platform_data {
113 /* charge Full Timeout */ 189 /* charge Full Timeout */
114 int timeout; /* 0 (no timeout), 5, 6, 7 hours */ 190 int timeout; /* 0 (no timeout), 5, 6, 7 hours */
115 191
116 /* MUIC: Not implemented */ 192 /* ---- MUIC ---- */
193 struct max8997_muic_platform_data *muic_pdata;
194
117 /* HAPTIC: Not implemented */ 195 /* HAPTIC: Not implemented */
118 /* RTC: Not implemented */ 196 /* RTC: Not implemented */
119 /* Flash: Not implemented */ 197 /* ---- LED ---- */
198 struct max8997_led_platform_data *led_pdata;
120}; 199};
121 200
122#endif /* __LINUX_MFD_MAX8998_H */ 201#endif /* __LINUX_MFD_MAX8998_H */
diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h
index 3816c2fac0ad..b86ee45c8b03 100644
--- a/include/linux/mfd/mc13xxx.h
+++ b/include/linux/mfd/mc13xxx.h
@@ -69,6 +69,7 @@ struct regulator_init_data;
69struct mc13xxx_regulator_init_data { 69struct mc13xxx_regulator_init_data {
70 int id; 70 int id;
71 struct regulator_init_data *init_data; 71 struct regulator_init_data *init_data;
72 struct device_node *node;
72}; 73};
73 74
74struct mc13xxx_regulator_platform_data { 75struct mc13xxx_regulator_platform_data {
@@ -173,6 +174,9 @@ struct mc13xxx_platform_data {
173#define MC13XXX_ADC_MODE_MULT_CHAN 3 174#define MC13XXX_ADC_MODE_MULT_CHAN 3
174 175
175#define MC13XXX_ADC0 43 176#define MC13XXX_ADC0 43
177#define MC13XXX_ADC0_LICELLCON (1 << 0)
178#define MC13XXX_ADC0_CHRGICON (1 << 1)
179#define MC13XXX_ADC0_BATICON (1 << 2)
176#define MC13XXX_ADC0_ADREFEN (1 << 10) 180#define MC13XXX_ADC0_ADREFEN (1 << 10)
177#define MC13XXX_ADC0_TSMOD0 (1 << 12) 181#define MC13XXX_ADC0_TSMOD0 (1 << 12)
178#define MC13XXX_ADC0_TSMOD1 (1 << 13) 182#define MC13XXX_ADC0_TSMOD1 (1 << 13)
@@ -184,4 +188,9 @@ struct mc13xxx_platform_data {
184 MC13XXX_ADC0_TSMOD1 | \ 188 MC13XXX_ADC0_TSMOD1 | \
185 MC13XXX_ADC0_TSMOD2) 189 MC13XXX_ADC0_TSMOD2)
186 190
191#define MC13XXX_ADC0_CONFIG_MASK (MC13XXX_ADC0_TSMOD_MASK | \
192 MC13XXX_ADC0_LICELLCON | \
193 MC13XXX_ADC0_CHRGICON | \
194 MC13XXX_ADC0_BATICON)
195
187#endif /* ifndef __LINUX_MFD_MC13XXX_H */ 196#endif /* ifndef __LINUX_MFD_MC13XXX_H */
diff --git a/include/linux/mfd/mcp.h b/include/linux/mfd/mcp.h
index ee496708e38b..1515e64e3663 100644
--- a/include/linux/mfd/mcp.h
+++ b/include/linux/mfd/mcp.h
@@ -10,6 +10,7 @@
10#ifndef MCP_H 10#ifndef MCP_H
11#define MCP_H 11#define MCP_H
12 12
13#include <linux/mod_devicetable.h>
13#include <mach/dma.h> 14#include <mach/dma.h>
14 15
15struct mcp_ops; 16struct mcp_ops;
@@ -26,7 +27,7 @@ struct mcp {
26 dma_device_t dma_telco_rd; 27 dma_device_t dma_telco_rd;
27 dma_device_t dma_telco_wr; 28 dma_device_t dma_telco_wr;
28 struct device attached_device; 29 struct device attached_device;
29 int gpio_base; 30 const char *codec;
30}; 31};
31 32
32struct mcp_ops { 33struct mcp_ops {
@@ -44,10 +45,11 @@ void mcp_reg_write(struct mcp *, unsigned int, unsigned int);
44unsigned int mcp_reg_read(struct mcp *, unsigned int); 45unsigned int mcp_reg_read(struct mcp *, unsigned int);
45void mcp_enable(struct mcp *); 46void mcp_enable(struct mcp *);
46void mcp_disable(struct mcp *); 47void mcp_disable(struct mcp *);
48const struct mcp_device_id *mcp_get_device_id(const struct mcp *mcp);
47#define mcp_get_sclk_rate(mcp) ((mcp)->sclk_rate) 49#define mcp_get_sclk_rate(mcp) ((mcp)->sclk_rate)
48 50
49struct mcp *mcp_host_alloc(struct device *, size_t); 51struct mcp *mcp_host_alloc(struct device *, size_t);
50int mcp_host_register(struct mcp *); 52int mcp_host_register(struct mcp *, void *);
51void mcp_host_unregister(struct mcp *); 53void mcp_host_unregister(struct mcp *);
52 54
53struct mcp_driver { 55struct mcp_driver {
@@ -56,6 +58,7 @@ struct mcp_driver {
56 void (*remove)(struct mcp *); 58 void (*remove)(struct mcp *);
57 int (*suspend)(struct mcp *, pm_message_t); 59 int (*suspend)(struct mcp *, pm_message_t);
58 int (*resume)(struct mcp *); 60 int (*resume)(struct mcp *);
61 const struct mcp_device_id *id_table;
59}; 62};
60 63
61int mcp_driver_register(struct mcp_driver *); 64int mcp_driver_register(struct mcp_driver *);
diff --git a/include/linux/mfd/s5m87xx/s5m-core.h b/include/linux/mfd/s5m87xx/s5m-core.h
new file mode 100644
index 000000000000..a7480b57f92d
--- /dev/null
+++ b/include/linux/mfd/s5m87xx/s5m-core.h
@@ -0,0 +1,373 @@
1/*
2 * s5m-core.h
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#ifndef __LINUX_MFD_S5M_CORE_H
15#define __LINUX_MFD_S5M_CORE_H
16
17#define NUM_IRQ_REGS 4
18
19enum s5m_device_type {
20 S5M8751X,
21 S5M8763X,
22 S5M8767X,
23};
24
25/* S5M8767 registers */
26enum s5m8767_reg {
27 S5M8767_REG_ID,
28 S5M8767_REG_INT1,
29 S5M8767_REG_INT2,
30 S5M8767_REG_INT3,
31 S5M8767_REG_INT1M,
32 S5M8767_REG_INT2M,
33 S5M8767_REG_INT3M,
34 S5M8767_REG_STATUS1,
35 S5M8767_REG_STATUS2,
36 S5M8767_REG_STATUS3,
37 S5M8767_REG_CTRL1,
38 S5M8767_REG_CTRL2,
39 S5M8767_REG_LOWBAT1,
40 S5M8767_REG_LOWBAT2,
41 S5M8767_REG_BUCHG,
42 S5M8767_REG_DVSRAMP,
43 S5M8767_REG_DVSTIMER2 = 0x10,
44 S5M8767_REG_DVSTIMER3,
45 S5M8767_REG_DVSTIMER4,
46 S5M8767_REG_LDO1,
47 S5M8767_REG_LDO2,
48 S5M8767_REG_LDO3,
49 S5M8767_REG_LDO4,
50 S5M8767_REG_LDO5,
51 S5M8767_REG_LDO6,
52 S5M8767_REG_LDO7,
53 S5M8767_REG_LDO8,
54 S5M8767_REG_LDO9,
55 S5M8767_REG_LDO10,
56 S5M8767_REG_LDO11,
57 S5M8767_REG_LDO12,
58 S5M8767_REG_LDO13,
59 S5M8767_REG_LDO14 = 0x20,
60 S5M8767_REG_LDO15,
61 S5M8767_REG_LDO16,
62 S5M8767_REG_LDO17,
63 S5M8767_REG_LDO18,
64 S5M8767_REG_LDO19,
65 S5M8767_REG_LDO20,
66 S5M8767_REG_LDO21,
67 S5M8767_REG_LDO22,
68 S5M8767_REG_LDO23,
69 S5M8767_REG_LDO24,
70 S5M8767_REG_LDO25,
71 S5M8767_REG_LDO26,
72 S5M8767_REG_LDO27,
73 S5M8767_REG_LDO28,
74 S5M8767_REG_UVLO = 0x31,
75 S5M8767_REG_BUCK1CTRL1,
76 S5M8767_REG_BUCK1CTRL2,
77 S5M8767_REG_BUCK2CTRL,
78 S5M8767_REG_BUCK2DVS1,
79 S5M8767_REG_BUCK2DVS2,
80 S5M8767_REG_BUCK2DVS3,
81 S5M8767_REG_BUCK2DVS4,
82 S5M8767_REG_BUCK2DVS5,
83 S5M8767_REG_BUCK2DVS6,
84 S5M8767_REG_BUCK2DVS7,
85 S5M8767_REG_BUCK2DVS8,
86 S5M8767_REG_BUCK3CTRL,
87 S5M8767_REG_BUCK3DVS1,
88 S5M8767_REG_BUCK3DVS2,
89 S5M8767_REG_BUCK3DVS3,
90 S5M8767_REG_BUCK3DVS4,
91 S5M8767_REG_BUCK3DVS5,
92 S5M8767_REG_BUCK3DVS6,
93 S5M8767_REG_BUCK3DVS7,
94 S5M8767_REG_BUCK3DVS8,
95 S5M8767_REG_BUCK4CTRL,
96 S5M8767_REG_BUCK4DVS1,
97 S5M8767_REG_BUCK4DVS2,
98 S5M8767_REG_BUCK4DVS3,
99 S5M8767_REG_BUCK4DVS4,
100 S5M8767_REG_BUCK4DVS5,
101 S5M8767_REG_BUCK4DVS6,
102 S5M8767_REG_BUCK4DVS7,
103 S5M8767_REG_BUCK4DVS8,
104 S5M8767_REG_BUCK5CTRL1,
105 S5M8767_REG_BUCK5CTRL2,
106 S5M8767_REG_BUCK5CTRL3,
107 S5M8767_REG_BUCK5CTRL4,
108 S5M8767_REG_BUCK5CTRL5,
109 S5M8767_REG_BUCK6CTRL1,
110 S5M8767_REG_BUCK6CTRL2,
111 S5M8767_REG_BUCK7CTRL1,
112 S5M8767_REG_BUCK7CTRL2,
113 S5M8767_REG_BUCK8CTRL1,
114 S5M8767_REG_BUCK8CTRL2,
115 S5M8767_REG_BUCK9CTRL1,
116 S5M8767_REG_BUCK9CTRL2,
117 S5M8767_REG_LDO1CTRL,
118 S5M8767_REG_LDO2_1CTRL,
119 S5M8767_REG_LDO2_2CTRL,
120 S5M8767_REG_LDO2_3CTRL,
121 S5M8767_REG_LDO2_4CTRL,
122 S5M8767_REG_LDO3CTRL,
123 S5M8767_REG_LDO4CTRL,
124 S5M8767_REG_LDO5CTRL,
125 S5M8767_REG_LDO6CTRL,
126 S5M8767_REG_LDO7CTRL,
127 S5M8767_REG_LDO8CTRL,
128 S5M8767_REG_LDO9CTRL,
129 S5M8767_REG_LDO10CTRL,
130 S5M8767_REG_LDO11CTRL,
131 S5M8767_REG_LDO12CTRL,
132 S5M8767_REG_LDO13CTRL,
133 S5M8767_REG_LDO14CTRL,
134 S5M8767_REG_LDO15CTRL,
135 S5M8767_REG_LDO16CTRL,
136 S5M8767_REG_LDO17CTRL,
137 S5M8767_REG_LDO18CTRL,
138 S5M8767_REG_LDO19CTRL,
139 S5M8767_REG_LDO20CTRL,
140 S5M8767_REG_LDO21CTRL,
141 S5M8767_REG_LDO22CTRL,
142 S5M8767_REG_LDO23CTRL,
143 S5M8767_REG_LDO24CTRL,
144 S5M8767_REG_LDO25CTRL,
145 S5M8767_REG_LDO26CTRL,
146 S5M8767_REG_LDO27CTRL,
147 S5M8767_REG_LDO28CTRL,
148};
149
150/* S5M8763 registers */
151enum s5m8763_reg {
152 S5M8763_REG_IRQ1,
153 S5M8763_REG_IRQ2,
154 S5M8763_REG_IRQ3,
155 S5M8763_REG_IRQ4,
156 S5M8763_REG_IRQM1,
157 S5M8763_REG_IRQM2,
158 S5M8763_REG_IRQM3,
159 S5M8763_REG_IRQM4,
160 S5M8763_REG_STATUS1,
161 S5M8763_REG_STATUS2,
162 S5M8763_REG_STATUSM1,
163 S5M8763_REG_STATUSM2,
164 S5M8763_REG_CHGR1,
165 S5M8763_REG_CHGR2,
166 S5M8763_REG_LDO_ACTIVE_DISCHARGE1,
167 S5M8763_REG_LDO_ACTIVE_DISCHARGE2,
168 S5M8763_REG_BUCK_ACTIVE_DISCHARGE3,
169 S5M8763_REG_ONOFF1,
170 S5M8763_REG_ONOFF2,
171 S5M8763_REG_ONOFF3,
172 S5M8763_REG_ONOFF4,
173 S5M8763_REG_BUCK1_VOLTAGE1,
174 S5M8763_REG_BUCK1_VOLTAGE2,
175 S5M8763_REG_BUCK1_VOLTAGE3,
176 S5M8763_REG_BUCK1_VOLTAGE4,
177 S5M8763_REG_BUCK2_VOLTAGE1,
178 S5M8763_REG_BUCK2_VOLTAGE2,
179 S5M8763_REG_BUCK3,
180 S5M8763_REG_BUCK4,
181 S5M8763_REG_LDO1_LDO2,
182 S5M8763_REG_LDO3,
183 S5M8763_REG_LDO4,
184 S5M8763_REG_LDO5,
185 S5M8763_REG_LDO6,
186 S5M8763_REG_LDO7,
187 S5M8763_REG_LDO7_LDO8,
188 S5M8763_REG_LDO9_LDO10,
189 S5M8763_REG_LDO11,
190 S5M8763_REG_LDO12,
191 S5M8763_REG_LDO13,
192 S5M8763_REG_LDO14,
193 S5M8763_REG_LDO15,
194 S5M8763_REG_LDO16,
195 S5M8763_REG_BKCHR,
196 S5M8763_REG_LBCNFG1,
197 S5M8763_REG_LBCNFG2,
198};
199
200enum s5m8767_irq {
201 S5M8767_IRQ_PWRR,
202 S5M8767_IRQ_PWRF,
203 S5M8767_IRQ_PWR1S,
204 S5M8767_IRQ_JIGR,
205 S5M8767_IRQ_JIGF,
206 S5M8767_IRQ_LOWBAT2,
207 S5M8767_IRQ_LOWBAT1,
208
209 S5M8767_IRQ_MRB,
210 S5M8767_IRQ_DVSOK2,
211 S5M8767_IRQ_DVSOK3,
212 S5M8767_IRQ_DVSOK4,
213
214 S5M8767_IRQ_RTC60S,
215 S5M8767_IRQ_RTCA1,
216 S5M8767_IRQ_RTCA2,
217 S5M8767_IRQ_SMPL,
218 S5M8767_IRQ_RTC1S,
219 S5M8767_IRQ_WTSR,
220
221 S5M8767_IRQ_NR,
222};
223
224#define S5M8767_IRQ_PWRR_MASK (1 << 0)
225#define S5M8767_IRQ_PWRF_MASK (1 << 1)
226#define S5M8767_IRQ_PWR1S_MASK (1 << 3)
227#define S5M8767_IRQ_JIGR_MASK (1 << 4)
228#define S5M8767_IRQ_JIGF_MASK (1 << 5)
229#define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
230#define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
231
232#define S5M8767_IRQ_MRB_MASK (1 << 2)
233#define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
234#define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
235#define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
236
237#define S5M8767_IRQ_RTC60S_MASK (1 << 0)
238#define S5M8767_IRQ_RTCA1_MASK (1 << 1)
239#define S5M8767_IRQ_RTCA2_MASK (1 << 2)
240#define S5M8767_IRQ_SMPL_MASK (1 << 3)
241#define S5M8767_IRQ_RTC1S_MASK (1 << 4)
242#define S5M8767_IRQ_WTSR_MASK (1 << 5)
243
244enum s5m8763_irq {
245 S5M8763_IRQ_DCINF,
246 S5M8763_IRQ_DCINR,
247 S5M8763_IRQ_JIGF,
248 S5M8763_IRQ_JIGR,
249 S5M8763_IRQ_PWRONF,
250 S5M8763_IRQ_PWRONR,
251
252 S5M8763_IRQ_WTSREVNT,
253 S5M8763_IRQ_SMPLEVNT,
254 S5M8763_IRQ_ALARM1,
255 S5M8763_IRQ_ALARM0,
256
257 S5M8763_IRQ_ONKEY1S,
258 S5M8763_IRQ_TOPOFFR,
259 S5M8763_IRQ_DCINOVPR,
260 S5M8763_IRQ_CHGRSTF,
261 S5M8763_IRQ_DONER,
262 S5M8763_IRQ_CHGFAULT,
263
264 S5M8763_IRQ_LOBAT1,
265 S5M8763_IRQ_LOBAT2,
266
267 S5M8763_IRQ_NR,
268};
269
270#define S5M8763_IRQ_DCINF_MASK (1 << 2)
271#define S5M8763_IRQ_DCINR_MASK (1 << 3)
272#define S5M8763_IRQ_JIGF_MASK (1 << 4)
273#define S5M8763_IRQ_JIGR_MASK (1 << 5)
274#define S5M8763_IRQ_PWRONF_MASK (1 << 6)
275#define S5M8763_IRQ_PWRONR_MASK (1 << 7)
276
277#define S5M8763_IRQ_WTSREVNT_MASK (1 << 0)
278#define S5M8763_IRQ_SMPLEVNT_MASK (1 << 1)
279#define S5M8763_IRQ_ALARM1_MASK (1 << 2)
280#define S5M8763_IRQ_ALARM0_MASK (1 << 3)
281
282#define S5M8763_IRQ_ONKEY1S_MASK (1 << 0)
283#define S5M8763_IRQ_TOPOFFR_MASK (1 << 2)
284#define S5M8763_IRQ_DCINOVPR_MASK (1 << 3)
285#define S5M8763_IRQ_CHGRSTF_MASK (1 << 4)
286#define S5M8763_IRQ_DONER_MASK (1 << 5)
287#define S5M8763_IRQ_CHGFAULT_MASK (1 << 7)
288
289#define S5M8763_IRQ_LOBAT1_MASK (1 << 0)
290#define S5M8763_IRQ_LOBAT2_MASK (1 << 1)
291
292#define S5M8763_ENRAMP (1 << 4)
293
294/**
295 * struct s5m87xx_dev - s5m87xx master device for sub-drivers
296 * @dev: master device of the chip (can be used to access platform data)
297 * @i2c: i2c client private data for regulator
298 * @rtc: i2c client private data for rtc
299 * @iolock: mutex for serializing io access
300 * @irqlock: mutex for buslock
301 * @irq_base: base IRQ number for s5m87xx, required for IRQs
302 * @irq: generic IRQ number for s5m87xx
303 * @ono: power onoff IRQ number for s5m87xx
304 * @irq_masks_cur: currently active value
305 * @irq_masks_cache: cached hardware value
306 * @type: indicate which s5m87xx "variant" is used
307 */
308struct s5m87xx_dev {
309 struct device *dev;
310 struct regmap *regmap;
311 struct i2c_client *i2c;
312 struct i2c_client *rtc;
313 struct mutex iolock;
314 struct mutex irqlock;
315
316 int device_type;
317 int irq_base;
318 int irq;
319 int ono;
320 u8 irq_masks_cur[NUM_IRQ_REGS];
321 u8 irq_masks_cache[NUM_IRQ_REGS];
322 int type;
323 bool wakeup;
324};
325
326int s5m_irq_init(struct s5m87xx_dev *s5m87xx);
327void s5m_irq_exit(struct s5m87xx_dev *s5m87xx);
328int s5m_irq_resume(struct s5m87xx_dev *s5m87xx);
329
330extern int s5m_reg_read(struct s5m87xx_dev *s5m87xx, u8 reg, void *dest);
331extern int s5m_bulk_read(struct s5m87xx_dev *s5m87xx, u8 reg, int count, u8 *buf);
332extern int s5m_reg_write(struct s5m87xx_dev *s5m87xx, u8 reg, u8 value);
333extern int s5m_bulk_write(struct s5m87xx_dev *s5m87xx, u8 reg, int count, u8 *buf);
334extern int s5m_reg_update(struct s5m87xx_dev *s5m87xx, u8 reg, u8 val, u8 mask);
335
336struct s5m_platform_data {
337 struct s5m_regulator_data *regulators;
338 int device_type;
339 int num_regulators;
340
341 int irq_base;
342 int (*cfg_pmic_irq)(void);
343
344 int ono;
345 bool wakeup;
346 bool buck_voltage_lock;
347
348 int buck_gpios[3];
349 int buck2_voltage[8];
350 bool buck2_gpiodvs;
351 int buck3_voltage[8];
352 bool buck3_gpiodvs;
353 int buck4_voltage[8];
354 bool buck4_gpiodvs;
355
356 int buck_set1;
357 int buck_set2;
358 int buck_set3;
359 int buck2_enable;
360 int buck3_enable;
361 int buck4_enable;
362 int buck_default_idx;
363 int buck2_default_idx;
364 int buck3_default_idx;
365 int buck4_default_idx;
366
367 int buck_ramp_delay;
368 bool buck2_ramp_enable;
369 bool buck3_ramp_enable;
370 bool buck4_ramp_enable;
371};
372
373#endif /* __LINUX_MFD_S5M_CORE_H */
diff --git a/include/linux/mfd/s5m87xx/s5m-pmic.h b/include/linux/mfd/s5m87xx/s5m-pmic.h
new file mode 100644
index 000000000000..a72a5d27e62e
--- /dev/null
+++ b/include/linux/mfd/s5m87xx/s5m-pmic.h
@@ -0,0 +1,100 @@
1/* s5m87xx.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#ifndef __LINUX_MFD_S5M_PMIC_H
12#define __LINUX_MFD_S5M_PMIC_H
13
14#include <linux/regulator/machine.h>
15
16/* S5M8767 regulator ids */
17enum s5m8767_regulators {
18 S5M8767_LDO1,
19 S5M8767_LDO2,
20 S5M8767_LDO3,
21 S5M8767_LDO4,
22 S5M8767_LDO5,
23 S5M8767_LDO6,
24 S5M8767_LDO7,
25 S5M8767_LDO8,
26 S5M8767_LDO9,
27 S5M8767_LDO10,
28 S5M8767_LDO11,
29 S5M8767_LDO12,
30 S5M8767_LDO13,
31 S5M8767_LDO14,
32 S5M8767_LDO15,
33 S5M8767_LDO16,
34 S5M8767_LDO17,
35 S5M8767_LDO18,
36 S5M8767_LDO19,
37 S5M8767_LDO20,
38 S5M8767_LDO21,
39 S5M8767_LDO22,
40 S5M8767_LDO23,
41 S5M8767_LDO24,
42 S5M8767_LDO25,
43 S5M8767_LDO26,
44 S5M8767_LDO27,
45 S5M8767_LDO28,
46 S5M8767_BUCK1,
47 S5M8767_BUCK2,
48 S5M8767_BUCK3,
49 S5M8767_BUCK4,
50 S5M8767_BUCK5,
51 S5M8767_BUCK6,
52 S5M8767_BUCK7,
53 S5M8767_BUCK8,
54 S5M8767_BUCK9,
55 S5M8767_AP_EN32KHZ,
56 S5M8767_CP_EN32KHZ,
57
58 S5M8767_REG_MAX,
59};
60
61/* S5M8763 regulator ids */
62enum s5m8763_regulators {
63 S5M8763_LDO1,
64 S5M8763_LDO2,
65 S5M8763_LDO3,
66 S5M8763_LDO4,
67 S5M8763_LDO5,
68 S5M8763_LDO6,
69 S5M8763_LDO7,
70 S5M8763_LDO8,
71 S5M8763_LDO9,
72 S5M8763_LDO10,
73 S5M8763_LDO11,
74 S5M8763_LDO12,
75 S5M8763_LDO13,
76 S5M8763_LDO14,
77 S5M8763_LDO15,
78 S5M8763_LDO16,
79 S5M8763_BUCK1,
80 S5M8763_BUCK2,
81 S5M8763_BUCK3,
82 S5M8763_BUCK4,
83 S5M8763_AP_EN32KHZ,
84 S5M8763_CP_EN32KHZ,
85 S5M8763_ENCHGVI,
86 S5M8763_ESAFEUSB1,
87 S5M8763_ESAFEUSB2,
88};
89
90/**
91 * s5m87xx_regulator_data - regulator data
92 * @id: regulator id
93 * @initdata: regulator init data (contraints, supplies, ...)
94 */
95struct s5m_regulator_data {
96 int id;
97 struct regulator_init_data *initdata;
98};
99
100#endif /* __LINUX_MFD_S5M_PMIC_H */
diff --git a/include/linux/mfd/s5m87xx/s5m-rtc.h b/include/linux/mfd/s5m87xx/s5m-rtc.h
new file mode 100644
index 000000000000..6ce8da264cec
--- /dev/null
+++ b/include/linux/mfd/s5m87xx/s5m-rtc.h
@@ -0,0 +1,84 @@
1/*
2 * s5m-rtc.h
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#ifndef __LINUX_MFD_S5M_RTC_H
15#define __LINUX_MFD_S5M_RTC_H
16
17enum s5m87xx_rtc_reg {
18 S5M87XX_RTC_SEC,
19 S5M87XX_RTC_MIN,
20 S5M87XX_RTC_HOUR,
21 S5M87XX_RTC_WEEKDAY,
22 S5M87XX_RTC_DATE,
23 S5M87XX_RTC_MONTH,
24 S5M87XX_RTC_YEAR1,
25 S5M87XX_RTC_YEAR2,
26 S5M87XX_ALARM0_SEC,
27 S5M87XX_ALARM0_MIN,
28 S5M87XX_ALARM0_HOUR,
29 S5M87XX_ALARM0_WEEKDAY,
30 S5M87XX_ALARM0_DATE,
31 S5M87XX_ALARM0_MONTH,
32 S5M87XX_ALARM0_YEAR1,
33 S5M87XX_ALARM0_YEAR2,
34 S5M87XX_ALARM1_SEC,
35 S5M87XX_ALARM1_MIN,
36 S5M87XX_ALARM1_HOUR,
37 S5M87XX_ALARM1_WEEKDAY,
38 S5M87XX_ALARM1_DATE,
39 S5M87XX_ALARM1_MONTH,
40 S5M87XX_ALARM1_YEAR1,
41 S5M87XX_ALARM1_YEAR2,
42 S5M87XX_ALARM0_CONF,
43 S5M87XX_ALARM1_CONF,
44 S5M87XX_RTC_STATUS,
45 S5M87XX_WTSR_SMPL_CNTL,
46 S5M87XX_RTC_UDR_CON,
47};
48
49#define RTC_I2C_ADDR (0x0C >> 1)
50
51#define HOUR_12 (1 << 7)
52#define HOUR_AMPM (1 << 6)
53#define HOUR_PM (1 << 5)
54#define ALARM0_STATUS (1 << 1)
55#define ALARM1_STATUS (1 << 2)
56#define UPDATE_AD (1 << 0)
57
58/* RTC Control Register */
59#define BCD_EN_SHIFT 0
60#define BCD_EN_MASK (1 << BCD_EN_SHIFT)
61#define MODEL24_SHIFT 1
62#define MODEL24_MASK (1 << MODEL24_SHIFT)
63/* RTC Update Register1 */
64#define RTC_UDR_SHIFT 0
65#define RTC_UDR_MASK (1 << RTC_UDR_SHIFT)
66/* RTC Hour register */
67#define HOUR_PM_SHIFT 6
68#define HOUR_PM_MASK (1 << HOUR_PM_SHIFT)
69/* RTC Alarm Enable */
70#define ALARM_ENABLE_SHIFT 7
71#define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT)
72
73enum {
74 RTC_SEC = 0,
75 RTC_MIN,
76 RTC_HOUR,
77 RTC_WEEKDAY,
78 RTC_DATE,
79 RTC_MONTH,
80 RTC_YEAR1,
81 RTC_YEAR2,
82};
83
84#endif /* __LINUX_MFD_S5M_RTC_H */
diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
index be1af7c42e57..ca1d7a347600 100644
--- a/include/linux/mfd/stmpe.h
+++ b/include/linux/mfd/stmpe.h
@@ -20,6 +20,8 @@ enum stmpe_block {
20}; 20};
21 21
22enum stmpe_partnum { 22enum stmpe_partnum {
23 STMPE610,
24 STMPE801,
23 STMPE811, 25 STMPE811,
24 STMPE1601, 26 STMPE1601,
25 STMPE2401, 27 STMPE2401,
@@ -50,17 +52,20 @@ enum {
50 52
51 53
52struct stmpe_variant_info; 54struct stmpe_variant_info;
55struct stmpe_client_info;
53 56
54/** 57/**
55 * struct stmpe - STMPE MFD structure 58 * struct stmpe - STMPE MFD structure
56 * @lock: lock protecting I/O operations 59 * @lock: lock protecting I/O operations
57 * @irq_lock: IRQ bus lock 60 * @irq_lock: IRQ bus lock
58 * @dev: device, mostly for dev_dbg() 61 * @dev: device, mostly for dev_dbg()
59 * @i2c: i2c client 62 * @client: client - i2c or spi
63 * @ci: client specific information
60 * @partnum: part number 64 * @partnum: part number
61 * @variant: the detected STMPE model number 65 * @variant: the detected STMPE model number
62 * @regs: list of addresses of registers which are at different addresses on 66 * @regs: list of addresses of registers which are at different addresses on
63 * different variants. Indexed by one of STMPE_IDX_*. 67 * different variants. Indexed by one of STMPE_IDX_*.
68 * @irq: irq number for stmpe
64 * @irq_base: starting IRQ number for internal IRQs 69 * @irq_base: starting IRQ number for internal IRQs
65 * @num_gpios: number of gpios, differs for variants 70 * @num_gpios: number of gpios, differs for variants
66 * @ier: cache of IER registers for bus_lock 71 * @ier: cache of IER registers for bus_lock
@@ -71,11 +76,13 @@ struct stmpe {
71 struct mutex lock; 76 struct mutex lock;
72 struct mutex irq_lock; 77 struct mutex irq_lock;
73 struct device *dev; 78 struct device *dev;
74 struct i2c_client *i2c; 79 void *client;
80 struct stmpe_client_info *ci;
75 enum stmpe_partnum partnum; 81 enum stmpe_partnum partnum;
76 struct stmpe_variant_info *variant; 82 struct stmpe_variant_info *variant;
77 const u8 *regs; 83 const u8 *regs;
78 84
85 int irq;
79 int irq_base; 86 int irq_base;
80 int num_gpios; 87 int num_gpios;
81 u8 ier[2]; 88 u8 ier[2];
@@ -183,6 +190,9 @@ struct stmpe_ts_platform_data {
183 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep 190 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep
184 * @irq_base: base IRQ number. %STMPE_NR_IRQS irqs will be used, or 191 * @irq_base: base IRQ number. %STMPE_NR_IRQS irqs will be used, or
185 * %STMPE_NR_INTERNAL_IRQS if the GPIO driver is not used. 192 * %STMPE_NR_INTERNAL_IRQS if the GPIO driver is not used.
193 * @irq_over_gpio: true if gpio is used to get irq
194 * @irq_gpio: gpio number over which irq will be requested (significant only if
195 * irq_over_gpio is true)
186 * @gpio: GPIO-specific platform data 196 * @gpio: GPIO-specific platform data
187 * @keypad: keypad-specific platform data 197 * @keypad: keypad-specific platform data
188 * @ts: touchscreen-specific platform data 198 * @ts: touchscreen-specific platform data
@@ -194,6 +204,8 @@ struct stmpe_platform_data {
194 unsigned int irq_trigger; 204 unsigned int irq_trigger;
195 bool irq_invert_polarity; 205 bool irq_invert_polarity;
196 bool autosleep; 206 bool autosleep;
207 bool irq_over_gpio;
208 int irq_gpio;
197 int autosleep_timeout; 209 int autosleep_timeout;
198 210
199 struct stmpe_gpio_platform_data *gpio; 211 struct stmpe_gpio_platform_data *gpio;
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
index 8bf2cb9502dd..d0cb12eba402 100644
--- a/include/linux/mfd/tps65910.h
+++ b/include/linux/mfd/tps65910.h
@@ -740,6 +740,34 @@
740#define TPS65910_GPIO_STS BIT(1) 740#define TPS65910_GPIO_STS BIT(1)
741#define TPS65910_GPIO_SET BIT(0) 741#define TPS65910_GPIO_SET BIT(0)
742 742
743/* Regulator Index Definitions */
744#define TPS65910_REG_VRTC 0
745#define TPS65910_REG_VIO 1
746#define TPS65910_REG_VDD1 2
747#define TPS65910_REG_VDD2 3
748#define TPS65910_REG_VDD3 4
749#define TPS65910_REG_VDIG1 5
750#define TPS65910_REG_VDIG2 6
751#define TPS65910_REG_VPLL 7
752#define TPS65910_REG_VDAC 8
753#define TPS65910_REG_VAUX1 9
754#define TPS65910_REG_VAUX2 10
755#define TPS65910_REG_VAUX33 11
756#define TPS65910_REG_VMMC 12
757
758#define TPS65911_REG_VDDCTRL 4
759#define TPS65911_REG_LDO1 5
760#define TPS65911_REG_LDO2 6
761#define TPS65911_REG_LDO3 7
762#define TPS65911_REG_LDO4 8
763#define TPS65911_REG_LDO5 9
764#define TPS65911_REG_LDO6 10
765#define TPS65911_REG_LDO7 11
766#define TPS65911_REG_LDO8 12
767
768/* Max number of TPS65910/11 regulators */
769#define TPS65910_NUM_REGS 13
770
743/** 771/**
744 * struct tps65910_board 772 * struct tps65910_board
745 * Board platform data may be used to initialize regulators. 773 * Board platform data may be used to initialize regulators.
@@ -751,7 +779,7 @@ struct tps65910_board {
751 int irq_base; 779 int irq_base;
752 int vmbch_threshold; 780 int vmbch_threshold;
753 int vmbch2_threshold; 781 int vmbch2_threshold;
754 struct regulator_init_data *tps65910_pmic_init_data; 782 struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
755}; 783};
756 784
757/** 785/**
diff --git a/include/linux/mfd/ucb1x00.h b/include/linux/mfd/ucb1x00.h
index 4321f044d1e4..bc19e5fb7ea8 100644
--- a/include/linux/mfd/ucb1x00.h
+++ b/include/linux/mfd/ucb1x00.h
@@ -104,6 +104,9 @@
104#define UCB_MODE_DYN_VFLAG_ENA (1 << 12) 104#define UCB_MODE_DYN_VFLAG_ENA (1 << 12)
105#define UCB_MODE_AUD_OFF_CAN (1 << 13) 105#define UCB_MODE_AUD_OFF_CAN (1 << 13)
106 106
107struct ucb1x00_plat_data {
108 int gpio_base;
109};
107 110
108struct ucb1x00_irq { 111struct ucb1x00_irq {
109 void *devid; 112 void *devid;
@@ -116,7 +119,7 @@ struct ucb1x00 {
116 unsigned int irq; 119 unsigned int irq;
117 struct semaphore adc_sem; 120 struct semaphore adc_sem;
118 spinlock_t io_lock; 121 spinlock_t io_lock;
119 u16 id; 122 const struct mcp_device_id *id;
120 u16 io_dir; 123 u16 io_dir;
121 u16 io_out; 124 u16 io_out;
122 u16 adc_cr; 125 u16 adc_cr;
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h
index f44bdb7273bd..9eff2a351ec5 100644
--- a/include/linux/mfd/wm8994/core.h
+++ b/include/linux/mfd/wm8994/core.h
@@ -15,6 +15,7 @@
15#ifndef __MFD_WM8994_CORE_H__ 15#ifndef __MFD_WM8994_CORE_H__
16#define __MFD_WM8994_CORE_H__ 16#define __MFD_WM8994_CORE_H__
17 17
18#include <linux/mutex.h>
18#include <linux/interrupt.h> 19#include <linux/interrupt.h>
19 20
20enum wm8994_type { 21enum wm8994_type {
@@ -55,6 +56,7 @@ struct wm8994 {
55 struct mutex irq_lock; 56 struct mutex irq_lock;
56 57
57 enum wm8994_type type; 58 enum wm8994_type type;
59 int revision;
58 60
59 struct device *dev; 61 struct device *dev;
60 struct regmap *regmap; 62 struct regmap *regmap;
@@ -65,13 +67,10 @@ struct wm8994 {
65 int irq_base; 67 int irq_base;
66 68
67 int irq; 69 int irq;
68 u16 irq_masks_cur[WM8994_NUM_IRQ_REGS]; 70 struct regmap_irq_chip_data *irq_data;
69 u16 irq_masks_cache[WM8994_NUM_IRQ_REGS];
70 71
71 /* Used over suspend/resume */ 72 /* Used over suspend/resume */
72 bool suspended; 73 bool suspended;
73 u16 ldo_regs[WM8994_NUM_LDO_REGS];
74 u16 gpio_regs[WM8994_NUM_GPIO_REGS];
75 74
76 struct regulator_dev *dbvdd; 75 struct regulator_dev *dbvdd;
77 int num_supplies; 76 int num_supplies;
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h
index ea32f306dca6..3fb1f407d5e6 100644
--- a/include/linux/mfd/wm8994/pdata.h
+++ b/include/linux/mfd/wm8994/pdata.h
@@ -23,7 +23,7 @@ struct wm8994_ldo_pdata {
23 int enable; 23 int enable;
24 24
25 const char *supply; 25 const char *supply;
26 struct regulator_init_data *init_data; 26 const struct regulator_init_data *init_data;
27}; 27};
28 28
29#define WM8994_CONFIGURE_GPIO 0x10000 29#define WM8994_CONFIGURE_GPIO 0x10000
@@ -113,6 +113,23 @@ struct wm8958_enh_eq_cfg {
113 u16 regs[WM8958_ENH_EQ_REGS]; 113 u16 regs[WM8958_ENH_EQ_REGS];
114}; 114};
115 115
116/**
117 * Microphone detection rates, used to tune response rates and power
118 * consumption for WM8958/WM1811 microphone detection.
119 *
120 * @sysclk: System clock rate to use this configuration for.
121 * @idle: True if this configuration should use when no accessory is detected,
122 * false otherwise.
123 * @start: Value for MICD_BIAS_START_TIME register field (not shifted).
124 * @rate: Value for MICD_RATE register field (not shifted).
125 */
126struct wm8958_micd_rate {
127 int sysclk;
128 bool idle;
129 int start;
130 int rate;
131};
132
116struct wm8994_pdata { 133struct wm8994_pdata {
117 int gpio_base; 134 int gpio_base;
118 135
@@ -144,6 +161,9 @@ struct wm8994_pdata {
144 int num_enh_eq_cfgs; 161 int num_enh_eq_cfgs;
145 struct wm8958_enh_eq_cfg *enh_eq_cfgs; 162 struct wm8958_enh_eq_cfg *enh_eq_cfgs;
146 163
164 int num_micd_rates;
165 struct wm8958_micd_rate *micd_rates;
166
147 /* LINEOUT can be differential or single ended */ 167 /* LINEOUT can be differential or single ended */
148 unsigned int lineout1_diff:1; 168 unsigned int lineout1_diff:1;
149 unsigned int lineout2_diff:1; 169 unsigned int lineout2_diff:1;
@@ -168,12 +188,21 @@ struct wm8994_pdata {
168 /* WM8958 microphone bias configuration */ 188 /* WM8958 microphone bias configuration */
169 int micbias[2]; 189 int micbias[2];
170 190
191 /* WM8958 microphone detection ranges */
192 u16 micd_lvl_sel;
193
171 /* Disable the internal pull downs on the LDOs if they are 194 /* Disable the internal pull downs on the LDOs if they are
172 * always driven (eg, connected to an always on supply or 195 * always driven (eg, connected to an always on supply or
173 * GPIO that always drives an output. If they float power 196 * GPIO that always drives an output. If they float power
174 * consumption will rise. 197 * consumption will rise.
175 */ 198 */
176 bool ldo_ena_always_driven; 199 bool ldo_ena_always_driven;
200
201 /*
202 * SPKMODE must be pulled internally by the device on this
203 * system.
204 */
205 bool spkmode_pu;
177}; 206};
178 207
179#endif 208#endif
diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h
index 83a9caec0e43..86e6a032a078 100644
--- a/include/linux/mfd/wm8994/registers.h
+++ b/include/linux/mfd/wm8994/registers.h
@@ -95,11 +95,15 @@
95#define WM8994_FLL1_CONTROL_3 0x222 95#define WM8994_FLL1_CONTROL_3 0x222
96#define WM8994_FLL1_CONTROL_4 0x223 96#define WM8994_FLL1_CONTROL_4 0x223
97#define WM8994_FLL1_CONTROL_5 0x224 97#define WM8994_FLL1_CONTROL_5 0x224
98#define WM8958_FLL1_EFS_1 0x226
99#define WM8958_FLL1_EFS_2 0x227
98#define WM8994_FLL2_CONTROL_1 0x240 100#define WM8994_FLL2_CONTROL_1 0x240
99#define WM8994_FLL2_CONTROL_2 0x241 101#define WM8994_FLL2_CONTROL_2 0x241
100#define WM8994_FLL2_CONTROL_3 0x242 102#define WM8994_FLL2_CONTROL_3 0x242
101#define WM8994_FLL2_CONTROL_4 0x243 103#define WM8994_FLL2_CONTROL_4 0x243
102#define WM8994_FLL2_CONTROL_5 0x244 104#define WM8994_FLL2_CONTROL_5 0x244
105#define WM8958_FLL2_EFS_1 0x246
106#define WM8958_FLL2_EFS_2 0x247
103#define WM8994_AIF1_CONTROL_1 0x300 107#define WM8994_AIF1_CONTROL_1 0x300
104#define WM8994_AIF1_CONTROL_2 0x301 108#define WM8994_AIF1_CONTROL_2 0x301
105#define WM8994_AIF1_MASTER_SLAVE 0x302 109#define WM8994_AIF1_MASTER_SLAVE 0x302
@@ -116,6 +120,7 @@
116#define WM8994_AIF2DAC_LRCLK 0x315 120#define WM8994_AIF2DAC_LRCLK 0x315
117#define WM8994_AIF2DAC_DATA 0x316 121#define WM8994_AIF2DAC_DATA 0x316
118#define WM8994_AIF2ADC_DATA 0x317 122#define WM8994_AIF2ADC_DATA 0x317
123#define WM1811_AIF2TX_CONTROL 0x318
119#define WM8958_AIF3_CONTROL_1 0x320 124#define WM8958_AIF3_CONTROL_1 0x320
120#define WM8958_AIF3_CONTROL_2 0x321 125#define WM8958_AIF3_CONTROL_2 0x321
121#define WM8958_AIF3DAC_DATA 0x322 126#define WM8958_AIF3DAC_DATA 0x322
@@ -166,6 +171,7 @@
166#define WM8994_AIF1_DAC1_EQ_BAND_5_A 0x491 171#define WM8994_AIF1_DAC1_EQ_BAND_5_A 0x491
167#define WM8994_AIF1_DAC1_EQ_BAND_5_B 0x492 172#define WM8994_AIF1_DAC1_EQ_BAND_5_B 0x492
168#define WM8994_AIF1_DAC1_EQ_BAND_5_PG 0x493 173#define WM8994_AIF1_DAC1_EQ_BAND_5_PG 0x493
174#define WM8994_AIF1_DAC1_EQ_BAND_1_C 0x494
169#define WM8994_AIF1_DAC2_EQ_GAINS_1 0x4A0 175#define WM8994_AIF1_DAC2_EQ_GAINS_1 0x4A0
170#define WM8994_AIF1_DAC2_EQ_GAINS_2 0x4A1 176#define WM8994_AIF1_DAC2_EQ_GAINS_2 0x4A1
171#define WM8994_AIF1_DAC2_EQ_BAND_1_A 0x4A2 177#define WM8994_AIF1_DAC2_EQ_BAND_1_A 0x4A2
@@ -186,6 +192,7 @@
186#define WM8994_AIF1_DAC2_EQ_BAND_5_A 0x4B1 192#define WM8994_AIF1_DAC2_EQ_BAND_5_A 0x4B1
187#define WM8994_AIF1_DAC2_EQ_BAND_5_B 0x4B2 193#define WM8994_AIF1_DAC2_EQ_BAND_5_B 0x4B2
188#define WM8994_AIF1_DAC2_EQ_BAND_5_PG 0x4B3 194#define WM8994_AIF1_DAC2_EQ_BAND_5_PG 0x4B3
195#define WM8994_AIF1_DAC2_EQ_BAND_1_C 0x4B4
189#define WM8994_AIF2_ADC_LEFT_VOLUME 0x500 196#define WM8994_AIF2_ADC_LEFT_VOLUME 0x500
190#define WM8994_AIF2_ADC_RIGHT_VOLUME 0x501 197#define WM8994_AIF2_ADC_RIGHT_VOLUME 0x501
191#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502 198#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502
@@ -219,6 +226,7 @@
219#define WM8994_AIF2_EQ_BAND_5_A 0x591 226#define WM8994_AIF2_EQ_BAND_5_A 0x591
220#define WM8994_AIF2_EQ_BAND_5_B 0x592 227#define WM8994_AIF2_EQ_BAND_5_B 0x592
221#define WM8994_AIF2_EQ_BAND_5_PG 0x593 228#define WM8994_AIF2_EQ_BAND_5_PG 0x593
229#define WM8994_AIF2_EQ_BAND_1_C 0x594
222#define WM8994_DAC1_MIXER_VOLUMES 0x600 230#define WM8994_DAC1_MIXER_VOLUMES 0x600
223#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601 231#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601
224#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602 232#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602
@@ -242,6 +250,7 @@
242#define WM8994_GPIO_4 0x703 250#define WM8994_GPIO_4 0x703
243#define WM8994_GPIO_5 0x704 251#define WM8994_GPIO_5 0x704
244#define WM8994_GPIO_6 0x705 252#define WM8994_GPIO_6 0x705
253#define WM1811_JACKDET_CTRL 0x705
245#define WM8994_GPIO_7 0x706 254#define WM8994_GPIO_7 0x706
246#define WM8994_GPIO_8 0x707 255#define WM8994_GPIO_8 0x707
247#define WM8994_GPIO_9 0x708 256#define WM8994_GPIO_9 0x708
@@ -264,7 +273,43 @@
264#define WM8958_DSP2_RELEASETIME 0xA03 273#define WM8958_DSP2_RELEASETIME 0xA03
265#define WM8958_DSP2_VERMAJMIN 0xA04 274#define WM8958_DSP2_VERMAJMIN 0xA04
266#define WM8958_DSP2_VERBUILD 0xA05 275#define WM8958_DSP2_VERBUILD 0xA05
276#define WM8958_DSP2_TESTREG 0xA06
277#define WM8958_DSP2_XORREG 0xA07
278#define WM8958_DSP2_SHIFTMAXX 0xA08
279#define WM8958_DSP2_SHIFTMAXY 0xA09
280#define WM8958_DSP2_SHIFTMAXZ 0xA0A
281#define WM8958_DSP2_SHIFTMAXEXTLO 0xA0B
282#define WM8958_DSP2_AESSELECT 0xA0C
267#define WM8958_DSP2_EXECCONTROL 0xA0D 283#define WM8958_DSP2_EXECCONTROL 0xA0D
284#define WM8958_DSP2_SAMPLEBREAK 0xA0E
285#define WM8958_DSP2_COUNTBREAK 0xA0F
286#define WM8958_DSP2_INTSTATUS 0xA10
287#define WM8958_DSP2_EVENTSTATUS 0xA11
288#define WM8958_DSP2_INTMASK 0xA12
289#define WM8958_DSP2_CONFIGDWIDTH 0xA13
290#define WM8958_DSP2_CONFIGINSTR 0xA14
291#define WM8958_DSP2_CONFIGDMEM 0xA15
292#define WM8958_DSP2_CONFIGDELAYS 0xA16
293#define WM8958_DSP2_CONFIGNUMIO 0xA17
294#define WM8958_DSP2_CONFIGEXTDEPTH 0xA18
295#define WM8958_DSP2_CONFIGMULTIPLIER 0xA19
296#define WM8958_DSP2_CONFIGCTRLDWIDTH 0xA1A
297#define WM8958_DSP2_CONFIGPIPELINE 0xA1B
298#define WM8958_DSP2_SHIFTMAXEXTHI 0xA1C
299#define WM8958_DSP2_SWVERSIONREG 0xA1D
300#define WM8958_DSP2_CONFIGXMEM 0xA1E
301#define WM8958_DSP2_CONFIGYMEM 0xA1F
302#define WM8958_DSP2_CONFIGZMEM 0xA20
303#define WM8958_FW_BUILD_1 0x2000
304#define WM8958_FW_BUILD_0 0x2001
305#define WM8958_FW_ID_1 0x2002
306#define WM8958_FW_ID_0 0x2003
307#define WM8958_FW_MAJOR_1 0x2004
308#define WM8958_FW_MAJOR_0 0x2005
309#define WM8958_FW_MINOR_1 0x2006
310#define WM8958_FW_MINOR_0 0x2007
311#define WM8958_FW_PATCH_1 0x2008
312#define WM8958_FW_PATCH_0 0x2009
268#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1 0x2200 313#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1 0x2200
269#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2 0x2201 314#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2 0x2201
270#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1 0x2202 315#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1 0x2202
@@ -333,6 +378,14 @@
333#define WM8958_MBC_B2_PG2_2 0x242D 378#define WM8958_MBC_B2_PG2_2 0x242D
334#define WM8958_MBC_B1_PG2_1 0x242E 379#define WM8958_MBC_B1_PG2_1 0x242E
335#define WM8958_MBC_B1_PG2_2 0x242F 380#define WM8958_MBC_B1_PG2_2 0x242F
381#define WM8958_MBC_CROSSOVER_1 0x2600
382#define WM8958_MBC_CROSSOVER_2 0x2601
383#define WM8958_MBC_HPF_1 0x2602
384#define WM8958_MBC_HPF_2 0x2603
385#define WM8958_MBC_LPF_1 0x2606
386#define WM8958_MBC_LPF_2 0x2607
387#define WM8958_MBC_RMS_LIMIT_1 0x260A
388#define WM8958_MBC_RMS_LIMIT_2 0x260B
336#define WM8994_WRITE_SEQUENCER_0 0x3000 389#define WM8994_WRITE_SEQUENCER_0 0x3000
337#define WM8994_WRITE_SEQUENCER_1 0x3001 390#define WM8994_WRITE_SEQUENCER_1 0x3001
338#define WM8994_WRITE_SEQUENCER_2 0x3002 391#define WM8994_WRITE_SEQUENCER_2 0x3002
@@ -1852,6 +1905,9 @@
1852/* 1905/*
1853 * R57 (0x39) - AntiPOP (2) 1906 * R57 (0x39) - AntiPOP (2)
1854 */ 1907 */
1908#define WM1811_JACKDET_MODE_MASK 0x0180 /* JACKDET_MODE - [8:7] */
1909#define WM1811_JACKDET_MODE_SHIFT 7 /* JACKDET_MODE - [8:7] */
1910#define WM1811_JACKDET_MODE_WIDTH 2 /* JACKDET_MODE - [8:7] */
1855#define WM8994_MICB2_DISCH 0x0100 /* MICB2_DISCH */ 1911#define WM8994_MICB2_DISCH 0x0100 /* MICB2_DISCH */
1856#define WM8994_MICB2_DISCH_MASK 0x0100 /* MICB2_DISCH */ 1912#define WM8994_MICB2_DISCH_MASK 0x0100 /* MICB2_DISCH */
1857#define WM8994_MICB2_DISCH_SHIFT 8 /* MICB2_DISCH */ 1913#define WM8994_MICB2_DISCH_SHIFT 8 /* MICB2_DISCH */
@@ -2389,6 +2445,10 @@
2389/* 2445/*
2390 * R548 (0x224) - FLL1 Control (5) 2446 * R548 (0x224) - FLL1 Control (5)
2391 */ 2447 */
2448#define WM8958_FLL1_BYP 0x8000 /* FLL1_BYP */
2449#define WM8958_FLL1_BYP_MASK 0x8000 /* FLL1_BYP */
2450#define WM8958_FLL1_BYP_SHIFT 15 /* FLL1_BYP */
2451#define WM8958_FLL1_BYP_WIDTH 1 /* FLL1_BYP */
2392#define WM8994_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */ 2452#define WM8994_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */
2393#define WM8994_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */ 2453#define WM8994_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */
2394#define WM8994_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */ 2454#define WM8994_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */
@@ -2404,6 +2464,24 @@
2404#define WM8994_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */ 2464#define WM8994_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */
2405 2465
2406/* 2466/*
2467 * R550 (0x226) - FLL1 EFS 1
2468 */
2469#define WM8958_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */
2470#define WM8958_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */
2471#define WM8958_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */
2472
2473/*
2474 * R551 (0x227) - FLL1 EFS 2
2475 */
2476#define WM8958_FLL1_LFSR_SEL_MASK 0x0006 /* FLL1_LFSR_SEL - [2:1] */
2477#define WM8958_FLL1_LFSR_SEL_SHIFT 1 /* FLL1_LFSR_SEL - [2:1] */
2478#define WM8958_FLL1_LFSR_SEL_WIDTH 2 /* FLL1_LFSR_SEL - [2:1] */
2479#define WM8958_FLL1_EFS_ENA 0x0001 /* FLL1_EFS_ENA */
2480#define WM8958_FLL1_EFS_ENA_MASK 0x0001 /* FLL1_EFS_ENA */
2481#define WM8958_FLL1_EFS_ENA_SHIFT 0 /* FLL1_EFS_ENA */
2482#define WM8958_FLL1_EFS_ENA_WIDTH 1 /* FLL1_EFS_ENA */
2483
2484/*
2407 * R576 (0x240) - FLL2 Control (1) 2485 * R576 (0x240) - FLL2 Control (1)
2408 */ 2486 */
2409#define WM8994_FLL2_FRAC 0x0004 /* FLL2_FRAC */ 2487#define WM8994_FLL2_FRAC 0x0004 /* FLL2_FRAC */
@@ -2452,6 +2530,10 @@
2452/* 2530/*
2453 * R580 (0x244) - FLL2 Control (5) 2531 * R580 (0x244) - FLL2 Control (5)
2454 */ 2532 */
2533#define WM8958_FLL2_BYP 0x8000 /* FLL2_BYP */
2534#define WM8958_FLL2_BYP_MASK 0x8000 /* FLL2_BYP */
2535#define WM8958_FLL2_BYP_SHIFT 15 /* FLL2_BYP */
2536#define WM8958_FLL2_BYP_WIDTH 1 /* FLL2_BYP */
2455#define WM8994_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */ 2537#define WM8994_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */
2456#define WM8994_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */ 2538#define WM8994_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */
2457#define WM8994_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */ 2539#define WM8994_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */
@@ -2467,6 +2549,24 @@
2467#define WM8994_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */ 2549#define WM8994_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */
2468 2550
2469/* 2551/*
2552 * R582 (0x246) - FLL2 EFS 1
2553 */
2554#define WM8958_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */
2555#define WM8958_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */
2556#define WM8958_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */
2557
2558/*
2559 * R583 (0x247) - FLL2 EFS 2
2560 */
2561#define WM8958_FLL2_LFSR_SEL_MASK 0x0006 /* FLL2_LFSR_SEL - [2:1] */
2562#define WM8958_FLL2_LFSR_SEL_SHIFT 1 /* FLL2_LFSR_SEL - [2:1] */
2563#define WM8958_FLL2_LFSR_SEL_WIDTH 2 /* FLL2_LFSR_SEL - [2:1] */
2564#define WM8958_FLL2_EFS_ENA 0x0001 /* FLL2_EFS_ENA */
2565#define WM8958_FLL2_EFS_ENA_MASK 0x0001 /* FLL2_EFS_ENA */
2566#define WM8958_FLL2_EFS_ENA_SHIFT 0 /* FLL2_EFS_ENA */
2567#define WM8958_FLL2_EFS_ENA_WIDTH 1 /* FLL2_EFS_ENA */
2568
2569/*
2470 * R768 (0x300) - AIF1 Control (1) 2570 * R768 (0x300) - AIF1 Control (1)
2471 */ 2571 */
2472#define WM8994_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */ 2572#define WM8994_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */
@@ -4187,6 +4287,18 @@
4187#define WM8994_STL_SEL_WIDTH 1 /* STL_SEL */ 4287#define WM8994_STL_SEL_WIDTH 1 /* STL_SEL */
4188 4288
4189/* 4289/*
4290 * R1797 (0x705) - JACKDET Ctrl
4291 */
4292#define WM1811_JACKDET_DB 0x0100 /* JACKDET_DB */
4293#define WM1811_JACKDET_DB_MASK 0x0100 /* JACKDET_DB */
4294#define WM1811_JACKDET_DB_SHIFT 8 /* JACKDET_DB */
4295#define WM1811_JACKDET_DB_WIDTH 1 /* JACKDET_DB */
4296#define WM1811_JACKDET_LVL 0x0040 /* JACKDET_LVL */
4297#define WM1811_JACKDET_LVL_MASK 0x0040 /* JACKDET_LVL */
4298#define WM1811_JACKDET_LVL_SHIFT 6 /* JACKDET_LVL */
4299#define WM1811_JACKDET_LVL_WIDTH 1 /* JACKDET_LVL */
4300
4301/*
4190 * R1824 (0x720) - Pull Control (1) 4302 * R1824 (0x720) - Pull Control (1)
4191 */ 4303 */
4192#define WM8994_DMICDAT2_PU 0x0800 /* DMICDAT2_PU */ 4304#define WM8994_DMICDAT2_PU 0x0800 /* DMICDAT2_PU */
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-12 02:13:14 -0400