1 files changed, 35 insertions, 34 deletions
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
index 5097831387ff..8430e45427f4 100644
--- a/drivers/clk/clk-ls1x.c
+++ b/drivers/clk/clk-ls1x.c
@@ -48,13 +48,13 @@ static const struct clk_ops ls1x_pll_clk_ops = {
        .recalc_rate = ls1x_pll_recalc_rate,
 };
-static struct clk *__init clk_register_pll(struct device *dev,
+static struct clk_hw *__init clk_hw_register_pll(struct device *dev,
-                                           const char *name,
+                                                 const char *name,
-                                           const char *parent_name,
+                                                 const char *parent_name,
-                                           unsigned long flags)
+                                                 unsigned long flags)
 {
+        int ret;
        struct clk_hw *hw;
-        struct clk *clk;
        struct clk_init_data init;
        /* allocate the divider */
@@ -72,12 +72,13 @@ static struct clk *__init clk_register_pll(struct device *dev,
        hw->init = &init;
        /* register the clock */
-        clk = clk_register(dev, hw);
+        ret = clk_hw_register(dev, hw);
+        if (ret) {
-        if (IS_ERR(clk))
                kfree(hw);
+                hw = ERR_PTR(ret);
+        }
-        return clk;
+        return hw;
 }
 static const char * const cpu_parents[] = { "cpu_clk_div", "osc_33m_clk", };
@@ -86,14 +87,14 @@ static const char * const dc_parents[] = { "dc_clk_div", "osc_33m_clk", };
 void __init ls1x_clk_init(void)
 {
-        struct clk *clk;
+        struct clk_hw *hw;
-        clk = clk_register_fixed_rate(NULL, "osc_33m_clk", NULL, 0, OSC);
+        hw = clk_hw_register_fixed_rate(NULL, "osc_33m_clk", NULL, 0, OSC);
-        clk_register_clkdev(clk, "osc_33m_clk", NULL);
+        clk_hw_register_clkdev(hw, "osc_33m_clk", NULL);
        /* clock derived from 33 MHz OSC clk */
-        clk = clk_register_pll(NULL, "pll_clk", "osc_33m_clk", 0);
+        hw = clk_hw_register_pll(NULL, "pll_clk", "osc_33m_clk", 0);
-        clk_register_clkdev(clk, "pll_clk", NULL);
+        clk_hw_register_clkdev(hw, "pll_clk", NULL);
        /* clock derived from PLL clk */
        /*                                 _____
@@ -102,17 +103,17 @@ void __init ls1x_clk_init(void)
         *        \___ PLL ___ CPU DIV ___|     |
         *                                |_____|
         */
-        clk = clk_register_divider(NULL, "cpu_clk_div", "pll_clk",
+        hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk",
                                   CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
                                   DIV_CPU_SHIFT, DIV_CPU_WIDTH,
                                   CLK_DIVIDER_ONE_BASED |
                                   CLK_DIVIDER_ROUND_CLOSEST, &_lock);
-        clk_register_clkdev(clk, "cpu_clk_div", NULL);
+        clk_hw_register_clkdev(hw, "cpu_clk_div", NULL);
-        clk = clk_register_mux(NULL, "cpu_clk", cpu_parents,
+        hw = clk_hw_register_mux(NULL, "cpu_clk", cpu_parents,
                               ARRAY_SIZE(cpu_parents),
                               CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
                               BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, &_lock);
-        clk_register_clkdev(clk, "cpu_clk", NULL);
+        clk_hw_register_clkdev(hw, "cpu_clk", NULL);
        /*                                 _____
         *         _______________________|     |
@@ -120,15 +121,15 @@ void __init ls1x_clk_init(void)
         *        \___ PLL ___ DC  DIV ___|     |
         *                                |_____|
         */
-        clk = clk_register_divider(NULL, "dc_clk_div", "pll_clk",
+        hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk",
                                   0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
                                   DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
-        clk_register_clkdev(clk, "dc_clk_div", NULL);
+        clk_hw_register_clkdev(hw, "dc_clk_div", NULL);
-        clk = clk_register_mux(NULL, "dc_clk", dc_parents,
+        hw = clk_hw_register_mux(NULL, "dc_clk", dc_parents,
                               ARRAY_SIZE(dc_parents),
                               CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
                               BYPASS_DC_SHIFT, BYPASS_DC_WIDTH, 0, &_lock);
-        clk_register_clkdev(clk, "dc_clk", NULL);
+        clk_hw_register_clkdev(hw, "dc_clk", NULL);
        /*                                 _____
         *         _______________________|     |
@@ -136,26 +137,26 @@ void __init ls1x_clk_init(void)
         *        \___ PLL ___ DDR DIV ___|     |
         *                                |_____|
         */
-        clk = clk_register_divider(NULL, "ahb_clk_div", "pll_clk",
+        hw = clk_hw_register_divider(NULL, "ahb_clk_div", "pll_clk",
                                   0, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
                                   DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED,
                                   &_lock);
-        clk_register_clkdev(clk, "ahb_clk_div", NULL);
+        clk_hw_register_clkdev(hw, "ahb_clk_div", NULL);
-        clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
+        hw = clk_hw_register_mux(NULL, "ahb_clk", ahb_parents,
                               ARRAY_SIZE(ahb_parents),
                               CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
                               BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock);
-        clk_register_clkdev(clk, "ahb_clk", NULL);
+        clk_hw_register_clkdev(hw, "ahb_clk", NULL);
-        clk_register_clkdev(clk, "stmmaceth", NULL);
+        clk_hw_register_clkdev(hw, "stmmaceth", NULL);
        /* clock derived from AHB clk */
        /* APB clk is always half of the AHB clk */
-        clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
+        hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
                                        DIV_APB);
-        clk_register_clkdev(clk, "apb_clk", NULL);
+        clk_hw_register_clkdev(hw, "apb_clk", NULL);
-        clk_register_clkdev(clk, "ls1x_i2c", NULL);
+        clk_hw_register_clkdev(hw, "ls1x_i2c", NULL);
-        clk_register_clkdev(clk, "ls1x_pwmtimer", NULL);
+        clk_hw_register_clkdev(hw, "ls1x_pwmtimer", NULL);
-        clk_register_clkdev(clk, "ls1x_spi", NULL);
+        clk_hw_register_clkdev(hw, "ls1x_spi", NULL);
-        clk_register_clkdev(clk, "ls1x_wdt", NULL);
+        clk_hw_register_clkdev(hw, "ls1x_wdt", NULL);
-        clk_register_clkdev(clk, "serial8250", NULL);
+        clk_hw_register_clkdev(hw, "serial8250", NULL);
 }

diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c index 5097831387ff..8430e45427f4 100644 --- a/drivers/clk/clk-ls1x.c +++ b/drivers/clk/clk-ls1x.c
@@ -48,13 +48,13 @@ static const struct clk_ops ls1x_pll_clk_ops = {
48	.recalc_rate = ls1x_pll_recalc_rate,	48	.recalc_rate = ls1x_pll_recalc_rate,
49	};	49	};
50		50
51	static struct clk __init clk_register_pll(struct device dev,	51	static struct clk_hw __init clk_hw_register_pll(struct device dev,
52	const char *name,	52	const char *name,
53	const char *parent_name,	53	const char *parent_name,
54	unsigned long flags)	54	unsigned long flags)
55	{	55	{
		56	int ret;
56	struct clk_hw *hw;	57	struct clk_hw *hw;
57	struct clk *clk;
58	struct clk_init_data init;	58	struct clk_init_data init;
59		59
60	/* allocate the divider */	60	/* allocate the divider */
@@ -72,12 +72,13 @@ static struct clk __init clk_register_pll(struct device dev,
72	hw->init = &init;	72	hw->init = &init;
73		73
74	/* register the clock */	74	/* register the clock */
75	clk = clk_register(dev, hw);	75	ret = clk_hw_register(dev, hw);
76		76	if (ret) {
77	if (IS_ERR(clk))
78	kfree(hw);	77	kfree(hw);
		78	hw = ERR_PTR(ret);
		79	}
79		80
80	return clk;	81	return hw;
81	}	82	}
82		83
83	static const char * const cpu_parents[] = { "cpu_clk_div", "osc_33m_clk", };	84	static const char * const cpu_parents[] = { "cpu_clk_div", "osc_33m_clk", };
@@ -86,14 +87,14 @@ static const char * const dc_parents[] = { "dc_clk_div", "osc_33m_clk", };
86		87
87	void __init ls1x_clk_init(void)	88	void __init ls1x_clk_init(void)
88	{	89	{
89	struct clk *clk;	90	struct clk_hw *hw;
90		91
91	clk = clk_register_fixed_rate(NULL, "osc_33m_clk", NULL, 0, OSC);	92	hw = clk_hw_register_fixed_rate(NULL, "osc_33m_clk", NULL, 0, OSC);
92	clk_register_clkdev(clk, "osc_33m_clk", NULL);	93	clk_hw_register_clkdev(hw, "osc_33m_clk", NULL);
93		94
94	/* clock derived from 33 MHz OSC clk */	95	/* clock derived from 33 MHz OSC clk */
95	clk = clk_register_pll(NULL, "pll_clk", "osc_33m_clk", 0);	96	hw = clk_hw_register_pll(NULL, "pll_clk", "osc_33m_clk", 0);
96	clk_register_clkdev(clk, "pll_clk", NULL);	97	clk_hw_register_clkdev(hw, "pll_clk", NULL);
97		98
98	/* clock derived from PLL clk */	99	/* clock derived from PLL clk */
99	/* _____	100	/* _____
@@ -102,17 +103,17 @@ void __init ls1x_clk_init(void)
102	* \___ PLL ___ CPU DIV ___\| \|	103	* \___ PLL ___ CPU DIV ___\| \|
103	* \|_____\|	104	* \|_____\|
104	*/	105	*/
105	clk = clk_register_divider(NULL, "cpu_clk_div", "pll_clk",	106	hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk",
106	CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,	107	CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
107	DIV_CPU_SHIFT, DIV_CPU_WIDTH,	108	DIV_CPU_SHIFT, DIV_CPU_WIDTH,
108	CLK_DIVIDER_ONE_BASED \|	109	CLK_DIVIDER_ONE_BASED \|
109	CLK_DIVIDER_ROUND_CLOSEST, &_lock);	110	CLK_DIVIDER_ROUND_CLOSEST, &_lock);
110	clk_register_clkdev(clk, "cpu_clk_div", NULL);	111	clk_hw_register_clkdev(hw, "cpu_clk_div", NULL);
111	clk = clk_register_mux(NULL, "cpu_clk", cpu_parents,	112	hw = clk_hw_register_mux(NULL, "cpu_clk", cpu_parents,
112	ARRAY_SIZE(cpu_parents),	113	ARRAY_SIZE(cpu_parents),
113	CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,	114	CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
114	BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, &_lock);	115	BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, &_lock);
115	clk_register_clkdev(clk, "cpu_clk", NULL);	116	clk_hw_register_clkdev(hw, "cpu_clk", NULL);
116		117
117	/* _____	118	/* _____
118	* _______________________\| \|	119	* _______________________\| \|
@@ -120,15 +121,15 @@ void __init ls1x_clk_init(void)
120	* \___ PLL ___ DC DIV ___\| \|	121	* \___ PLL ___ DC DIV ___\| \|
121	* \|_____\|	122	* \|_____\|
122	*/	123	*/
123	clk = clk_register_divider(NULL, "dc_clk_div", "pll_clk",	124	hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk",
124	0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,	125	0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
125	DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);	126	DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
126	clk_register_clkdev(clk, "dc_clk_div", NULL);	127	clk_hw_register_clkdev(hw, "dc_clk_div", NULL);
127	clk = clk_register_mux(NULL, "dc_clk", dc_parents,	128	hw = clk_hw_register_mux(NULL, "dc_clk", dc_parents,
128	ARRAY_SIZE(dc_parents),	129	ARRAY_SIZE(dc_parents),
129	CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,	130	CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
130	BYPASS_DC_SHIFT, BYPASS_DC_WIDTH, 0, &_lock);	131	BYPASS_DC_SHIFT, BYPASS_DC_WIDTH, 0, &_lock);
131	clk_register_clkdev(clk, "dc_clk", NULL);	132	clk_hw_register_clkdev(hw, "dc_clk", NULL);
132		133
133	/* _____	134	/* _____
134	* _______________________\| \|	135	* _______________________\| \|
@@ -136,26 +137,26 @@ void __init ls1x_clk_init(void)
136	* \___ PLL ___ DDR DIV ___\| \|	137	* \___ PLL ___ DDR DIV ___\| \|
137	* \|_____\|	138	* \|_____\|
138	*/	139	*/
139	clk = clk_register_divider(NULL, "ahb_clk_div", "pll_clk",	140	hw = clk_hw_register_divider(NULL, "ahb_clk_div", "pll_clk",
140	0, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,	141	0, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
141	DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED,	142	DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED,
142	&_lock);	143	&_lock);
143	clk_register_clkdev(clk, "ahb_clk_div", NULL);	144	clk_hw_register_clkdev(hw, "ahb_clk_div", NULL);
144	clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,	145	hw = clk_hw_register_mux(NULL, "ahb_clk", ahb_parents,
145	ARRAY_SIZE(ahb_parents),	146	ARRAY_SIZE(ahb_parents),
146	CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,	147	CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
147	BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock);	148	BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock);
148	clk_register_clkdev(clk, "ahb_clk", NULL);	149	clk_hw_register_clkdev(hw, "ahb_clk", NULL);
149	clk_register_clkdev(clk, "stmmaceth", NULL);	150	clk_hw_register_clkdev(hw, "stmmaceth", NULL);
150		151
151	/* clock derived from AHB clk */	152	/* clock derived from AHB clk */
152	/* APB clk is always half of the AHB clk */	153	/* APB clk is always half of the AHB clk */
153	clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,	154	hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
154	DIV_APB);	155	DIV_APB);
155	clk_register_clkdev(clk, "apb_clk", NULL);	156	clk_hw_register_clkdev(hw, "apb_clk", NULL);
156	clk_register_clkdev(clk, "ls1x_i2c", NULL);	157	clk_hw_register_clkdev(hw, "ls1x_i2c", NULL);
157	clk_register_clkdev(clk, "ls1x_pwmtimer", NULL);	158	clk_hw_register_clkdev(hw, "ls1x_pwmtimer", NULL);
158	clk_register_clkdev(clk, "ls1x_spi", NULL);	159	clk_hw_register_clkdev(hw, "ls1x_spi", NULL);
159	clk_register_clkdev(clk, "ls1x_wdt", NULL);	160	clk_hw_register_clkdev(hw, "ls1x_wdt", NULL);
160	clk_register_clkdev(clk, "serial8250", NULL);	161	clk_hw_register_clkdev(hw, "serial8250", NULL);
161	}	162	}