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-rw-r--r--drivers/clk/mvebu/common.c11
-rw-r--r--drivers/clk/mvebu/dove-divider.c3
2 files changed, 6 insertions, 8 deletions
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index daa6ebdac131..66be2e0c82b4 100644
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -137,8 +137,8 @@ void __init mvebu_coreclk_setup(struct device_node *np,
137 of_property_read_string_index(np, "clock-output-names", 0, 137 of_property_read_string_index(np, "clock-output-names", 0,
138 &tclk_name); 138 &tclk_name);
139 rate = desc->get_tclk_freq(base); 139 rate = desc->get_tclk_freq(base);
140 clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL, 140 clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL, 0,
141 CLK_IS_ROOT, rate); 141 rate);
142 WARN_ON(IS_ERR(clk_data.clks[0])); 142 WARN_ON(IS_ERR(clk_data.clks[0]));
143 143
144 /* Register CPU clock */ 144 /* Register CPU clock */
@@ -150,8 +150,8 @@ void __init mvebu_coreclk_setup(struct device_node *np,
150 && desc->is_sscg_enabled(base)) 150 && desc->is_sscg_enabled(base))
151 rate = desc->fix_sscg_deviation(rate); 151 rate = desc->fix_sscg_deviation(rate);
152 152
153 clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL, 153 clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL, 0,
154 CLK_IS_ROOT, rate); 154 rate);
155 WARN_ON(IS_ERR(clk_data.clks[1])); 155 WARN_ON(IS_ERR(clk_data.clks[1]));
156 156
157 /* Register fixed-factor clocks derived from CPU clock */ 157 /* Register fixed-factor clocks derived from CPU clock */
@@ -174,8 +174,7 @@ void __init mvebu_coreclk_setup(struct device_node *np,
174 2 + desc->num_ratios, &name); 174 2 + desc->num_ratios, &name);
175 rate = desc->get_refclk_freq(base); 175 rate = desc->get_refclk_freq(base);
176 clk_data.clks[2 + desc->num_ratios] = 176 clk_data.clks[2 + desc->num_ratios] =
177 clk_register_fixed_rate(NULL, name, NULL, 177 clk_register_fixed_rate(NULL, name, NULL, 0, rate);
178 CLK_IS_ROOT, rate);
179 WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios])); 178 WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
180 } 179 }
181 180
diff --git a/drivers/clk/mvebu/dove-divider.c b/drivers/clk/mvebu/dove-divider.c
index 3e0b52daa35f..4091f3cfee19 100644
--- a/drivers/clk/mvebu/dove-divider.c
+++ b/drivers/clk/mvebu/dove-divider.c
@@ -225,8 +225,7 @@ static int dove_divider_init(struct device *dev, void __iomem *base,
225 * Create the core PLL clock. We treat this as a fixed rate 225 * Create the core PLL clock. We treat this as a fixed rate
226 * clock as we don't know any better, and documentation is sparse. 226 * clock as we don't know any better, and documentation is sparse.
227 */ 227 */
228 clk = clk_register_fixed_rate(dev, core_pll[0], NULL, CLK_IS_ROOT, 228 clk = clk_register_fixed_rate(dev, core_pll[0], NULL, 0, 2000000000UL);
229 2000000000UL);
230 if (IS_ERR(clk)) 229 if (IS_ERR(clk))
231 return PTR_ERR(clk); 230 return PTR_ERR(clk);
232 231