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-rw-r--r--drivers/clk/samsung/clk-exynos5250.c290
1 files changed, 188 insertions, 102 deletions
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index e52359cf9b6f..84dd55fc0fc0 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -66,6 +66,7 @@
66#define DIV_PERIC4 0x10568 66#define DIV_PERIC4 0x10568
67#define DIV_PERIC5 0x1056c 67#define DIV_PERIC5 0x1056c
68#define GATE_IP_GSCL 0x10920 68#define GATE_IP_GSCL 0x10920
69#define GATE_IP_DISP1 0x10928
69#define GATE_IP_MFC 0x1092c 70#define GATE_IP_MFC 0x1092c
70#define GATE_IP_GEN 0x10934 71#define GATE_IP_GEN 0x10934
71#define GATE_IP_FSYS 0x10944 72#define GATE_IP_FSYS 0x10944
@@ -75,7 +76,6 @@
75#define BPLL_CON0 0x20110 76#define BPLL_CON0 0x20110
76#define SRC_CDREX 0x20200 77#define SRC_CDREX 0x20200
77#define PLL_DIV2_SEL 0x20a24 78#define PLL_DIV2_SEL 0x20a24
78#define GATE_IP_DISP1 0x10928
79 79
80/* list of PLLs to be registered */ 80/* list of PLLs to be registered */
81enum exynos5250_plls { 81enum exynos5250_plls {
@@ -239,111 +239,250 @@ static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
239}; 239};
240 240
241static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { 241static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
242 /*
243 * NOTE: Following table is sorted by (clock domain, register address,
244 * bitfield shift) triplet in ascending order. When adding new entries,
245 * please make sure that the order is kept, to avoid merge conflicts
246 * and make further work with defined data easier.
247 */
248
249 /*
250 * CMU_CPU
251 */
242 MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"), 252 MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"),
243 MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), 253 MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
244 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), 254
255 /*
256 * CMU_CORE
257 */
245 MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), 258 MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
246 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), 259
247 MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1), 260 /*
248 MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1), 261 * CMU_TOP
249 MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1), 262 */
263 MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
264 MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
265 MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
266
250 MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1), 267 MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
268 MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1),
269 MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
251 MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1), 270 MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
252 MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), 271 MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
253 MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), 272
254 MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
255 MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
256 MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), 273 MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
257 MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4), 274 MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
258 MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4), 275 MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
259 MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4), 276 MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
260 MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4), 277 MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
278
261 MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4), 279 MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
262 MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4), 280 MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
263 MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4), 281 MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
264 MUX(mout_hdmi, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1), 282 MUX(mout_hdmi, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
283
265 MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4), 284 MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
285
266 MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4), 286 MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
267 MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4), 287 MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
268 MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4), 288 MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
269 MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4), 289 MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
270 MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1), 290 MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
271 MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1), 291 MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
292
272 MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4), 293 MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
294
273 MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4), 295 MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
274 MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4), 296 MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
275 MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4), 297 MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
276 MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4), 298 MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
277 MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4), 299 MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
300
278 MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4), 301 MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
279 MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4), 302 MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
280 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2), 303 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
281 MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4), 304 MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
282 MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4), 305 MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
283 MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4), 306 MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
307
308 /*
309 * CMU_CDREX
310 */
311 MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
312
313 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
314 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
284}; 315};
285 316
286static struct samsung_div_clock exynos5250_div_clks[] __initdata = { 317static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
318 /*
319 * NOTE: Following table is sorted by (clock domain, register address,
320 * bitfield shift) triplet in ascending order. When adding new entries,
321 * please make sure that the order is kept, to avoid merge conflicts
322 * and make further work with defined data easier.
323 */
324
325 /*
326 * CMU_CPU
327 */
287 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 328 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
288 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 329 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
289 DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3), 330 DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
331
332 /*
333 * CMU_TOP
334 */
290 DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3), 335 DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
291 DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3),
292 DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3), 336 DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
293 DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
294 DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3), 337 DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
338 DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3),
339 DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
340
341 DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3),
342
295 DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4), 343 DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
296 DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4), 344 DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
297 DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4), 345 DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
298 DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4), 346 DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
299 DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4), 347 DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
348
300 DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4), 349 DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
301 DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4), 350 DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
351 DIV_F(none, "div_mipi1_pre", "div_mipi1",
352 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
302 DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4), 353 DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
354 DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
355
303 DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4), 356 DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
357
304 DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4), 358 DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
305 DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), 359 DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
360
306 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 361 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
307 DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4), 362 DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
363
308 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 364 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
365 DIV_F(none, "div_mmc_pre0", "div_mmc0",
366 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
309 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 367 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
368 DIV_F(none, "div_mmc_pre1", "div_mmc1",
369 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
370
310 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 371 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
372 DIV_F(none, "div_mmc_pre2", "div_mmc2",
373 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
311 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 374 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
375 DIV_F(none, "div_mmc_pre3", "div_mmc3",
376 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
377
312 DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4), 378 DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
313 DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4), 379 DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
314 DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4), 380 DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
315 DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4), 381 DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
382
316 DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4), 383 DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
384 DIV_F(none, "div_spi_pre0", "div_spi0",
385 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
317 DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4), 386 DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
387 DIV_F(none, "div_spi_pre1", "div_spi1",
388 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
389
318 DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4), 390 DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
391 DIV_F(none, "div_spi_pre2", "div_spi2",
392 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
393
319 DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4), 394 DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
395
320 DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4), 396 DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
321 DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8), 397 DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
322 DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4), 398 DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
323 DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8), 399 DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
400
324 DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6), 401 DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
325 DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6), 402 DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
326 DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
327 DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
328 DIV_F(none, "div_mipi1_pre", "div_mipi1",
329 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
330 DIV_F(none, "div_mmc_pre0", "div_mmc0",
331 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
332 DIV_F(none, "div_mmc_pre1", "div_mmc1",
333 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
334 DIV_F(none, "div_mmc_pre2", "div_mmc2",
335 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
336 DIV_F(none, "div_mmc_pre3", "div_mmc3",
337 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
338 DIV_F(none, "div_spi_pre0", "div_spi0",
339 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
340 DIV_F(none, "div_spi_pre1", "div_spi1",
341 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
342 DIV_F(none, "div_spi_pre2", "div_spi2",
343 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
344}; 403};
345 404
346static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { 405static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
406 /*
407 * NOTE: Following table is sorted by (clock domain, register address,
408 * bitfield shift) triplet in ascending order. When adding new entries,
409 * please make sure that the order is kept, to avoid merge conflicts
410 * and make further work with defined data easier.
411 */
412
413 /*
414 * CMU_ACP
415 */
416 GATE(mdma0, "mdma0", "aclk266", GATE_IP_ACP, 1, 0, 0),
417 GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
418 GATE(smmu_mdma0, "smmu_mdma0", "aclk266", GATE_IP_ACP, 5, 0, 0),
419
420 /*
421 * CMU_TOP
422 */
423 GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer",
424 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
425 GATE(sclk_cam0, "sclk_cam0", "div_cam0",
426 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
427 GATE(sclk_cam1, "sclk_cam1", "div_cam1",
428 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
429 GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa",
430 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
431 GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb",
432 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
433
434 GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1",
435 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
436 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1",
437 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
438 GATE(sclk_dp, "sclk_dp", "div_dp",
439 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
440 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
441 SRC_MASK_DISP1_0, 20, 0, 0),
442
443 GATE(sclk_audio0, "sclk_audio0", "div_audio0",
444 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
445
446 GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0",
447 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
448 GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1",
449 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
450 GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2",
451 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
452 GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3",
453 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
454 GATE(sclk_sata, "sclk_sata", "div_sata",
455 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
456 GATE(sclk_usb3, "sclk_usb3", "div_usb3",
457 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
458
459 GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg",
460 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
461
462 GATE(sclk_uart0, "sclk_uart0", "div_uart0",
463 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
464 GATE(sclk_uart1, "sclk_uart1", "div_uart1",
465 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
466 GATE(sclk_uart2, "sclk_uart2", "div_uart2",
467 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
468 GATE(sclk_uart3, "sclk_uart3", "div_uart3",
469 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
470 GATE(sclk_pwm, "sclk_pwm", "div_pwm",
471 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
472
473 GATE(sclk_audio1, "sclk_audio1", "div_audio1",
474 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
475 GATE(sclk_audio2, "sclk_audio2", "div_audio2",
476 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
477 GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
478 SRC_MASK_PERIC1, 4, 0, 0),
479 GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0",
480 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
481 GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1",
482 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
483 GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2",
484 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
485
347 GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0), 486 GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0),
348 GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0), 487 GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0),
349 GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0), 488 GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0),
@@ -354,15 +493,25 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
354 GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0), 493 GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0),
355 GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0), 494 GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
356 GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0), 495 GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
496
497 GATE(fimd1, "fimd1", "aclk200", GATE_IP_DISP1, 0, 0, 0),
498 GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0),
499 GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0),
500 GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
501 GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
502 GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
503
357 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 504 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
358 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 2, 0, 0),
359 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 1, 0, 0), 505 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 1, 0, 0),
506 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 2, 0, 0),
507
360 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), 508 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
361 GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0), 509 GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0),
362 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0), 510 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
363 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0), 511 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
364 GATE(smmu_jpeg, "smmu_jpeg", "aclk166", GATE_IP_GEN, 7, 0, 0), 512 GATE(smmu_jpeg, "smmu_jpeg", "aclk166", GATE_IP_GEN, 7, 0, 0),
365 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0), 513 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
514
366 GATE(pdma0, "pdma0", "aclk200", GATE_IP_FSYS, 1, 0, 0), 515 GATE(pdma0, "pdma0", "aclk200", GATE_IP_FSYS, 1, 0, 0),
367 GATE(pdma1, "pdma1", "aclk200", GATE_IP_FSYS, 2, 0, 0), 516 GATE(pdma1, "pdma1", "aclk200", GATE_IP_FSYS, 2, 0, 0),
368 GATE(sata, "sata", "aclk200", GATE_IP_FSYS, 6, 0, 0), 517 GATE(sata, "sata", "aclk200", GATE_IP_FSYS, 6, 0, 0),
@@ -377,6 +526,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
377 GATE(usb3, "usb3", "aclk200", GATE_IP_FSYS, 19, 0, 0), 526 GATE(usb3, "usb3", "aclk200", GATE_IP_FSYS, 19, 0, 0),
378 GATE(sata_phyctrl, "sata_phyctrl", "aclk200", GATE_IP_FSYS, 24, 0, 0), 527 GATE(sata_phyctrl, "sata_phyctrl", "aclk200", GATE_IP_FSYS, 24, 0, 0),
379 GATE(sata_phyi2c, "sata_phyi2c", "aclk200", GATE_IP_FSYS, 25, 0, 0), 528 GATE(sata_phyi2c, "sata_phyi2c", "aclk200", GATE_IP_FSYS, 25, 0, 0),
529
380 GATE(uart0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0), 530 GATE(uart0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
381 GATE(uart1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0), 531 GATE(uart1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
382 GATE(uart2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0), 532 GATE(uart2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
@@ -406,10 +556,17 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
406 GATE(hsi2c1, "hsi2c1", "aclk66", GATE_IP_PERIC, 29, 0, 0), 556 GATE(hsi2c1, "hsi2c1", "aclk66", GATE_IP_PERIC, 29, 0, 0),
407 GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0), 557 GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
408 GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0), 558 GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
559
409 GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0), 560 GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
410 GATE(sysreg, "sysreg", "aclk66", 561 GATE(sysreg, "sysreg", "aclk66",
411 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 562 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
412 GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0), 563 GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
564 GATE(cmu_top, "cmu_top", "aclk66",
565 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
566 GATE(cmu_core, "cmu_core", "aclk66",
567 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
568 GATE(cmu_mem, "cmu_mem", "aclk66",
569 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
413 GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0), 570 GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
414 GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0), 571 GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
415 GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0), 572 GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0),
@@ -425,77 +582,6 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
425 GATE(wdt, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0), 582 GATE(wdt, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
426 GATE(rtc, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0), 583 GATE(rtc, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
427 GATE(tmu, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0), 584 GATE(tmu, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
428 GATE(cmu_top, "cmu_top", "aclk66",
429 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
430 GATE(cmu_core, "cmu_core", "aclk66",
431 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
432 GATE(cmu_mem, "cmu_mem", "aclk66",
433 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
434 GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer",
435 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
436 GATE(sclk_cam0, "sclk_cam0", "div_cam0",
437 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
438 GATE(sclk_cam1, "sclk_cam1", "div_cam1",
439 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
440 GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa",
441 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
442 GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb",
443 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
444 GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1",
445 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
446 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1",
447 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
448 GATE(sclk_dp, "sclk_dp", "div_dp",
449 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
450 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
451 SRC_MASK_DISP1_0, 20, 0, 0),
452 GATE(sclk_audio0, "sclk_audio0", "div_audio0",
453 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
454 GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0",
455 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
456 GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1",
457 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
458 GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2",
459 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
460 GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3",
461 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
462 GATE(sclk_sata, "sclk_sata", "div_sata",
463 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
464 GATE(sclk_usb3, "sclk_usb3", "div_usb3",
465 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
466 GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg",
467 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
468 GATE(sclk_uart0, "sclk_uart0", "div_uart0",
469 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
470 GATE(sclk_uart1, "sclk_uart1", "div_uart1",
471 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
472 GATE(sclk_uart2, "sclk_uart2", "div_uart2",
473 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
474 GATE(sclk_uart3, "sclk_uart3", "div_uart3",
475 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
476 GATE(sclk_pwm, "sclk_pwm", "div_pwm",
477 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
478 GATE(sclk_audio1, "sclk_audio1", "div_audio1",
479 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
480 GATE(sclk_audio2, "sclk_audio2", "div_audio2",
481 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
482 GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
483 SRC_MASK_PERIC1, 4, 0, 0),
484 GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0",
485 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
486 GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1",
487 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
488 GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2",
489 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
490 GATE(fimd1, "fimd1", "aclk200", GATE_IP_DISP1, 0, 0, 0),
491 GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0),
492 GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0),
493 GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
494 GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
495 GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
496 GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
497 GATE(mdma0, "mdma0", "aclk266", GATE_IP_ACP, 1, 0, 0),
498 GATE(smmu_mdma0, "smmu_mdma0", "aclk266", GATE_IP_ACP, 5, 0, 0),
499}; 585};
500 586
501static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { 587static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 01:25:06 -0500