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-rw-r--r--drivers/video/via/hw.c296
-rw-r--r--drivers/video/via/hw.h273
-rw-r--r--drivers/video/via/share.h19
-rw-r--r--drivers/video/via/via_modesetting.c100
-rw-r--r--drivers/video/via/via_modesetting.h18
5 files changed, 128 insertions, 578 deletions
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 47b13535ed2b..372ce4f071c2 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -191,67 +191,6 @@ static struct fetch_count fetch_count_reg = {
191 {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } } 191 {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
192}; 192};
193 193
194static struct iga1_crtc_timing iga1_crtc_reg = {
195 /* IGA1 Horizontal Total */
196 {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
197 /* IGA1 Horizontal Addressable Video */
198 {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
199 /* IGA1 Horizontal Blank Start */
200 {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
201 /* IGA1 Horizontal Blank End */
202 {IGA1_HOR_BLANK_END_REG_NUM,
203 {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
204 /* IGA1 Horizontal Sync Start */
205 {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
206 /* IGA1 Horizontal Sync End */
207 {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
208 /* IGA1 Vertical Total */
209 {IGA1_VER_TOTAL_REG_NUM,
210 {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
211 /* IGA1 Vertical Addressable Video */
212 {IGA1_VER_ADDR_REG_NUM,
213 {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
214 /* IGA1 Vertical Blank Start */
215 {IGA1_VER_BLANK_START_REG_NUM,
216 {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
217 /* IGA1 Vertical Blank End */
218 {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
219 /* IGA1 Vertical Sync Start */
220 {IGA1_VER_SYNC_START_REG_NUM,
221 {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
222 /* IGA1 Vertical Sync End */
223 {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
224};
225
226static struct iga2_crtc_timing iga2_crtc_reg = {
227 /* IGA2 Horizontal Total */
228 {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
229 /* IGA2 Horizontal Addressable Video */
230 {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
231 /* IGA2 Horizontal Blank Start */
232 {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
233 /* IGA2 Horizontal Blank End */
234 {IGA2_HOR_BLANK_END_REG_NUM,
235 {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
236 /* IGA2 Horizontal Sync Start */
237 {IGA2_HOR_SYNC_START_REG_NUM,
238 {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
239 /* IGA2 Horizontal Sync End */
240 {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
241 /* IGA2 Vertical Total */
242 {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
243 /* IGA2 Vertical Addressable Video */
244 {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
245 /* IGA2 Vertical Blank Start */
246 {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
247 /* IGA2 Vertical Blank End */
248 {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
249 /* IGA2 Vertical Sync Start */
250 {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
251 /* IGA2 Vertical Sync End */
252 {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
253};
254
255static struct rgbLUT palLUT_table[] = { 194static struct rgbLUT palLUT_table[] = {
256 /* {R,G,B} */ 195 /* {R,G,B} */
257 /* Index 0x00~0x03 */ 196 /* Index 0x00~0x03 */
@@ -1531,234 +1470,15 @@ void viafb_set_vclock(u32 clk, int set_iga)
1531void viafb_load_crtc_timing(struct display_timing device_timing, 1470void viafb_load_crtc_timing(struct display_timing device_timing,
1532 int set_iga) 1471 int set_iga)
1533{ 1472{
1534 int i; 1473 device_timing.hor_blank_end += device_timing.hor_blank_start;
1535 int viafb_load_reg_num = 0; 1474 device_timing.hor_sync_end += device_timing.hor_sync_start;
1536 int reg_value = 0; 1475 device_timing.ver_blank_end += device_timing.ver_blank_start;
1537 struct io_register *reg = NULL; 1476 device_timing.ver_sync_end += device_timing.ver_sync_start;
1538
1539 viafb_unlock_crt();
1540
1541 for (i = 0; i < 12; i++) {
1542 if (set_iga == IGA1) {
1543 switch (i) {
1544 case H_TOTAL_INDEX:
1545 reg_value =
1546 IGA1_HOR_TOTAL_FORMULA(device_timing.
1547 hor_total);
1548 viafb_load_reg_num =
1549 iga1_crtc_reg.hor_total.reg_num;
1550 reg = iga1_crtc_reg.hor_total.reg;
1551 break;
1552 case H_ADDR_INDEX:
1553 reg_value =
1554 IGA1_HOR_ADDR_FORMULA(device_timing.
1555 hor_addr);
1556 viafb_load_reg_num =
1557 iga1_crtc_reg.hor_addr.reg_num;
1558 reg = iga1_crtc_reg.hor_addr.reg;
1559 break;
1560 case H_BLANK_START_INDEX:
1561 reg_value =
1562 IGA1_HOR_BLANK_START_FORMULA
1563 (device_timing.hor_blank_start);
1564 viafb_load_reg_num =
1565 iga1_crtc_reg.hor_blank_start.reg_num;
1566 reg = iga1_crtc_reg.hor_blank_start.reg;
1567 break;
1568 case H_BLANK_END_INDEX:
1569 reg_value =
1570 IGA1_HOR_BLANK_END_FORMULA
1571 (device_timing.hor_blank_start,
1572 device_timing.hor_blank_end);
1573 viafb_load_reg_num =
1574 iga1_crtc_reg.hor_blank_end.reg_num;
1575 reg = iga1_crtc_reg.hor_blank_end.reg;
1576 break;
1577 case H_SYNC_START_INDEX:
1578 reg_value =
1579 IGA1_HOR_SYNC_START_FORMULA
1580 (device_timing.hor_sync_start);
1581 viafb_load_reg_num =
1582 iga1_crtc_reg.hor_sync_start.reg_num;
1583 reg = iga1_crtc_reg.hor_sync_start.reg;
1584 break;
1585 case H_SYNC_END_INDEX:
1586 reg_value =
1587 IGA1_HOR_SYNC_END_FORMULA
1588 (device_timing.hor_sync_start,
1589 device_timing.hor_sync_end);
1590 viafb_load_reg_num =
1591 iga1_crtc_reg.hor_sync_end.reg_num;
1592 reg = iga1_crtc_reg.hor_sync_end.reg;
1593 break;
1594 case V_TOTAL_INDEX:
1595 reg_value =
1596 IGA1_VER_TOTAL_FORMULA(device_timing.
1597 ver_total);
1598 viafb_load_reg_num =
1599 iga1_crtc_reg.ver_total.reg_num;
1600 reg = iga1_crtc_reg.ver_total.reg;
1601 break;
1602 case V_ADDR_INDEX:
1603 reg_value =
1604 IGA1_VER_ADDR_FORMULA(device_timing.
1605 ver_addr);
1606 viafb_load_reg_num =
1607 iga1_crtc_reg.ver_addr.reg_num;
1608 reg = iga1_crtc_reg.ver_addr.reg;
1609 break;
1610 case V_BLANK_START_INDEX:
1611 reg_value =
1612 IGA1_VER_BLANK_START_FORMULA
1613 (device_timing.ver_blank_start);
1614 viafb_load_reg_num =
1615 iga1_crtc_reg.ver_blank_start.reg_num;
1616 reg = iga1_crtc_reg.ver_blank_start.reg;
1617 break;
1618 case V_BLANK_END_INDEX:
1619 reg_value =
1620 IGA1_VER_BLANK_END_FORMULA
1621 (device_timing.ver_blank_start,
1622 device_timing.ver_blank_end);
1623 viafb_load_reg_num =
1624 iga1_crtc_reg.ver_blank_end.reg_num;
1625 reg = iga1_crtc_reg.ver_blank_end.reg;
1626 break;
1627 case V_SYNC_START_INDEX:
1628 reg_value =
1629 IGA1_VER_SYNC_START_FORMULA
1630 (device_timing.ver_sync_start);
1631 viafb_load_reg_num =
1632 iga1_crtc_reg.ver_sync_start.reg_num;
1633 reg = iga1_crtc_reg.ver_sync_start.reg;
1634 break;
1635 case V_SYNC_END_INDEX:
1636 reg_value =
1637 IGA1_VER_SYNC_END_FORMULA
1638 (device_timing.ver_sync_start,
1639 device_timing.ver_sync_end);
1640 viafb_load_reg_num =
1641 iga1_crtc_reg.ver_sync_end.reg_num;
1642 reg = iga1_crtc_reg.ver_sync_end.reg;
1643 break;
1644
1645 }
1646 }
1647
1648 if (set_iga == IGA2) {
1649 switch (i) {
1650 case H_TOTAL_INDEX:
1651 reg_value =
1652 IGA2_HOR_TOTAL_FORMULA(device_timing.
1653 hor_total);
1654 viafb_load_reg_num =
1655 iga2_crtc_reg.hor_total.reg_num;
1656 reg = iga2_crtc_reg.hor_total.reg;
1657 break;
1658 case H_ADDR_INDEX:
1659 reg_value =
1660 IGA2_HOR_ADDR_FORMULA(device_timing.
1661 hor_addr);
1662 viafb_load_reg_num =
1663 iga2_crtc_reg.hor_addr.reg_num;
1664 reg = iga2_crtc_reg.hor_addr.reg;
1665 break;
1666 case H_BLANK_START_INDEX:
1667 reg_value =
1668 IGA2_HOR_BLANK_START_FORMULA
1669 (device_timing.hor_blank_start);
1670 viafb_load_reg_num =
1671 iga2_crtc_reg.hor_blank_start.reg_num;
1672 reg = iga2_crtc_reg.hor_blank_start.reg;
1673 break;
1674 case H_BLANK_END_INDEX:
1675 reg_value =
1676 IGA2_HOR_BLANK_END_FORMULA
1677 (device_timing.hor_blank_start,
1678 device_timing.hor_blank_end);
1679 viafb_load_reg_num =
1680 iga2_crtc_reg.hor_blank_end.reg_num;
1681 reg = iga2_crtc_reg.hor_blank_end.reg;
1682 break;
1683 case H_SYNC_START_INDEX:
1684 reg_value =
1685 IGA2_HOR_SYNC_START_FORMULA
1686 (device_timing.hor_sync_start);
1687 if (UNICHROME_CN700 <=
1688 viaparinfo->chip_info->gfx_chip_name)
1689 viafb_load_reg_num =
1690 iga2_crtc_reg.hor_sync_start.
1691 reg_num;
1692 else
1693 viafb_load_reg_num = 3;
1694 reg = iga2_crtc_reg.hor_sync_start.reg;
1695 break;
1696 case H_SYNC_END_INDEX:
1697 reg_value =
1698 IGA2_HOR_SYNC_END_FORMULA
1699 (device_timing.hor_sync_start,
1700 device_timing.hor_sync_end);
1701 viafb_load_reg_num =
1702 iga2_crtc_reg.hor_sync_end.reg_num;
1703 reg = iga2_crtc_reg.hor_sync_end.reg;
1704 break;
1705 case V_TOTAL_INDEX:
1706 reg_value =
1707 IGA2_VER_TOTAL_FORMULA(device_timing.
1708 ver_total);
1709 viafb_load_reg_num =
1710 iga2_crtc_reg.ver_total.reg_num;
1711 reg = iga2_crtc_reg.ver_total.reg;
1712 break;
1713 case V_ADDR_INDEX:
1714 reg_value =
1715 IGA2_VER_ADDR_FORMULA(device_timing.
1716 ver_addr);
1717 viafb_load_reg_num =
1718 iga2_crtc_reg.ver_addr.reg_num;
1719 reg = iga2_crtc_reg.ver_addr.reg;
1720 break;
1721 case V_BLANK_START_INDEX:
1722 reg_value =
1723 IGA2_VER_BLANK_START_FORMULA
1724 (device_timing.ver_blank_start);
1725 viafb_load_reg_num =
1726 iga2_crtc_reg.ver_blank_start.reg_num;
1727 reg = iga2_crtc_reg.ver_blank_start.reg;
1728 break;
1729 case V_BLANK_END_INDEX:
1730 reg_value =
1731 IGA2_VER_BLANK_END_FORMULA
1732 (device_timing.ver_blank_start,
1733 device_timing.ver_blank_end);
1734 viafb_load_reg_num =
1735 iga2_crtc_reg.ver_blank_end.reg_num;
1736 reg = iga2_crtc_reg.ver_blank_end.reg;
1737 break;
1738 case V_SYNC_START_INDEX:
1739 reg_value =
1740 IGA2_VER_SYNC_START_FORMULA
1741 (device_timing.ver_sync_start);
1742 viafb_load_reg_num =
1743 iga2_crtc_reg.ver_sync_start.reg_num;
1744 reg = iga2_crtc_reg.ver_sync_start.reg;
1745 break;
1746 case V_SYNC_END_INDEX:
1747 reg_value =
1748 IGA2_VER_SYNC_END_FORMULA
1749 (device_timing.ver_sync_start,
1750 device_timing.ver_sync_end);
1751 viafb_load_reg_num =
1752 iga2_crtc_reg.ver_sync_end.reg_num;
1753 reg = iga2_crtc_reg.ver_sync_end.reg;
1754 break;
1755 1477
1756 } 1478 if (set_iga == IGA1)
1757 } 1479 via_set_primary_timing(&device_timing);
1758 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); 1480 else if (set_iga == IGA2)
1759 } 1481 via_set_secondary_timing(&device_timing);
1760
1761 viafb_lock_crt();
1762} 1482}
1763 1483
1764void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, 1484void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
diff --git a/drivers/video/via/hw.h b/drivers/video/via/hw.h
index c7239eb83bae..267c669be736 100644
--- a/drivers/video/via/hw.h
+++ b/drivers/video/via/hw.h
@@ -51,40 +51,6 @@
51#define VIA_HSYNC_NEGATIVE 0x01 51#define VIA_HSYNC_NEGATIVE 0x01
52#define VIA_VSYNC_NEGATIVE 0x02 52#define VIA_VSYNC_NEGATIVE 0x02
53 53
54/***************************************************
55* Definition IGA1 Design Method of CRTC Registers *
56****************************************************/
57#define IGA1_HOR_TOTAL_FORMULA(x) (((x)/8)-5)
58#define IGA1_HOR_ADDR_FORMULA(x) (((x)/8)-1)
59#define IGA1_HOR_BLANK_START_FORMULA(x) (((x)/8)-1)
60#define IGA1_HOR_BLANK_END_FORMULA(x, y) (((x+y)/8)-1)
61#define IGA1_HOR_SYNC_START_FORMULA(x) ((x)/8)
62#define IGA1_HOR_SYNC_END_FORMULA(x, y) ((x+y)/8)
63
64#define IGA1_VER_TOTAL_FORMULA(x) ((x)-2)
65#define IGA1_VER_ADDR_FORMULA(x) ((x)-1)
66#define IGA1_VER_BLANK_START_FORMULA(x) ((x)-1)
67#define IGA1_VER_BLANK_END_FORMULA(x, y) ((x+y)-1)
68#define IGA1_VER_SYNC_START_FORMULA(x) ((x)-1)
69#define IGA1_VER_SYNC_END_FORMULA(x, y) ((x+y)-1)
70
71/***************************************************
72** Definition IGA2 Design Method of CRTC Registers *
73****************************************************/
74#define IGA2_HOR_TOTAL_FORMULA(x) ((x)-1)
75#define IGA2_HOR_ADDR_FORMULA(x) ((x)-1)
76#define IGA2_HOR_BLANK_START_FORMULA(x) ((x)-1)
77#define IGA2_HOR_BLANK_END_FORMULA(x, y) ((x+y)-1)
78#define IGA2_HOR_SYNC_START_FORMULA(x) ((x)-1)
79#define IGA2_HOR_SYNC_END_FORMULA(x, y) ((x+y)-1)
80
81#define IGA2_VER_TOTAL_FORMULA(x) ((x)-1)
82#define IGA2_VER_ADDR_FORMULA(x) ((x)-1)
83#define IGA2_VER_BLANK_START_FORMULA(x) ((x)-1)
84#define IGA2_VER_BLANK_END_FORMULA(x, y) ((x+y)-1)
85#define IGA2_VER_SYNC_START_FORMULA(x) ((x)-1)
86#define IGA2_VER_SYNC_END_FORMULA(x, y) ((x+y)-1)
87
88/**********************************************************/ 54/**********************************************************/
89/* Definition IGA2 Design Method of CRTC Shadow Registers */ 55/* Definition IGA2 Design Method of CRTC Shadow Registers */
90/**********************************************************/ 56/**********************************************************/
@@ -97,33 +63,6 @@
97#define IGA2_VER_SYNC_START_SHADOW_FORMULA(x) (x) 63#define IGA2_VER_SYNC_START_SHADOW_FORMULA(x) (x)
98#define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y) (x+y) 64#define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y) (x+y)
99 65
100/* Define Register Number for IGA1 CRTC Timing */
101
102/* location: {CR00,0,7},{CR36,3,3} */
103#define IGA1_HOR_TOTAL_REG_NUM 2
104/* location: {CR01,0,7} */
105#define IGA1_HOR_ADDR_REG_NUM 1
106/* location: {CR02,0,7} */
107#define IGA1_HOR_BLANK_START_REG_NUM 1
108/* location: {CR03,0,4},{CR05,7,7},{CR33,5,5} */
109#define IGA1_HOR_BLANK_END_REG_NUM 3
110/* location: {CR04,0,7},{CR33,4,4} */
111#define IGA1_HOR_SYNC_START_REG_NUM 2
112/* location: {CR05,0,4} */
113#define IGA1_HOR_SYNC_END_REG_NUM 1
114/* location: {CR06,0,7},{CR07,0,0},{CR07,5,5},{CR35,0,0} */
115#define IGA1_VER_TOTAL_REG_NUM 4
116/* location: {CR12,0,7},{CR07,1,1},{CR07,6,6},{CR35,2,2} */
117#define IGA1_VER_ADDR_REG_NUM 4
118/* location: {CR15,0,7},{CR07,3,3},{CR09,5,5},{CR35,3,3} */
119#define IGA1_VER_BLANK_START_REG_NUM 4
120/* location: {CR16,0,7} */
121#define IGA1_VER_BLANK_END_REG_NUM 1
122/* location: {CR10,0,7},{CR07,2,2},{CR07,7,7},{CR35,1,1} */
123#define IGA1_VER_SYNC_START_REG_NUM 4
124/* location: {CR11,0,3} */
125#define IGA1_VER_SYNC_END_REG_NUM 1
126
127/* Define Register Number for IGA2 Shadow CRTC Timing */ 66/* Define Register Number for IGA2 Shadow CRTC Timing */
128 67
129/* location: {CR6D,0,7},{CR71,3,3} */ 68/* location: {CR6D,0,7},{CR71,3,3} */
@@ -143,37 +82,6 @@
143/* location: {CR76,0,3} */ 82/* location: {CR76,0,3} */
144#define IGA2_SHADOW_VER_SYNC_END_REG_NUM 1 83#define IGA2_SHADOW_VER_SYNC_END_REG_NUM 1
145 84
146/* Define Register Number for IGA2 CRTC Timing */
147
148/* location: {CR50,0,7},{CR55,0,3} */
149#define IGA2_HOR_TOTAL_REG_NUM 2
150/* location: {CR51,0,7},{CR55,4,6} */
151#define IGA2_HOR_ADDR_REG_NUM 2
152/* location: {CR52,0,7},{CR54,0,2} */
153#define IGA2_HOR_BLANK_START_REG_NUM 2
154/* location: CLE266: {CR53,0,7},{CR54,3,5} => CLE266's CR5D[6]
155is reserved, so it may have problem to set 1600x1200 on IGA2. */
156/* Others: {CR53,0,7},{CR54,3,5},{CR5D,6,6} */
157#define IGA2_HOR_BLANK_END_REG_NUM 3
158/* location: {CR56,0,7},{CR54,6,7},{CR5C,7,7} */
159/* VT3314 and Later: {CR56,0,7},{CR54,6,7},{CR5C,7,7}, {CR5D,7,7} */
160#define IGA2_HOR_SYNC_START_REG_NUM 4
161
162/* location: {CR57,0,7},{CR5C,6,6} */
163#define IGA2_HOR_SYNC_END_REG_NUM 2
164/* location: {CR58,0,7},{CR5D,0,2} */
165#define IGA2_VER_TOTAL_REG_NUM 2
166/* location: {CR59,0,7},{CR5D,3,5} */
167#define IGA2_VER_ADDR_REG_NUM 2
168/* location: {CR5A,0,7},{CR5C,0,2} */
169#define IGA2_VER_BLANK_START_REG_NUM 2
170/* location: {CR5E,0,7},{CR5C,3,5} */
171#define IGA2_VER_BLANK_END_REG_NUM 2
172/* location: {CR5E,0,7},{CR5F,5,7} */
173#define IGA2_VER_SYNC_START_REG_NUM 2
174/* location: {CR5F,0,4} */
175#define IGA2_VER_SYNC_END_REG_NUM 1
176
177/* Define Fetch Count Register*/ 85/* Define Fetch Count Register*/
178 86
179/* location: {SR1C,0,7},{SR1D,0,1} */ 87/* location: {SR1C,0,7},{SR1D,0,1} */
@@ -446,87 +354,12 @@ is reserved, so it may have problem to set 1600x1200 on IGA2. */
446/* location: {CR78,0,7},{CR79,6,7} */ 354/* location: {CR78,0,7},{CR79,6,7} */
447#define LCD_VER_SCALING_FACTOR_REG_NUM_CLE 2 355#define LCD_VER_SCALING_FACTOR_REG_NUM_CLE 2
448 356
449/************************************************
450 ***** Define IGA1 Display Timing *****
451 ************************************************/
452struct io_register { 357struct io_register {
453 u8 io_addr; 358 u8 io_addr;
454 u8 start_bit; 359 u8 start_bit;
455 u8 end_bit; 360 u8 end_bit;
456}; 361};
457 362
458/* IGA1 Horizontal Total */
459struct iga1_hor_total {
460 int reg_num;
461 struct io_register reg[IGA1_HOR_TOTAL_REG_NUM];
462};
463
464/* IGA1 Horizontal Addressable Video */
465struct iga1_hor_addr {
466 int reg_num;
467 struct io_register reg[IGA1_HOR_ADDR_REG_NUM];
468};
469
470/* IGA1 Horizontal Blank Start */
471struct iga1_hor_blank_start {
472 int reg_num;
473 struct io_register reg[IGA1_HOR_BLANK_START_REG_NUM];
474};
475
476/* IGA1 Horizontal Blank End */
477struct iga1_hor_blank_end {
478 int reg_num;
479 struct io_register reg[IGA1_HOR_BLANK_END_REG_NUM];
480};
481
482/* IGA1 Horizontal Sync Start */
483struct iga1_hor_sync_start {
484 int reg_num;
485 struct io_register reg[IGA1_HOR_SYNC_START_REG_NUM];
486};
487
488/* IGA1 Horizontal Sync End */
489struct iga1_hor_sync_end {
490 int reg_num;
491 struct io_register reg[IGA1_HOR_SYNC_END_REG_NUM];
492};
493
494/* IGA1 Vertical Total */
495struct iga1_ver_total {
496 int reg_num;
497 struct io_register reg[IGA1_VER_TOTAL_REG_NUM];
498};
499
500/* IGA1 Vertical Addressable Video */
501struct iga1_ver_addr {
502 int reg_num;
503 struct io_register reg[IGA1_VER_ADDR_REG_NUM];
504};
505
506/* IGA1 Vertical Blank Start */
507struct iga1_ver_blank_start {
508 int reg_num;
509 struct io_register reg[IGA1_VER_BLANK_START_REG_NUM];
510};
511
512/* IGA1 Vertical Blank End */
513struct iga1_ver_blank_end {
514 int reg_num;
515 struct io_register reg[IGA1_VER_BLANK_END_REG_NUM];
516};
517
518/* IGA1 Vertical Sync Start */
519struct iga1_ver_sync_start {
520 int reg_num;
521 struct io_register reg[IGA1_VER_SYNC_START_REG_NUM];
522};
523
524/* IGA1 Vertical Sync End */
525struct iga1_ver_sync_end {
526 int reg_num;
527 struct io_register reg[IGA1_VER_SYNC_END_REG_NUM];
528};
529
530/***************************************************** 363/*****************************************************
531** Define IGA2 Shadow Display Timing **** 364** Define IGA2 Shadow Display Timing ****
532*****************************************************/ 365*****************************************************/
@@ -579,82 +412,6 @@ struct iga2_shadow_ver_sync_end {
579 struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM]; 412 struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
580}; 413};
581 414
582/*****************************************************
583** Define IGA2 Display Timing ****
584******************************************************/
585
586/* IGA2 Horizontal Total */
587struct iga2_hor_total {
588 int reg_num;
589 struct io_register reg[IGA2_HOR_TOTAL_REG_NUM];
590};
591
592/* IGA2 Horizontal Addressable Video */
593struct iga2_hor_addr {
594 int reg_num;
595 struct io_register reg[IGA2_HOR_ADDR_REG_NUM];
596};
597
598/* IGA2 Horizontal Blank Start */
599struct iga2_hor_blank_start {
600 int reg_num;
601 struct io_register reg[IGA2_HOR_BLANK_START_REG_NUM];
602};
603
604/* IGA2 Horizontal Blank End */
605struct iga2_hor_blank_end {
606 int reg_num;
607 struct io_register reg[IGA2_HOR_BLANK_END_REG_NUM];
608};
609
610/* IGA2 Horizontal Sync Start */
611struct iga2_hor_sync_start {
612 int reg_num;
613 struct io_register reg[IGA2_HOR_SYNC_START_REG_NUM];
614};
615
616/* IGA2 Horizontal Sync End */
617struct iga2_hor_sync_end {
618 int reg_num;
619 struct io_register reg[IGA2_HOR_SYNC_END_REG_NUM];
620};
621
622/* IGA2 Vertical Total */
623struct iga2_ver_total {
624 int reg_num;
625 struct io_register reg[IGA2_VER_TOTAL_REG_NUM];
626};
627
628/* IGA2 Vertical Addressable Video */
629struct iga2_ver_addr {
630 int reg_num;
631 struct io_register reg[IGA2_VER_ADDR_REG_NUM];
632};
633
634/* IGA2 Vertical Blank Start */
635struct iga2_ver_blank_start {
636 int reg_num;
637 struct io_register reg[IGA2_VER_BLANK_START_REG_NUM];
638};
639
640/* IGA2 Vertical Blank End */
641struct iga2_ver_blank_end {
642 int reg_num;
643 struct io_register reg[IGA2_VER_BLANK_END_REG_NUM];
644};
645
646/* IGA2 Vertical Sync Start */
647struct iga2_ver_sync_start {
648 int reg_num;
649 struct io_register reg[IGA2_VER_SYNC_START_REG_NUM];
650};
651
652/* IGA2 Vertical Sync End */
653struct iga2_ver_sync_end {
654 int reg_num;
655 struct io_register reg[IGA2_VER_SYNC_END_REG_NUM];
656};
657
658/* IGA1 Fetch Count Register */ 415/* IGA1 Fetch Count Register */
659struct iga1_fetch_count { 416struct iga1_fetch_count {
660 int reg_num; 417 int reg_num;
@@ -817,21 +574,6 @@ struct display_queue_expire_num {
817 iga2_display_queue_expire_num_reg; 574 iga2_display_queue_expire_num_reg;
818}; 575};
819 576
820struct iga1_crtc_timing {
821 struct iga1_hor_total hor_total;
822 struct iga1_hor_addr hor_addr;
823 struct iga1_hor_blank_start hor_blank_start;
824 struct iga1_hor_blank_end hor_blank_end;
825 struct iga1_hor_sync_start hor_sync_start;
826 struct iga1_hor_sync_end hor_sync_end;
827 struct iga1_ver_total ver_total;
828 struct iga1_ver_addr ver_addr;
829 struct iga1_ver_blank_start ver_blank_start;
830 struct iga1_ver_blank_end ver_blank_end;
831 struct iga1_ver_sync_start ver_sync_start;
832 struct iga1_ver_sync_end ver_sync_end;
833};
834
835struct iga2_shadow_crtc_timing { 577struct iga2_shadow_crtc_timing {
836 struct iga2_shadow_hor_total hor_total_shadow; 578 struct iga2_shadow_hor_total hor_total_shadow;
837 struct iga2_shadow_hor_blank_end hor_blank_end_shadow; 579 struct iga2_shadow_hor_blank_end hor_blank_end_shadow;
@@ -843,21 +585,6 @@ struct iga2_shadow_crtc_timing {
843 struct iga2_shadow_ver_sync_end ver_sync_end_shadow; 585 struct iga2_shadow_ver_sync_end ver_sync_end_shadow;
844}; 586};
845 587
846struct iga2_crtc_timing {
847 struct iga2_hor_total hor_total;
848 struct iga2_hor_addr hor_addr;
849 struct iga2_hor_blank_start hor_blank_start;
850 struct iga2_hor_blank_end hor_blank_end;
851 struct iga2_hor_sync_start hor_sync_start;
852 struct iga2_hor_sync_end hor_sync_end;
853 struct iga2_ver_total ver_total;
854 struct iga2_ver_addr ver_addr;
855 struct iga2_ver_blank_start ver_blank_start;
856 struct iga2_ver_blank_end ver_blank_end;
857 struct iga2_ver_sync_start ver_sync_start;
858 struct iga2_ver_sync_end ver_sync_end;
859};
860
861/* device ID */ 588/* device ID */
862#define CLE266_FUNCTION3 0x3123 589#define CLE266_FUNCTION3 0x3123
863#define KM400_FUNCTION3 0x3205 590#define KM400_FUNCTION3 0x3205
diff --git a/drivers/video/via/share.h b/drivers/video/via/share.h
index 61b0bd596b85..2906b2d23434 100644
--- a/drivers/video/via/share.h
+++ b/drivers/video/via/share.h
@@ -22,6 +22,8 @@
22#ifndef __SHARE_H__ 22#ifndef __SHARE_H__
23#define __SHARE_H__ 23#define __SHARE_H__
24 24
25#include "via_modesetting.h"
26
25/* Define Bit Field */ 27/* Define Bit Field */
26#define BIT0 0x01 28#define BIT0 0x01
27#define BIT1 0x02 29#define BIT1 0x02
@@ -648,23 +650,6 @@
648#define LCD_OPENLDI 0x00 650#define LCD_OPENLDI 0x00
649#define LCD_SPWG 0x01 651#define LCD_SPWG 0x01
650 652
651/* Define display timing
652*/
653struct display_timing {
654 u16 hor_total;
655 u16 hor_addr;
656 u16 hor_blank_start;
657 u16 hor_blank_end;
658 u16 hor_sync_start;
659 u16 hor_sync_end;
660 u16 ver_total;
661 u16 ver_addr;
662 u16 ver_blank_start;
663 u16 ver_blank_end;
664 u16 ver_sync_start;
665 u16 ver_sync_end;
666};
667
668struct crt_mode_table { 653struct crt_mode_table {
669 int refresh_rate; 654 int refresh_rate;
670 int h_sync_polarity; 655 int h_sync_polarity;
diff --git a/drivers/video/via/via_modesetting.c b/drivers/video/via/via_modesetting.c
index 3cddcff88ab9..016d457b6681 100644
--- a/drivers/video/via/via_modesetting.c
+++ b/drivers/video/via/via_modesetting.c
@@ -29,6 +29,106 @@
29#include "share.h" 29#include "share.h"
30#include "debug.h" 30#include "debug.h"
31 31
32
33void via_set_primary_timing(const struct display_timing *timing)
34{
35 struct display_timing raw;
36
37 raw.hor_total = timing->hor_total / 8 - 5;
38 raw.hor_addr = timing->hor_addr / 8 - 1;
39 raw.hor_blank_start = timing->hor_blank_start / 8 - 1;
40 raw.hor_blank_end = timing->hor_blank_end / 8 - 1;
41 raw.hor_sync_start = timing->hor_sync_start / 8;
42 raw.hor_sync_end = timing->hor_sync_end / 8;
43 raw.ver_total = timing->ver_total - 2;
44 raw.ver_addr = timing->ver_addr - 1;
45 raw.ver_blank_start = timing->ver_blank_start - 1;
46 raw.ver_blank_end = timing->ver_blank_end - 1;
47 raw.ver_sync_start = timing->ver_sync_start - 1;
48 raw.ver_sync_end = timing->ver_sync_end - 1;
49
50 /* unlock timing registers */
51 via_write_reg_mask(VIACR, 0x11, 0x00, 0x80);
52
53 via_write_reg(VIACR, 0x00, raw.hor_total & 0xFF);
54 via_write_reg(VIACR, 0x01, raw.hor_addr & 0xFF);
55 via_write_reg(VIACR, 0x02, raw.hor_blank_start & 0xFF);
56 via_write_reg_mask(VIACR, 0x03, raw.hor_blank_end & 0x1F, 0x1F);
57 via_write_reg(VIACR, 0x04, raw.hor_sync_start & 0xFF);
58 via_write_reg_mask(VIACR, 0x05, (raw.hor_sync_end & 0x1F)
59 | (raw.hor_blank_end << (7 - 5) & 0x80), 0x9F);
60 via_write_reg(VIACR, 0x06, raw.ver_total & 0xFF);
61 via_write_reg_mask(VIACR, 0x07, (raw.ver_total >> 8 & 0x01)
62 | (raw.ver_addr >> (8 - 1) & 0x02)
63 | (raw.ver_sync_start >> (8 - 2) & 0x04)
64 | (raw.ver_blank_start >> (8 - 3) & 0x08)
65 | (raw.ver_total >> (9 - 5) & 0x20)
66 | (raw.ver_addr >> (9 - 6) & 0x40)
67 | (raw.ver_sync_start >> (9 - 7) & 0x80), 0xEF);
68 via_write_reg_mask(VIACR, 0x09, raw.ver_blank_start >> (9 - 5) & 0x20,
69 0x20);
70 via_write_reg(VIACR, 0x10, raw.ver_sync_start & 0xFF);
71 via_write_reg_mask(VIACR, 0x11, raw.ver_sync_end & 0x0F, 0x0F);
72 via_write_reg(VIACR, 0x12, raw.ver_addr & 0xFF);
73 via_write_reg(VIACR, 0x15, raw.ver_blank_start & 0xFF);
74 via_write_reg(VIACR, 0x16, raw.ver_blank_end & 0xFF);
75 via_write_reg_mask(VIACR, 0x33, (raw.hor_sync_start >> (8 - 4) & 0x10)
76 | (raw.hor_blank_end >> (6 - 5) & 0x20), 0x30);
77 via_write_reg_mask(VIACR, 0x35, (raw.ver_total >> 10 & 0x01)
78 | (raw.ver_sync_start >> (10 - 1) & 0x02)
79 | (raw.ver_addr >> (10 - 2) & 0x04)
80 | (raw.ver_blank_start >> (10 - 3) & 0x08), 0x0F);
81 via_write_reg_mask(VIACR, 0x36, raw.hor_total >> (8 - 3) & 0x08, 0x08);
82
83 /* lock timing registers */
84 via_write_reg_mask(VIACR, 0x11, 0x80, 0x80);
85}
86
87void via_set_secondary_timing(const struct display_timing *timing)
88{
89 struct display_timing raw;
90
91 raw.hor_total = timing->hor_total - 1;
92 raw.hor_addr = timing->hor_addr - 1;
93 raw.hor_blank_start = timing->hor_blank_start - 1;
94 raw.hor_blank_end = timing->hor_blank_end - 1;
95 raw.hor_sync_start = timing->hor_sync_start - 1;
96 raw.hor_sync_end = timing->hor_sync_end - 1;
97 raw.ver_total = timing->ver_total - 1;
98 raw.ver_addr = timing->ver_addr - 1;
99 raw.ver_blank_start = timing->ver_blank_start - 1;
100 raw.ver_blank_end = timing->ver_blank_end - 1;
101 raw.ver_sync_start = timing->ver_sync_start - 1;
102 raw.ver_sync_end = timing->ver_sync_end - 1;
103
104 via_write_reg(VIACR, 0x50, raw.hor_total & 0xFF);
105 via_write_reg(VIACR, 0x51, raw.hor_addr & 0xFF);
106 via_write_reg(VIACR, 0x52, raw.hor_blank_start & 0xFF);
107 via_write_reg(VIACR, 0x53, raw.hor_blank_end & 0xFF);
108 via_write_reg(VIACR, 0x54, (raw.hor_blank_start >> 8 & 0x07)
109 | (raw.hor_blank_end >> (8 - 3) & 0x38)
110 | (raw.hor_sync_start >> (8 - 6) & 0xC0));
111 via_write_reg_mask(VIACR, 0x55, (raw.hor_total >> 8 & 0x0F)
112 | (raw.hor_addr >> (8 - 4) & 0x70), 0x7F);
113 via_write_reg(VIACR, 0x56, raw.hor_sync_start & 0xFF);
114 via_write_reg(VIACR, 0x57, raw.hor_sync_end & 0xFF);
115 via_write_reg(VIACR, 0x58, raw.ver_total & 0xFF);
116 via_write_reg(VIACR, 0x59, raw.ver_addr & 0xFF);
117 via_write_reg(VIACR, 0x5A, raw.ver_blank_start & 0xFF);
118 via_write_reg(VIACR, 0x5B, raw.ver_blank_end & 0xFF);
119 via_write_reg(VIACR, 0x5C, (raw.ver_blank_start >> 8 & 0x07)
120 | (raw.ver_blank_end >> (8 - 3) & 0x38)
121 | (raw.hor_sync_end >> (8 - 6) & 0x40)
122 | (raw.hor_sync_start >> (10 - 7) & 0x80));
123 via_write_reg(VIACR, 0x5D, (raw.ver_total >> 8 & 0x07)
124 | (raw.ver_addr >> (8 - 3) & 0x38)
125 | (raw.hor_blank_end >> (11 - 6) & 0x40)
126 | (raw.hor_sync_start >> (11 - 7) & 0x80));
127 via_write_reg(VIACR, 0x5E, raw.ver_sync_start & 0xFF);
128 via_write_reg(VIACR, 0x5F, (raw.ver_sync_end & 0x1F)
129 | (raw.ver_sync_start >> (8 - 5) & 0xE0));
130}
131
32void via_set_primary_address(u32 addr) 132void via_set_primary_address(u32 addr)
33{ 133{
34 DEBUG_MSG(KERN_DEBUG "via_set_primary_address(0x%08X)\n", addr); 134 DEBUG_MSG(KERN_DEBUG "via_set_primary_address(0x%08X)\n", addr);
diff --git a/drivers/video/via/via_modesetting.h b/drivers/video/via/via_modesetting.h
index 013884543e91..06e09fe351ae 100644
--- a/drivers/video/via/via_modesetting.h
+++ b/drivers/video/via/via_modesetting.h
@@ -33,6 +33,24 @@
33#define VIA_PITCH_MAX 0x3FF8 33#define VIA_PITCH_MAX 0x3FF8
34 34
35 35
36struct display_timing {
37 u16 hor_total;
38 u16 hor_addr;
39 u16 hor_blank_start;
40 u16 hor_blank_end;
41 u16 hor_sync_start;
42 u16 hor_sync_end;
43 u16 ver_total;
44 u16 ver_addr;
45 u16 ver_blank_start;
46 u16 ver_blank_end;
47 u16 ver_sync_start;
48 u16 ver_sync_end;
49};
50
51
52void via_set_primary_timing(const struct display_timing *timing);
53void via_set_secondary_timing(const struct display_timing *timing);
36void via_set_primary_address(u32 addr); 54void via_set_primary_address(u32 addr);
37void via_set_secondary_address(u32 addr); 55void via_set_secondary_address(u32 addr);
38void via_set_primary_pitch(u32 pitch); 56void via_set_primary_pitch(u32 pitch);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-26 02:26:46 -0500