aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pinctrl/mediatek/pinctrl-mt8173.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/pinctrl/mediatek/pinctrl-mt8173.c')
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt8173.c452
1 files changed, 452 insertions, 0 deletions
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
new file mode 100644
index 000000000000..66b01bb11778
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
@@ -0,0 +1,452 @@
1/*
2 * Copyright (c) 2014-2015 MediaTek Inc.
3 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/regmap.h>
21#include <dt-bindings/pinctrl/mt65xx.h>
22
23#include "pinctrl-mtk-common.h"
24#include "pinctrl-mtk-mt8173.h"
25
26#define DRV_BASE 0xb00
27
28/**
29 * struct mtk_pin_ies_smt_set - For special pins' ies and smt setting.
30 * @start: The start pin number of those special pins.
31 * @end: The end pin number of those special pins.
32 * @offset: The offset of special setting register.
33 * @bit: The bit of special setting register.
34 */
35struct mtk_pin_ies_smt_set {
36 unsigned int start;
37 unsigned int end;
38 unsigned int offset;
39 unsigned char bit;
40};
41
42#define MTK_PIN_IES_SMT_SET(_start, _end, _offset, _bit) \
43 { \
44 .start = _start, \
45 .end = _end, \
46 .bit = _bit, \
47 .offset = _offset, \
48 }
49
50/**
51 * struct mtk_pin_spec_pupd_set - For special pins' pull up/down setting.
52 * @pin: The pin number.
53 * @offset: The offset of special pull up/down setting register.
54 * @pupd_bit: The pull up/down bit in this register.
55 * @r0_bit: The r0 bit of pull resistor.
56 * @r1_bit: The r1 bit of pull resistor.
57 */
58struct mtk_pin_spec_pupd_set {
59 unsigned int pin;
60 unsigned int offset;
61 unsigned char pupd_bit;
62 unsigned char r1_bit;
63 unsigned char r0_bit;
64};
65
66#define MTK_PIN_PUPD_SPEC(_pin, _offset, _pupd, _r1, _r0) \
67 { \
68 .pin = _pin, \
69 .offset = _offset, \
70 .pupd_bit = _pupd, \
71 .r1_bit = _r1, \
72 .r0_bit = _r0, \
73 }
74
75static const struct mtk_pin_spec_pupd_set mt8173_spec_pupd[] = {
76 MTK_PIN_PUPD_SPEC(119, 0xe00, 2, 1, 0), /* KROW0 */
77 MTK_PIN_PUPD_SPEC(120, 0xe00, 6, 5, 4), /* KROW1 */
78 MTK_PIN_PUPD_SPEC(121, 0xe00, 10, 9, 8), /* KROW2 */
79 MTK_PIN_PUPD_SPEC(122, 0xe10, 2, 1, 0), /* KCOL0 */
80 MTK_PIN_PUPD_SPEC(123, 0xe10, 6, 5, 4), /* KCOL1 */
81 MTK_PIN_PUPD_SPEC(124, 0xe10, 10, 9, 8), /* KCOL2 */
82
83 MTK_PIN_PUPD_SPEC(67, 0xd10, 2, 1, 0), /* ms0 DS */
84 MTK_PIN_PUPD_SPEC(68, 0xd00, 2, 1, 0), /* ms0 RST */
85 MTK_PIN_PUPD_SPEC(66, 0xc10, 2, 1, 0), /* ms0 cmd */
86 MTK_PIN_PUPD_SPEC(65, 0xc00, 2, 1, 0), /* ms0 clk */
87 MTK_PIN_PUPD_SPEC(57, 0xc20, 2, 1, 0), /* ms0 data0 */
88 MTK_PIN_PUPD_SPEC(58, 0xc20, 2, 1, 0), /* ms0 data1 */
89 MTK_PIN_PUPD_SPEC(59, 0xc20, 2, 1, 0), /* ms0 data2 */
90 MTK_PIN_PUPD_SPEC(60, 0xc20, 2, 1, 0), /* ms0 data3 */
91 MTK_PIN_PUPD_SPEC(61, 0xc20, 2, 1, 0), /* ms0 data4 */
92 MTK_PIN_PUPD_SPEC(62, 0xc20, 2, 1, 0), /* ms0 data5 */
93 MTK_PIN_PUPD_SPEC(63, 0xc20, 2, 1, 0), /* ms0 data6 */
94 MTK_PIN_PUPD_SPEC(64, 0xc20, 2, 1, 0), /* ms0 data7 */
95
96 MTK_PIN_PUPD_SPEC(78, 0xc50, 2, 1, 0), /* ms1 cmd */
97 MTK_PIN_PUPD_SPEC(73, 0xd20, 2, 1, 0), /* ms1 dat0 */
98 MTK_PIN_PUPD_SPEC(74, 0xd20, 6, 5, 4), /* ms1 dat1 */
99 MTK_PIN_PUPD_SPEC(75, 0xd20, 10, 9, 8), /* ms1 dat2 */
100 MTK_PIN_PUPD_SPEC(76, 0xd20, 14, 13, 12), /* ms1 dat3 */
101 MTK_PIN_PUPD_SPEC(77, 0xc40, 2, 1, 0), /* ms1 clk */
102
103 MTK_PIN_PUPD_SPEC(100, 0xd40, 2, 1, 0), /* ms2 dat0 */
104 MTK_PIN_PUPD_SPEC(101, 0xd40, 6, 5, 4), /* ms2 dat1 */
105 MTK_PIN_PUPD_SPEC(102, 0xd40, 10, 9, 8), /* ms2 dat2 */
106 MTK_PIN_PUPD_SPEC(103, 0xd40, 14, 13, 12), /* ms2 dat3 */
107 MTK_PIN_PUPD_SPEC(104, 0xc80, 2, 1, 0), /* ms2 clk */
108 MTK_PIN_PUPD_SPEC(105, 0xc90, 2, 1, 0), /* ms2 cmd */
109
110 MTK_PIN_PUPD_SPEC(22, 0xd60, 2, 1, 0), /* ms3 dat0 */
111 MTK_PIN_PUPD_SPEC(23, 0xd60, 6, 5, 4), /* ms3 dat1 */
112 MTK_PIN_PUPD_SPEC(24, 0xd60, 10, 9, 8), /* ms3 dat2 */
113 MTK_PIN_PUPD_SPEC(25, 0xd60, 14, 13, 12), /* ms3 dat3 */
114 MTK_PIN_PUPD_SPEC(26, 0xcc0, 2, 1, 0), /* ms3 clk */
115 MTK_PIN_PUPD_SPEC(27, 0xcd0, 2, 1, 0) /* ms3 cmd */
116};
117
118static int spec_pull_set(struct regmap *regmap, unsigned int pin,
119 unsigned char align, bool isup, unsigned int r1r0)
120{
121 unsigned int i;
122 unsigned int reg_pupd, reg_set, reg_rst;
123 unsigned int bit_pupd, bit_r0, bit_r1;
124 const struct mtk_pin_spec_pupd_set *spec_pupd_pin;
125 bool find = false;
126
127 for (i = 0; i < ARRAY_SIZE(mt8173_spec_pupd); i++) {
128 if (pin == mt8173_spec_pupd[i].pin) {
129 find = true;
130 break;
131 }
132 }
133
134 if (!find)
135 return -EINVAL;
136
137 spec_pupd_pin = mt8173_spec_pupd + i;
138 reg_set = spec_pupd_pin->offset + align;
139 reg_rst = spec_pupd_pin->offset + (align << 1);
140
141 if (isup)
142 reg_pupd = reg_rst;
143 else
144 reg_pupd = reg_set;
145
146 bit_pupd = BIT(spec_pupd_pin->pupd_bit);
147 regmap_write(regmap, reg_pupd, bit_pupd);
148
149 bit_r0 = BIT(spec_pupd_pin->r0_bit);
150 bit_r1 = BIT(spec_pupd_pin->r1_bit);
151
152 switch (r1r0) {
153 case MTK_PUPD_SET_R1R0_00:
154 regmap_write(regmap, reg_rst, bit_r0);
155 regmap_write(regmap, reg_rst, bit_r1);
156 break;
157 case MTK_PUPD_SET_R1R0_01:
158 regmap_write(regmap, reg_set, bit_r0);
159 regmap_write(regmap, reg_rst, bit_r1);
160 break;
161 case MTK_PUPD_SET_R1R0_10:
162 regmap_write(regmap, reg_rst, bit_r0);
163 regmap_write(regmap, reg_set, bit_r1);
164 break;
165 case MTK_PUPD_SET_R1R0_11:
166 regmap_write(regmap, reg_set, bit_r0);
167 regmap_write(regmap, reg_set, bit_r1);
168 break;
169 default:
170 return -EINVAL;
171 }
172
173 return 0;
174}
175
176static const struct mtk_pin_ies_smt_set mt8173_ies_smt_set[] = {
177 MTK_PIN_IES_SMT_SET(0, 4, 0x930, 1),
178 MTK_PIN_IES_SMT_SET(5, 9, 0x930, 2),
179 MTK_PIN_IES_SMT_SET(10, 13, 0x930, 10),
180 MTK_PIN_IES_SMT_SET(14, 15, 0x940, 10),
181 MTK_PIN_IES_SMT_SET(16, 16, 0x930, 0),
182 MTK_PIN_IES_SMT_SET(17, 17, 0x950, 2),
183 MTK_PIN_IES_SMT_SET(18, 21, 0x940, 3),
184 MTK_PIN_IES_SMT_SET(29, 32, 0x930, 3),
185 MTK_PIN_IES_SMT_SET(33, 33, 0x930, 4),
186 MTK_PIN_IES_SMT_SET(34, 36, 0x930, 5),
187 MTK_PIN_IES_SMT_SET(37, 38, 0x930, 6),
188 MTK_PIN_IES_SMT_SET(39, 39, 0x930, 7),
189 MTK_PIN_IES_SMT_SET(40, 41, 0x930, 9),
190 MTK_PIN_IES_SMT_SET(42, 42, 0x940, 0),
191 MTK_PIN_IES_SMT_SET(43, 44, 0x930, 11),
192 MTK_PIN_IES_SMT_SET(45, 46, 0x930, 12),
193 MTK_PIN_IES_SMT_SET(57, 64, 0xc20, 13),
194 MTK_PIN_IES_SMT_SET(65, 65, 0xc10, 13),
195 MTK_PIN_IES_SMT_SET(66, 66, 0xc00, 13),
196 MTK_PIN_IES_SMT_SET(67, 67, 0xd10, 13),
197 MTK_PIN_IES_SMT_SET(68, 68, 0xd00, 13),
198 MTK_PIN_IES_SMT_SET(69, 72, 0x940, 14),
199 MTK_PIN_IES_SMT_SET(73, 76, 0xc60, 13),
200 MTK_PIN_IES_SMT_SET(77, 77, 0xc40, 13),
201 MTK_PIN_IES_SMT_SET(78, 78, 0xc50, 13),
202 MTK_PIN_IES_SMT_SET(79, 82, 0x940, 15),
203 MTK_PIN_IES_SMT_SET(83, 83, 0x950, 0),
204 MTK_PIN_IES_SMT_SET(84, 85, 0x950, 1),
205 MTK_PIN_IES_SMT_SET(86, 91, 0x950, 2),
206 MTK_PIN_IES_SMT_SET(92, 92, 0x930, 13),
207 MTK_PIN_IES_SMT_SET(93, 95, 0x930, 14),
208 MTK_PIN_IES_SMT_SET(96, 99, 0x930, 15),
209 MTK_PIN_IES_SMT_SET(100, 103, 0xca0, 13),
210 MTK_PIN_IES_SMT_SET(104, 104, 0xc80, 13),
211 MTK_PIN_IES_SMT_SET(105, 105, 0xc90, 13),
212 MTK_PIN_IES_SMT_SET(106, 107, 0x940, 4),
213 MTK_PIN_IES_SMT_SET(108, 112, 0x940, 1),
214 MTK_PIN_IES_SMT_SET(113, 116, 0x940, 2),
215 MTK_PIN_IES_SMT_SET(117, 118, 0x940, 5),
216 MTK_PIN_IES_SMT_SET(119, 124, 0x940, 6),
217 MTK_PIN_IES_SMT_SET(125, 126, 0x940, 7),
218 MTK_PIN_IES_SMT_SET(127, 127, 0x940, 0),
219 MTK_PIN_IES_SMT_SET(128, 128, 0x950, 8),
220 MTK_PIN_IES_SMT_SET(129, 130, 0x950, 9),
221 MTK_PIN_IES_SMT_SET(131, 132, 0x950, 8),
222 MTK_PIN_IES_SMT_SET(133, 134, 0x910, 8)
223};
224
225static int spec_ies_smt_set(struct regmap *regmap, unsigned int pin,
226 unsigned char align, int value)
227{
228 unsigned int i, reg_addr, bit;
229 bool find = false;
230
231 for (i = 0; i < ARRAY_SIZE(mt8173_ies_smt_set); i++) {
232 if (pin >= mt8173_ies_smt_set[i].start &&
233 pin <= mt8173_ies_smt_set[i].end) {
234 find = true;
235 break;
236 }
237 }
238
239 if (!find)
240 return -EINVAL;
241
242 if (value)
243 reg_addr = mt8173_ies_smt_set[i].offset + align;
244 else
245 reg_addr = mt8173_ies_smt_set[i].offset + (align << 1);
246
247 bit = BIT(mt8173_ies_smt_set[i].bit);
248 regmap_write(regmap, reg_addr, bit);
249 return 0;
250}
251
252static const struct mtk_drv_group_desc mt8173_drv_grp[] = {
253 /* 0E4E8SR 4/8/12/16 */
254 MTK_DRV_GRP(4, 16, 1, 2, 4),
255 /* 0E2E4SR 2/4/6/8 */
256 MTK_DRV_GRP(2, 8, 1, 2, 2),
257 /* E8E4E2 2/4/6/8/10/12/14/16 */
258 MTK_DRV_GRP(2, 16, 0, 2, 2)
259};
260
261static const struct mtk_pin_drv_grp mt8173_pin_drv[] = {
262 MTK_PIN_DRV_GRP(0, DRV_BASE+0x20, 12, 0),
263 MTK_PIN_DRV_GRP(1, DRV_BASE+0x20, 12, 0),
264 MTK_PIN_DRV_GRP(2, DRV_BASE+0x20, 12, 0),
265 MTK_PIN_DRV_GRP(3, DRV_BASE+0x20, 12, 0),
266 MTK_PIN_DRV_GRP(4, DRV_BASE+0x20, 12, 0),
267 MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0),
268 MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0),
269 MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0),
270 MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0),
271 MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0),
272 MTK_PIN_DRV_GRP(10, DRV_BASE+0x30, 4, 1),
273 MTK_PIN_DRV_GRP(11, DRV_BASE+0x30, 4, 1),
274 MTK_PIN_DRV_GRP(12, DRV_BASE+0x30, 4, 1),
275 MTK_PIN_DRV_GRP(13, DRV_BASE+0x30, 4, 1),
276 MTK_PIN_DRV_GRP(14, DRV_BASE+0x40, 8, 1),
277 MTK_PIN_DRV_GRP(15, DRV_BASE+0x40, 8, 1),
278 MTK_PIN_DRV_GRP(16, DRV_BASE, 8, 1),
279 MTK_PIN_DRV_GRP(17, 0xce0, 8, 2),
280 MTK_PIN_DRV_GRP(22, 0xce0, 8, 2),
281 MTK_PIN_DRV_GRP(23, 0xce0, 8, 2),
282 MTK_PIN_DRV_GRP(24, 0xce0, 8, 2),
283 MTK_PIN_DRV_GRP(25, 0xce0, 8, 2),
284 MTK_PIN_DRV_GRP(26, 0xcc0, 8, 2),
285 MTK_PIN_DRV_GRP(27, 0xcd0, 8, 2),
286 MTK_PIN_DRV_GRP(28, 0xd70, 8, 2),
287 MTK_PIN_DRV_GRP(29, DRV_BASE+0x80, 12, 1),
288 MTK_PIN_DRV_GRP(30, DRV_BASE+0x80, 12, 1),
289 MTK_PIN_DRV_GRP(31, DRV_BASE+0x80, 12, 1),
290 MTK_PIN_DRV_GRP(32, DRV_BASE+0x80, 12, 1),
291 MTK_PIN_DRV_GRP(33, DRV_BASE+0x10, 12, 1),
292 MTK_PIN_DRV_GRP(34, DRV_BASE+0x10, 8, 1),
293 MTK_PIN_DRV_GRP(35, DRV_BASE+0x10, 8, 1),
294 MTK_PIN_DRV_GRP(36, DRV_BASE+0x10, 8, 1),
295 MTK_PIN_DRV_GRP(37, DRV_BASE+0x10, 4, 1),
296 MTK_PIN_DRV_GRP(38, DRV_BASE+0x10, 4, 1),
297 MTK_PIN_DRV_GRP(39, DRV_BASE+0x20, 0, 0),
298 MTK_PIN_DRV_GRP(40, DRV_BASE+0x20, 8, 0),
299 MTK_PIN_DRV_GRP(41, DRV_BASE+0x20, 8, 0),
300 MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1),
301 MTK_PIN_DRV_GRP(57, 0xc20, 8, 2),
302 MTK_PIN_DRV_GRP(58, 0xc20, 8, 2),
303 MTK_PIN_DRV_GRP(59, 0xc20, 8, 2),
304 MTK_PIN_DRV_GRP(60, 0xc20, 8, 2),
305 MTK_PIN_DRV_GRP(61, 0xc20, 8, 2),
306 MTK_PIN_DRV_GRP(62, 0xc20, 8, 2),
307 MTK_PIN_DRV_GRP(63, 0xc20, 8, 2),
308 MTK_PIN_DRV_GRP(64, 0xc20, 8, 2),
309 MTK_PIN_DRV_GRP(65, 0xc00, 8, 2),
310 MTK_PIN_DRV_GRP(66, 0xc10, 8, 2),
311 MTK_PIN_DRV_GRP(67, 0xd10, 8, 2),
312 MTK_PIN_DRV_GRP(68, 0xd00, 8, 2),
313 MTK_PIN_DRV_GRP(69, DRV_BASE+0x80, 0, 1),
314 MTK_PIN_DRV_GRP(70, DRV_BASE+0x80, 0, 1),
315 MTK_PIN_DRV_GRP(71, DRV_BASE+0x80, 0, 1),
316 MTK_PIN_DRV_GRP(72, DRV_BASE+0x80, 0, 1),
317 MTK_PIN_DRV_GRP(73, 0xc60, 8, 2),
318 MTK_PIN_DRV_GRP(74, 0xc60, 8, 2),
319 MTK_PIN_DRV_GRP(75, 0xc60, 8, 2),
320 MTK_PIN_DRV_GRP(76, 0xc60, 8, 2),
321 MTK_PIN_DRV_GRP(77, 0xc40, 8, 2),
322 MTK_PIN_DRV_GRP(78, 0xc50, 8, 2),
323 MTK_PIN_DRV_GRP(79, DRV_BASE+0x70, 12, 1),
324 MTK_PIN_DRV_GRP(80, DRV_BASE+0x70, 12, 1),
325 MTK_PIN_DRV_GRP(81, DRV_BASE+0x70, 12, 1),
326 MTK_PIN_DRV_GRP(82, DRV_BASE+0x70, 12, 1),
327 MTK_PIN_DRV_GRP(83, DRV_BASE, 4, 1),
328 MTK_PIN_DRV_GRP(84, DRV_BASE, 0, 1),
329 MTK_PIN_DRV_GRP(85, DRV_BASE, 0, 1),
330 MTK_PIN_DRV_GRP(85, DRV_BASE+0x60, 8, 1),
331 MTK_PIN_DRV_GRP(86, DRV_BASE+0x60, 8, 1),
332 MTK_PIN_DRV_GRP(87, DRV_BASE+0x60, 8, 1),
333 MTK_PIN_DRV_GRP(88, DRV_BASE+0x60, 8, 1),
334 MTK_PIN_DRV_GRP(89, DRV_BASE+0x60, 8, 1),
335 MTK_PIN_DRV_GRP(90, DRV_BASE+0x60, 8, 1),
336 MTK_PIN_DRV_GRP(91, DRV_BASE+0x60, 8, 1),
337 MTK_PIN_DRV_GRP(92, DRV_BASE+0x60, 4, 0),
338 MTK_PIN_DRV_GRP(93, DRV_BASE+0x60, 0, 0),
339 MTK_PIN_DRV_GRP(94, DRV_BASE+0x60, 0, 0),
340 MTK_PIN_DRV_GRP(95, DRV_BASE+0x60, 0, 0),
341 MTK_PIN_DRV_GRP(96, DRV_BASE+0x80, 8, 1),
342 MTK_PIN_DRV_GRP(97, DRV_BASE+0x80, 8, 1),
343 MTK_PIN_DRV_GRP(98, DRV_BASE+0x80, 8, 1),
344 MTK_PIN_DRV_GRP(99, DRV_BASE+0x80, 8, 1),
345 MTK_PIN_DRV_GRP(100, 0xca0, 8, 2),
346 MTK_PIN_DRV_GRP(101, 0xca0, 8, 2),
347 MTK_PIN_DRV_GRP(102, 0xca0, 8, 2),
348 MTK_PIN_DRV_GRP(103, 0xca0, 8, 2),
349 MTK_PIN_DRV_GRP(104, 0xc80, 8, 2),
350 MTK_PIN_DRV_GRP(105, 0xc90, 8, 2),
351 MTK_PIN_DRV_GRP(108, DRV_BASE+0x50, 0, 1),
352 MTK_PIN_DRV_GRP(109, DRV_BASE+0x50, 0, 1),
353 MTK_PIN_DRV_GRP(110, DRV_BASE+0x50, 0, 1),
354 MTK_PIN_DRV_GRP(111, DRV_BASE+0x50, 0, 1),
355 MTK_PIN_DRV_GRP(112, DRV_BASE+0x50, 0, 1),
356 MTK_PIN_DRV_GRP(113, DRV_BASE+0x80, 4, 1),
357 MTK_PIN_DRV_GRP(114, DRV_BASE+0x80, 4, 1),
358 MTK_PIN_DRV_GRP(115, DRV_BASE+0x80, 4, 1),
359 MTK_PIN_DRV_GRP(116, DRV_BASE+0x80, 4, 1),
360 MTK_PIN_DRV_GRP(117, DRV_BASE+0x90, 0, 1),
361 MTK_PIN_DRV_GRP(118, DRV_BASE+0x90, 0, 1),
362 MTK_PIN_DRV_GRP(119, DRV_BASE+0x50, 4, 1),
363 MTK_PIN_DRV_GRP(120, DRV_BASE+0x50, 4, 1),
364 MTK_PIN_DRV_GRP(121, DRV_BASE+0x50, 4, 1),
365 MTK_PIN_DRV_GRP(122, DRV_BASE+0x50, 4, 1),
366 MTK_PIN_DRV_GRP(123, DRV_BASE+0x50, 4, 1),
367 MTK_PIN_DRV_GRP(124, DRV_BASE+0x50, 4, 1),
368 MTK_PIN_DRV_GRP(125, DRV_BASE+0x30, 12, 1),
369 MTK_PIN_DRV_GRP(126, DRV_BASE+0x30, 12, 1),
370 MTK_PIN_DRV_GRP(127, DRV_BASE+0x50, 8, 1),
371 MTK_PIN_DRV_GRP(128, DRV_BASE+0x40, 0, 1),
372 MTK_PIN_DRV_GRP(129, DRV_BASE+0x40, 0, 1),
373 MTK_PIN_DRV_GRP(130, DRV_BASE+0x40, 0, 1),
374 MTK_PIN_DRV_GRP(131, DRV_BASE+0x40, 0, 1),
375 MTK_PIN_DRV_GRP(132, DRV_BASE+0x40, 0, 1)
376};
377
378static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
379 .pins = mtk_pins_mt8173,
380 .npins = ARRAY_SIZE(mtk_pins_mt8173),
381 .grp_desc = mt8173_drv_grp,
382 .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp),
383 .pin_drv_grp = mt8173_pin_drv,
384 .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
385 .spec_pull_set = spec_pull_set,
386 .spec_ies_smt_set = spec_ies_smt_set,
387 .dir_offset = 0x0000,
388 .pullen_offset = 0x0100,
389 .pullsel_offset = 0x0200,
390 .dout_offset = 0x0400,
391 .din_offset = 0x0500,
392 .pinmux_offset = 0x0600,
393 .type1_start = 135,
394 .type1_end = 135,
395 .port_shf = 4,
396 .port_mask = 0xf,
397 .port_align = 4,
398 .eint_offsets = {
399 .name = "mt8173_eint",
400 .stat = 0x000,
401 .ack = 0x040,
402 .mask = 0x080,
403 .mask_set = 0x0c0,
404 .mask_clr = 0x100,
405 .sens = 0x140,
406 .sens_set = 0x180,
407 .sens_clr = 0x1c0,
408 .pol = 0x300,
409 .pol_set = 0x340,
410 .pol_clr = 0x380,
411 .dom_en = 0x400,
412 .dbnc_ctrl = 0x500,
413 .dbnc_set = 0x600,
414 .dbnc_clr = 0x700,
415 .port_mask = 7,
416 .ports = 6,
417 },
418 .ap_num = 224,
419 .db_cnt = 16,
420};
421
422static int mt8173_pinctrl_probe(struct platform_device *pdev)
423{
424 return mtk_pctrl_init(pdev, &mt8173_pinctrl_data);
425}
426
427static struct of_device_id mt8173_pctrl_match[] = {
428 {
429 .compatible = "mediatek,mt8173-pinctrl",
430 }, {
431 }
432};
433MODULE_DEVICE_TABLE(of, mt8173_pctrl_match);
434
435static struct platform_driver mtk_pinctrl_driver = {
436 .probe = mt8173_pinctrl_probe,
437 .driver = {
438 .name = "mediatek-mt8173-pinctrl",
439 .of_match_table = mt8173_pctrl_match,
440 },
441};
442
443static int __init mtk_pinctrl_init(void)
444{
445 return platform_driver_register(&mtk_pinctrl_driver);
446}
447
448module_init(mtk_pinctrl_init);
449
450MODULE_LICENSE("GPL v2");
451MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
452MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 14:43:01 -0400