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path: root/drivers/net/wireless/rt2x00/rt2400pci.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2400pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.c323
1 files changed, 162 insertions, 161 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c
index dcfb54e0c516..f7143733d7e9 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.c
+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
@@ -41,7 +41,7 @@
41/* 41/*
42 * Register access. 42 * Register access.
43 * All access to the CSR registers will go through the methods 43 * All access to the CSR registers will go through the methods
44 * rt2x00pci_register_read and rt2x00pci_register_write. 44 * rt2x00mmio_register_read and rt2x00mmio_register_write.
45 * BBP and RF register require indirect register access, 45 * BBP and RF register require indirect register access,
46 * and use the CSR registers BBPCSR and RFCSR to achieve this. 46 * and use the CSR registers BBPCSR and RFCSR to achieve this.
47 * These indirect registers work with busy bits, 47 * These indirect registers work with busy bits,
@@ -52,9 +52,9 @@
52 * and we will print an error. 52 * and we will print an error.
53 */ 53 */
54#define WAIT_FOR_BBP(__dev, __reg) \ 54#define WAIT_FOR_BBP(__dev, __reg) \
55 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg)) 55 rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
56#define WAIT_FOR_RF(__dev, __reg) \ 56#define WAIT_FOR_RF(__dev, __reg) \
57 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg)) 57 rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
58 58
59static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev, 59static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
60 const unsigned int word, const u8 value) 60 const unsigned int word, const u8 value)
@@ -74,7 +74,7 @@ static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
74 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1); 74 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
75 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1); 75 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
76 76
77 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg); 77 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
78 } 78 }
79 79
80 mutex_unlock(&rt2x00dev->csr_mutex); 80 mutex_unlock(&rt2x00dev->csr_mutex);
@@ -101,7 +101,7 @@ static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
101 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1); 101 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
102 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0); 102 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
103 103
104 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg); 104 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
105 105
106 WAIT_FOR_BBP(rt2x00dev, &reg); 106 WAIT_FOR_BBP(rt2x00dev, &reg);
107 } 107 }
@@ -129,7 +129,7 @@ static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
129 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0); 129 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
130 rt2x00_set_field32(&reg, RFCSR_BUSY, 1); 130 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
131 131
132 rt2x00pci_register_write(rt2x00dev, RFCSR, reg); 132 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
133 rt2x00_rf_write(rt2x00dev, word, value); 133 rt2x00_rf_write(rt2x00dev, word, value);
134 } 134 }
135 135
@@ -141,7 +141,7 @@ static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
141 struct rt2x00_dev *rt2x00dev = eeprom->data; 141 struct rt2x00_dev *rt2x00dev = eeprom->data;
142 u32 reg; 142 u32 reg;
143 143
144 rt2x00pci_register_read(rt2x00dev, CSR21, &reg); 144 rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
145 145
146 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); 146 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
147 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); 147 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
@@ -163,15 +163,15 @@ static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
163 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT, 163 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
164 !!eeprom->reg_chip_select); 164 !!eeprom->reg_chip_select);
165 165
166 rt2x00pci_register_write(rt2x00dev, CSR21, reg); 166 rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
167} 167}
168 168
169#ifdef CONFIG_RT2X00_LIB_DEBUGFS 169#ifdef CONFIG_RT2X00_LIB_DEBUGFS
170static const struct rt2x00debug rt2400pci_rt2x00debug = { 170static const struct rt2x00debug rt2400pci_rt2x00debug = {
171 .owner = THIS_MODULE, 171 .owner = THIS_MODULE,
172 .csr = { 172 .csr = {
173 .read = rt2x00pci_register_read, 173 .read = rt2x00mmio_register_read,
174 .write = rt2x00pci_register_write, 174 .write = rt2x00mmio_register_write,
175 .flags = RT2X00DEBUGFS_OFFSET, 175 .flags = RT2X00DEBUGFS_OFFSET,
176 .word_base = CSR_REG_BASE, 176 .word_base = CSR_REG_BASE,
177 .word_size = sizeof(u32), 177 .word_size = sizeof(u32),
@@ -205,7 +205,7 @@ static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
205{ 205{
206 u32 reg; 206 u32 reg;
207 207
208 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg); 208 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
209 return rt2x00_get_field32(reg, GPIOCSR_VAL0); 209 return rt2x00_get_field32(reg, GPIOCSR_VAL0);
210} 210}
211 211
@@ -218,14 +218,14 @@ static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
218 unsigned int enabled = brightness != LED_OFF; 218 unsigned int enabled = brightness != LED_OFF;
219 u32 reg; 219 u32 reg;
220 220
221 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg); 221 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
222 222
223 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) 223 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
224 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled); 224 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
225 else if (led->type == LED_TYPE_ACTIVITY) 225 else if (led->type == LED_TYPE_ACTIVITY)
226 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled); 226 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
227 227
228 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg); 228 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
229} 229}
230 230
231static int rt2400pci_blink_set(struct led_classdev *led_cdev, 231static int rt2400pci_blink_set(struct led_classdev *led_cdev,
@@ -236,10 +236,10 @@ static int rt2400pci_blink_set(struct led_classdev *led_cdev,
236 container_of(led_cdev, struct rt2x00_led, led_dev); 236 container_of(led_cdev, struct rt2x00_led, led_dev);
237 u32 reg; 237 u32 reg;
238 238
239 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg); 239 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
240 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on); 240 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
241 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off); 241 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
242 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg); 242 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
243 243
244 return 0; 244 return 0;
245} 245}
@@ -269,7 +269,7 @@ static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
269 * Note that the version error will always be dropped 269 * Note that the version error will always be dropped
270 * since there is no filter for it at this time. 270 * since there is no filter for it at this time.
271 */ 271 */
272 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg); 272 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
273 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC, 273 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
274 !(filter_flags & FIF_FCSFAIL)); 274 !(filter_flags & FIF_FCSFAIL));
275 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, 275 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
@@ -282,7 +282,7 @@ static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
282 !(filter_flags & FIF_PROMISC_IN_BSS) && 282 !(filter_flags & FIF_PROMISC_IN_BSS) &&
283 !rt2x00dev->intf_ap_count); 283 !rt2x00dev->intf_ap_count);
284 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1); 284 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
285 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); 285 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
286} 286}
287 287
288static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev, 288static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
@@ -298,25 +298,26 @@ static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
298 * Enable beacon config 298 * Enable beacon config
299 */ 299 */
300 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20); 300 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
301 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg); 301 rt2x00mmio_register_read(rt2x00dev, BCNCSR1, &reg);
302 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload); 302 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
303 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg); 303 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
304 304
305 /* 305 /*
306 * Enable synchronisation. 306 * Enable synchronisation.
307 */ 307 */
308 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 308 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
309 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync); 309 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
310 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 310 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
311 } 311 }
312 312
313 if (flags & CONFIG_UPDATE_MAC) 313 if (flags & CONFIG_UPDATE_MAC)
314 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, 314 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
315 conf->mac, sizeof(conf->mac)); 315 conf->mac, sizeof(conf->mac));
316 316
317 if (flags & CONFIG_UPDATE_BSSID) 317 if (flags & CONFIG_UPDATE_BSSID)
318 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, 318 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
319 conf->bssid, sizeof(conf->bssid)); 319 conf->bssid,
320 sizeof(conf->bssid));
320} 321}
321 322
322static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev, 323static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
@@ -332,68 +333,68 @@ static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
332 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 333 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
333 preamble_mask = erp->short_preamble << 3; 334 preamble_mask = erp->short_preamble << 3;
334 335
335 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg); 336 rt2x00mmio_register_read(rt2x00dev, TXCSR1, &reg);
336 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff); 337 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
337 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a); 338 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
338 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); 339 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
339 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1); 340 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
340 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); 341 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
341 342
342 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg); 343 rt2x00mmio_register_read(rt2x00dev, ARCSR2, &reg);
343 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00); 344 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
344 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04); 345 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
345 rt2x00_set_field32(&reg, ARCSR2_LENGTH, 346 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
346 GET_DURATION(ACK_SIZE, 10)); 347 GET_DURATION(ACK_SIZE, 10));
347 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg); 348 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
348 349
349 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg); 350 rt2x00mmio_register_read(rt2x00dev, ARCSR3, &reg);
350 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask); 351 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
351 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04); 352 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
352 rt2x00_set_field32(&reg, ARCSR2_LENGTH, 353 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
353 GET_DURATION(ACK_SIZE, 20)); 354 GET_DURATION(ACK_SIZE, 20));
354 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg); 355 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
355 356
356 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg); 357 rt2x00mmio_register_read(rt2x00dev, ARCSR4, &reg);
357 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask); 358 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
358 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04); 359 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
359 rt2x00_set_field32(&reg, ARCSR2_LENGTH, 360 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
360 GET_DURATION(ACK_SIZE, 55)); 361 GET_DURATION(ACK_SIZE, 55));
361 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg); 362 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
362 363
363 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg); 364 rt2x00mmio_register_read(rt2x00dev, ARCSR5, &reg);
364 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask); 365 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
365 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84); 366 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
366 rt2x00_set_field32(&reg, ARCSR2_LENGTH, 367 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
367 GET_DURATION(ACK_SIZE, 110)); 368 GET_DURATION(ACK_SIZE, 110));
368 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg); 369 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
369 } 370 }
370 371
371 if (changed & BSS_CHANGED_BASIC_RATES) 372 if (changed & BSS_CHANGED_BASIC_RATES)
372 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates); 373 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
373 374
374 if (changed & BSS_CHANGED_ERP_SLOT) { 375 if (changed & BSS_CHANGED_ERP_SLOT) {
375 rt2x00pci_register_read(rt2x00dev, CSR11, &reg); 376 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
376 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time); 377 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
377 rt2x00pci_register_write(rt2x00dev, CSR11, reg); 378 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
378 379
379 rt2x00pci_register_read(rt2x00dev, CSR18, &reg); 380 rt2x00mmio_register_read(rt2x00dev, CSR18, &reg);
380 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs); 381 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
381 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs); 382 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
382 rt2x00pci_register_write(rt2x00dev, CSR18, reg); 383 rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
383 384
384 rt2x00pci_register_read(rt2x00dev, CSR19, &reg); 385 rt2x00mmio_register_read(rt2x00dev, CSR19, &reg);
385 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs); 386 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
386 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs); 387 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
387 rt2x00pci_register_write(rt2x00dev, CSR19, reg); 388 rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
388 } 389 }
389 390
390 if (changed & BSS_CHANGED_BEACON_INT) { 391 if (changed & BSS_CHANGED_BEACON_INT) {
391 rt2x00pci_register_read(rt2x00dev, CSR12, &reg); 392 rt2x00mmio_register_read(rt2x00dev, CSR12, &reg);
392 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, 393 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
393 erp->beacon_int * 16); 394 erp->beacon_int * 16);
394 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, 395 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
395 erp->beacon_int * 16); 396 erp->beacon_int * 16);
396 rt2x00pci_register_write(rt2x00dev, CSR12, reg); 397 rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
397 } 398 }
398} 399}
399 400
@@ -497,7 +498,7 @@ static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
497 /* 498 /*
498 * Clear false CRC during channel switch. 499 * Clear false CRC during channel switch.
499 */ 500 */
500 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1); 501 rt2x00mmio_register_read(rt2x00dev, CNT0, &rf->rf1);
501} 502}
502 503
503static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower) 504static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
@@ -510,12 +511,12 @@ static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
510{ 511{
511 u32 reg; 512 u32 reg;
512 513
513 rt2x00pci_register_read(rt2x00dev, CSR11, &reg); 514 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
514 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, 515 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
515 libconf->conf->long_frame_max_tx_count); 516 libconf->conf->long_frame_max_tx_count);
516 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, 517 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
517 libconf->conf->short_frame_max_tx_count); 518 libconf->conf->short_frame_max_tx_count);
518 rt2x00pci_register_write(rt2x00dev, CSR11, reg); 519 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
519} 520}
520 521
521static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev, 522static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
@@ -527,7 +528,7 @@ static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
527 u32 reg; 528 u32 reg;
528 529
529 if (state == STATE_SLEEP) { 530 if (state == STATE_SLEEP) {
530 rt2x00pci_register_read(rt2x00dev, CSR20, &reg); 531 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
531 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN, 532 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
532 (rt2x00dev->beacon_int - 20) * 16); 533 (rt2x00dev->beacon_int - 20) * 16);
533 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP, 534 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
@@ -535,14 +536,14 @@ static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
535 536
536 /* We must first disable autowake before it can be enabled */ 537 /* We must first disable autowake before it can be enabled */
537 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0); 538 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
538 rt2x00pci_register_write(rt2x00dev, CSR20, reg); 539 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
539 540
540 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1); 541 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
541 rt2x00pci_register_write(rt2x00dev, CSR20, reg); 542 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
542 } else { 543 } else {
543 rt2x00pci_register_read(rt2x00dev, CSR20, &reg); 544 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
544 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0); 545 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
545 rt2x00pci_register_write(rt2x00dev, CSR20, reg); 546 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
546 } 547 }
547 548
548 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 549 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
@@ -568,10 +569,10 @@ static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
568{ 569{
569 u32 reg; 570 u32 reg;
570 571
571 rt2x00pci_register_read(rt2x00dev, CSR11, &reg); 572 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
572 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min); 573 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
573 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max); 574 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
574 rt2x00pci_register_write(rt2x00dev, CSR11, reg); 575 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
575} 576}
576 577
577/* 578/*
@@ -586,7 +587,7 @@ static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
586 /* 587 /*
587 * Update FCS error count from register. 588 * Update FCS error count from register.
588 */ 589 */
589 rt2x00pci_register_read(rt2x00dev, CNT0, &reg); 590 rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
590 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); 591 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
591 592
592 /* 593 /*
@@ -641,16 +642,16 @@ static void rt2400pci_start_queue(struct data_queue *queue)
641 642
642 switch (queue->qid) { 643 switch (queue->qid) {
643 case QID_RX: 644 case QID_RX:
644 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg); 645 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
645 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0); 646 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
646 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); 647 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
647 break; 648 break;
648 case QID_BEACON: 649 case QID_BEACON:
649 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 650 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
650 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1); 651 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
651 rt2x00_set_field32(&reg, CSR14_TBCN, 1); 652 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
652 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1); 653 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
653 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 654 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
654 break; 655 break;
655 default: 656 default:
656 break; 657 break;
@@ -664,19 +665,19 @@ static void rt2400pci_kick_queue(struct data_queue *queue)
664 665
665 switch (queue->qid) { 666 switch (queue->qid) {
666 case QID_AC_VO: 667 case QID_AC_VO:
667 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg); 668 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
668 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1); 669 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
669 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); 670 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
670 break; 671 break;
671 case QID_AC_VI: 672 case QID_AC_VI:
672 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg); 673 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
673 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1); 674 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
674 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); 675 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
675 break; 676 break;
676 case QID_ATIM: 677 case QID_ATIM:
677 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg); 678 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
678 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1); 679 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
679 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); 680 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
680 break; 681 break;
681 default: 682 default:
682 break; 683 break;
@@ -692,21 +693,21 @@ static void rt2400pci_stop_queue(struct data_queue *queue)
692 case QID_AC_VO: 693 case QID_AC_VO:
693 case QID_AC_VI: 694 case QID_AC_VI:
694 case QID_ATIM: 695 case QID_ATIM:
695 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg); 696 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
696 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1); 697 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
697 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); 698 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
698 break; 699 break;
699 case QID_RX: 700 case QID_RX:
700 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg); 701 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
701 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1); 702 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
702 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); 703 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
703 break; 704 break;
704 case QID_BEACON: 705 case QID_BEACON:
705 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 706 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
706 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0); 707 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
707 rt2x00_set_field32(&reg, CSR14_TBCN, 0); 708 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
708 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); 709 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
709 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 710 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
710 711
711 /* 712 /*
712 * Wait for possibly running tbtt tasklets. 713 * Wait for possibly running tbtt tasklets.
@@ -723,7 +724,7 @@ static void rt2400pci_stop_queue(struct data_queue *queue)
723 */ 724 */
724static bool rt2400pci_get_entry_state(struct queue_entry *entry) 725static bool rt2400pci_get_entry_state(struct queue_entry *entry)
725{ 726{
726 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 727 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
727 u32 word; 728 u32 word;
728 729
729 if (entry->queue->qid == QID_RX) { 730 if (entry->queue->qid == QID_RX) {
@@ -740,7 +741,7 @@ static bool rt2400pci_get_entry_state(struct queue_entry *entry)
740 741
741static void rt2400pci_clear_entry(struct queue_entry *entry) 742static void rt2400pci_clear_entry(struct queue_entry *entry)
742{ 743{
743 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 744 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
744 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 745 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
745 u32 word; 746 u32 word;
746 747
@@ -766,53 +767,53 @@ static void rt2400pci_clear_entry(struct queue_entry *entry)
766 767
767static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) 768static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
768{ 769{
769 struct queue_entry_priv_pci *entry_priv; 770 struct queue_entry_priv_mmio *entry_priv;
770 u32 reg; 771 u32 reg;
771 772
772 /* 773 /*
773 * Initialize registers. 774 * Initialize registers.
774 */ 775 */
775 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg); 776 rt2x00mmio_register_read(rt2x00dev, TXCSR2, &reg);
776 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); 777 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
777 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); 778 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
778 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); 779 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
779 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); 780 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
780 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); 781 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
781 782
782 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; 783 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
783 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg); 784 rt2x00mmio_register_read(rt2x00dev, TXCSR3, &reg);
784 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, 785 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
785 entry_priv->desc_dma); 786 entry_priv->desc_dma);
786 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); 787 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
787 788
788 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; 789 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
789 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg); 790 rt2x00mmio_register_read(rt2x00dev, TXCSR5, &reg);
790 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, 791 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
791 entry_priv->desc_dma); 792 entry_priv->desc_dma);
792 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); 793 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
793 794
794 entry_priv = rt2x00dev->atim->entries[0].priv_data; 795 entry_priv = rt2x00dev->atim->entries[0].priv_data;
795 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg); 796 rt2x00mmio_register_read(rt2x00dev, TXCSR4, &reg);
796 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, 797 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
797 entry_priv->desc_dma); 798 entry_priv->desc_dma);
798 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); 799 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
799 800
800 entry_priv = rt2x00dev->bcn->entries[0].priv_data; 801 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
801 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg); 802 rt2x00mmio_register_read(rt2x00dev, TXCSR6, &reg);
802 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, 803 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
803 entry_priv->desc_dma); 804 entry_priv->desc_dma);
804 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); 805 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
805 806
806 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg); 807 rt2x00mmio_register_read(rt2x00dev, RXCSR1, &reg);
807 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); 808 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
808 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); 809 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
809 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); 810 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
810 811
811 entry_priv = rt2x00dev->rx->entries[0].priv_data; 812 entry_priv = rt2x00dev->rx->entries[0].priv_data;
812 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg); 813 rt2x00mmio_register_read(rt2x00dev, RXCSR2, &reg);
813 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, 814 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
814 entry_priv->desc_dma); 815 entry_priv->desc_dma);
815 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); 816 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
816 817
817 return 0; 818 return 0;
818} 819}
@@ -821,23 +822,23 @@ static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
821{ 822{
822 u32 reg; 823 u32 reg;
823 824
824 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002); 825 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
825 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002); 826 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
826 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20); 827 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20);
827 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002); 828 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
828 829
829 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg); 830 rt2x00mmio_register_read(rt2x00dev, TIMECSR, &reg);
830 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33); 831 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
831 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63); 832 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
832 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0); 833 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
833 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg); 834 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
834 835
835 rt2x00pci_register_read(rt2x00dev, CSR9, &reg); 836 rt2x00mmio_register_read(rt2x00dev, CSR9, &reg);
836 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT, 837 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
837 (rt2x00dev->rx->data_size / 128)); 838 (rt2x00dev->rx->data_size / 128));
838 rt2x00pci_register_write(rt2x00dev, CSR9, reg); 839 rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
839 840
840 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 841 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
841 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0); 842 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
842 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0); 843 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
843 rt2x00_set_field32(&reg, CSR14_TBCN, 0); 844 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
@@ -846,63 +847,63 @@ static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
846 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); 847 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
847 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0); 848 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
848 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0); 849 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
849 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 850 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
850 851
851 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000); 852 rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000);
852 853
853 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg); 854 rt2x00mmio_register_read(rt2x00dev, ARCSR0, &reg);
854 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133); 855 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
855 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134); 856 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
856 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136); 857 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
857 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135); 858 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
858 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg); 859 rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg);
859 860
860 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg); 861 rt2x00mmio_register_read(rt2x00dev, RXCSR3, &reg);
861 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/ 862 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
862 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1); 863 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
863 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */ 864 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
864 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1); 865 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
865 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */ 866 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
866 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1); 867 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
867 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg); 868 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
868 869
869 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); 870 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
870 871
871 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) 872 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
872 return -EBUSY; 873 return -EBUSY;
873 874
874 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223); 875 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223);
875 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518); 876 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
876 877
877 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg); 878 rt2x00mmio_register_read(rt2x00dev, MACCSR2, &reg);
878 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64); 879 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
879 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg); 880 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
880 881
881 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg); 882 rt2x00mmio_register_read(rt2x00dev, RALINKCSR, &reg);
882 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17); 883 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
883 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154); 884 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
884 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0); 885 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
885 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154); 886 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
886 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg); 887 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
887 888
888 rt2x00pci_register_read(rt2x00dev, CSR1, &reg); 889 rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
889 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1); 890 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
890 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0); 891 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
891 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0); 892 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
892 rt2x00pci_register_write(rt2x00dev, CSR1, reg); 893 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
893 894
894 rt2x00pci_register_read(rt2x00dev, CSR1, &reg); 895 rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
895 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0); 896 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
896 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1); 897 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
897 rt2x00pci_register_write(rt2x00dev, CSR1, reg); 898 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
898 899
899 /* 900 /*
900 * We must clear the FCS and FIFO error count. 901 * We must clear the FCS and FIFO error count.
901 * These registers are cleared on read, 902 * These registers are cleared on read,
902 * so we may pass a useless variable to store the value. 903 * so we may pass a useless variable to store the value.
903 */ 904 */
904 rt2x00pci_register_read(rt2x00dev, CNT0, &reg); 905 rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
905 rt2x00pci_register_read(rt2x00dev, CNT4, &reg); 906 rt2x00mmio_register_read(rt2x00dev, CNT4, &reg);
906 907
907 return 0; 908 return 0;
908} 909}
@@ -919,7 +920,7 @@ static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
919 udelay(REGISTER_BUSY_DELAY); 920 udelay(REGISTER_BUSY_DELAY);
920 } 921 }
921 922
922 ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); 923 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
923 return -EACCES; 924 return -EACCES;
924} 925}
925 926
@@ -976,8 +977,8 @@ static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
976 * should clear the register to assure a clean state. 977 * should clear the register to assure a clean state.
977 */ 978 */
978 if (state == STATE_RADIO_IRQ_ON) { 979 if (state == STATE_RADIO_IRQ_ON) {
979 rt2x00pci_register_read(rt2x00dev, CSR7, &reg); 980 rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
980 rt2x00pci_register_write(rt2x00dev, CSR7, reg); 981 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
981 } 982 }
982 983
983 /* 984 /*
@@ -986,13 +987,13 @@ static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
986 */ 987 */
987 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); 988 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
988 989
989 rt2x00pci_register_read(rt2x00dev, CSR8, &reg); 990 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
990 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask); 991 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
991 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask); 992 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
992 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask); 993 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
993 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask); 994 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
994 rt2x00_set_field32(&reg, CSR8_RXDONE, mask); 995 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
995 rt2x00pci_register_write(rt2x00dev, CSR8, reg); 996 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
996 997
997 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); 998 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
998 999
@@ -1025,7 +1026,7 @@ static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1025 /* 1026 /*
1026 * Disable power 1027 * Disable power
1027 */ 1028 */
1028 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0); 1029 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
1029} 1030}
1030 1031
1031static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, 1032static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
@@ -1039,12 +1040,12 @@ static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1039 1040
1040 put_to_sleep = (state != STATE_AWAKE); 1041 put_to_sleep = (state != STATE_AWAKE);
1041 1042
1042 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg); 1043 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg);
1043 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1); 1044 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1044 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state); 1045 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1045 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state); 1046 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1046 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); 1047 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1047 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg); 1048 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1048 1049
1049 /* 1050 /*
1050 * Device is not guaranteed to be in the requested state yet. 1051 * Device is not guaranteed to be in the requested state yet.
@@ -1052,12 +1053,12 @@ static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1052 * device has entered the correct state. 1053 * device has entered the correct state.
1053 */ 1054 */
1054 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1055 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1055 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2); 1056 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg2);
1056 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE); 1057 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1057 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE); 1058 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1058 if (bbp_state == state && rf_state == state) 1059 if (bbp_state == state && rf_state == state)
1059 return 0; 1060 return 0;
1060 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg); 1061 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1061 msleep(10); 1062 msleep(10);
1062 } 1063 }
1063 1064
@@ -1092,8 +1093,8 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1092 } 1093 }
1093 1094
1094 if (unlikely(retval)) 1095 if (unlikely(retval))
1095 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n", 1096 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1096 state, retval); 1097 state, retval);
1097 1098
1098 return retval; 1099 return retval;
1099} 1100}
@@ -1105,7 +1106,7 @@ static void rt2400pci_write_tx_desc(struct queue_entry *entry,
1105 struct txentry_desc *txdesc) 1106 struct txentry_desc *txdesc)
1106{ 1107{
1107 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1108 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1108 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1109 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1109 __le32 *txd = entry_priv->desc; 1110 __le32 *txd = entry_priv->desc;
1110 u32 word; 1111 u32 word;
1111 1112
@@ -1182,12 +1183,12 @@ static void rt2400pci_write_beacon(struct queue_entry *entry,
1182 * Disable beaconing while we are reloading the beacon data, 1183 * Disable beaconing while we are reloading the beacon data,
1183 * otherwise we might be sending out invalid data. 1184 * otherwise we might be sending out invalid data.
1184 */ 1185 */
1185 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 1186 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
1186 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); 1187 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1187 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1188 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1188 1189
1189 if (rt2x00queue_map_txskb(entry)) { 1190 if (rt2x00queue_map_txskb(entry)) {
1190 ERROR(rt2x00dev, "Fail to map beacon, aborting\n"); 1191 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
1191 goto out; 1192 goto out;
1192 } 1193 }
1193 /* 1194 /*
@@ -1208,7 +1209,7 @@ out:
1208 * Enable beaconing again. 1209 * Enable beaconing again.
1209 */ 1210 */
1210 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1); 1211 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1211 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1212 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1212} 1213}
1213 1214
1214/* 1215/*
@@ -1218,7 +1219,7 @@ static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1218 struct rxdone_entry_desc *rxdesc) 1219 struct rxdone_entry_desc *rxdesc)
1219{ 1220{
1220 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1221 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1221 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1222 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1222 u32 word0; 1223 u32 word0;
1223 u32 word2; 1224 u32 word2;
1224 u32 word3; 1225 u32 word3;
@@ -1276,7 +1277,7 @@ static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1276 const enum data_queue_qid queue_idx) 1277 const enum data_queue_qid queue_idx)
1277{ 1278{
1278 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 1279 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1279 struct queue_entry_priv_pci *entry_priv; 1280 struct queue_entry_priv_mmio *entry_priv;
1280 struct queue_entry *entry; 1281 struct queue_entry *entry;
1281 struct txdone_entry_desc txdesc; 1282 struct txdone_entry_desc txdesc;
1282 u32 word; 1283 u32 word;
@@ -1322,9 +1323,9 @@ static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1322 */ 1323 */
1323 spin_lock_irq(&rt2x00dev->irqmask_lock); 1324 spin_lock_irq(&rt2x00dev->irqmask_lock);
1324 1325
1325 rt2x00pci_register_read(rt2x00dev, CSR8, &reg); 1326 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1326 rt2x00_set_field32(&reg, irq_field, 0); 1327 rt2x00_set_field32(&reg, irq_field, 0);
1327 rt2x00pci_register_write(rt2x00dev, CSR8, reg); 1328 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1328 1329
1329 spin_unlock_irq(&rt2x00dev->irqmask_lock); 1330 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1330} 1331}
@@ -1347,11 +1348,11 @@ static void rt2400pci_txstatus_tasklet(unsigned long data)
1347 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) { 1348 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1348 spin_lock_irq(&rt2x00dev->irqmask_lock); 1349 spin_lock_irq(&rt2x00dev->irqmask_lock);
1349 1350
1350 rt2x00pci_register_read(rt2x00dev, CSR8, &reg); 1351 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1351 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0); 1352 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1352 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0); 1353 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1353 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0); 1354 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1354 rt2x00pci_register_write(rt2x00dev, CSR8, reg); 1355 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1355 1356
1356 spin_unlock_irq(&rt2x00dev->irqmask_lock); 1357 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1357 } 1358 }
@@ -1368,7 +1369,7 @@ static void rt2400pci_tbtt_tasklet(unsigned long data)
1368static void rt2400pci_rxdone_tasklet(unsigned long data) 1369static void rt2400pci_rxdone_tasklet(unsigned long data)
1369{ 1370{
1370 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; 1371 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1371 if (rt2x00pci_rxdone(rt2x00dev)) 1372 if (rt2x00mmio_rxdone(rt2x00dev))
1372 tasklet_schedule(&rt2x00dev->rxdone_tasklet); 1373 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1373 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 1374 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1374 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE); 1375 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
@@ -1383,8 +1384,8 @@ static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1383 * Get the interrupt sources & saved to local variable. 1384 * Get the interrupt sources & saved to local variable.
1384 * Write register value back to clear pending interrupts. 1385 * Write register value back to clear pending interrupts.
1385 */ 1386 */
1386 rt2x00pci_register_read(rt2x00dev, CSR7, &reg); 1387 rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
1387 rt2x00pci_register_write(rt2x00dev, CSR7, reg); 1388 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1388 1389
1389 if (!reg) 1390 if (!reg)
1390 return IRQ_NONE; 1391 return IRQ_NONE;
@@ -1421,9 +1422,9 @@ static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1421 */ 1422 */
1422 spin_lock(&rt2x00dev->irqmask_lock); 1423 spin_lock(&rt2x00dev->irqmask_lock);
1423 1424
1424 rt2x00pci_register_read(rt2x00dev, CSR8, &reg); 1425 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1425 reg |= mask; 1426 reg |= mask;
1426 rt2x00pci_register_write(rt2x00dev, CSR8, reg); 1427 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1427 1428
1428 spin_unlock(&rt2x00dev->irqmask_lock); 1429 spin_unlock(&rt2x00dev->irqmask_lock);
1429 1430
@@ -1442,7 +1443,7 @@ static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1442 u16 word; 1443 u16 word;
1443 u8 *mac; 1444 u8 *mac;
1444 1445
1445 rt2x00pci_register_read(rt2x00dev, CSR21, &reg); 1446 rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
1446 1447
1447 eeprom.data = rt2x00dev; 1448 eeprom.data = rt2x00dev;
1448 eeprom.register_read = rt2400pci_eepromregister_read; 1449 eeprom.register_read = rt2400pci_eepromregister_read;
@@ -1463,12 +1464,12 @@ static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1463 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 1464 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1464 if (!is_valid_ether_addr(mac)) { 1465 if (!is_valid_ether_addr(mac)) {
1465 eth_random_addr(mac); 1466 eth_random_addr(mac);
1466 EEPROM(rt2x00dev, "MAC: %pM\n", mac); 1467 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
1467 } 1468 }
1468 1469
1469 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); 1470 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1470 if (word == 0xffff) { 1471 if (word == 0xffff) {
1471 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n"); 1472 rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n");
1472 return -EINVAL; 1473 return -EINVAL;
1473 } 1474 }
1474 1475
@@ -1490,12 +1491,12 @@ static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1490 * Identify RF chipset. 1491 * Identify RF chipset.
1491 */ 1492 */
1492 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 1493 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1493 rt2x00pci_register_read(rt2x00dev, CSR0, &reg); 1494 rt2x00mmio_register_read(rt2x00dev, CSR0, &reg);
1494 rt2x00_set_chip(rt2x00dev, RT2460, value, 1495 rt2x00_set_chip(rt2x00dev, RT2460, value,
1495 rt2x00_get_field32(reg, CSR0_REVISION)); 1496 rt2x00_get_field32(reg, CSR0_REVISION));
1496 1497
1497 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) { 1498 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
1498 ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); 1499 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1499 return -ENODEV; 1500 return -ENODEV;
1500 } 1501 }
1501 1502
@@ -1635,9 +1636,9 @@ static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1635 * Enable rfkill polling by setting GPIO direction of the 1636 * Enable rfkill polling by setting GPIO direction of the
1636 * rfkill switch GPIO pin correctly. 1637 * rfkill switch GPIO pin correctly.
1637 */ 1638 */
1638 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg); 1639 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
1639 rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1); 1640 rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
1640 rt2x00pci_register_write(rt2x00dev, GPIOCSR, reg); 1641 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
1641 1642
1642 /* 1643 /*
1643 * Initialize hw specifications. 1644 * Initialize hw specifications.
@@ -1697,9 +1698,9 @@ static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw,
1697 u64 tsf; 1698 u64 tsf;
1698 u32 reg; 1699 u32 reg;
1699 1700
1700 rt2x00pci_register_read(rt2x00dev, CSR17, &reg); 1701 rt2x00mmio_register_read(rt2x00dev, CSR17, &reg);
1701 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; 1702 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1702 rt2x00pci_register_read(rt2x00dev, CSR16, &reg); 1703 rt2x00mmio_register_read(rt2x00dev, CSR16, &reg);
1703 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); 1704 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1704 1705
1705 return tsf; 1706 return tsf;
@@ -1710,7 +1711,7 @@ static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1710 struct rt2x00_dev *rt2x00dev = hw->priv; 1711 struct rt2x00_dev *rt2x00dev = hw->priv;
1711 u32 reg; 1712 u32 reg;
1712 1713
1713 rt2x00pci_register_read(rt2x00dev, CSR15, &reg); 1714 rt2x00mmio_register_read(rt2x00dev, CSR15, &reg);
1714 return rt2x00_get_field32(reg, CSR15_BEACON_SENT); 1715 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1715} 1716}
1716 1717
@@ -1743,8 +1744,8 @@ static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1743 .tbtt_tasklet = rt2400pci_tbtt_tasklet, 1744 .tbtt_tasklet = rt2400pci_tbtt_tasklet,
1744 .rxdone_tasklet = rt2400pci_rxdone_tasklet, 1745 .rxdone_tasklet = rt2400pci_rxdone_tasklet,
1745 .probe_hw = rt2400pci_probe_hw, 1746 .probe_hw = rt2400pci_probe_hw,
1746 .initialize = rt2x00pci_initialize, 1747 .initialize = rt2x00mmio_initialize,
1747 .uninitialize = rt2x00pci_uninitialize, 1748 .uninitialize = rt2x00mmio_uninitialize,
1748 .get_entry_state = rt2400pci_get_entry_state, 1749 .get_entry_state = rt2400pci_get_entry_state,
1749 .clear_entry = rt2400pci_clear_entry, 1750 .clear_entry = rt2400pci_clear_entry,
1750 .set_device_state = rt2400pci_set_device_state, 1751 .set_device_state = rt2400pci_set_device_state,
@@ -1755,7 +1756,7 @@ static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1755 .start_queue = rt2400pci_start_queue, 1756 .start_queue = rt2400pci_start_queue,
1756 .kick_queue = rt2400pci_kick_queue, 1757 .kick_queue = rt2400pci_kick_queue,
1757 .stop_queue = rt2400pci_stop_queue, 1758 .stop_queue = rt2400pci_stop_queue,
1758 .flush_queue = rt2x00pci_flush_queue, 1759 .flush_queue = rt2x00mmio_flush_queue,
1759 .write_tx_desc = rt2400pci_write_tx_desc, 1760 .write_tx_desc = rt2400pci_write_tx_desc,
1760 .write_beacon = rt2400pci_write_beacon, 1761 .write_beacon = rt2400pci_write_beacon,
1761 .fill_rxdone = rt2400pci_fill_rxdone, 1762 .fill_rxdone = rt2400pci_fill_rxdone,
@@ -1770,28 +1771,28 @@ static const struct data_queue_desc rt2400pci_queue_rx = {
1770 .entry_num = 24, 1771 .entry_num = 24,
1771 .data_size = DATA_FRAME_SIZE, 1772 .data_size = DATA_FRAME_SIZE,
1772 .desc_size = RXD_DESC_SIZE, 1773 .desc_size = RXD_DESC_SIZE,
1773 .priv_size = sizeof(struct queue_entry_priv_pci), 1774 .priv_size = sizeof(struct queue_entry_priv_mmio),
1774}; 1775};
1775 1776
1776static const struct data_queue_desc rt2400pci_queue_tx = { 1777static const struct data_queue_desc rt2400pci_queue_tx = {
1777 .entry_num = 24, 1778 .entry_num = 24,
1778 .data_size = DATA_FRAME_SIZE, 1779 .data_size = DATA_FRAME_SIZE,
1779 .desc_size = TXD_DESC_SIZE, 1780 .desc_size = TXD_DESC_SIZE,
1780 .priv_size = sizeof(struct queue_entry_priv_pci), 1781 .priv_size = sizeof(struct queue_entry_priv_mmio),
1781}; 1782};
1782 1783
1783static const struct data_queue_desc rt2400pci_queue_bcn = { 1784static const struct data_queue_desc rt2400pci_queue_bcn = {
1784 .entry_num = 1, 1785 .entry_num = 1,
1785 .data_size = MGMT_FRAME_SIZE, 1786 .data_size = MGMT_FRAME_SIZE,
1786 .desc_size = TXD_DESC_SIZE, 1787 .desc_size = TXD_DESC_SIZE,
1787 .priv_size = sizeof(struct queue_entry_priv_pci), 1788 .priv_size = sizeof(struct queue_entry_priv_mmio),
1788}; 1789};
1789 1790
1790static const struct data_queue_desc rt2400pci_queue_atim = { 1791static const struct data_queue_desc rt2400pci_queue_atim = {
1791 .entry_num = 8, 1792 .entry_num = 8,
1792 .data_size = DATA_FRAME_SIZE, 1793 .data_size = DATA_FRAME_SIZE,
1793 .desc_size = TXD_DESC_SIZE, 1794 .desc_size = TXD_DESC_SIZE,
1794 .priv_size = sizeof(struct queue_entry_priv_pci), 1795 .priv_size = sizeof(struct queue_entry_priv_mmio),
1795}; 1796};
1796 1797
1797static const struct rt2x00_ops rt2400pci_ops = { 1798static const struct rt2x00_ops rt2400pci_ops = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-26 15:51:02 -0500