diff options
Diffstat (limited to 'drivers/net/wireless/ath/carl9170/hw.h')
-rw-r--r-- | drivers/net/wireless/ath/carl9170/hw.h | 41 |
1 files changed, 39 insertions, 2 deletions
diff --git a/drivers/net/wireless/ath/carl9170/hw.h b/drivers/net/wireless/ath/carl9170/hw.h index 261f89351070..fa834c1460f0 100644 --- a/drivers/net/wireless/ath/carl9170/hw.h +++ b/drivers/net/wireless/ath/carl9170/hw.h | |||
@@ -174,6 +174,7 @@ | |||
174 | #define AR9170_MAC_SNIFFER_ENABLE_PROMISC BIT(0) | 174 | #define AR9170_MAC_SNIFFER_ENABLE_PROMISC BIT(0) |
175 | #define AR9170_MAC_SNIFFER_DEFAULTS 0x02000000 | 175 | #define AR9170_MAC_SNIFFER_DEFAULTS 0x02000000 |
176 | #define AR9170_MAC_REG_ENCRYPTION (AR9170_MAC_REG_BASE + 0x678) | 176 | #define AR9170_MAC_REG_ENCRYPTION (AR9170_MAC_REG_BASE + 0x678) |
177 | #define AR9170_MAC_ENCRYPTION_MGMT_RX_SOFTWARE BIT(2) | ||
177 | #define AR9170_MAC_ENCRYPTION_RX_SOFTWARE BIT(3) | 178 | #define AR9170_MAC_ENCRYPTION_RX_SOFTWARE BIT(3) |
178 | #define AR9170_MAC_ENCRYPTION_DEFAULTS 0x70 | 179 | #define AR9170_MAC_ENCRYPTION_DEFAULTS 0x70 |
179 | 180 | ||
@@ -222,6 +223,12 @@ | |||
222 | #define AR9170_MAC_REG_TX_BLOCKACKS (AR9170_MAC_REG_BASE + 0x6c0) | 223 | #define AR9170_MAC_REG_TX_BLOCKACKS (AR9170_MAC_REG_BASE + 0x6c0) |
223 | #define AR9170_MAC_REG_NAV_COUNT (AR9170_MAC_REG_BASE + 0x6c4) | 224 | #define AR9170_MAC_REG_NAV_COUNT (AR9170_MAC_REG_BASE + 0x6c4) |
224 | #define AR9170_MAC_REG_BACKOFF_STATUS (AR9170_MAC_REG_BASE + 0x6c8) | 225 | #define AR9170_MAC_REG_BACKOFF_STATUS (AR9170_MAC_REG_BASE + 0x6c8) |
226 | #define AR9170_MAC_BACKOFF_CCA BIT(24) | ||
227 | #define AR9170_MAC_BACKOFF_TX_PEX BIT(25) | ||
228 | #define AR9170_MAC_BACKOFF_RX_PE BIT(26) | ||
229 | #define AR9170_MAC_BACKOFF_MD_READY BIT(27) | ||
230 | #define AR9170_MAC_BACKOFF_TX_PE BIT(28) | ||
231 | |||
225 | #define AR9170_MAC_REG_TX_RETRY (AR9170_MAC_REG_BASE + 0x6cc) | 232 | #define AR9170_MAC_REG_TX_RETRY (AR9170_MAC_REG_BASE + 0x6cc) |
226 | 233 | ||
227 | #define AR9170_MAC_REG_TX_COMPLETE (AR9170_MAC_REG_BASE + 0x6d4) | 234 | #define AR9170_MAC_REG_TX_COMPLETE (AR9170_MAC_REG_BASE + 0x6d4) |
@@ -388,10 +395,40 @@ | |||
388 | 395 | ||
389 | #define AR9170_MAC_REG_BCN_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd98) | 396 | #define AR9170_MAC_REG_BCN_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd98) |
390 | #define AR9170_MAC_REG_BCN_COUNT (AR9170_MAC_REG_BASE + 0xd9c) | 397 | #define AR9170_MAC_REG_BCN_COUNT (AR9170_MAC_REG_BASE + 0xd9c) |
391 | |||
392 | |||
393 | #define AR9170_MAC_REG_BCN_HT1 (AR9170_MAC_REG_BASE + 0xda0) | 398 | #define AR9170_MAC_REG_BCN_HT1 (AR9170_MAC_REG_BASE + 0xda0) |
399 | #define AR9170_MAC_BCN_HT1_HT_EN BIT(0) | ||
400 | #define AR9170_MAC_BCN_HT1_GF_PMB BIT(1) | ||
401 | #define AR9170_MAC_BCN_HT1_SP_EXP BIT(2) | ||
402 | #define AR9170_MAC_BCN_HT1_TX_BF BIT(3) | ||
403 | #define AR9170_MAC_BCN_HT1_PWR_CTRL_S 4 | ||
404 | #define AR9170_MAC_BCN_HT1_PWR_CTRL 0x70 | ||
405 | #define AR9170_MAC_BCN_HT1_TX_ANT1 BIT(7) | ||
406 | #define AR9170_MAC_BCN_HT1_TX_ANT0 BIT(8) | ||
407 | #define AR9170_MAC_BCN_HT1_NUM_LFT_S 9 | ||
408 | #define AR9170_MAC_BCN_HT1_NUM_LFT 0x600 | ||
409 | #define AR9170_MAC_BCN_HT1_BWC_20M_EXT BIT(16) | ||
410 | #define AR9170_MAC_BCN_HT1_BWC_40M_SHARED BIT(17) | ||
411 | #define AR9170_MAC_BCN_HT1_BWC_40M_DUP (BIT(16) | BIT(17)) | ||
412 | #define AR9170_MAC_BCN_HT1_BF_MCS_S 18 | ||
413 | #define AR9170_MAC_BCN_HT1_BF_MCS 0x1c0000 | ||
414 | #define AR9170_MAC_BCN_HT1_TPC_S 21 | ||
415 | #define AR9170_MAC_BCN_HT1_TPC 0x7e00000 | ||
416 | #define AR9170_MAC_BCN_HT1_CHAIN_MASK_S 27 | ||
417 | #define AR9170_MAC_BCN_HT1_CHAIN_MASK 0x38000000 | ||
418 | |||
394 | #define AR9170_MAC_REG_BCN_HT2 (AR9170_MAC_REG_BASE + 0xda4) | 419 | #define AR9170_MAC_REG_BCN_HT2 (AR9170_MAC_REG_BASE + 0xda4) |
420 | #define AR9170_MAC_BCN_HT2_MCS_S 0 | ||
421 | #define AR9170_MAC_BCN_HT2_MCS 0x7f | ||
422 | #define AR9170_MAC_BCN_HT2_BW40 BIT(8) | ||
423 | #define AR9170_MAC_BCN_HT2_SMOOTHING BIT(9) | ||
424 | #define AR9170_MAC_BCN_HT2_SS BIT(10) | ||
425 | #define AR9170_MAC_BCN_HT2_NSS BIT(11) | ||
426 | #define AR9170_MAC_BCN_HT2_STBC_S 12 | ||
427 | #define AR9170_MAC_BCN_HT2_STBC 0x3000 | ||
428 | #define AR9170_MAC_BCN_HT2_ADV_COD BIT(14) | ||
429 | #define AR9170_MAC_BCN_HT2_SGI BIT(15) | ||
430 | #define AR9170_MAC_BCN_HT2_LEN_S 16 | ||
431 | #define AR9170_MAC_BCN_HT2_LEN 0xffff0000 | ||
395 | 432 | ||
396 | #define AR9170_MAC_REG_DMA_TXQX_ADDR_CURR (AR9170_MAC_REG_BASE + 0xdc0) | 433 | #define AR9170_MAC_REG_DMA_TXQX_ADDR_CURR (AR9170_MAC_REG_BASE + 0xdc0) |
397 | 434 | ||