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path: root/drivers/net/wireless/ath/ath9k/calib.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/calib.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.c25
1 files changed, 21 insertions, 4 deletions
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index 20f74b5b5703..47a024da29c9 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -861,7 +861,7 @@ static void ath9k_hw_9271_pa_cal(struct ath_hw *ah)
861 REG_WRITE(ah, regList[i][0], regList[i][1]); 861 REG_WRITE(ah, regList[i][0], regList[i][1]);
862} 862}
863 863
864static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah) 864static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
865{ 865{
866 866
867 u32 regVal; 867 u32 regVal;
@@ -877,6 +877,8 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah)
877 { 0x7838, 0 }, 877 { 0x7838, 0 },
878 }; 878 };
879 879
880 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
881
880 if (AR_SREV_9285_11(ah)) { 882 if (AR_SREV_9285_11(ah)) {
881 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); 883 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
882 udelay(10); 884 udelay(10);
@@ -936,6 +938,17 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah)
936 offs_6_1 = offset>>1; 938 offs_6_1 = offset>>1;
937 offs_0 = offset & 1; 939 offs_0 = offset & 1;
938 940
941 if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
942 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
943 ah->pacal_info.max_skipcount =
944 2 * ah->pacal_info.max_skipcount;
945 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
946 } else {
947 ah->pacal_info.max_skipcount = 1;
948 ah->pacal_info.skipcount = 0;
949 ah->pacal_info.prev_offset = offset;
950 }
951
939 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1); 952 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
940 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0); 953 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
941 954
@@ -982,8 +995,12 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
982 /* Do periodic PAOffset Cal */ 995 /* Do periodic PAOffset Cal */
983 if (AR_SREV_9271(ah)) 996 if (AR_SREV_9271(ah))
984 ath9k_hw_9271_pa_cal(ah); 997 ath9k_hw_9271_pa_cal(ah);
985 else if (AR_SREV_9285_11_OR_LATER(ah)) 998 else if (AR_SREV_9285_11_OR_LATER(ah)) {
986 ath9k_hw_9285_pa_cal(ah); 999 if (!ah->pacal_info.skipcount)
1000 ath9k_hw_9285_pa_cal(ah, false);
1001 else
1002 ah->pacal_info.skipcount--;
1003 }
987 1004
988 if (OLC_FOR_AR9280_20_LATER || OLC_FOR_AR9287_10_LATER) 1005 if (OLC_FOR_AR9280_20_LATER || OLC_FOR_AR9287_10_LATER)
989 ath9k_olc_temp_compensation(ah); 1006 ath9k_olc_temp_compensation(ah);
@@ -1081,7 +1098,7 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1081 1098
1082 /* Do PA Calibration */ 1099 /* Do PA Calibration */
1083 if (AR_SREV_9285_11_OR_LATER(ah)) 1100 if (AR_SREV_9285_11_OR_LATER(ah))
1084 ath9k_hw_9285_pa_cal(ah); 1101 ath9k_hw_9285_pa_cal(ah, true);
1085 1102
1086 /* Do NF Calibration after DC offset and other calibrations */ 1103 /* Do NF Calibration after DC offset and other calibrations */
1087 REG_WRITE(ah, AR_PHY_AGC_CONTROL, 1104 REG_WRITE(ah, AR_PHY_AGC_CONTROL,