diff options
Diffstat (limited to 'drivers/net/ethernet/chelsio/cxgb4vf/t4vf_common.h')
-rw-r--r-- | drivers/net/ethernet/chelsio/cxgb4vf/t4vf_common.h | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_common.h b/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_common.h index 53cbfed21d0b..61362450d05b 100644 --- a/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_common.h +++ b/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_common.h | |||
@@ -39,21 +39,28 @@ | |||
39 | #include "../cxgb4/t4fw_api.h" | 39 | #include "../cxgb4/t4fw_api.h" |
40 | 40 | ||
41 | #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) | 41 | #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) |
42 | #define CHELSIO_CHIP_VERSION(code) ((code) >> 4) | 42 | #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf) |
43 | #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) | 43 | #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) |
44 | 44 | ||
45 | /* All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where: | ||
46 | * | ||
47 | * V = "4" for T4; "5" for T5, etc. or | ||
48 | * = "a" for T4 FPGA; "b" for T4 FPGA, etc. | ||
49 | * F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs | ||
50 | * PP = adapter product designation | ||
51 | */ | ||
45 | #define CHELSIO_T4 0x4 | 52 | #define CHELSIO_T4 0x4 |
46 | #define CHELSIO_T5 0x5 | 53 | #define CHELSIO_T5 0x5 |
47 | 54 | ||
48 | enum chip_type { | 55 | enum chip_type { |
49 | T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 0), | 56 | T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), |
50 | T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), | 57 | T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), |
51 | T4_A3 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), | ||
52 | T4_FIRST_REV = T4_A1, | 58 | T4_FIRST_REV = T4_A1, |
53 | T4_LAST_REV = T4_A3, | 59 | T4_LAST_REV = T4_A2, |
54 | 60 | ||
55 | T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), | 61 | T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), |
56 | T5_FIRST_REV = T5_A1, | 62 | T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1), |
63 | T5_FIRST_REV = T5_A0, | ||
57 | T5_LAST_REV = T5_A1, | 64 | T5_LAST_REV = T5_A1, |
58 | }; | 65 | }; |
59 | 66 | ||
@@ -203,6 +210,7 @@ struct adapter_params { | |||
203 | struct vpd_params vpd; /* Vital Product Data */ | 210 | struct vpd_params vpd; /* Vital Product Data */ |
204 | struct rss_params rss; /* Receive Side Scaling */ | 211 | struct rss_params rss; /* Receive Side Scaling */ |
205 | struct vf_resources vfres; /* Virtual Function Resource limits */ | 212 | struct vf_resources vfres; /* Virtual Function Resource limits */ |
213 | enum chip_type chip; /* chip code */ | ||
206 | u8 nports; /* # of Ethernet "ports" */ | 214 | u8 nports; /* # of Ethernet "ports" */ |
207 | }; | 215 | }; |
208 | 216 | ||
@@ -253,7 +261,7 @@ static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd, | |||
253 | 261 | ||
254 | static inline int is_t4(enum chip_type chip) | 262 | static inline int is_t4(enum chip_type chip) |
255 | { | 263 | { |
256 | return (chip >= T4_FIRST_REV && chip <= T4_LAST_REV); | 264 | return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4; |
257 | } | 265 | } |
258 | 266 | ||
259 | int t4vf_wait_dev_ready(struct adapter *); | 267 | int t4vf_wait_dev_ready(struct adapter *); |