1 files changed, 499 insertions, 0 deletions
diff --git a/drivers/net/ethernet/atheros/alx/hw.h b/drivers/net/ethernet/atheros/alx/hw.h
new file mode 100644
index 000000000000..65e723d2172a
--- /dev/null
+++ b/drivers/net/ethernet/atheros/alx/hw.h
@@ -0,0 +1,499 @@
+/*
+ * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
+ *
+ *  This file is free software: you may copy, redistribute and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation, either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  This file is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef ALX_HW_H_
+#define ALX_HW_H_
+#include <linux/types.h>
+#include <linux/mdio.h>
+#include <linux/pci.h>
+#include "reg.h"
+/* Transmit Packet Descriptor, contains 4 32-bit words.
+ *
+ *   31               16               0
+ *   +----------------+----------------+
+ *   |    vlan-tag    |   buf length   |
+ *   +----------------+----------------+
+ *   |              Word 1             |
+ *   +----------------+----------------+
+ *   |      Word 2: buf addr lo        |
+ *   +----------------+----------------+
+ *   |      Word 3: buf addr hi        |
+ *   +----------------+----------------+
+ *
+ * Word 2 and 3 combine to form a 64-bit buffer address
+ *
+ * Word 1 has three forms, depending on the state of bit 8/12/13:
+ * if bit8 =='1', the definition is just for custom checksum offload.
+ * if bit8 == '0' && bit12 == '1' && bit13 == '1', the *FIRST* descriptor
+ *     for the skb is special for LSO V2, Word 2 become total skb length ,
+ *     Word 3 is meaningless.
+ * other condition, the definition is for general skb or ip/tcp/udp
+ *     checksum or LSO(TSO) offload.
+ *
+ * Here is the depiction:
+ *
+ *   0-+                                  0-+
+ *   1 |                                  1 |
+ *   2 |                                  2 |
+ *   3 |    Payload offset                3 |    L4 header offset
+ *   4 |        (7:0)                     4 |        (7:0)
+ *   5 |                                  5 |
+ *   6 |                                  6 |
+ *   7-+                                  7-+
+ *   8      Custom csum enable = 1        8      Custom csum enable = 0
+ *   9      General IPv4 checksum         9      General IPv4 checksum
+ *   10     General TCP checksum          10     General TCP checksum
+ *   11     General UDP checksum          11     General UDP checksum
+ *   12     Large Send Segment enable     12     Large Send Segment enable
+ *   13     Large Send Segment type       13     Large Send Segment type
+ *   14     VLAN tagged                   14     VLAN tagged
+ *   15     Insert VLAN tag               15     Insert VLAN tag
+ *   16     IPv4 packet                   16     IPv4 packet
+ *   17     Ethernet frame type           17     Ethernet frame type
+ *   18-+                                 18-+
+ *   19 |                                 19 |
+ *   20 |                                 20 |
+ *   21 |   Custom csum offset            21 |
+ *   22 |       (25:18)                   22 |
+ *   23 |                                 23 |   MSS (30:18)
+ *   24 |                                 24 |
+ *   25-+                                 25 |
+ *   26-+                                 26 |
+ *   27 |                                 27 |
+ *   28 |   Reserved                      28 |
+ *   29 |                                 29 |
+ *   30-+                                 30-+
+ *   31     End of packet                 31     End of packet
+ */
+struct alx_txd {
+        __le16 len;
+        __le16 vlan_tag;
+        __le32 word1;
+        union {
+                __le64 addr;
+                struct {
+                        __le32 pkt_len;
+                        __le32 resvd;
+                } l;
+        } adrl;
+} __packed;
+/* tpd word 1 */
+#define TPD_CXSUMSTART_MASK             0x00FF
+#define TPD_CXSUMSTART_SHIFT            0
+#define TPD_L4HDROFFSET_MASK            0x00FF
+#define TPD_L4HDROFFSET_SHIFT           0
+#define TPD_CXSUM_EN_MASK               0x0001
+#define TPD_CXSUM_EN_SHIFT              8
+#define TPD_IP_XSUM_MASK                0x0001
+#define TPD_IP_XSUM_SHIFT               9
+#define TPD_TCP_XSUM_MASK               0x0001
+#define TPD_TCP_XSUM_SHIFT              10
+#define TPD_UDP_XSUM_MASK               0x0001
+#define TPD_UDP_XSUM_SHIFT              11
+#define TPD_LSO_EN_MASK                 0x0001
+#define TPD_LSO_EN_SHIFT                12
+#define TPD_LSO_V2_MASK                 0x0001
+#define TPD_LSO_V2_SHIFT                13
+#define TPD_VLTAGGED_MASK               0x0001
+#define TPD_VLTAGGED_SHIFT              14
+#define TPD_INS_VLTAG_MASK              0x0001
+#define TPD_INS_VLTAG_SHIFT             15
+#define TPD_IPV4_MASK                   0x0001
+#define TPD_IPV4_SHIFT                  16
+#define TPD_ETHTYPE_MASK                0x0001
+#define TPD_ETHTYPE_SHIFT               17
+#define TPD_CXSUMOFFSET_MASK            0x00FF
+#define TPD_CXSUMOFFSET_SHIFT           18
+#define TPD_MSS_MASK                    0x1FFF
+#define TPD_MSS_SHIFT                   18
+#define TPD_EOP_MASK                    0x0001
+#define TPD_EOP_SHIFT                   31
+#define DESC_GET(_x, _name) ((_x) >> _name##SHIFT & _name##MASK)
+/* Receive Free Descriptor */
+struct alx_rfd {
+        __le64 addr;            /* data buffer address, length is
+                                 * declared in register --- every
+                                 * buffer has the same size
+                                 */
+} __packed;
+/* Receive Return Descriptor, contains 4 32-bit words.
+ *
+ *   31               16               0
+ *   +----------------+----------------+
+ *   |              Word 0             |
+ *   +----------------+----------------+
+ *   |     Word 1: RSS Hash value      |
+ *   +----------------+----------------+
+ *   |              Word 2             |
+ *   +----------------+----------------+
+ *   |              Word 3             |
+ *   +----------------+----------------+
+ *
+ * Word 0 depiction         &            Word 2 depiction:
+ *
+ *   0--+                                 0--+
+ *   1  |                                 1  |
+ *   2  |                                 2  |
+ *   3  |                                 3  |
+ *   4  |                                 4  |
+ *   5  |                                 5  |
+ *   6  |                                 6  |
+ *   7  |    IP payload checksum          7  |     VLAN tag
+ *   8  |         (15:0)                  8  |      (15:0)
+ *   9  |                                 9  |
+ *   10 |                                 10 |
+ *   11 |                                 11 |
+ *   12 |                                 12 |
+ *   13 |                                 13 |
+ *   14 |                                 14 |
+ *   15-+                                 15-+
+ *   16-+                                 16-+
+ *   17 |     Number of RFDs              17 |
+ *   18 |        (19:16)                  18 |
+ *   19-+                                 19 |     Protocol ID
+ *   20-+                                 20 |      (23:16)
+ *   21 |                                 21 |
+ *   22 |                                 22 |
+ *   23 |                                 23-+
+ *   24 |                                 24 |     Reserved
+ *   25 |     Start index of RFD-ring     25-+
+ *   26 |         (31:20)                 26 |     RSS Q-num (27:25)
+ *   27 |                                 27-+
+ *   28 |                                 28-+
+ *   29 |                                 29 |     RSS Hash algorithm
+ *   30 |                                 30 |      (31:28)
+ *   31-+                                 31-+
+ *
+ * Word 3 depiction:
+ *
+ *   0--+
+ *   1  |
+ *   2  |
+ *   3  |
+ *   4  |
+ *   5  |
+ *   6  |
+ *   7  |    Packet length (include FCS)
+ *   8  |         (13:0)
+ *   9  |
+ *   10 |
+ *   11 |
+ *   12 |
+ *   13-+
+ *   14      L4 Header checksum error
+ *   15      IPv4 checksum error
+ *   16      VLAN tagged
+ *   17-+
+ *   18 |    Protocol ID (19:17)
+ *   19-+
+ *   20      Receive error summary
+ *   21      FCS(CRC) error
+ *   22      Frame alignment error
+ *   23      Truncated packet
+ *   24      Runt packet
+ *   25      Incomplete packet due to insufficient rx-desc
+ *   26      Broadcast packet
+ *   27      Multicast packet
+ *   28      Ethernet type (EII or 802.3)
+ *   29      FIFO overflow
+ *   30      Length error (for 802.3, length field mismatch with actual len)
+ *   31      Updated, indicate to driver that this RRD is refreshed.
+ */
+struct alx_rrd {
+        __le32 word0;
+        __le32 rss_hash;
+        __le32 word2;
+        __le32 word3;
+} __packed;
+/* rrd word 0 */
+#define RRD_XSUM_MASK           0xFFFF
+#define RRD_XSUM_SHIFT          0
+#define RRD_NOR_MASK            0x000F
+#define RRD_NOR_SHIFT           16
+#define RRD_SI_MASK             0x0FFF
+#define RRD_SI_SHIFT            20
+/* rrd word 2 */
+#define RRD_VLTAG_MASK          0xFFFF
+#define RRD_VLTAG_SHIFT         0
+#define RRD_PID_MASK            0x00FF
+#define RRD_PID_SHIFT           16
+/* non-ip packet */
+#define RRD_PID_NONIP           0
+/* ipv4(only) */
+#define RRD_PID_IPV4            1
+/* tcp/ipv6 */
+#define RRD_PID_IPV6TCP         2
+/* tcp/ipv4 */
+#define RRD_PID_IPV4TCP         3
+/* udp/ipv6 */
+#define RRD_PID_IPV6UDP         4
+/* udp/ipv4 */
+#define RRD_PID_IPV4UDP         5
+/* ipv6(only) */
+#define RRD_PID_IPV6            6
+/* LLDP packet */
+#define RRD_PID_LLDP            7
+/* 1588 packet */
+#define RRD_PID_1588            8
+#define RRD_RSSQ_MASK           0x0007
+#define RRD_RSSQ_SHIFT          25
+#define RRD_RSSALG_MASK         0x000F
+#define RRD_RSSALG_SHIFT        28
+#define RRD_RSSALG_TCPV6        0x1
+#define RRD_RSSALG_IPV6         0x2
+#define RRD_RSSALG_TCPV4        0x4
+#define RRD_RSSALG_IPV4         0x8
+/* rrd word 3 */
+#define RRD_PKTLEN_MASK         0x3FFF
+#define RRD_PKTLEN_SHIFT        0
+#define RRD_ERR_L4_MASK         0x0001
+#define RRD_ERR_L4_SHIFT        14
+#define RRD_ERR_IPV4_MASK       0x0001
+#define RRD_ERR_IPV4_SHIFT      15
+#define RRD_VLTAGGED_MASK       0x0001
+#define RRD_VLTAGGED_SHIFT      16
+#define RRD_OLD_PID_MASK        0x0007
+#define RRD_OLD_PID_SHIFT       17
+#define RRD_ERR_RES_MASK        0x0001
+#define RRD_ERR_RES_SHIFT       20
+#define RRD_ERR_FCS_MASK        0x0001
+#define RRD_ERR_FCS_SHIFT       21
+#define RRD_ERR_FAE_MASK        0x0001
+#define RRD_ERR_FAE_SHIFT       22
+#define RRD_ERR_TRUNC_MASK      0x0001
+#define RRD_ERR_TRUNC_SHIFT     23
+#define RRD_ERR_RUNT_MASK       0x0001
+#define RRD_ERR_RUNT_SHIFT      24
+#define RRD_ERR_ICMP_MASK       0x0001
+#define RRD_ERR_ICMP_SHIFT      25
+#define RRD_BCAST_MASK          0x0001
+#define RRD_BCAST_SHIFT         26
+#define RRD_MCAST_MASK          0x0001
+#define RRD_MCAST_SHIFT         27
+#define RRD_ETHTYPE_MASK        0x0001
+#define RRD_ETHTYPE_SHIFT       28
+#define RRD_ERR_FIFOV_MASK      0x0001
+#define RRD_ERR_FIFOV_SHIFT     29
+#define RRD_ERR_LEN_MASK        0x0001
+#define RRD_ERR_LEN_SHIFT       30
+#define RRD_UPDATED_MASK        0x0001
+#define RRD_UPDATED_SHIFT       31
+#define ALX_MAX_SETUP_LNK_CYCLE 50
+/* for FlowControl */
+#define ALX_FC_RX               0x01
+#define ALX_FC_TX               0x02
+#define ALX_FC_ANEG             0x04
+/* for sleep control */
+#define ALX_SLEEP_WOL_PHY       0x00000001
+#define ALX_SLEEP_WOL_MAGIC     0x00000002
+#define ALX_SLEEP_CIFS          0x00000004
+#define ALX_SLEEP_ACTIVE        (ALX_SLEEP_WOL_PHY | \
+                                 ALX_SLEEP_WOL_MAGIC | \
+                                 ALX_SLEEP_CIFS)
+/* for RSS hash type */
+#define ALX_RSS_HASH_TYPE_IPV4          0x1
+#define ALX_RSS_HASH_TYPE_IPV4_TCP      0x2
+#define ALX_RSS_HASH_TYPE_IPV6          0x4
+#define ALX_RSS_HASH_TYPE_IPV6_TCP      0x8
+#define ALX_RSS_HASH_TYPE_ALL           (ALX_RSS_HASH_TYPE_IPV4 | \
+                                         ALX_RSS_HASH_TYPE_IPV4_TCP | \
+                                         ALX_RSS_HASH_TYPE_IPV6 | \
+                                         ALX_RSS_HASH_TYPE_IPV6_TCP)
+#define ALX_DEF_RXBUF_SIZE      1536
+#define ALX_MAX_JUMBO_PKT_SIZE  (9*1024)
+#define ALX_MAX_TSO_PKT_SIZE    (7*1024)
+#define ALX_MAX_FRAME_SIZE      ALX_MAX_JUMBO_PKT_SIZE
+#define ALX_MIN_FRAME_SIZE      68
+#define ALX_RAW_MTU(_mtu)       (_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
+#define ALX_MAX_RX_QUEUES       8
+#define ALX_MAX_TX_QUEUES       4
+#define ALX_MAX_HANDLED_INTRS   5
+#define ALX_ISR_MISC            (ALX_ISR_PCIE_LNKDOWN | \
+                                 ALX_ISR_DMAW | \
+                                 ALX_ISR_DMAR | \
+                                 ALX_ISR_SMB | \
+                                 ALX_ISR_MANU | \
+                                 ALX_ISR_TIMER)
+#define ALX_ISR_FATAL           (ALX_ISR_PCIE_LNKDOWN | \
+                                 ALX_ISR_DMAW | ALX_ISR_DMAR)
+#define ALX_ISR_ALERT           (ALX_ISR_RXF_OV | \
+                                 ALX_ISR_TXF_UR | \
+                                 ALX_ISR_RFD_UR)
+#define ALX_ISR_ALL_QUEUES      (ALX_ISR_TX_Q0 | \
+                                 ALX_ISR_TX_Q1 | \
+                                 ALX_ISR_TX_Q2 | \
+                                 ALX_ISR_TX_Q3 | \
+                                 ALX_ISR_RX_Q0 | \
+                                 ALX_ISR_RX_Q1 | \
+                                 ALX_ISR_RX_Q2 | \
+                                 ALX_ISR_RX_Q3 | \
+                                 ALX_ISR_RX_Q4 | \
+                                 ALX_ISR_RX_Q5 | \
+                                 ALX_ISR_RX_Q6 | \
+                                 ALX_ISR_RX_Q7)
+/* maximum interrupt vectors for msix */
+#define ALX_MAX_MSIX_INTRS      16
+#define ALX_GET_FIELD(_data, _field)                                    \
+        (((_data) >> _field ## _SHIFT) & _field ## _MASK)
+#define ALX_SET_FIELD(_data, _field, _value)    do {                    \
+                (_data) &= ~(_field ## _MASK << _field ## _SHIFT);      \
+                (_data) |= ((_value) & _field ## _MASK) << _field ## _SHIFT;\
+        } while (0)
+struct alx_hw {
+        struct pci_dev *pdev;
+        u8 __iomem *hw_addr;
+        /* current & permanent mac addr */
+        u8 mac_addr[ETH_ALEN];
+        u8 perm_addr[ETH_ALEN];
+        u16 mtu;
+        u16 imt;
+        u8 dma_chnl;
+        u8 max_dma_chnl;
+        /* tpd threshold to trig INT */
+        u32 ith_tpd;
+        u32 rx_ctrl;
+        u32 mc_hash[2];
+        u32 smb_timer;
+        /* SPEED_* + DUPLEX_*, SPEED_UNKNOWN if link is down */
+        int link_speed;
+        /* auto-neg advertisement or force mode config */
+        u32 adv_cfg;
+        u8 flowctrl;
+        u32 sleep_ctrl;
+        spinlock_t mdio_lock;
+        struct mdio_if_info mdio;
+        u16 phy_id[2];
+        /* PHY link patch flag */
+        bool lnk_patch;
+};
+static inline int alx_hw_revision(struct alx_hw *hw)
+{
+        return hw->pdev->revision >> ALX_PCI_REVID_SHIFT;
+}
+static inline bool alx_hw_with_cr(struct alx_hw *hw)
+{
+        return hw->pdev->revision & 1;
+}
+static inline bool alx_hw_giga(struct alx_hw *hw)
+{
+        return hw->pdev->device & 1;
+}
+static inline void alx_write_mem8(struct alx_hw *hw, u32 reg, u8 val)
+{
+        writeb(val, hw->hw_addr + reg);
+}
+static inline void alx_write_mem16(struct alx_hw *hw, u32 reg, u16 val)
+{
+        writew(val, hw->hw_addr + reg);
+}
+static inline u16 alx_read_mem16(struct alx_hw *hw, u32 reg)
+{
+        return readw(hw->hw_addr + reg);
+}
+static inline void alx_write_mem32(struct alx_hw *hw, u32 reg, u32 val)
+{
+        writel(val, hw->hw_addr + reg);
+}
+static inline u32 alx_read_mem32(struct alx_hw *hw, u32 reg)
+{
+        return readl(hw->hw_addr + reg);
+}
+static inline void alx_post_write(struct alx_hw *hw)
+{
+        readl(hw->hw_addr);
+}
+int alx_get_perm_macaddr(struct alx_hw *hw, u8 *addr);
+void alx_reset_phy(struct alx_hw *hw);
+void alx_reset_pcie(struct alx_hw *hw);
+void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en);
+int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl);
+void alx_post_phy_link(struct alx_hw *hw);
+int alx_pre_suspend(struct alx_hw *hw, int speed);
+int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data);
+int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data);
+int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata);
+int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data);
+int alx_get_phy_link(struct alx_hw *hw, int *speed);
+int alx_clear_phy_intr(struct alx_hw *hw);
+int alx_config_wol(struct alx_hw *hw);
+void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc);
+void alx_start_mac(struct alx_hw *hw);
+int alx_reset_mac(struct alx_hw *hw);
+void alx_set_macaddr(struct alx_hw *hw, const u8 *addr);
+bool alx_phy_configured(struct alx_hw *hw);
+void alx_configure_basic(struct alx_hw *hw);
+void alx_disable_rss(struct alx_hw *hw);
+int alx_select_powersaving_speed(struct alx_hw *hw, int *speed);
+bool alx_get_phy_info(struct alx_hw *hw);
+#endif

diff --git a/drivers/net/ethernet/atheros/alx/hw.h b/drivers/net/ethernet/atheros/alx/hw.h new file mode 100644 index 000000000000..65e723d2172a --- /dev/null +++ b/drivers/net/ethernet/atheros/alx/hw.h
@@ -0,0 +1,499 @@
	1	/*
	2	* Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
	3	*
	4	* This file is free software: you may copy, redistribute and/or modify it
	5	* under the terms of the GNU General Public License as published by the
	6	* Free Software Foundation, either version 2 of the License, or (at your
	7	* option) any later version.
	8	*
	9	* This file is distributed in the hope that it will be useful, but
	10	* WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	12	* General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*
	17	* This file incorporates work covered by the following copyright and
	18	* permission notice:
	19	*
	20	* Copyright (c) 2012 Qualcomm Atheros, Inc.
	21	*
	22	* Permission to use, copy, modify, and/or distribute this software for any
	23	* purpose with or without fee is hereby granted, provided that the above
	24	* copyright notice and this permission notice appear in all copies.
	25	*
	26	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	27	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	28	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	29	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	30	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	31	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	32	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	33	*/
	34
	35	#ifndef ALX_HW_H_
	36	#define ALX_HW_H_
	37	#include <linux/types.h>
	38	#include <linux/mdio.h>
	39	#include <linux/pci.h>
	40	#include "reg.h"
	41
	42	/* Transmit Packet Descriptor, contains 4 32-bit words.
	43	*
	44	* 31 16 0
	45	* +----------------+----------------+
	46	* \| vlan-tag \| buf length \|
	47	* +----------------+----------------+
	48	* \| Word 1 \|
	49	* +----------------+----------------+
	50	* \| Word 2: buf addr lo \|
	51	* +----------------+----------------+
	52	* \| Word 3: buf addr hi \|
	53	* +----------------+----------------+
	54	*
	55	* Word 2 and 3 combine to form a 64-bit buffer address
	56	*
	57	* Word 1 has three forms, depending on the state of bit 8/12/13:
	58	* if bit8 =='1', the definition is just for custom checksum offload.
	59	* if bit8 == '0' && bit12 == '1' && bit13 == '1', the FIRST descriptor
	60	* for the skb is special for LSO V2, Word 2 become total skb length ,
	61	* Word 3 is meaningless.
	62	* other condition, the definition is for general skb or ip/tcp/udp
	63	* checksum or LSO(TSO) offload.
	64	*
	65	* Here is the depiction:
	66	*
	67	* 0-+ 0-+
	68	* 1 \| 1 \|
	69	* 2 \| 2 \|
	70	* 3 \| Payload offset 3 \| L4 header offset
	71	* 4 \| (7:0) 4 \| (7:0)
	72	* 5 \| 5 \|
	73	* 6 \| 6 \|
	74	* 7-+ 7-+
	75	* 8 Custom csum enable = 1 8 Custom csum enable = 0
	76	* 9 General IPv4 checksum 9 General IPv4 checksum
	77	* 10 General TCP checksum 10 General TCP checksum
	78	* 11 General UDP checksum 11 General UDP checksum
	79	* 12 Large Send Segment enable 12 Large Send Segment enable
	80	* 13 Large Send Segment type 13 Large Send Segment type
	81	* 14 VLAN tagged 14 VLAN tagged
	82	* 15 Insert VLAN tag 15 Insert VLAN tag
	83	* 16 IPv4 packet 16 IPv4 packet
	84	* 17 Ethernet frame type 17 Ethernet frame type
	85	* 18-+ 18-+
	86	* 19 \| 19 \|
	87	* 20 \| 20 \|
	88	* 21 \| Custom csum offset 21 \|
	89	* 22 \| (25:18) 22 \|
	90	* 23 \| 23 \| MSS (30:18)
	91	* 24 \| 24 \|
	92	* 25-+ 25 \|
	93	* 26-+ 26 \|
	94	* 27 \| 27 \|
	95	* 28 \| Reserved 28 \|
	96	* 29 \| 29 \|
	97	* 30-+ 30-+
	98	* 31 End of packet 31 End of packet
	99	*/
	100	struct alx_txd {
	101	__le16 len;
	102	__le16 vlan_tag;
	103	__le32 word1;
	104	union {
	105	__le64 addr;
	106	struct {
	107	__le32 pkt_len;
	108	__le32 resvd;
	109	} l;
	110	} adrl;
	111	} __packed;
	112
	113	/* tpd word 1 */
	114	#define TPD_CXSUMSTART_MASK 0x00FF
	115	#define TPD_CXSUMSTART_SHIFT 0
	116	#define TPD_L4HDROFFSET_MASK 0x00FF
	117	#define TPD_L4HDROFFSET_SHIFT 0
	118	#define TPD_CXSUM_EN_MASK 0x0001
	119	#define TPD_CXSUM_EN_SHIFT 8
	120	#define TPD_IP_XSUM_MASK 0x0001
	121	#define TPD_IP_XSUM_SHIFT 9
	122	#define TPD_TCP_XSUM_MASK 0x0001
	123	#define TPD_TCP_XSUM_SHIFT 10
	124	#define TPD_UDP_XSUM_MASK 0x0001
	125	#define TPD_UDP_XSUM_SHIFT 11
	126	#define TPD_LSO_EN_MASK 0x0001
	127	#define TPD_LSO_EN_SHIFT 12
	128	#define TPD_LSO_V2_MASK 0x0001
	129	#define TPD_LSO_V2_SHIFT 13
	130	#define TPD_VLTAGGED_MASK 0x0001
	131	#define TPD_VLTAGGED_SHIFT 14
	132	#define TPD_INS_VLTAG_MASK 0x0001
	133	#define TPD_INS_VLTAG_SHIFT 15
	134	#define TPD_IPV4_MASK 0x0001
	135	#define TPD_IPV4_SHIFT 16
	136	#define TPD_ETHTYPE_MASK 0x0001
	137	#define TPD_ETHTYPE_SHIFT 17
	138	#define TPD_CXSUMOFFSET_MASK 0x00FF
	139	#define TPD_CXSUMOFFSET_SHIFT 18
	140	#define TPD_MSS_MASK 0x1FFF
	141	#define TPD_MSS_SHIFT 18
	142	#define TPD_EOP_MASK 0x0001
	143	#define TPD_EOP_SHIFT 31
	144
	145	#define DESC_GET(_x, _name) ((_x) >> _name##SHIFT & _name##MASK)
	146
	147	/* Receive Free Descriptor */
	148	struct alx_rfd {
	149	__le64 addr; /* data buffer address, length is
	150	* declared in register --- every
	151	* buffer has the same size
	152	*/
	153	} __packed;
	154
	155	/* Receive Return Descriptor, contains 4 32-bit words.
	156	*
	157	* 31 16 0
	158	* +----------------+----------------+
	159	* \| Word 0 \|
	160	* +----------------+----------------+
	161	* \| Word 1: RSS Hash value \|
	162	* +----------------+----------------+
	163	* \| Word 2 \|
	164	* +----------------+----------------+
	165	* \| Word 3 \|
	166	* +----------------+----------------+
	167	*
	168	* Word 0 depiction & Word 2 depiction:
	169	*
	170	* 0--+ 0--+
	171	* 1 \| 1 \|
	172	* 2 \| 2 \|
	173	* 3 \| 3 \|
	174	* 4 \| 4 \|
	175	* 5 \| 5 \|
	176	* 6 \| 6 \|
	177	* 7 \| IP payload checksum 7 \| VLAN tag
	178	* 8 \| (15:0) 8 \| (15:0)
	179	* 9 \| 9 \|
	180	* 10 \| 10 \|
	181	* 11 \| 11 \|
	182	* 12 \| 12 \|
	183	* 13 \| 13 \|
	184	* 14 \| 14 \|
	185	* 15-+ 15-+
	186	* 16-+ 16-+
	187	* 17 \| Number of RFDs 17 \|
	188	* 18 \| (19:16) 18 \|
	189	* 19-+ 19 \| Protocol ID
	190	* 20-+ 20 \| (23:16)
	191	* 21 \| 21 \|
	192	* 22 \| 22 \|
	193	* 23 \| 23-+
	194	* 24 \| 24 \| Reserved
	195	* 25 \| Start index of RFD-ring 25-+
	196	* 26 \| (31:20) 26 \| RSS Q-num (27:25)
	197	* 27 \| 27-+
	198	* 28 \| 28-+
	199	* 29 \| 29 \| RSS Hash algorithm
	200	* 30 \| 30 \| (31:28)
	201	* 31-+ 31-+
	202	*
	203	* Word 3 depiction:
	204	*
	205	* 0--+
	206	* 1 \|
	207	* 2 \|
	208	* 3 \|
	209	* 4 \|
	210	* 5 \|
	211	* 6 \|
	212	* 7 \| Packet length (include FCS)
	213	* 8 \| (13:0)
	214	* 9 \|
	215	* 10 \|
	216	* 11 \|
	217	* 12 \|
	218	* 13-+
	219	* 14 L4 Header checksum error
	220	* 15 IPv4 checksum error
	221	* 16 VLAN tagged
	222	* 17-+
	223	* 18 \| Protocol ID (19:17)
	224	* 19-+
	225	* 20 Receive error summary
	226	* 21 FCS(CRC) error
	227	* 22 Frame alignment error
	228	* 23 Truncated packet
	229	* 24 Runt packet
	230	* 25 Incomplete packet due to insufficient rx-desc
	231	* 26 Broadcast packet
	232	* 27 Multicast packet
	233	* 28 Ethernet type (EII or 802.3)
	234	* 29 FIFO overflow
	235	* 30 Length error (for 802.3, length field mismatch with actual len)
	236	* 31 Updated, indicate to driver that this RRD is refreshed.
	237	*/
	238	struct alx_rrd {
	239	__le32 word0;
	240	__le32 rss_hash;
	241	__le32 word2;
	242	__le32 word3;
	243	} __packed;
	244
	245	/* rrd word 0 */
	246	#define RRD_XSUM_MASK 0xFFFF
	247	#define RRD_XSUM_SHIFT 0
	248	#define RRD_NOR_MASK 0x000F
	249	#define RRD_NOR_SHIFT 16
	250	#define RRD_SI_MASK 0x0FFF
	251	#define RRD_SI_SHIFT 20
	252
	253	/* rrd word 2 */
	254	#define RRD_VLTAG_MASK 0xFFFF
	255	#define RRD_VLTAG_SHIFT 0
	256	#define RRD_PID_MASK 0x00FF
	257	#define RRD_PID_SHIFT 16
	258	/* non-ip packet */
	259	#define RRD_PID_NONIP 0
	260	/* ipv4(only) */
	261	#define RRD_PID_IPV4 1
	262	/* tcp/ipv6 */
	263	#define RRD_PID_IPV6TCP 2
	264	/* tcp/ipv4 */
	265	#define RRD_PID_IPV4TCP 3
	266	/* udp/ipv6 */
	267	#define RRD_PID_IPV6UDP 4
	268	/* udp/ipv4 */
	269	#define RRD_PID_IPV4UDP 5
	270	/* ipv6(only) */
	271	#define RRD_PID_IPV6 6
	272	/* LLDP packet */
	273	#define RRD_PID_LLDP 7
	274	/* 1588 packet */
	275	#define RRD_PID_1588 8
	276	#define RRD_RSSQ_MASK 0x0007
	277	#define RRD_RSSQ_SHIFT 25
	278	#define RRD_RSSALG_MASK 0x000F
	279	#define RRD_RSSALG_SHIFT 28
	280	#define RRD_RSSALG_TCPV6 0x1
	281	#define RRD_RSSALG_IPV6 0x2
	282	#define RRD_RSSALG_TCPV4 0x4
	283	#define RRD_RSSALG_IPV4 0x8
	284
	285	/* rrd word 3 */
	286	#define RRD_PKTLEN_MASK 0x3FFF
	287	#define RRD_PKTLEN_SHIFT 0
	288	#define RRD_ERR_L4_MASK 0x0001
	289	#define RRD_ERR_L4_SHIFT 14
	290	#define RRD_ERR_IPV4_MASK 0x0001
	291	#define RRD_ERR_IPV4_SHIFT 15
	292	#define RRD_VLTAGGED_MASK 0x0001
	293	#define RRD_VLTAGGED_SHIFT 16
	294	#define RRD_OLD_PID_MASK 0x0007
	295	#define RRD_OLD_PID_SHIFT 17
	296	#define RRD_ERR_RES_MASK 0x0001
	297	#define RRD_ERR_RES_SHIFT 20
	298	#define RRD_ERR_FCS_MASK 0x0001
	299	#define RRD_ERR_FCS_SHIFT 21
	300	#define RRD_ERR_FAE_MASK 0x0001
	301	#define RRD_ERR_FAE_SHIFT 22
	302	#define RRD_ERR_TRUNC_MASK 0x0001
	303	#define RRD_ERR_TRUNC_SHIFT 23
	304	#define RRD_ERR_RUNT_MASK 0x0001
	305	#define RRD_ERR_RUNT_SHIFT 24
	306	#define RRD_ERR_ICMP_MASK 0x0001
	307	#define RRD_ERR_ICMP_SHIFT 25
	308	#define RRD_BCAST_MASK 0x0001
	309	#define RRD_BCAST_SHIFT 26
	310	#define RRD_MCAST_MASK 0x0001
	311	#define RRD_MCAST_SHIFT 27
	312	#define RRD_ETHTYPE_MASK 0x0001
	313	#define RRD_ETHTYPE_SHIFT 28
	314	#define RRD_ERR_FIFOV_MASK 0x0001
	315	#define RRD_ERR_FIFOV_SHIFT 29
	316	#define RRD_ERR_LEN_MASK 0x0001
	317	#define RRD_ERR_LEN_SHIFT 30
	318	#define RRD_UPDATED_MASK 0x0001
	319	#define RRD_UPDATED_SHIFT 31
	320
	321
	322	#define ALX_MAX_SETUP_LNK_CYCLE 50
	323
	324	/* for FlowControl */
	325	#define ALX_FC_RX 0x01
	326	#define ALX_FC_TX 0x02
	327	#define ALX_FC_ANEG 0x04
	328
	329	/* for sleep control */
	330	#define ALX_SLEEP_WOL_PHY 0x00000001
	331	#define ALX_SLEEP_WOL_MAGIC 0x00000002
	332	#define ALX_SLEEP_CIFS 0x00000004
	333	#define ALX_SLEEP_ACTIVE (ALX_SLEEP_WOL_PHY \| \
	334	ALX_SLEEP_WOL_MAGIC \| \
	335	ALX_SLEEP_CIFS)
	336
	337	/* for RSS hash type */
	338	#define ALX_RSS_HASH_TYPE_IPV4 0x1
	339	#define ALX_RSS_HASH_TYPE_IPV4_TCP 0x2
	340	#define ALX_RSS_HASH_TYPE_IPV6 0x4
	341	#define ALX_RSS_HASH_TYPE_IPV6_TCP 0x8
	342	#define ALX_RSS_HASH_TYPE_ALL (ALX_RSS_HASH_TYPE_IPV4 \| \
	343	ALX_RSS_HASH_TYPE_IPV4_TCP \| \
	344	ALX_RSS_HASH_TYPE_IPV6 \| \
	345	ALX_RSS_HASH_TYPE_IPV6_TCP)
	346	#define ALX_DEF_RXBUF_SIZE 1536
	347	#define ALX_MAX_JUMBO_PKT_SIZE (9*1024)
	348	#define ALX_MAX_TSO_PKT_SIZE (7*1024)
	349	#define ALX_MAX_FRAME_SIZE ALX_MAX_JUMBO_PKT_SIZE
	350	#define ALX_MIN_FRAME_SIZE 68
	351	#define ALX_RAW_MTU(_mtu) (_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
	352
	353	#define ALX_MAX_RX_QUEUES 8
	354	#define ALX_MAX_TX_QUEUES 4
	355	#define ALX_MAX_HANDLED_INTRS 5
	356
	357	#define ALX_ISR_MISC (ALX_ISR_PCIE_LNKDOWN \| \
	358	ALX_ISR_DMAW \| \
	359	ALX_ISR_DMAR \| \
	360	ALX_ISR_SMB \| \
	361	ALX_ISR_MANU \| \
	362	ALX_ISR_TIMER)
	363
	364	#define ALX_ISR_FATAL (ALX_ISR_PCIE_LNKDOWN \| \
	365	ALX_ISR_DMAW \| ALX_ISR_DMAR)
	366
	367	#define ALX_ISR_ALERT (ALX_ISR_RXF_OV \| \
	368	ALX_ISR_TXF_UR \| \
	369	ALX_ISR_RFD_UR)
	370
	371	#define ALX_ISR_ALL_QUEUES (ALX_ISR_TX_Q0 \| \
	372	ALX_ISR_TX_Q1 \| \
	373	ALX_ISR_TX_Q2 \| \
	374	ALX_ISR_TX_Q3 \| \
	375	ALX_ISR_RX_Q0 \| \
	376	ALX_ISR_RX_Q1 \| \
	377	ALX_ISR_RX_Q2 \| \
	378	ALX_ISR_RX_Q3 \| \
	379	ALX_ISR_RX_Q4 \| \
	380	ALX_ISR_RX_Q5 \| \
	381	ALX_ISR_RX_Q6 \| \
	382	ALX_ISR_RX_Q7)
	383
	384	/* maximum interrupt vectors for msix */
	385	#define ALX_MAX_MSIX_INTRS 16
	386
	387	#define ALX_GET_FIELD(_data, _field) \
	388	(((_data) >> _field ## _SHIFT) & _field ## _MASK)
	389
	390	#define ALX_SET_FIELD(_data, _field, _value) do { \
	391	(_data) &= ~(_field ## _MASK << _field ## _SHIFT); \
	392	(_data) \|= ((_value) & _field ## _MASK) << _field ## _SHIFT;\
	393	} while (0)
	394
	395	struct alx_hw {
	396	struct pci_dev *pdev;
	397	u8 __iomem *hw_addr;
	398
	399	/* current & permanent mac addr */
	400	u8 mac_addr[ETH_ALEN];
	401	u8 perm_addr[ETH_ALEN];
	402
	403	u16 mtu;
	404	u16 imt;
	405	u8 dma_chnl;
	406	u8 max_dma_chnl;
	407	/* tpd threshold to trig INT */
	408	u32 ith_tpd;
	409	u32 rx_ctrl;
	410	u32 mc_hash[2];
	411
	412	u32 smb_timer;
	413	/* SPEED_* + DUPLEX_, SPEED_UNKNOWN if link is down /
	414	int link_speed;
	415
	416	/* auto-neg advertisement or force mode config */
	417	u32 adv_cfg;
	418	u8 flowctrl;
	419
	420	u32 sleep_ctrl;
	421
	422	spinlock_t mdio_lock;
	423	struct mdio_if_info mdio;
	424	u16 phy_id[2];
	425
	426	/* PHY link patch flag */
	427	bool lnk_patch;
	428	};
	429
	430	static inline int alx_hw_revision(struct alx_hw *hw)
	431	{
	432	return hw->pdev->revision >> ALX_PCI_REVID_SHIFT;
	433	}
	434
	435	static inline bool alx_hw_with_cr(struct alx_hw *hw)
	436	{
	437	return hw->pdev->revision & 1;
	438	}
	439
	440	static inline bool alx_hw_giga(struct alx_hw *hw)
	441	{
	442	return hw->pdev->device & 1;
	443	}
	444
	445	static inline void alx_write_mem8(struct alx_hw *hw, u32 reg, u8 val)
	446	{
	447	writeb(val, hw->hw_addr + reg);
	448	}
	449
	450	static inline void alx_write_mem16(struct alx_hw *hw, u32 reg, u16 val)
	451	{
	452	writew(val, hw->hw_addr + reg);
	453	}
	454
	455	static inline u16 alx_read_mem16(struct alx_hw *hw, u32 reg)
	456	{
	457	return readw(hw->hw_addr + reg);
	458	}
	459
	460	static inline void alx_write_mem32(struct alx_hw *hw, u32 reg, u32 val)
	461	{
	462	writel(val, hw->hw_addr + reg);
	463	}
	464
	465	static inline u32 alx_read_mem32(struct alx_hw *hw, u32 reg)
	466	{
	467	return readl(hw->hw_addr + reg);
	468	}
	469
	470	static inline void alx_post_write(struct alx_hw *hw)
	471	{
	472	readl(hw->hw_addr);
	473	}
	474
	475	int alx_get_perm_macaddr(struct alx_hw hw, u8 addr);
	476	void alx_reset_phy(struct alx_hw *hw);
	477	void alx_reset_pcie(struct alx_hw *hw);
	478	void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en);
	479	int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl);
	480	void alx_post_phy_link(struct alx_hw *hw);
	481	int alx_pre_suspend(struct alx_hw *hw, int speed);
	482	int alx_read_phy_reg(struct alx_hw hw, u16 reg, u16 phy_data);
	483	int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data);
	484	int alx_read_phy_ext(struct alx_hw hw, u8 dev, u16 reg, u16 pdata);
	485	int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data);
	486	int alx_get_phy_link(struct alx_hw hw, int speed);
	487	int alx_clear_phy_intr(struct alx_hw *hw);
	488	int alx_config_wol(struct alx_hw *hw);
	489	void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc);
	490	void alx_start_mac(struct alx_hw *hw);
	491	int alx_reset_mac(struct alx_hw *hw);
	492	void alx_set_macaddr(struct alx_hw hw, const u8 addr);
	493	bool alx_phy_configured(struct alx_hw *hw);
	494	void alx_configure_basic(struct alx_hw *hw);
	495	void alx_disable_rss(struct alx_hw *hw);
	496	int alx_select_powersaving_speed(struct alx_hw hw, int speed);
	497	bool alx_get_phy_info(struct alx_hw *hw);
	498
	499	#endif