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-rw-r--r--drivers/media/dvb/frontends/Kconfig7
-rw-r--r--drivers/media/dvb/frontends/Makefile1
-rw-r--r--drivers/media/dvb/frontends/af9013.c1727
-rw-r--r--drivers/media/dvb/frontends/af9013.h113
-rw-r--r--drivers/media/dvb/frontends/af9013_priv.h93
-rw-r--r--drivers/media/dvb/frontends/atbm8830.c27
-rw-r--r--drivers/media/dvb/frontends/au8522_dig.c58
-rw-r--r--drivers/media/dvb/frontends/bcm3510.c18
-rw-r--r--drivers/media/dvb/frontends/bsbe1.h7
-rw-r--r--drivers/media/dvb/frontends/bsru6.h9
-rw-r--r--drivers/media/dvb/frontends/cx22700.c51
-rw-r--r--drivers/media/dvb/frontends/cx22702.c69
-rw-r--r--drivers/media/dvb/frontends/cx24110.c20
-rw-r--r--drivers/media/dvb/frontends/cx24113.c10
-rw-r--r--drivers/media/dvb/frontends/cx24116.c36
-rw-r--r--drivers/media/dvb/frontends/cx24123.c56
-rw-r--r--drivers/media/dvb/frontends/cxd2820r.h13
-rw-r--r--drivers/media/dvb/frontends/cxd2820r_c.c25
-rw-r--r--drivers/media/dvb/frontends/cxd2820r_core.c641
-rw-r--r--drivers/media/dvb/frontends/cxd2820r_priv.h23
-rw-r--r--drivers/media/dvb/frontends/cxd2820r_t.c63
-rw-r--r--drivers/media/dvb/frontends/cxd2820r_t2.c70
-rw-r--r--drivers/media/dvb/frontends/dib0070.c10
-rw-r--r--drivers/media/dvb/frontends/dib0090.c165
-rw-r--r--drivers/media/dvb/frontends/dib0090.h54
-rw-r--r--drivers/media/dvb/frontends/dib3000mb.c113
-rw-r--r--drivers/media/dvb/frontends/dib3000mb_priv.h2
-rw-r--r--drivers/media/dvb/frontends/dib3000mc.c132
-rw-r--r--drivers/media/dvb/frontends/dib7000m.c136
-rw-r--r--drivers/media/dvb/frontends/dib7000p.c456
-rw-r--r--drivers/media/dvb/frontends/dib7000p.h16
-rw-r--r--drivers/media/dvb/frontends/dib8000.c1073
-rw-r--r--drivers/media/dvb/frontends/dib8000.h42
-rw-r--r--drivers/media/dvb/frontends/dib9000.c36
-rw-r--r--drivers/media/dvb/frontends/dibx000_common.h17
-rw-r--r--drivers/media/dvb/frontends/drxd.h2
-rw-r--r--drivers/media/dvb/frontends/drxd_hard.c62
-rw-r--r--drivers/media/dvb/frontends/drxk.h11
-rw-r--r--drivers/media/dvb/frontends/drxk_hard.c314
-rw-r--r--drivers/media/dvb/frontends/drxk_hard.h8
-rw-r--r--drivers/media/dvb/frontends/ds3000.c36
-rw-r--r--drivers/media/dvb/frontends/dvb-pll.c65
-rw-r--r--drivers/media/dvb/frontends/dvb_dummy_fe.c18
-rw-r--r--drivers/media/dvb/frontends/ec100.c20
-rw-r--r--drivers/media/dvb/frontends/hd29l2.c861
-rw-r--r--drivers/media/dvb/frontends/hd29l2.h66
-rw-r--r--drivers/media/dvb/frontends/hd29l2_priv.h314
-rw-r--r--drivers/media/dvb/frontends/it913x-fe-priv.h806
-rw-r--r--drivers/media/dvb/frontends/it913x-fe.c289
-rw-r--r--drivers/media/dvb/frontends/it913x-fe.h43
-rw-r--r--drivers/media/dvb/frontends/itd1000.c7
-rw-r--r--drivers/media/dvb/frontends/ix2505v.c8
-rw-r--r--drivers/media/dvb/frontends/l64781.c117
-rw-r--r--drivers/media/dvb/frontends/lgdt3305.c98
-rw-r--r--drivers/media/dvb/frontends/lgdt330x.c37
-rw-r--r--drivers/media/dvb/frontends/lgs8gl5.c29
-rw-r--r--drivers/media/dvb/frontends/lgs8gxx.c26
-rw-r--r--drivers/media/dvb/frontends/mb86a16.c8
-rw-r--r--drivers/media/dvb/frontends/mb86a20s.c546
-rw-r--r--drivers/media/dvb/frontends/mt312.c37
-rw-r--r--drivers/media/dvb/frontends/mt352.c65
-rw-r--r--drivers/media/dvb/frontends/nxt200x.c17
-rw-r--r--drivers/media/dvb/frontends/nxt6000.c32
-rw-r--r--drivers/media/dvb/frontends/or51132.c52
-rw-r--r--drivers/media/dvb/frontends/or51211.c13
-rw-r--r--drivers/media/dvb/frontends/s5h1409.c48
-rw-r--r--drivers/media/dvb/frontends/s5h1411.c48
-rw-r--r--drivers/media/dvb/frontends/s5h1420.c71
-rw-r--r--drivers/media/dvb/frontends/s5h1432.c36
-rw-r--r--drivers/media/dvb/frontends/s921.c23
-rw-r--r--drivers/media/dvb/frontends/si21xx.c20
-rw-r--r--drivers/media/dvb/frontends/sp8870.c29
-rw-r--r--drivers/media/dvb/frontends/sp887x.c50
-rw-r--r--drivers/media/dvb/frontends/stb0899_drv.c37
-rw-r--r--drivers/media/dvb/frontends/stb6000.c8
-rw-r--r--drivers/media/dvb/frontends/stb6100.c6
-rw-r--r--drivers/media/dvb/frontends/stv0288.c17
-rw-r--r--drivers/media/dvb/frontends/stv0297.c37
-rw-r--r--drivers/media/dvb/frontends/stv0299.c32
-rw-r--r--drivers/media/dvb/frontends/stv0367.c156
-rw-r--r--drivers/media/dvb/frontends/stv0900_core.c37
-rw-r--r--drivers/media/dvb/frontends/stv090x.c13
-rw-r--r--drivers/media/dvb/frontends/stv6110.c3
-rw-r--r--drivers/media/dvb/frontends/tda10021.c111
-rw-r--r--drivers/media/dvb/frontends/tda10023.c103
-rw-r--r--drivers/media/dvb/frontends/tda10048.c83
-rw-r--r--drivers/media/dvb/frontends/tda1004x.c111
-rw-r--r--drivers/media/dvb/frontends/tda10071.c8
-rw-r--r--drivers/media/dvb/frontends/tda10086.c62
-rw-r--r--drivers/media/dvb/frontends/tda18271c2dd.c52
-rw-r--r--drivers/media/dvb/frontends/tda8083.c19
-rw-r--r--drivers/media/dvb/frontends/tda826x.c7
-rw-r--r--drivers/media/dvb/frontends/tdhd1.h11
-rw-r--r--drivers/media/dvb/frontends/tua6100.c31
-rw-r--r--drivers/media/dvb/frontends/ves1820.c23
-rw-r--r--drivers/media/dvb/frontends/ves1x93.c23
-rw-r--r--drivers/media/dvb/frontends/zl10036.c10
-rw-r--r--drivers/media/dvb/frontends/zl10039.c10
-rw-r--r--drivers/media/dvb/frontends/zl10353.c116
99 files changed, 6977 insertions, 3870 deletions
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index 4a2d2e6c91ab..ebb5ed7a7783 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -404,6 +404,13 @@ config DVB_EC100
404 help 404 help
405 Say Y when you want to support this frontend. 405 Say Y when you want to support this frontend.
406 406
407config DVB_HD29L2
408 tristate "HDIC HD29L2"
409 depends on DVB_CORE && I2C
410 default m if DVB_FE_CUSTOMISE
411 help
412 Say Y when you want to support this frontend.
413
407config DVB_STV0367 414config DVB_STV0367
408 tristate "ST STV0367 based" 415 tristate "ST STV0367 based"
409 depends on DVB_CORE && I2C 416 depends on DVB_CORE && I2C
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index f639f6781551..00a20636df62 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_DVB_STV090x) += stv090x.o
84obj-$(CONFIG_DVB_STV6110x) += stv6110x.o 84obj-$(CONFIG_DVB_STV6110x) += stv6110x.o
85obj-$(CONFIG_DVB_ISL6423) += isl6423.o 85obj-$(CONFIG_DVB_ISL6423) += isl6423.o
86obj-$(CONFIG_DVB_EC100) += ec100.o 86obj-$(CONFIG_DVB_EC100) += ec100.o
87obj-$(CONFIG_DVB_HD29L2) += hd29l2.o
87obj-$(CONFIG_DVB_DS3000) += ds3000.o 88obj-$(CONFIG_DVB_DS3000) += ds3000.o
88obj-$(CONFIG_DVB_MB86A16) += mb86a16.o 89obj-$(CONFIG_DVB_MB86A16) += mb86a16.o
89obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o 90obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o
diff --git a/drivers/media/dvb/frontends/af9013.c b/drivers/media/dvb/frontends/af9013.c
index 345311c33383..6bcbcf543b38 100644
--- a/drivers/media/dvb/frontends/af9013.c
+++ b/drivers/media/dvb/frontends/af9013.c
@@ -2,6 +2,7 @@
2 * Afatech AF9013 demodulator driver 2 * Afatech AF9013 demodulator driver
3 * 3 *
4 * Copyright (C) 2007 Antti Palosaari <crope@iki.fi> 4 * Copyright (C) 2007 Antti Palosaari <crope@iki.fi>
5 * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
5 * 6 *
6 * Thanks to Afatech who kindly provided information. 7 * Thanks to Afatech who kindly provided information.
7 * 8 *
@@ -21,25 +22,15 @@
21 * 22 *
22 */ 23 */
23 24
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/string.h>
30#include <linux/slab.h>
31#include <linux/firmware.h>
32
33#include "dvb_frontend.h"
34#include "af9013_priv.h" 25#include "af9013_priv.h"
35#include "af9013.h"
36 26
37int af9013_debug; 27int af9013_debug;
28module_param_named(debug, af9013_debug, int, 0644);
29MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
38 30
39struct af9013_state { 31struct af9013_state {
40 struct i2c_adapter *i2c; 32 struct i2c_adapter *i2c;
41 struct dvb_frontend frontend; 33 struct dvb_frontend fe;
42
43 struct af9013_config config; 34 struct af9013_config config;
44 35
45 /* tuner/demod RF and IF AGC limits used for signal strength calc */ 36 /* tuner/demod RF and IF AGC limits used for signal strength calc */
@@ -48,107 +39,178 @@ struct af9013_state {
48 u32 ber; 39 u32 ber;
49 u32 ucblocks; 40 u32 ucblocks;
50 u16 snr; 41 u16 snr;
51 u32 frequency; 42 u32 bandwidth_hz;
52 unsigned long next_statistics_check; 43 fe_status_t fe_status;
44 unsigned long set_frontend_jiffies;
45 unsigned long read_status_jiffies;
46 bool first_tune;
47 bool i2c_gate_state;
48 unsigned int statistics_step:3;
49 struct delayed_work statistics_work;
53}; 50};
54 51
55static u8 regmask[8] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff }; 52/* write multiple registers */
56 53static int af9013_wr_regs_i2c(struct af9013_state *priv, u8 mbox, u16 reg,
57static int af9013_write_regs(struct af9013_state *state, u8 mbox, u16 reg, 54 const u8 *val, int len)
58 u8 *val, u8 len)
59{ 55{
56 int ret;
60 u8 buf[3+len]; 57 u8 buf[3+len];
61 struct i2c_msg msg = { 58 struct i2c_msg msg[1] = {
62 .addr = state->config.demod_address, 59 {
63 .flags = 0, 60 .addr = priv->config.i2c_addr,
64 .len = sizeof(buf), 61 .flags = 0,
65 .buf = buf }; 62 .len = sizeof(buf),
66 63 .buf = buf,
67 buf[0] = reg >> 8; 64 }
68 buf[1] = reg & 0xff; 65 };
66
67 buf[0] = (reg >> 8) & 0xff;
68 buf[1] = (reg >> 0) & 0xff;
69 buf[2] = mbox; 69 buf[2] = mbox;
70 memcpy(&buf[3], val, len); 70 memcpy(&buf[3], val, len);
71 71
72 if (i2c_transfer(state->i2c, &msg, 1) != 1) { 72 ret = i2c_transfer(priv->i2c, msg, 1);
73 warn("I2C write failed reg:%04x len:%d", reg, len); 73 if (ret == 1) {
74 return -EREMOTEIO; 74 ret = 0;
75 } else {
76 warn("i2c wr failed=%d reg=%04x len=%d", ret, reg, len);
77 ret = -EREMOTEIO;
75 } 78 }
76 return 0; 79 return ret;
77} 80}
78 81
79static int af9013_write_ofdm_regs(struct af9013_state *state, u16 reg, u8 *val, 82/* read multiple registers */
80 u8 len) 83static int af9013_rd_regs_i2c(struct af9013_state *priv, u8 mbox, u16 reg,
84 u8 *val, int len)
81{ 85{
82 u8 mbox = (1 << 0)|(1 << 1)|((len - 1) << 2)|(0 << 6)|(0 << 7); 86 int ret;
83 return af9013_write_regs(state, mbox, reg, val, len); 87 u8 buf[3];
88 struct i2c_msg msg[2] = {
89 {
90 .addr = priv->config.i2c_addr,
91 .flags = 0,
92 .len = 3,
93 .buf = buf,
94 }, {
95 .addr = priv->config.i2c_addr,
96 .flags = I2C_M_RD,
97 .len = len,
98 .buf = val,
99 }
100 };
101
102 buf[0] = (reg >> 8) & 0xff;
103 buf[1] = (reg >> 0) & 0xff;
104 buf[2] = mbox;
105
106 ret = i2c_transfer(priv->i2c, msg, 2);
107 if (ret == 2) {
108 ret = 0;
109 } else {
110 warn("i2c rd failed=%d reg=%04x len=%d", ret, reg, len);
111 ret = -EREMOTEIO;
112 }
113 return ret;
84} 114}
85 115
86static int af9013_write_ofsm_regs(struct af9013_state *state, u16 reg, u8 *val, 116/* write multiple registers */
87 u8 len) 117static int af9013_wr_regs(struct af9013_state *priv, u16 reg, const u8 *val,
118 int len)
119{
120 int ret, i;
121 u8 mbox = (0 << 7)|(0 << 6)|(1 << 1)|(1 << 0);
122
123 if ((priv->config.ts_mode == AF9013_TS_USB) &&
124 ((reg & 0xff00) != 0xff00) && ((reg & 0xff00) != 0xae00)) {
125 mbox |= ((len - 1) << 2);
126 ret = af9013_wr_regs_i2c(priv, mbox, reg, val, len);
127 } else {
128 for (i = 0; i < len; i++) {
129 ret = af9013_wr_regs_i2c(priv, mbox, reg+i, val+i, 1);
130 if (ret)
131 goto err;
132 }
133 }
134
135err:
136 return 0;
137}
138
139/* read multiple registers */
140static int af9013_rd_regs(struct af9013_state *priv, u16 reg, u8 *val, int len)
88{ 141{
89 u8 mbox = (1 << 0)|(1 << 1)|((len - 1) << 2)|(1 << 6)|(1 << 7); 142 int ret, i;
90 return af9013_write_regs(state, mbox, reg, val, len); 143 u8 mbox = (0 << 7)|(0 << 6)|(1 << 1)|(0 << 0);
144
145 if ((priv->config.ts_mode == AF9013_TS_USB) &&
146 ((reg & 0xff00) != 0xff00) && ((reg & 0xff00) != 0xae00)) {
147 mbox |= ((len - 1) << 2);
148 ret = af9013_rd_regs_i2c(priv, mbox, reg, val, len);
149 } else {
150 for (i = 0; i < len; i++) {
151 ret = af9013_rd_regs_i2c(priv, mbox, reg+i, val+i, 1);
152 if (ret)
153 goto err;
154 }
155 }
156
157err:
158 return 0;
91} 159}
92 160
93/* write single register */ 161/* write single register */
94static int af9013_write_reg(struct af9013_state *state, u16 reg, u8 val) 162static int af9013_wr_reg(struct af9013_state *priv, u16 reg, u8 val)
95{ 163{
96 return af9013_write_ofdm_regs(state, reg, &val, 1); 164 return af9013_wr_regs(priv, reg, &val, 1);
97} 165}
98 166
99/* read single register */ 167/* read single register */
100static int af9013_read_reg(struct af9013_state *state, u16 reg, u8 *val) 168static int af9013_rd_reg(struct af9013_state *priv, u16 reg, u8 *val)
101{ 169{
102 u8 obuf[3] = { reg >> 8, reg & 0xff, 0 }; 170 return af9013_rd_regs(priv, reg, val, 1);
103 u8 ibuf[1]; 171}
104 struct i2c_msg msg[2] = {
105 {
106 .addr = state->config.demod_address,
107 .flags = 0,
108 .len = sizeof(obuf),
109 .buf = obuf
110 }, {
111 .addr = state->config.demod_address,
112 .flags = I2C_M_RD,
113 .len = sizeof(ibuf),
114 .buf = ibuf
115 }
116 };
117 172
118 if (i2c_transfer(state->i2c, msg, 2) != 2) { 173static int af9013_write_ofsm_regs(struct af9013_state *state, u16 reg, u8 *val,
119 warn("I2C read failed reg:%04x", reg); 174 u8 len)
120 return -EREMOTEIO; 175{
121 } 176 u8 mbox = (1 << 7)|(1 << 6)|((len - 1) << 2)|(1 << 1)|(1 << 0);
122 *val = ibuf[0]; 177 return af9013_wr_regs_i2c(state, mbox, reg, val, len);
123 return 0;
124} 178}
125 179
126static int af9013_write_reg_bits(struct af9013_state *state, u16 reg, u8 pos, 180static int af9013_wr_reg_bits(struct af9013_state *state, u16 reg, int pos,
127 u8 len, u8 val) 181 int len, u8 val)
128{ 182{
129 int ret; 183 int ret;
130 u8 tmp, mask; 184 u8 tmp, mask;
131 185
132 ret = af9013_read_reg(state, reg, &tmp); 186 /* no need for read if whole reg is written */
133 if (ret) 187 if (len != 8) {
134 return ret; 188 ret = af9013_rd_reg(state, reg, &tmp);
189 if (ret)
190 return ret;
135 191
136 mask = regmask[len - 1] << pos; 192 mask = (0xff >> (8 - len)) << pos;
137 tmp = (tmp & ~mask) | ((val << pos) & mask); 193 val <<= pos;
194 tmp &= ~mask;
195 val |= tmp;
196 }
138 197
139 return af9013_write_reg(state, reg, tmp); 198 return af9013_wr_reg(state, reg, val);
140} 199}
141 200
142static int af9013_read_reg_bits(struct af9013_state *state, u16 reg, u8 pos, 201static int af9013_rd_reg_bits(struct af9013_state *state, u16 reg, int pos,
143 u8 len, u8 *val) 202 int len, u8 *val)
144{ 203{
145 int ret; 204 int ret;
146 u8 tmp; 205 u8 tmp;
147 206
148 ret = af9013_read_reg(state, reg, &tmp); 207 ret = af9013_rd_reg(state, reg, &tmp);
149 if (ret) 208 if (ret)
150 return ret; 209 return ret;
151 *val = (tmp >> pos) & regmask[len - 1]; 210
211 *val = (tmp >> pos);
212 *val &= (0xff >> (8 - len));
213
152 return 0; 214 return 0;
153} 215}
154 216
@@ -157,10 +219,13 @@ static int af9013_set_gpio(struct af9013_state *state, u8 gpio, u8 gpioval)
157 int ret; 219 int ret;
158 u8 pos; 220 u8 pos;
159 u16 addr; 221 u16 addr;
160 deb_info("%s: gpio:%d gpioval:%02x\n", __func__, gpio, gpioval);
161 222
162/* GPIO0 & GPIO1 0xd735 223 dbg("%s: gpio=%d gpioval=%02x", __func__, gpio, gpioval);
163 GPIO2 & GPIO3 0xd736 */ 224
225 /*
226 * GPIO0 & GPIO1 0xd735
227 * GPIO2 & GPIO3 0xd736
228 */
164 229
165 switch (gpio) { 230 switch (gpio) {
166 case 0: 231 case 0:
@@ -175,7 +240,7 @@ static int af9013_set_gpio(struct af9013_state *state, u8 gpio, u8 gpioval)
175 default: 240 default:
176 err("invalid gpio:%d\n", gpio); 241 err("invalid gpio:%d\n", gpio);
177 ret = -EINVAL; 242 ret = -EINVAL;
178 goto error; 243 goto err;
179 }; 244 };
180 245
181 switch (gpio) { 246 switch (gpio) {
@@ -190,16 +255,21 @@ static int af9013_set_gpio(struct af9013_state *state, u8 gpio, u8 gpioval)
190 break; 255 break;
191 }; 256 };
192 257
193 ret = af9013_write_reg_bits(state, addr, pos, 4, gpioval); 258 ret = af9013_wr_reg_bits(state, addr, pos, 4, gpioval);
259 if (ret)
260 goto err;
194 261
195error: 262 return ret;
263err:
264 dbg("%s: failed=%d", __func__, ret);
196 return ret; 265 return ret;
197} 266}
198 267
199static u32 af913_div(u32 a, u32 b, u32 x) 268static u32 af913_div(u32 a, u32 b, u32 x)
200{ 269{
201 u32 r = 0, c = 0, i; 270 u32 r = 0, c = 0, i;
202 deb_info("%s: a:%d b:%d x:%d\n", __func__, a, b, x); 271
272 dbg("%s: a=%d b=%d x=%d", __func__, a, b, x);
203 273
204 if (a > b) { 274 if (a > b) {
205 c = a / b; 275 c = a / b;
@@ -216,205 +286,407 @@ static u32 af913_div(u32 a, u32 b, u32 x)
216 } 286 }
217 r = (c << (u32)x) + r; 287 r = (c << (u32)x) + r;
218 288
219 deb_info("%s: a:%d b:%d x:%d r:%d r:%x\n", __func__, a, b, x, r, r); 289 dbg("%s: a=%d b=%d x=%d r=%x", __func__, a, b, x, r);
220 return r; 290 return r;
221} 291}
222 292
223static int af9013_set_coeff(struct af9013_state *state, fe_bandwidth_t bw) 293static int af9013_power_ctrl(struct af9013_state *state, u8 onoff)
224{ 294{
225 int ret, i, j, found; 295 int ret, i;
226 deb_info("%s: adc_clock:%d bw:%d\n", __func__, 296 u8 tmp;
227 state->config.adc_clock, bw);
228
229 /* lookup coeff from table */
230 for (i = 0, found = 0; i < ARRAY_SIZE(coeff_table); i++) {
231 if (coeff_table[i].adc_clock == state->config.adc_clock &&
232 coeff_table[i].bw == bw) {
233 found = 1;
234 break;
235 }
236 }
237 297
238 if (!found) { 298 dbg("%s: onoff=%d", __func__, onoff);
239 err("invalid bw or clock"); 299
240 ret = -EINVAL; 300 /* enable reset */
241 goto error; 301 ret = af9013_wr_reg_bits(state, 0xd417, 4, 1, 1);
302 if (ret)
303 goto err;
304
305 /* start reset mechanism */
306 ret = af9013_wr_reg(state, 0xaeff, 1);
307 if (ret)
308 goto err;
309
310 /* wait reset performs */
311 for (i = 0; i < 150; i++) {
312 ret = af9013_rd_reg_bits(state, 0xd417, 1, 1, &tmp);
313 if (ret)
314 goto err;
315
316 if (tmp)
317 break; /* reset done */
318
319 usleep_range(5000, 25000);
242 } 320 }
243 321
244 deb_info("%s: coeff: ", __func__); 322 if (!tmp)
245 debug_dump(coeff_table[i].val, sizeof(coeff_table[i].val), deb_info); 323 return -ETIMEDOUT;
246 324
247 /* program */ 325 if (onoff) {
248 for (j = 0; j < sizeof(coeff_table[i].val); j++) { 326 /* clear reset */
249 ret = af9013_write_reg(state, 0xae00 + j, 327 ret = af9013_wr_reg_bits(state, 0xd417, 1, 1, 0);
250 coeff_table[i].val[j]);
251 if (ret) 328 if (ret)
252 break; 329 goto err;
330
331 /* disable reset */
332 ret = af9013_wr_reg_bits(state, 0xd417, 4, 1, 0);
333
334 /* power on */
335 ret = af9013_wr_reg_bits(state, 0xd73a, 3, 1, 0);
336 } else {
337 /* power off */
338 ret = af9013_wr_reg_bits(state, 0xd73a, 3, 1, 1);
253 } 339 }
254 340
255error: 341 return ret;
342err:
343 dbg("%s: failed=%d", __func__, ret);
344 return ret;
345}
346
347static int af9013_statistics_ber_unc_start(struct dvb_frontend *fe)
348{
349 struct af9013_state *state = fe->demodulator_priv;
350 int ret;
351
352 dbg("%s", __func__);
353
354 /* reset and start BER counter */
355 ret = af9013_wr_reg_bits(state, 0xd391, 4, 1, 1);
356 if (ret)
357 goto err;
358
359 return ret;
360err:
361 dbg("%s: failed=%d", __func__, ret);
256 return ret; 362 return ret;
257} 363}
258 364
259static int af9013_set_adc_ctrl(struct af9013_state *state) 365static int af9013_statistics_ber_unc_result(struct dvb_frontend *fe)
260{ 366{
367 struct af9013_state *state = fe->demodulator_priv;
261 int ret; 368 int ret;
262 u8 buf[3], tmp, i; 369 u8 buf[5];
263 u32 adc_cw;
264 370
265 deb_info("%s: adc_clock:%d\n", __func__, state->config.adc_clock); 371 dbg("%s", __func__);
266 372
267 /* adc frequency type */ 373 /* check if error bit count is ready */
268 switch (state->config.adc_clock) { 374 ret = af9013_rd_reg_bits(state, 0xd391, 4, 1, &buf[0]);
269 case 28800: /* 28.800 MHz */ 375 if (ret)
270 tmp = 0; 376 goto err;
271 break; 377
272 case 20480: /* 20.480 MHz */ 378 if (!buf[0]) {
273 tmp = 1; 379 dbg("%s: not ready", __func__);
380 return 0;
381 }
382
383 ret = af9013_rd_regs(state, 0xd387, buf, 5);
384 if (ret)
385 goto err;
386
387 state->ber = (buf[2] << 16) | (buf[1] << 8) | buf[0];
388 state->ucblocks += (buf[4] << 8) | buf[3];
389
390 return ret;
391err:
392 dbg("%s: failed=%d", __func__, ret);
393 return ret;
394}
395
396static int af9013_statistics_snr_start(struct dvb_frontend *fe)
397{
398 struct af9013_state *state = fe->demodulator_priv;
399 int ret;
400
401 dbg("%s", __func__);
402
403 /* start SNR meas */
404 ret = af9013_wr_reg_bits(state, 0xd2e1, 3, 1, 1);
405 if (ret)
406 goto err;
407
408 return ret;
409err:
410 dbg("%s: failed=%d", __func__, ret);
411 return ret;
412}
413
414static int af9013_statistics_snr_result(struct dvb_frontend *fe)
415{
416 struct af9013_state *state = fe->demodulator_priv;
417 int ret, i, len;
418 u8 buf[3], tmp;
419 u32 snr_val;
420 const struct af9013_snr *uninitialized_var(snr_lut);
421
422 dbg("%s", __func__);
423
424 /* check if SNR ready */
425 ret = af9013_rd_reg_bits(state, 0xd2e1, 3, 1, &tmp);
426 if (ret)
427 goto err;
428
429 if (!tmp) {
430 dbg("%s: not ready", __func__);
431 return 0;
432 }
433
434 /* read value */
435 ret = af9013_rd_regs(state, 0xd2e3, buf, 3);
436 if (ret)
437 goto err;
438
439 snr_val = (buf[2] << 16) | (buf[1] << 8) | buf[0];
440
441 /* read current modulation */
442 ret = af9013_rd_reg(state, 0xd3c1, &tmp);
443 if (ret)
444 goto err;
445
446 switch ((tmp >> 6) & 3) {
447 case 0:
448 len = ARRAY_SIZE(qpsk_snr_lut);
449 snr_lut = qpsk_snr_lut;
274 break; 450 break;
275 case 28000: /* 28.000 MHz */ 451 case 1:
276 tmp = 2; 452 len = ARRAY_SIZE(qam16_snr_lut);
453 snr_lut = qam16_snr_lut;
277 break; 454 break;
278 case 25000: /* 25.000 MHz */ 455 case 2:
279 tmp = 3; 456 len = ARRAY_SIZE(qam64_snr_lut);
457 snr_lut = qam64_snr_lut;
280 break; 458 break;
281 default: 459 default:
282 err("invalid xtal"); 460 goto err;
283 return -EINVAL; 461 break;
284 } 462 }
285 463
286 adc_cw = af913_div(state->config.adc_clock*1000, 1000000ul, 19ul); 464 for (i = 0; i < len; i++) {
465 tmp = snr_lut[i].snr;
287 466
288 buf[0] = (u8) ((adc_cw & 0x000000ff)); 467 if (snr_val < snr_lut[i].val)
289 buf[1] = (u8) ((adc_cw & 0x0000ff00) >> 8); 468 break;
290 buf[2] = (u8) ((adc_cw & 0x00ff0000) >> 16); 469 }
470 state->snr = tmp * 10; /* dB/10 */
291 471
292 deb_info("%s: adc_cw:", __func__); 472 return ret;
293 debug_dump(buf, sizeof(buf), deb_info); 473err:
474 dbg("%s: failed=%d", __func__, ret);
475 return ret;
476}
477
478static int af9013_statistics_signal_strength(struct dvb_frontend *fe)
479{
480 struct af9013_state *state = fe->demodulator_priv;
481 int ret = 0;
482 u8 buf[2], rf_gain, if_gain;
483 int signal_strength;
484
485 dbg("%s", __func__);
486
487 if (!state->signal_strength_en)
488 return 0;
489
490 ret = af9013_rd_regs(state, 0xd07c, buf, 2);
491 if (ret)
492 goto err;
493
494 rf_gain = buf[0];
495 if_gain = buf[1];
496
497 signal_strength = (0xffff / \
498 (9 * (state->rf_50 + state->if_50) - \
499 11 * (state->rf_80 + state->if_80))) * \
500 (10 * (rf_gain + if_gain) - \
501 11 * (state->rf_80 + state->if_80));
502 if (signal_strength < 0)
503 signal_strength = 0;
504 else if (signal_strength > 0xffff)
505 signal_strength = 0xffff;
506
507 state->signal_strength = signal_strength;
294 508
295 /* program */ 509 return ret;
296 for (i = 0; i < sizeof(buf); i++) { 510err:
297 ret = af9013_write_reg(state, 0xd180 + i, buf[i]); 511 dbg("%s: failed=%d", __func__, ret);
298 if (ret)
299 goto error;
300 }
301 ret = af9013_write_reg_bits(state, 0x9bd2, 0, 4, tmp);
302error:
303 return ret; 512 return ret;
304} 513}
305 514
306static int af9013_set_freq_ctrl(struct af9013_state *state, fe_bandwidth_t bw) 515static void af9013_statistics_work(struct work_struct *work)
307{ 516{
308 int ret; 517 int ret;
309 u16 addr; 518 struct af9013_state *state = container_of(work,
310 u8 buf[3], i, j; 519 struct af9013_state, statistics_work.work);
311 u32 adc_freq, freq_cw; 520 unsigned int next_msec;
312 s8 bfs_spec_inv; 521
313 int if_sample_freq; 522 /* update only signal strength when demod is not locked */
314 523 if (!(state->fe_status & FE_HAS_LOCK)) {
315 for (j = 0; j < 3; j++) { 524 state->statistics_step = 0;
316 if (j == 0) { 525 state->ber = 0;
317 addr = 0xd140; /* fcw normal */ 526 state->snr = 0;
318 bfs_spec_inv = state->config.rf_spec_inv ? -1 : 1; 527 }
319 } else if (j == 1) { 528
320 addr = 0x9be7; /* fcw dummy ram */ 529 switch (state->statistics_step) {
321 bfs_spec_inv = state->config.rf_spec_inv ? -1 : 1; 530 default:
322 } else { 531 state->statistics_step = 0;
323 addr = 0x9bea; /* fcw inverted */ 532 case 0:
324 bfs_spec_inv = state->config.rf_spec_inv ? 1 : -1; 533 ret = af9013_statistics_signal_strength(&state->fe);
325 } 534 state->statistics_step++;
535 next_msec = 300;
536 break;
537 case 1:
538 ret = af9013_statistics_snr_start(&state->fe);
539 state->statistics_step++;
540 next_msec = 200;
541 break;
542 case 2:
543 ret = af9013_statistics_ber_unc_start(&state->fe);
544 state->statistics_step++;
545 next_msec = 1000;
546 break;
547 case 3:
548 ret = af9013_statistics_snr_result(&state->fe);
549 state->statistics_step++;
550 next_msec = 400;
551 break;
552 case 4:
553 ret = af9013_statistics_ber_unc_result(&state->fe);
554 state->statistics_step++;
555 next_msec = 100;
556 break;
557 }
326 558
327 adc_freq = state->config.adc_clock * 1000; 559 schedule_delayed_work(&state->statistics_work,
328 if_sample_freq = state->config.tuner_if * 1000; 560 msecs_to_jiffies(next_msec));
329 561
330 /* TDA18271 uses different sampling freq for every bw */ 562 return;
331 if (state->config.tuner == AF9013_TUNER_TDA18271) { 563}
332 switch (bw) { 564
333 case BANDWIDTH_6_MHZ: 565static int af9013_get_tune_settings(struct dvb_frontend *fe,
334 if_sample_freq = 3300000; /* 3.3 MHz */ 566 struct dvb_frontend_tune_settings *fesettings)
335 break; 567{
336 case BANDWIDTH_7_MHZ: 568 fesettings->min_delay_ms = 800;
337 if_sample_freq = 3500000; /* 3.5 MHz */ 569 fesettings->step_size = 0;
338 break; 570 fesettings->max_drift = 0;
339 case BANDWIDTH_8_MHZ: 571
340 default: 572 return 0;
341 if_sample_freq = 4000000; /* 4.0 MHz */ 573}
342 break; 574
343 } 575static int af9013_set_frontend(struct dvb_frontend *fe)
344 } else if (state->config.tuner == AF9013_TUNER_TDA18218) { 576{
345 switch (bw) { 577 struct af9013_state *state = fe->demodulator_priv;
346 case BANDWIDTH_6_MHZ: 578 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
347 if_sample_freq = 3000000; /* 3 MHz */ 579 int ret, i, sampling_freq;
348 break; 580 bool auto_mode, spec_inv;
349 case BANDWIDTH_7_MHZ: 581 u8 buf[6];
350 if_sample_freq = 3500000; /* 3.5 MHz */ 582 u32 if_frequency, freq_cw;
351 break; 583
352 case BANDWIDTH_8_MHZ: 584 dbg("%s: frequency=%d bandwidth_hz=%d", __func__,
353 default: 585 c->frequency, c->bandwidth_hz);
354 if_sample_freq = 4000000; /* 4 MHz */ 586
587 /* program tuner */
588 if (fe->ops.tuner_ops.set_params)
589 fe->ops.tuner_ops.set_params(fe);
590
591 /* program CFOE coefficients */
592 if (c->bandwidth_hz != state->bandwidth_hz) {
593 for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
594 if (coeff_lut[i].clock == state->config.clock &&
595 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
355 break; 596 break;
356 } 597 }
357 } 598 }
358 599
359 while (if_sample_freq > (adc_freq / 2)) 600 ret = af9013_wr_regs(state, 0xae00, coeff_lut[i].val,
360 if_sample_freq = if_sample_freq - adc_freq; 601 sizeof(coeff_lut[i].val));
602 }
361 603
362 if (if_sample_freq >= 0) 604 /* program frequency control */
363 bfs_spec_inv = bfs_spec_inv * (-1); 605 if (c->bandwidth_hz != state->bandwidth_hz || state->first_tune) {
606 /* get used IF frequency */
607 if (fe->ops.tuner_ops.get_if_frequency)
608 fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
364 else 609 else
365 if_sample_freq = if_sample_freq * (-1); 610 if_frequency = state->config.if_frequency;
611
612 sampling_freq = if_frequency;
366 613
367 freq_cw = af913_div(if_sample_freq, adc_freq, 23ul); 614 while (sampling_freq > (state->config.clock / 2))
615 sampling_freq -= state->config.clock;
368 616
369 if (bfs_spec_inv == -1) 617 if (sampling_freq < 0) {
370 freq_cw = 0x00800000 - freq_cw; 618 sampling_freq *= -1;
619 spec_inv = state->config.spec_inv;
620 } else {
621 spec_inv = !state->config.spec_inv;
622 }
371 623
372 buf[0] = (u8) ((freq_cw & 0x000000ff)); 624 freq_cw = af913_div(sampling_freq, state->config.clock, 23);
373 buf[1] = (u8) ((freq_cw & 0x0000ff00) >> 8);
374 buf[2] = (u8) ((freq_cw & 0x007f0000) >> 16);
375 625
626 if (spec_inv)
627 freq_cw = 0x800000 - freq_cw;
376 628
377 deb_info("%s: freq_cw:", __func__); 629 buf[0] = (freq_cw >> 0) & 0xff;
378 debug_dump(buf, sizeof(buf), deb_info); 630 buf[1] = (freq_cw >> 8) & 0xff;
631 buf[2] = (freq_cw >> 16) & 0x7f;
379 632
380 /* program */ 633 freq_cw = 0x800000 - freq_cw;
381 for (i = 0; i < sizeof(buf); i++) { 634
382 ret = af9013_write_reg(state, addr++, buf[i]); 635 buf[3] = (freq_cw >> 0) & 0xff;
383 if (ret) 636 buf[4] = (freq_cw >> 8) & 0xff;
384 goto error; 637 buf[5] = (freq_cw >> 16) & 0x7f;
385 } 638
639 ret = af9013_wr_regs(state, 0xd140, buf, 3);
640 if (ret)
641 goto err;
642
643 ret = af9013_wr_regs(state, 0x9be7, buf, 6);
644 if (ret)
645 goto err;
386 } 646 }
387error:
388 return ret;
389}
390 647
391static int af9013_set_ofdm_params(struct af9013_state *state, 648 /* clear TPS lock flag */
392 struct dvb_ofdm_parameters *params, u8 *auto_mode) 649 ret = af9013_wr_reg_bits(state, 0xd330, 3, 1, 1);
393{ 650 if (ret)
394 int ret; 651 goto err;
395 u8 i, buf[3] = {0, 0, 0}; 652
396 *auto_mode = 0; /* set if parameters are requested to auto set */ 653 /* clear MPEG2 lock flag */
654 ret = af9013_wr_reg_bits(state, 0xd507, 6, 1, 0);
655 if (ret)
656 goto err;
657
658 /* empty channel function */
659 ret = af9013_wr_reg_bits(state, 0x9bfe, 0, 1, 0);
660 if (ret)
661 goto err;
397 662
398 /* Try auto-detect transmission parameters in case of AUTO requested or 663 /* empty DVB-T channel function */
399 garbage parameters given by application for compatibility. 664 ret = af9013_wr_reg_bits(state, 0x9bc2, 0, 1, 0);
400 MPlayer seems to provide garbage parameters currently. */ 665 if (ret)
666 goto err;
667
668 /* transmission parameters */
669 auto_mode = false;
670 memset(buf, 0, 3);
401 671
402 switch (params->transmission_mode) { 672 switch (c->transmission_mode) {
403 case TRANSMISSION_MODE_AUTO: 673 case TRANSMISSION_MODE_AUTO:
404 *auto_mode = 1; 674 auto_mode = 1;
675 break;
405 case TRANSMISSION_MODE_2K: 676 case TRANSMISSION_MODE_2K:
406 break; 677 break;
407 case TRANSMISSION_MODE_8K: 678 case TRANSMISSION_MODE_8K:
408 buf[0] |= (1 << 0); 679 buf[0] |= (1 << 0);
409 break; 680 break;
410 default: 681 default:
411 deb_info("%s: invalid transmission_mode\n", __func__); 682 dbg("%s: invalid transmission_mode", __func__);
412 *auto_mode = 1; 683 auto_mode = 1;
413 } 684 }
414 685
415 switch (params->guard_interval) { 686 switch (c->guard_interval) {
416 case GUARD_INTERVAL_AUTO: 687 case GUARD_INTERVAL_AUTO:
417 *auto_mode = 1; 688 auto_mode = 1;
689 break;
418 case GUARD_INTERVAL_1_32: 690 case GUARD_INTERVAL_1_32:
419 break; 691 break;
420 case GUARD_INTERVAL_1_16: 692 case GUARD_INTERVAL_1_16:
@@ -427,13 +699,14 @@ static int af9013_set_ofdm_params(struct af9013_state *state,
427 buf[0] |= (3 << 2); 699 buf[0] |= (3 << 2);
428 break; 700 break;
429 default: 701 default:
430 deb_info("%s: invalid guard_interval\n", __func__); 702 dbg("%s: invalid guard_interval", __func__);
431 *auto_mode = 1; 703 auto_mode = 1;
432 } 704 }
433 705
434 switch (params->hierarchy_information) { 706 switch (c->hierarchy) {
435 case HIERARCHY_AUTO: 707 case HIERARCHY_AUTO:
436 *auto_mode = 1; 708 auto_mode = 1;
709 break;
437 case HIERARCHY_NONE: 710 case HIERARCHY_NONE:
438 break; 711 break;
439 case HIERARCHY_1: 712 case HIERARCHY_1:
@@ -446,13 +719,14 @@ static int af9013_set_ofdm_params(struct af9013_state *state,
446 buf[0] |= (3 << 4); 719 buf[0] |= (3 << 4);
447 break; 720 break;
448 default: 721 default:
449 deb_info("%s: invalid hierarchy_information\n", __func__); 722 dbg("%s: invalid hierarchy", __func__);
450 *auto_mode = 1; 723 auto_mode = 1;
451 }; 724 };
452 725
453 switch (params->constellation) { 726 switch (c->modulation) {
454 case QAM_AUTO: 727 case QAM_AUTO:
455 *auto_mode = 1; 728 auto_mode = 1;
729 break;
456 case QPSK: 730 case QPSK:
457 break; 731 break;
458 case QAM_16: 732 case QAM_16:
@@ -462,16 +736,17 @@ static int af9013_set_ofdm_params(struct af9013_state *state,
462 buf[1] |= (2 << 6); 736 buf[1] |= (2 << 6);
463 break; 737 break;
464 default: 738 default:
465 deb_info("%s: invalid constellation\n", __func__); 739 dbg("%s: invalid modulation", __func__);
466 *auto_mode = 1; 740 auto_mode = 1;
467 } 741 }
468 742
469 /* Use HP. How and which case we can switch to LP? */ 743 /* Use HP. How and which case we can switch to LP? */
470 buf[1] |= (1 << 4); 744 buf[1] |= (1 << 4);
471 745
472 switch (params->code_rate_HP) { 746 switch (c->code_rate_HP) {
473 case FEC_AUTO: 747 case FEC_AUTO:
474 *auto_mode = 1; 748 auto_mode = 1;
749 break;
475 case FEC_1_2: 750 case FEC_1_2:
476 break; 751 break;
477 case FEC_2_3: 752 case FEC_2_3:
@@ -487,16 +762,14 @@ static int af9013_set_ofdm_params(struct af9013_state *state,
487 buf[2] |= (4 << 0); 762 buf[2] |= (4 << 0);
488 break; 763 break;
489 default: 764 default:
490 deb_info("%s: invalid code_rate_HP\n", __func__); 765 dbg("%s: invalid code_rate_HP", __func__);
491 *auto_mode = 1; 766 auto_mode = 1;
492 } 767 }
493 768
494 switch (params->code_rate_LP) { 769 switch (c->code_rate_LP) {
495 case FEC_AUTO: 770 case FEC_AUTO:
496 /* if HIERARCHY_NONE and FEC_NONE then LP FEC is set to FEC_AUTO 771 auto_mode = 1;
497 by dvb_frontend.c for compatibility */ 772 break;
498 if (params->hierarchy_information != HIERARCHY_NONE)
499 *auto_mode = 1;
500 case FEC_1_2: 773 case FEC_1_2:
501 break; 774 break;
502 case FEC_2_3: 775 case FEC_2_3:
@@ -512,709 +785,373 @@ static int af9013_set_ofdm_params(struct af9013_state *state,
512 buf[2] |= (4 << 3); 785 buf[2] |= (4 << 3);
513 break; 786 break;
514 case FEC_NONE: 787 case FEC_NONE:
515 if (params->hierarchy_information == HIERARCHY_AUTO) 788 break;
516 break;
517 default: 789 default:
518 deb_info("%s: invalid code_rate_LP\n", __func__); 790 dbg("%s: invalid code_rate_LP", __func__);
519 *auto_mode = 1; 791 auto_mode = 1;
520 } 792 }
521 793
522 switch (params->bandwidth) { 794 switch (c->bandwidth_hz) {
523 case BANDWIDTH_6_MHZ: 795 case 6000000:
524 break; 796 break;
525 case BANDWIDTH_7_MHZ: 797 case 7000000:
526 buf[1] |= (1 << 2); 798 buf[1] |= (1 << 2);
527 break; 799 break;
528 case BANDWIDTH_8_MHZ: 800 case 8000000:
529 buf[1] |= (2 << 2); 801 buf[1] |= (2 << 2);
530 break; 802 break;
531 default: 803 default:
532 deb_info("%s: invalid bandwidth\n", __func__); 804 dbg("%s: invalid bandwidth_hz", __func__);
533 buf[1] |= (2 << 2); /* cannot auto-detect BW, try 8 MHz */ 805 ret = -EINVAL;
534 } 806 goto err;
535
536 /* program */
537 for (i = 0; i < sizeof(buf); i++) {
538 ret = af9013_write_reg(state, 0xd3c0 + i, buf[i]);
539 if (ret)
540 break;
541 } 807 }
542 808
543 return ret; 809 ret = af9013_wr_regs(state, 0xd3c0, buf, 3);
544}
545
546static int af9013_reset(struct af9013_state *state, u8 sleep)
547{
548 int ret;
549 u8 tmp, i;
550 deb_info("%s\n", __func__);
551
552 /* enable OFDM reset */
553 ret = af9013_write_reg_bits(state, 0xd417, 4, 1, 1);
554 if (ret)
555 goto error;
556
557 /* start reset mechanism */
558 ret = af9013_write_reg(state, 0xaeff, 1);
559 if (ret) 810 if (ret)
560 goto error; 811 goto err;
561 812
562 /* reset is done when bit 1 is set */ 813 if (auto_mode) {
563 for (i = 0; i < 150; i++) { 814 /* clear easy mode flag */
564 ret = af9013_read_reg_bits(state, 0xd417, 1, 1, &tmp); 815 ret = af9013_wr_reg(state, 0xaefd, 0);
565 if (ret)
566 goto error;
567 if (tmp)
568 break; /* reset done */
569 msleep(10);
570 }
571 if (!tmp)
572 return -ETIMEDOUT;
573
574 /* don't clear reset when going to sleep */
575 if (!sleep) {
576 /* clear OFDM reset */
577 ret = af9013_write_reg_bits(state, 0xd417, 1, 1, 0);
578 if (ret) 816 if (ret)
579 goto error; 817 goto err;
580
581 /* disable OFDM reset */
582 ret = af9013_write_reg_bits(state, 0xd417, 4, 1, 0);
583 }
584error:
585 return ret;
586}
587
588static int af9013_power_ctrl(struct af9013_state *state, u8 onoff)
589{
590 int ret;
591 deb_info("%s: onoff:%d\n", __func__, onoff);
592 818
593 if (onoff) { 819 dbg("%s: auto params", __func__);
594 /* power on */
595 ret = af9013_write_reg_bits(state, 0xd73a, 3, 1, 0);
596 if (ret)
597 goto error;
598 ret = af9013_write_reg_bits(state, 0xd417, 1, 1, 0);
599 if (ret)
600 goto error;
601 ret = af9013_write_reg_bits(state, 0xd417, 4, 1, 0);
602 } else { 820 } else {
603 /* power off */ 821 /* set easy mode flag */
604 ret = af9013_reset(state, 1); 822 ret = af9013_wr_reg(state, 0xaefd, 1);
605 if (ret) 823 if (ret)
606 goto error; 824 goto err;
607 ret = af9013_write_reg_bits(state, 0xd73a, 3, 1, 1);
608 }
609error:
610 return ret;
611}
612
613static int af9013_lock_led(struct af9013_state *state, u8 onoff)
614{
615 deb_info("%s: onoff:%d\n", __func__, onoff);
616
617 return af9013_write_reg_bits(state, 0xd730, 0, 1, onoff);
618}
619
620static int af9013_set_frontend(struct dvb_frontend *fe,
621 struct dvb_frontend_parameters *params)
622{
623 struct af9013_state *state = fe->demodulator_priv;
624 int ret;
625 u8 auto_mode; /* auto set TPS */
626 825
627 deb_info("%s: freq:%d bw:%d\n", __func__, params->frequency, 826 ret = af9013_wr_reg(state, 0xaefe, 0);
628 params->u.ofdm.bandwidth);
629
630 state->frequency = params->frequency;
631
632 /* program tuner */
633 if (fe->ops.tuner_ops.set_params)
634 fe->ops.tuner_ops.set_params(fe, params);
635
636 /* program CFOE coefficients */
637 ret = af9013_set_coeff(state, params->u.ofdm.bandwidth);
638 if (ret)
639 goto error;
640
641 /* program frequency control */
642 ret = af9013_set_freq_ctrl(state, params->u.ofdm.bandwidth);
643 if (ret)
644 goto error;
645
646 /* clear TPS lock flag (inverted flag) */
647 ret = af9013_write_reg_bits(state, 0xd330, 3, 1, 1);
648 if (ret)
649 goto error;
650
651 /* clear MPEG2 lock flag */
652 ret = af9013_write_reg_bits(state, 0xd507, 6, 1, 0);
653 if (ret)
654 goto error;
655
656 /* empty channel function */
657 ret = af9013_write_reg_bits(state, 0x9bfe, 0, 1, 0);
658 if (ret)
659 goto error;
660
661 /* empty DVB-T channel function */
662 ret = af9013_write_reg_bits(state, 0x9bc2, 0, 1, 0);
663 if (ret)
664 goto error;
665
666 /* program TPS and bandwidth, check if auto mode needed */
667 ret = af9013_set_ofdm_params(state, &params->u.ofdm, &auto_mode);
668 if (ret)
669 goto error;
670
671 if (auto_mode) {
672 /* clear easy mode flag */
673 ret = af9013_write_reg(state, 0xaefd, 0);
674 deb_info("%s: auto TPS\n", __func__);
675 } else {
676 /* set easy mode flag */
677 ret = af9013_write_reg(state, 0xaefd, 1);
678 if (ret) 827 if (ret)
679 goto error; 828 goto err;
680 ret = af9013_write_reg(state, 0xaefe, 0); 829
681 deb_info("%s: manual TPS\n", __func__); 830 dbg("%s: manual params", __func__);
682 } 831 }
683 if (ret)
684 goto error;
685 832
686 /* everything is set, lets try to receive channel - OFSM GO! */ 833 /* tune */
687 ret = af9013_write_reg(state, 0xffff, 0); 834 ret = af9013_wr_reg(state, 0xffff, 0);
688 if (ret) 835 if (ret)
689 goto error; 836 goto err;
837
838 state->bandwidth_hz = c->bandwidth_hz;
839 state->set_frontend_jiffies = jiffies;
840 state->first_tune = false;
690 841
691error: 842 return ret;
843err:
844 dbg("%s: failed=%d", __func__, ret);
692 return ret; 845 return ret;
693} 846}
694 847
695static int af9013_get_frontend(struct dvb_frontend *fe, 848static int af9013_get_frontend(struct dvb_frontend *fe)
696 struct dvb_frontend_parameters *p)
697{ 849{
850 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
698 struct af9013_state *state = fe->demodulator_priv; 851 struct af9013_state *state = fe->demodulator_priv;
699 int ret; 852 int ret;
700 u8 i, buf[3]; 853 u8 buf[3];
701 deb_info("%s\n", __func__);
702 854
703 /* read TPS registers */ 855 dbg("%s", __func__);
704 for (i = 0; i < 3; i++) { 856
705 ret = af9013_read_reg(state, 0xd3c0 + i, &buf[i]); 857 ret = af9013_rd_regs(state, 0xd3c0, buf, 3);
706 if (ret) 858 if (ret)
707 goto error; 859 goto err;
708 }
709 860
710 switch ((buf[1] >> 6) & 3) { 861 switch ((buf[1] >> 6) & 3) {
711 case 0: 862 case 0:
712 p->u.ofdm.constellation = QPSK; 863 c->modulation = QPSK;
713 break; 864 break;
714 case 1: 865 case 1:
715 p->u.ofdm.constellation = QAM_16; 866 c->modulation = QAM_16;
716 break; 867 break;
717 case 2: 868 case 2:
718 p->u.ofdm.constellation = QAM_64; 869 c->modulation = QAM_64;
719 break; 870 break;
720 } 871 }
721 872
722 switch ((buf[0] >> 0) & 3) { 873 switch ((buf[0] >> 0) & 3) {
723 case 0: 874 case 0:
724 p->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; 875 c->transmission_mode = TRANSMISSION_MODE_2K;
725 break; 876 break;
726 case 1: 877 case 1:
727 p->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; 878 c->transmission_mode = TRANSMISSION_MODE_8K;
728 } 879 }
729 880
730 switch ((buf[0] >> 2) & 3) { 881 switch ((buf[0] >> 2) & 3) {
731 case 0: 882 case 0:
732 p->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; 883 c->guard_interval = GUARD_INTERVAL_1_32;
733 break; 884 break;
734 case 1: 885 case 1:
735 p->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; 886 c->guard_interval = GUARD_INTERVAL_1_16;
736 break; 887 break;
737 case 2: 888 case 2:
738 p->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; 889 c->guard_interval = GUARD_INTERVAL_1_8;
739 break; 890 break;
740 case 3: 891 case 3:
741 p->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; 892 c->guard_interval = GUARD_INTERVAL_1_4;
742 break; 893 break;
743 } 894 }
744 895
745 switch ((buf[0] >> 4) & 7) { 896 switch ((buf[0] >> 4) & 7) {
746 case 0: 897 case 0:
747 p->u.ofdm.hierarchy_information = HIERARCHY_NONE; 898 c->hierarchy = HIERARCHY_NONE;
748 break; 899 break;
749 case 1: 900 case 1:
750 p->u.ofdm.hierarchy_information = HIERARCHY_1; 901 c->hierarchy = HIERARCHY_1;
751 break; 902 break;
752 case 2: 903 case 2:
753 p->u.ofdm.hierarchy_information = HIERARCHY_2; 904 c->hierarchy = HIERARCHY_2;
754 break; 905 break;
755 case 3: 906 case 3:
756 p->u.ofdm.hierarchy_information = HIERARCHY_4; 907 c->hierarchy = HIERARCHY_4;
757 break; 908 break;
758 } 909 }
759 910
760 switch ((buf[2] >> 0) & 7) { 911 switch ((buf[2] >> 0) & 7) {
761 case 0: 912 case 0:
762 p->u.ofdm.code_rate_HP = FEC_1_2; 913 c->code_rate_HP = FEC_1_2;
763 break; 914 break;
764 case 1: 915 case 1:
765 p->u.ofdm.code_rate_HP = FEC_2_3; 916 c->code_rate_HP = FEC_2_3;
766 break; 917 break;
767 case 2: 918 case 2:
768 p->u.ofdm.code_rate_HP = FEC_3_4; 919 c->code_rate_HP = FEC_3_4;
769 break; 920 break;
770 case 3: 921 case 3:
771 p->u.ofdm.code_rate_HP = FEC_5_6; 922 c->code_rate_HP = FEC_5_6;
772 break; 923 break;
773 case 4: 924 case 4:
774 p->u.ofdm.code_rate_HP = FEC_7_8; 925 c->code_rate_HP = FEC_7_8;
775 break; 926 break;
776 } 927 }
777 928
778 switch ((buf[2] >> 3) & 7) { 929 switch ((buf[2] >> 3) & 7) {
779 case 0: 930 case 0:
780 p->u.ofdm.code_rate_LP = FEC_1_2; 931 c->code_rate_LP = FEC_1_2;
781 break; 932 break;
782 case 1: 933 case 1:
783 p->u.ofdm.code_rate_LP = FEC_2_3; 934 c->code_rate_LP = FEC_2_3;
784 break; 935 break;
785 case 2: 936 case 2:
786 p->u.ofdm.code_rate_LP = FEC_3_4; 937 c->code_rate_LP = FEC_3_4;
787 break; 938 break;
788 case 3: 939 case 3:
789 p->u.ofdm.code_rate_LP = FEC_5_6; 940 c->code_rate_LP = FEC_5_6;
790 break; 941 break;
791 case 4: 942 case 4:
792 p->u.ofdm.code_rate_LP = FEC_7_8; 943 c->code_rate_LP = FEC_7_8;
793 break; 944 break;
794 } 945 }
795 946
796 switch ((buf[1] >> 2) & 3) { 947 switch ((buf[1] >> 2) & 3) {
797 case 0: 948 case 0:
798 p->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; 949 c->bandwidth_hz = 6000000;
799 break; 950 break;
800 case 1: 951 case 1:
801 p->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; 952 c->bandwidth_hz = 7000000;
802 break; 953 break;
803 case 2: 954 case 2:
804 p->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; 955 c->bandwidth_hz = 8000000;
805 break; 956 break;
806 } 957 }
807 958
808 p->inversion = INVERSION_AUTO;
809 p->frequency = state->frequency;
810
811error:
812 return ret; 959 return ret;
813} 960err:
814 961 dbg("%s: failed=%d", __func__, ret);
815static int af9013_update_ber_unc(struct dvb_frontend *fe)
816{
817 struct af9013_state *state = fe->demodulator_priv;
818 int ret;
819 u8 buf[3], i;
820 u32 error_bit_count = 0;
821 u32 total_bit_count = 0;
822 u32 abort_packet_count = 0;
823
824 state->ber = 0;
825
826 /* check if error bit count is ready */
827 ret = af9013_read_reg_bits(state, 0xd391, 4, 1, &buf[0]);
828 if (ret)
829 goto error;
830 if (!buf[0])
831 goto exit;
832
833 /* get RSD packet abort count */
834 for (i = 0; i < 2; i++) {
835 ret = af9013_read_reg(state, 0xd38a + i, &buf[i]);
836 if (ret)
837 goto error;
838 }
839 abort_packet_count = (buf[1] << 8) + buf[0];
840
841 /* get error bit count */
842 for (i = 0; i < 3; i++) {
843 ret = af9013_read_reg(state, 0xd387 + i, &buf[i]);
844 if (ret)
845 goto error;
846 }
847 error_bit_count = (buf[2] << 16) + (buf[1] << 8) + buf[0];
848 error_bit_count = error_bit_count - abort_packet_count * 8 * 8;
849
850 /* get used RSD counting period (10000 RSD packets used) */
851 for (i = 0; i < 2; i++) {
852 ret = af9013_read_reg(state, 0xd385 + i, &buf[i]);
853 if (ret)
854 goto error;
855 }
856 total_bit_count = (buf[1] << 8) + buf[0];
857 total_bit_count = total_bit_count - abort_packet_count;
858 total_bit_count = total_bit_count * 204 * 8;
859
860 if (total_bit_count)
861 state->ber = error_bit_count * 1000000000 / total_bit_count;
862
863 state->ucblocks += abort_packet_count;
864
865 deb_info("%s: err bits:%d total bits:%d abort count:%d\n", __func__,
866 error_bit_count, total_bit_count, abort_packet_count);
867
868 /* set BER counting range */
869 ret = af9013_write_reg(state, 0xd385, 10000 & 0xff);
870 if (ret)
871 goto error;
872 ret = af9013_write_reg(state, 0xd386, 10000 >> 8);
873 if (ret)
874 goto error;
875 /* reset and start BER counter */
876 ret = af9013_write_reg_bits(state, 0xd391, 4, 1, 1);
877 if (ret)
878 goto error;
879
880exit:
881error:
882 return ret; 962 return ret;
883} 963}
884 964
885static int af9013_update_snr(struct dvb_frontend *fe) 965static int af9013_read_status(struct dvb_frontend *fe, fe_status_t *status)
886{ 966{
887 struct af9013_state *state = fe->demodulator_priv; 967 struct af9013_state *state = fe->demodulator_priv;
888 int ret; 968 int ret;
889 u8 buf[3], i, len; 969 u8 tmp;
890 u32 quant = 0;
891 struct snr_table *uninitialized_var(snr_table);
892
893 /* check if quantizer ready (for snr) */
894 ret = af9013_read_reg_bits(state, 0xd2e1, 3, 1, &buf[0]);
895 if (ret)
896 goto error;
897 if (buf[0]) {
898 /* quantizer ready - read it */
899 for (i = 0; i < 3; i++) {
900 ret = af9013_read_reg(state, 0xd2e3 + i, &buf[i]);
901 if (ret)
902 goto error;
903 }
904 quant = (buf[2] << 16) + (buf[1] << 8) + buf[0];
905
906 /* read current constellation */
907 ret = af9013_read_reg(state, 0xd3c1, &buf[0]);
908 if (ret)
909 goto error;
910
911 switch ((buf[0] >> 6) & 3) {
912 case 0:
913 len = ARRAY_SIZE(qpsk_snr_table);
914 snr_table = qpsk_snr_table;
915 break;
916 case 1:
917 len = ARRAY_SIZE(qam16_snr_table);
918 snr_table = qam16_snr_table;
919 break;
920 case 2:
921 len = ARRAY_SIZE(qam64_snr_table);
922 snr_table = qam64_snr_table;
923 break;
924 default:
925 len = 0;
926 break;
927 }
928
929 if (len) {
930 for (i = 0; i < len; i++) {
931 if (quant < snr_table[i].val) {
932 state->snr = snr_table[i].snr * 10;
933 break;
934 }
935 }
936 }
937
938 /* set quantizer super frame count */
939 ret = af9013_write_reg(state, 0xd2e2, 1);
940 if (ret)
941 goto error;
942
943 /* check quantizer availability */
944 for (i = 0; i < 10; i++) {
945 msleep(10);
946 ret = af9013_read_reg_bits(state, 0xd2e6, 0, 1,
947 &buf[0]);
948 if (ret)
949 goto error;
950 if (!buf[0])
951 break;
952 }
953
954 /* reset quantizer */
955 ret = af9013_write_reg_bits(state, 0xd2e1, 3, 1, 1);
956 if (ret)
957 goto error;
958 }
959
960error:
961 return ret;
962}
963
964static int af9013_update_signal_strength(struct dvb_frontend *fe)
965{
966 struct af9013_state *state = fe->demodulator_priv;
967 int ret = 0;
968 u8 rf_gain, if_gain;
969 int signal_strength;
970
971 deb_info("%s\n", __func__);
972 970
973 if (state->signal_strength_en) { 971 /*
974 ret = af9013_read_reg(state, 0xd07c, &rf_gain); 972 * Return status from the cache if it is younger than 2000ms with the
975 if (ret) 973 * exception of last tune is done during 4000ms.
976 goto error; 974 */
977 ret = af9013_read_reg(state, 0xd07d, &if_gain); 975 if (time_is_after_jiffies(
978 if (ret) 976 state->read_status_jiffies + msecs_to_jiffies(2000)) &&
979 goto error; 977 time_is_before_jiffies(
980 signal_strength = (0xffff / \ 978 state->set_frontend_jiffies + msecs_to_jiffies(4000))
981 (9 * (state->rf_50 + state->if_50) - \ 979 ) {
982 11 * (state->rf_80 + state->if_80))) * \ 980 *status = state->fe_status;
983 (10 * (rf_gain + if_gain) - \ 981 return 0;
984 11 * (state->rf_80 + state->if_80));
985 if (signal_strength < 0)
986 signal_strength = 0;
987 else if (signal_strength > 0xffff)
988 signal_strength = 0xffff;
989
990 state->signal_strength = signal_strength;
991 } else { 982 } else {
992 state->signal_strength = 0; 983 *status = 0;
993 } 984 }
994 985
995error:
996 return ret;
997}
998
999static int af9013_update_statistics(struct dvb_frontend *fe)
1000{
1001 struct af9013_state *state = fe->demodulator_priv;
1002 int ret;
1003
1004 if (time_before(jiffies, state->next_statistics_check))
1005 return 0;
1006
1007 /* set minimum statistic update interval */
1008 state->next_statistics_check = jiffies + msecs_to_jiffies(1200);
1009
1010 ret = af9013_update_signal_strength(fe);
1011 if (ret)
1012 goto error;
1013 ret = af9013_update_snr(fe);
1014 if (ret)
1015 goto error;
1016 ret = af9013_update_ber_unc(fe);
1017 if (ret)
1018 goto error;
1019
1020error:
1021 return ret;
1022}
1023
1024static int af9013_get_tune_settings(struct dvb_frontend *fe,
1025 struct dvb_frontend_tune_settings *fesettings)
1026{
1027 fesettings->min_delay_ms = 800;
1028 fesettings->step_size = 0;
1029 fesettings->max_drift = 0;
1030
1031 return 0;
1032}
1033
1034static int af9013_read_status(struct dvb_frontend *fe, fe_status_t *status)
1035{
1036 struct af9013_state *state = fe->demodulator_priv;
1037 int ret = 0;
1038 u8 tmp;
1039 *status = 0;
1040
1041 /* MPEG2 lock */ 986 /* MPEG2 lock */
1042 ret = af9013_read_reg_bits(state, 0xd507, 6, 1, &tmp); 987 ret = af9013_rd_reg_bits(state, 0xd507, 6, 1, &tmp);
1043 if (ret) 988 if (ret)
1044 goto error; 989 goto err;
990
1045 if (tmp) 991 if (tmp)
1046 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | 992 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI |
1047 FE_HAS_SYNC | FE_HAS_LOCK; 993 FE_HAS_SYNC | FE_HAS_LOCK;
1048 994
1049 if (!*status) { 995 if (!*status) {
1050 /* TPS lock */ 996 /* TPS lock */
1051 ret = af9013_read_reg_bits(state, 0xd330, 3, 1, &tmp); 997 ret = af9013_rd_reg_bits(state, 0xd330, 3, 1, &tmp);
1052 if (ret) 998 if (ret)
1053 goto error; 999 goto err;
1000
1054 if (tmp) 1001 if (tmp)
1055 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | 1002 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
1056 FE_HAS_VITERBI; 1003 FE_HAS_VITERBI;
1057 } 1004 }
1058 1005
1059 if (!*status) { 1006 state->fe_status = *status;
1060 /* CFO lock */ 1007 state->read_status_jiffies = jiffies;
1061 ret = af9013_read_reg_bits(state, 0xd333, 7, 1, &tmp);
1062 if (ret)
1063 goto error;
1064 if (tmp)
1065 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
1066 }
1067
1068 if (!*status) {
1069 /* SFOE lock */
1070 ret = af9013_read_reg_bits(state, 0xd334, 6, 1, &tmp);
1071 if (ret)
1072 goto error;
1073 if (tmp)
1074 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
1075 }
1076 1008
1077 if (!*status) { 1009 return ret;
1078 /* AGC lock */ 1010err:
1079 ret = af9013_read_reg_bits(state, 0xd1a0, 6, 1, &tmp); 1011 dbg("%s: failed=%d", __func__, ret);
1080 if (ret)
1081 goto error;
1082 if (tmp)
1083 *status |= FE_HAS_SIGNAL;
1084 }
1085
1086 ret = af9013_update_statistics(fe);
1087
1088error:
1089 return ret; 1012 return ret;
1090} 1013}
1091 1014
1092 1015static int af9013_read_snr(struct dvb_frontend *fe, u16 *snr)
1093static int af9013_read_ber(struct dvb_frontend *fe, u32 *ber)
1094{ 1016{
1095 struct af9013_state *state = fe->demodulator_priv; 1017 struct af9013_state *state = fe->demodulator_priv;
1096 int ret; 1018 *snr = state->snr;
1097 ret = af9013_update_statistics(fe); 1019 return 0;
1098 *ber = state->ber;
1099 return ret;
1100} 1020}
1101 1021
1102static int af9013_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 1022static int af9013_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
1103{ 1023{
1104 struct af9013_state *state = fe->demodulator_priv; 1024 struct af9013_state *state = fe->demodulator_priv;
1105 int ret;
1106 ret = af9013_update_statistics(fe);
1107 *strength = state->signal_strength; 1025 *strength = state->signal_strength;
1108 return ret; 1026 return 0;
1109} 1027}
1110 1028
1111static int af9013_read_snr(struct dvb_frontend *fe, u16 *snr) 1029static int af9013_read_ber(struct dvb_frontend *fe, u32 *ber)
1112{ 1030{
1113 struct af9013_state *state = fe->demodulator_priv; 1031 struct af9013_state *state = fe->demodulator_priv;
1114 int ret; 1032 *ber = state->ber;
1115 ret = af9013_update_statistics(fe); 1033 return 0;
1116 *snr = state->snr;
1117 return ret;
1118} 1034}
1119 1035
1120static int af9013_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 1036static int af9013_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1121{ 1037{
1122 struct af9013_state *state = fe->demodulator_priv; 1038 struct af9013_state *state = fe->demodulator_priv;
1123 int ret;
1124 ret = af9013_update_statistics(fe);
1125 *ucblocks = state->ucblocks; 1039 *ucblocks = state->ucblocks;
1126 return ret; 1040 return 0;
1127}
1128
1129static int af9013_sleep(struct dvb_frontend *fe)
1130{
1131 struct af9013_state *state = fe->demodulator_priv;
1132 int ret;
1133 deb_info("%s\n", __func__);
1134
1135 ret = af9013_lock_led(state, 0);
1136 if (ret)
1137 goto error;
1138
1139 ret = af9013_power_ctrl(state, 0);
1140error:
1141 return ret;
1142} 1041}
1143 1042
1144static int af9013_init(struct dvb_frontend *fe) 1043static int af9013_init(struct dvb_frontend *fe)
1145{ 1044{
1146 struct af9013_state *state = fe->demodulator_priv; 1045 struct af9013_state *state = fe->demodulator_priv;
1147 int ret, i, len; 1046 int ret, i, len;
1148 u8 tmp0, tmp1; 1047 u8 buf[3], tmp;
1149 struct regdesc *init; 1048 u32 adc_cw;
1150 deb_info("%s\n", __func__); 1049 const struct af9013_reg_bit *init;
1151 1050
1152 /* reset OFDM */ 1051 dbg("%s", __func__);
1153 ret = af9013_reset(state, 0);
1154 if (ret)
1155 goto error;
1156 1052
1157 /* power on */ 1053 /* power on */
1158 ret = af9013_power_ctrl(state, 1); 1054 ret = af9013_power_ctrl(state, 1);
1159 if (ret) 1055 if (ret)
1160 goto error; 1056 goto err;
1161 1057
1162 /* enable ADC */ 1058 /* enable ADC */
1163 ret = af9013_write_reg(state, 0xd73a, 0xa4); 1059 ret = af9013_wr_reg(state, 0xd73a, 0xa4);
1164 if (ret) 1060 if (ret)
1165 goto error; 1061 goto err;
1166 1062
1167 /* write API version to firmware */ 1063 /* write API version to firmware */
1168 for (i = 0; i < sizeof(state->config.api_version); i++) { 1064 ret = af9013_wr_regs(state, 0x9bf2, state->config.api_version, 4);
1169 ret = af9013_write_reg(state, 0x9bf2 + i, 1065 if (ret)
1170 state->config.api_version[i]); 1066 goto err;
1171 if (ret)
1172 goto error;
1173 }
1174 1067
1175 /* program ADC control */ 1068 /* program ADC control */
1176 ret = af9013_set_adc_ctrl(state); 1069 switch (state->config.clock) {
1070 case 28800000: /* 28.800 MHz */
1071 tmp = 0;
1072 break;
1073 case 20480000: /* 20.480 MHz */
1074 tmp = 1;
1075 break;
1076 case 28000000: /* 28.000 MHz */
1077 tmp = 2;
1078 break;
1079 case 25000000: /* 25.000 MHz */
1080 tmp = 3;
1081 break;
1082 default:
1083 err("invalid clock");
1084 return -EINVAL;
1085 }
1086
1087 adc_cw = af913_div(state->config.clock, 1000000ul, 19);
1088 buf[0] = (adc_cw >> 0) & 0xff;
1089 buf[1] = (adc_cw >> 8) & 0xff;
1090 buf[2] = (adc_cw >> 16) & 0xff;
1091
1092 ret = af9013_wr_regs(state, 0xd180, buf, 3);
1093 if (ret)
1094 goto err;
1095
1096 ret = af9013_wr_reg_bits(state, 0x9bd2, 0, 4, tmp);
1177 if (ret) 1097 if (ret)
1178 goto error; 1098 goto err;
1179 1099
1180 /* set I2C master clock */ 1100 /* set I2C master clock */
1181 ret = af9013_write_reg(state, 0xd416, 0x14); 1101 ret = af9013_wr_reg(state, 0xd416, 0x14);
1182 if (ret) 1102 if (ret)
1183 goto error; 1103 goto err;
1184 1104
1185 /* set 16 embx */ 1105 /* set 16 embx */
1186 ret = af9013_write_reg_bits(state, 0xd700, 1, 1, 1); 1106 ret = af9013_wr_reg_bits(state, 0xd700, 1, 1, 1);
1187 if (ret) 1107 if (ret)
1188 goto error; 1108 goto err;
1189 1109
1190 /* set no trigger */ 1110 /* set no trigger */
1191 ret = af9013_write_reg_bits(state, 0xd700, 2, 1, 0); 1111 ret = af9013_wr_reg_bits(state, 0xd700, 2, 1, 0);
1192 if (ret) 1112 if (ret)
1193 goto error; 1113 goto err;
1194 1114
1195 /* set read-update bit for constellation */ 1115 /* set read-update bit for constellation */
1196 ret = af9013_write_reg_bits(state, 0xd371, 1, 1, 1); 1116 ret = af9013_wr_reg_bits(state, 0xd371, 1, 1, 1);
1197 if (ret) 1117 if (ret)
1198 goto error; 1118 goto err;
1199 1119
1200 /* enable FEC monitor */ 1120 /* settings for mp2if */
1201 ret = af9013_write_reg_bits(state, 0xd392, 1, 1, 1); 1121 if (state->config.ts_mode == AF9013_TS_USB) {
1122 /* AF9015 split PSB to 1.5k + 0.5k */
1123 ret = af9013_wr_reg_bits(state, 0xd50b, 2, 1, 1);
1124 if (ret)
1125 goto err;
1126 } else {
1127 /* AF9013 change the output bit to data7 */
1128 ret = af9013_wr_reg_bits(state, 0xd500, 3, 1, 1);
1129 if (ret)
1130 goto err;
1131
1132 /* AF9013 set mpeg to full speed */
1133 ret = af9013_wr_reg_bits(state, 0xd502, 4, 1, 1);
1134 if (ret)
1135 goto err;
1136 }
1137
1138 ret = af9013_wr_reg_bits(state, 0xd520, 4, 1, 1);
1202 if (ret) 1139 if (ret)
1203 goto error; 1140 goto err;
1204 1141
1205 /* load OFSM settings */ 1142 /* load OFSM settings */
1206 deb_info("%s: load ofsm settings\n", __func__); 1143 dbg("%s: load ofsm settings", __func__);
1207 len = ARRAY_SIZE(ofsm_init); 1144 len = ARRAY_SIZE(ofsm_init);
1208 init = ofsm_init; 1145 init = ofsm_init;
1209 for (i = 0; i < len; i++) { 1146 for (i = 0; i < len; i++) {
1210 ret = af9013_write_reg_bits(state, init[i].addr, init[i].pos, 1147 ret = af9013_wr_reg_bits(state, init[i].addr, init[i].pos,
1211 init[i].len, init[i].val); 1148 init[i].len, init[i].val);
1212 if (ret) 1149 if (ret)
1213 goto error; 1150 goto err;
1214 } 1151 }
1215 1152
1216 /* load tuner specific settings */ 1153 /* load tuner specific settings */
1217 deb_info("%s: load tuner specific settings\n", __func__); 1154 dbg("%s: load tuner specific settings", __func__);
1218 switch (state->config.tuner) { 1155 switch (state->config.tuner) {
1219 case AF9013_TUNER_MXL5003D: 1156 case AF9013_TUNER_MXL5003D:
1220 len = ARRAY_SIZE(tuner_init_mxl5003d); 1157 len = ARRAY_SIZE(tuner_init_mxl5003d);
@@ -1260,65 +1197,133 @@ static int af9013_init(struct dvb_frontend *fe)
1260 } 1197 }
1261 1198
1262 for (i = 0; i < len; i++) { 1199 for (i = 0; i < len; i++) {
1263 ret = af9013_write_reg_bits(state, init[i].addr, init[i].pos, 1200 ret = af9013_wr_reg_bits(state, init[i].addr, init[i].pos,
1264 init[i].len, init[i].val); 1201 init[i].len, init[i].val);
1265 if (ret) 1202 if (ret)
1266 goto error; 1203 goto err;
1267 } 1204 }
1268 1205
1269 /* set TS mode */ 1206 /* TS mode */
1270 deb_info("%s: setting ts mode\n", __func__); 1207 ret = af9013_wr_reg_bits(state, 0xd500, 1, 2, state->config.ts_mode);
1271 tmp0 = 0; /* parallel mode */
1272 tmp1 = 0; /* serial mode */
1273 switch (state->config.output_mode) {
1274 case AF9013_OUTPUT_MODE_PARALLEL:
1275 tmp0 = 1;
1276 break;
1277 case AF9013_OUTPUT_MODE_SERIAL:
1278 tmp1 = 1;
1279 break;
1280 case AF9013_OUTPUT_MODE_USB:
1281 /* usb mode for AF9015 */
1282 default:
1283 break;
1284 }
1285 ret = af9013_write_reg_bits(state, 0xd500, 1, 1, tmp0); /* parallel */
1286 if (ret) 1208 if (ret)
1287 goto error; 1209 goto err;
1288 ret = af9013_write_reg_bits(state, 0xd500, 2, 1, tmp1); /* serial */
1289 if (ret)
1290 goto error;
1291 1210
1292 /* enable lock led */ 1211 /* enable lock led */
1293 ret = af9013_lock_led(state, 1); 1212 ret = af9013_wr_reg_bits(state, 0xd730, 0, 1, 1);
1294 if (ret) 1213 if (ret)
1295 goto error; 1214 goto err;
1296 1215
1297 /* read values needed for signal strength calculation */ 1216 /* check if we support signal strength */
1298 ret = af9013_read_reg_bits(state, 0x9bee, 0, 1, 1217 if (!state->signal_strength_en) {
1299 &state->signal_strength_en); 1218 ret = af9013_rd_reg_bits(state, 0x9bee, 0, 1,
1300 if (ret) 1219 &state->signal_strength_en);
1301 goto error; 1220 if (ret)
1221 goto err;
1222 }
1302 1223
1303 if (state->signal_strength_en) { 1224 /* read values needed for signal strength calculation */
1304 ret = af9013_read_reg(state, 0x9bbd, &state->rf_50); 1225 if (state->signal_strength_en && !state->rf_50) {
1226 ret = af9013_rd_reg(state, 0x9bbd, &state->rf_50);
1305 if (ret) 1227 if (ret)
1306 goto error; 1228 goto err;
1307 ret = af9013_read_reg(state, 0x9bd0, &state->rf_80); 1229
1230 ret = af9013_rd_reg(state, 0x9bd0, &state->rf_80);
1308 if (ret) 1231 if (ret)
1309 goto error; 1232 goto err;
1310 ret = af9013_read_reg(state, 0x9be2, &state->if_50); 1233
1234 ret = af9013_rd_reg(state, 0x9be2, &state->if_50);
1311 if (ret) 1235 if (ret)
1312 goto error; 1236 goto err;
1313 ret = af9013_read_reg(state, 0x9be4, &state->if_80); 1237
1238 ret = af9013_rd_reg(state, 0x9be4, &state->if_80);
1314 if (ret) 1239 if (ret)
1315 goto error; 1240 goto err;
1316 } 1241 }
1317 1242
1318error: 1243 /* SNR */
1244 ret = af9013_wr_reg(state, 0xd2e2, 1);
1245 if (ret)
1246 goto err;
1247
1248 /* BER / UCB */
1249 buf[0] = (10000 >> 0) & 0xff;
1250 buf[1] = (10000 >> 8) & 0xff;
1251 ret = af9013_wr_regs(state, 0xd385, buf, 2);
1252 if (ret)
1253 goto err;
1254
1255 /* enable FEC monitor */
1256 ret = af9013_wr_reg_bits(state, 0xd392, 1, 1, 1);
1257 if (ret)
1258 goto err;
1259
1260 state->first_tune = true;
1261 schedule_delayed_work(&state->statistics_work, msecs_to_jiffies(400));
1262
1263 return ret;
1264err:
1265 dbg("%s: failed=%d", __func__, ret);
1319 return ret; 1266 return ret;
1320} 1267}
1321 1268
1269static int af9013_sleep(struct dvb_frontend *fe)
1270{
1271 struct af9013_state *state = fe->demodulator_priv;
1272 int ret;
1273
1274 dbg("%s", __func__);
1275
1276 /* stop statistics polling */
1277 cancel_delayed_work_sync(&state->statistics_work);
1278
1279 /* disable lock led */
1280 ret = af9013_wr_reg_bits(state, 0xd730, 0, 1, 0);
1281 if (ret)
1282 goto err;
1283
1284 /* power off */
1285 ret = af9013_power_ctrl(state, 0);
1286 if (ret)
1287 goto err;
1288
1289 return ret;
1290err:
1291 dbg("%s: failed=%d", __func__, ret);
1292 return ret;
1293}
1294
1295static int af9013_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
1296{
1297 int ret;
1298 struct af9013_state *state = fe->demodulator_priv;
1299
1300 dbg("%s: enable=%d", __func__, enable);
1301
1302 /* gate already open or close */
1303 if (state->i2c_gate_state == enable)
1304 return 0;
1305
1306 if (state->config.ts_mode == AF9013_TS_USB)
1307 ret = af9013_wr_reg_bits(state, 0xd417, 3, 1, enable);
1308 else
1309 ret = af9013_wr_reg_bits(state, 0xd607, 2, 1, enable);
1310 if (ret)
1311 goto err;
1312
1313 state->i2c_gate_state = enable;
1314
1315 return ret;
1316err:
1317 dbg("%s: failed=%d", __func__, ret);
1318 return ret;
1319}
1320
1321static void af9013_release(struct dvb_frontend *fe)
1322{
1323 struct af9013_state *state = fe->demodulator_priv;
1324 kfree(state);
1325}
1326
1322static struct dvb_frontend_ops af9013_ops; 1327static struct dvb_frontend_ops af9013_ops;
1323 1328
1324static int af9013_download_firmware(struct af9013_state *state) 1329static int af9013_download_firmware(struct af9013_state *state)
@@ -1332,11 +1337,11 @@ static int af9013_download_firmware(struct af9013_state *state)
1332 1337
1333 msleep(100); 1338 msleep(100);
1334 /* check whether firmware is already running */ 1339 /* check whether firmware is already running */
1335 ret = af9013_read_reg(state, 0x98be, &val); 1340 ret = af9013_rd_reg(state, 0x98be, &val);
1336 if (ret) 1341 if (ret)
1337 goto error; 1342 goto err;
1338 else 1343 else
1339 deb_info("%s: firmware status:%02x\n", __func__, val); 1344 dbg("%s: firmware status=%02x", __func__, val);
1340 1345
1341 if (val == 0x0c) /* fw is running, no need for download */ 1346 if (val == 0x0c) /* fw is running, no need for download */
1342 goto exit; 1347 goto exit;
@@ -1351,7 +1356,7 @@ static int af9013_download_firmware(struct af9013_state *state)
1351 "Please see linux/Documentation/dvb/ for more details" \ 1356 "Please see linux/Documentation/dvb/ for more details" \
1352 " on firmware-problems. (%d)", 1357 " on firmware-problems. (%d)",
1353 fw_file, ret); 1358 fw_file, ret);
1354 goto error; 1359 goto err;
1355 } 1360 }
1356 1361
1357 info("downloading firmware from file '%s'", fw_file); 1362 info("downloading firmware from file '%s'", fw_file);
@@ -1369,7 +1374,7 @@ static int af9013_download_firmware(struct af9013_state *state)
1369 ret = af9013_write_ofsm_regs(state, 0x50fc, 1374 ret = af9013_write_ofsm_regs(state, 0x50fc,
1370 fw_params, sizeof(fw_params)); 1375 fw_params, sizeof(fw_params));
1371 if (ret) 1376 if (ret)
1372 goto error_release; 1377 goto err_release;
1373 1378
1374 #define FW_ADDR 0x5100 /* firmware start address */ 1379 #define FW_ADDR 0x5100 /* firmware start address */
1375 #define LEN_MAX 16 /* max packet size */ 1380 #define LEN_MAX 16 /* max packet size */
@@ -1383,24 +1388,24 @@ static int af9013_download_firmware(struct af9013_state *state)
1383 (u8 *) &fw->data[fw->size - remaining], len); 1388 (u8 *) &fw->data[fw->size - remaining], len);
1384 if (ret) { 1389 if (ret) {
1385 err("firmware download failed:%d", ret); 1390 err("firmware download failed:%d", ret);
1386 goto error_release; 1391 goto err_release;
1387 } 1392 }
1388 } 1393 }
1389 1394
1390 /* request boot firmware */ 1395 /* request boot firmware */
1391 ret = af9013_write_reg(state, 0xe205, 1); 1396 ret = af9013_wr_reg(state, 0xe205, 1);
1392 if (ret) 1397 if (ret)
1393 goto error_release; 1398 goto err_release;
1394 1399
1395 for (i = 0; i < 15; i++) { 1400 for (i = 0; i < 15; i++) {
1396 msleep(100); 1401 msleep(100);
1397 1402
1398 /* check firmware status */ 1403 /* check firmware status */
1399 ret = af9013_read_reg(state, 0x98be, &val); 1404 ret = af9013_rd_reg(state, 0x98be, &val);
1400 if (ret) 1405 if (ret)
1401 goto error_release; 1406 goto err_release;
1402 1407
1403 deb_info("%s: firmware status:%02x\n", __func__, val); 1408 dbg("%s: firmware status=%02x", __func__, val);
1404 1409
1405 if (val == 0x0c || val == 0x04) /* success or fail */ 1410 if (val == 0x0c || val == 0x04) /* success or fail */
1406 break; 1411 break;
@@ -1408,43 +1413,21 @@ static int af9013_download_firmware(struct af9013_state *state)
1408 1413
1409 if (val == 0x04) { 1414 if (val == 0x04) {
1410 err("firmware did not run"); 1415 err("firmware did not run");
1411 ret = -1; 1416 ret = -ENODEV;
1412 } else if (val != 0x0c) { 1417 } else if (val != 0x0c) {
1413 err("firmware boot timeout"); 1418 err("firmware boot timeout");
1414 ret = -1; 1419 ret = -ENODEV;
1415 } 1420 }
1416 1421
1417error_release: 1422err_release:
1418 release_firmware(fw); 1423 release_firmware(fw);
1419error: 1424err:
1420exit: 1425exit:
1421 if (!ret) 1426 if (!ret)
1422 info("found a '%s' in warm state.", af9013_ops.info.name); 1427 info("found a '%s' in warm state.", af9013_ops.info.name);
1423 return ret; 1428 return ret;
1424} 1429}
1425 1430
1426static int af9013_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
1427{
1428 int ret;
1429 struct af9013_state *state = fe->demodulator_priv;
1430 deb_info("%s: enable:%d\n", __func__, enable);
1431
1432 if (state->config.output_mode == AF9013_OUTPUT_MODE_USB)
1433 ret = af9013_write_reg_bits(state, 0xd417, 3, 1, enable);
1434 else
1435 ret = af9013_write_reg_bits(state, 0xd607, 2, 1, enable);
1436
1437 return ret;
1438}
1439
1440static void af9013_release(struct dvb_frontend *fe)
1441{
1442 struct af9013_state *state = fe->demodulator_priv;
1443 kfree(state);
1444}
1445
1446static struct dvb_frontend_ops af9013_ops;
1447
1448struct dvb_frontend *af9013_attach(const struct af9013_config *config, 1431struct dvb_frontend *af9013_attach(const struct af9013_config *config,
1449 struct i2c_adapter *i2c) 1432 struct i2c_adapter *i2c)
1450{ 1433{
@@ -1455,91 +1438,65 @@ struct dvb_frontend *af9013_attach(const struct af9013_config *config,
1455 /* allocate memory for the internal state */ 1438 /* allocate memory for the internal state */
1456 state = kzalloc(sizeof(struct af9013_state), GFP_KERNEL); 1439 state = kzalloc(sizeof(struct af9013_state), GFP_KERNEL);
1457 if (state == NULL) 1440 if (state == NULL)
1458 goto error; 1441 goto err;
1459 1442
1460 /* setup the state */ 1443 /* setup the state */
1461 state->i2c = i2c; 1444 state->i2c = i2c;
1462 memcpy(&state->config, config, sizeof(struct af9013_config)); 1445 memcpy(&state->config, config, sizeof(struct af9013_config));
1463 1446
1464 /* download firmware */ 1447 /* download firmware */
1465 if (state->config.output_mode != AF9013_OUTPUT_MODE_USB) { 1448 if (state->config.ts_mode != AF9013_TS_USB) {
1466 ret = af9013_download_firmware(state); 1449 ret = af9013_download_firmware(state);
1467 if (ret) 1450 if (ret)
1468 goto error; 1451 goto err;
1469 } 1452 }
1470 1453
1471 /* firmware version */ 1454 /* firmware version */
1472 for (i = 0; i < 4; i++) { 1455 ret = af9013_rd_regs(state, 0x5103, buf, 4);
1473 ret = af9013_read_reg(state, 0x5103 + i, &buf[i]);
1474 if (ret)
1475 goto error;
1476 }
1477 info("firmware version:%d.%d.%d.%d", buf[0], buf[1], buf[2], buf[3]);
1478
1479 /* chip version */
1480 ret = af9013_read_reg_bits(state, 0xd733, 4, 4, &buf[2]);
1481 if (ret) 1456 if (ret)
1482 goto error; 1457 goto err;
1483 1458
1484 /* ROM version */ 1459 info("firmware version %d.%d.%d.%d", buf[0], buf[1], buf[2], buf[3]);
1485 for (i = 0; i < 2; i++) {
1486 ret = af9013_read_reg(state, 0x116b + i, &buf[i]);
1487 if (ret)
1488 goto error;
1489 }
1490 deb_info("%s: chip version:%d ROM version:%d.%d\n", __func__,
1491 buf[2], buf[0], buf[1]);
1492
1493 /* settings for mp2if */
1494 if (state->config.output_mode == AF9013_OUTPUT_MODE_USB) {
1495 /* AF9015 split PSB to 1.5k + 0.5k */
1496 ret = af9013_write_reg_bits(state, 0xd50b, 2, 1, 1);
1497 } else {
1498 /* AF9013 change the output bit to data7 */
1499 ret = af9013_write_reg_bits(state, 0xd500, 3, 1, 1);
1500 if (ret)
1501 goto error;
1502 /* AF9013 set mpeg to full speed */
1503 ret = af9013_write_reg_bits(state, 0xd502, 4, 1, 1);
1504 }
1505 if (ret)
1506 goto error;
1507 ret = af9013_write_reg_bits(state, 0xd520, 4, 1, 1);
1508 if (ret)
1509 goto error;
1510 1460
1511 /* set GPIOs */ 1461 /* set GPIOs */
1512 for (i = 0; i < sizeof(state->config.gpio); i++) { 1462 for (i = 0; i < sizeof(state->config.gpio); i++) {
1513 ret = af9013_set_gpio(state, i, state->config.gpio[i]); 1463 ret = af9013_set_gpio(state, i, state->config.gpio[i]);
1514 if (ret) 1464 if (ret)
1515 goto error; 1465 goto err;
1516 } 1466 }
1517 1467
1518 /* create dvb_frontend */ 1468 /* create dvb_frontend */
1519 memcpy(&state->frontend.ops, &af9013_ops, 1469 memcpy(&state->fe.ops, &af9013_ops,
1520 sizeof(struct dvb_frontend_ops)); 1470 sizeof(struct dvb_frontend_ops));
1521 state->frontend.demodulator_priv = state; 1471 state->fe.demodulator_priv = state;
1472
1473 INIT_DELAYED_WORK(&state->statistics_work, af9013_statistics_work);
1522 1474
1523 return &state->frontend; 1475 return &state->fe;
1524error: 1476err:
1525 kfree(state); 1477 kfree(state);
1526 return NULL; 1478 return NULL;
1527} 1479}
1528EXPORT_SYMBOL(af9013_attach); 1480EXPORT_SYMBOL(af9013_attach);
1529 1481
1530static struct dvb_frontend_ops af9013_ops = { 1482static struct dvb_frontend_ops af9013_ops = {
1483 .delsys = { SYS_DVBT },
1531 .info = { 1484 .info = {
1532 .name = "Afatech AF9013 DVB-T", 1485 .name = "Afatech AF9013",
1533 .type = FE_OFDM,
1534 .frequency_min = 174000000, 1486 .frequency_min = 174000000,
1535 .frequency_max = 862000000, 1487 .frequency_max = 862000000,
1536 .frequency_stepsize = 250000, 1488 .frequency_stepsize = 250000,
1537 .frequency_tolerance = 0, 1489 .frequency_tolerance = 0,
1538 .caps = 1490 .caps = FE_CAN_FEC_1_2 |
1539 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1491 FE_CAN_FEC_2_3 |
1540 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1492 FE_CAN_FEC_3_4 |
1541 FE_CAN_QPSK | FE_CAN_QAM_16 | 1493 FE_CAN_FEC_5_6 |
1542 FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 1494 FE_CAN_FEC_7_8 |
1495 FE_CAN_FEC_AUTO |
1496 FE_CAN_QPSK |
1497 FE_CAN_QAM_16 |
1498 FE_CAN_QAM_64 |
1499 FE_CAN_QAM_AUTO |
1543 FE_CAN_TRANSMISSION_MODE_AUTO | 1500 FE_CAN_TRANSMISSION_MODE_AUTO |
1544 FE_CAN_GUARD_INTERVAL_AUTO | 1501 FE_CAN_GUARD_INTERVAL_AUTO |
1545 FE_CAN_HIERARCHY_AUTO | 1502 FE_CAN_HIERARCHY_AUTO |
@@ -1548,24 +1505,22 @@ static struct dvb_frontend_ops af9013_ops = {
1548 }, 1505 },
1549 1506
1550 .release = af9013_release, 1507 .release = af9013_release,
1508
1551 .init = af9013_init, 1509 .init = af9013_init,
1552 .sleep = af9013_sleep, 1510 .sleep = af9013_sleep,
1553 .i2c_gate_ctrl = af9013_i2c_gate_ctrl,
1554 1511
1512 .get_tune_settings = af9013_get_tune_settings,
1555 .set_frontend = af9013_set_frontend, 1513 .set_frontend = af9013_set_frontend,
1556 .get_frontend = af9013_get_frontend, 1514 .get_frontend = af9013_get_frontend,
1557 1515
1558 .get_tune_settings = af9013_get_tune_settings,
1559
1560 .read_status = af9013_read_status, 1516 .read_status = af9013_read_status,
1561 .read_ber = af9013_read_ber,
1562 .read_signal_strength = af9013_read_signal_strength,
1563 .read_snr = af9013_read_snr, 1517 .read_snr = af9013_read_snr,
1518 .read_signal_strength = af9013_read_signal_strength,
1519 .read_ber = af9013_read_ber,
1564 .read_ucblocks = af9013_read_ucblocks, 1520 .read_ucblocks = af9013_read_ucblocks,
1565};
1566 1521
1567module_param_named(debug, af9013_debug, int, 0644); 1522 .i2c_gate_ctrl = af9013_i2c_gate_ctrl,
1568MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); 1523};
1569 1524
1570MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); 1525MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1571MODULE_DESCRIPTION("Afatech AF9013 DVB-T demodulator driver"); 1526MODULE_DESCRIPTION("Afatech AF9013 DVB-T demodulator driver");
diff --git a/drivers/media/dvb/frontends/af9013.h b/drivers/media/dvb/frontends/af9013.h
index e53d873f7555..b973fc5a0384 100644
--- a/drivers/media/dvb/frontends/af9013.h
+++ b/drivers/media/dvb/frontends/af9013.h
@@ -2,6 +2,7 @@
2 * Afatech AF9013 demodulator driver 2 * Afatech AF9013 demodulator driver
3 * 3 *
4 * Copyright (C) 2007 Antti Palosaari <crope@iki.fi> 4 * Copyright (C) 2007 Antti Palosaari <crope@iki.fi>
5 * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
5 * 6 *
6 * Thanks to Afatech who kindly provided information. 7 * Thanks to Afatech who kindly provided information.
7 * 8 *
@@ -21,33 +22,11 @@
21 * 22 *
22 */ 23 */
23 24
24#ifndef _AF9013_H_ 25#ifndef AF9013_H
25#define _AF9013_H_ 26#define AF9013_H
26 27
27#include <linux/dvb/frontend.h> 28#include <linux/dvb/frontend.h>
28 29
29enum af9013_ts_mode {
30 AF9013_OUTPUT_MODE_PARALLEL,
31 AF9013_OUTPUT_MODE_SERIAL,
32 AF9013_OUTPUT_MODE_USB, /* only for AF9015 */
33};
34
35enum af9013_tuner {
36 AF9013_TUNER_MXL5003D = 3, /* MaxLinear */
37 AF9013_TUNER_MXL5005D = 13, /* MaxLinear */
38 AF9013_TUNER_MXL5005R = 30, /* MaxLinear */
39 AF9013_TUNER_ENV77H11D5 = 129, /* Panasonic */
40 AF9013_TUNER_MT2060 = 130, /* Microtune */
41 AF9013_TUNER_MC44S803 = 133, /* Freescale */
42 AF9013_TUNER_QT1010 = 134, /* Quantek */
43 AF9013_TUNER_UNKNOWN = 140, /* for can tuners ? */
44 AF9013_TUNER_MT2060_2 = 147, /* Microtune */
45 AF9013_TUNER_TDA18271 = 156, /* NXP */
46 AF9013_TUNER_QT1010A = 162, /* Quantek */
47 AF9013_TUNER_MXL5007T = 177, /* MaxLinear */
48 AF9013_TUNER_TDA18218 = 179, /* NXP */
49};
50
51/* AF9013/5 GPIOs (mostly guessed) 30/* AF9013/5 GPIOs (mostly guessed)
52 demod#1-gpio#0 - set demod#2 i2c-addr for dual devices 31 demod#1-gpio#0 - set demod#2 i2c-addr for dual devices
53 demod#1-gpio#1 - xtal setting (?) 32 demod#1-gpio#1 - xtal setting (?)
@@ -55,44 +34,74 @@ enum af9013_tuner {
55 demod#2-gpio#0 - tuner#2 34 demod#2-gpio#0 - tuner#2
56 demod#2-gpio#1 - xtal setting (?) 35 demod#2-gpio#1 - xtal setting (?)
57*/ 36*/
37
38struct af9013_config {
39 /*
40 * I2C address
41 */
42 u8 i2c_addr;
43
44 /*
45 * clock
46 * 20480000, 25000000, 28000000, 28800000
47 */
48 u32 clock;
49
50 /*
51 * tuner
52 */
53#define AF9013_TUNER_MXL5003D 3 /* MaxLinear */
54#define AF9013_TUNER_MXL5005D 13 /* MaxLinear */
55#define AF9013_TUNER_MXL5005R 30 /* MaxLinear */
56#define AF9013_TUNER_ENV77H11D5 129 /* Panasonic */
57#define AF9013_TUNER_MT2060 130 /* Microtune */
58#define AF9013_TUNER_MC44S803 133 /* Freescale */
59#define AF9013_TUNER_QT1010 134 /* Quantek */
60#define AF9013_TUNER_UNKNOWN 140 /* for can tuners ? */
61#define AF9013_TUNER_MT2060_2 147 /* Microtune */
62#define AF9013_TUNER_TDA18271 156 /* NXP */
63#define AF9013_TUNER_QT1010A 162 /* Quantek */
64#define AF9013_TUNER_MXL5007T 177 /* MaxLinear */
65#define AF9013_TUNER_TDA18218 179 /* NXP */
66 u8 tuner;
67
68 /*
69 * IF frequency
70 */
71 u32 if_frequency;
72
73 /*
74 * TS settings
75 */
76#define AF9013_TS_USB 0
77#define AF9013_TS_PARALLEL 1
78#define AF9013_TS_SERIAL 2
79 u8 ts_mode:2;
80
81 /*
82 * input spectrum inversion
83 */
84 bool spec_inv;
85
86 /*
87 * firmware API version
88 */
89 u8 api_version[4];
90
91 /*
92 * GPIOs
93 */
58#define AF9013_GPIO_ON (1 << 0) 94#define AF9013_GPIO_ON (1 << 0)
59#define AF9013_GPIO_EN (1 << 1) 95#define AF9013_GPIO_EN (1 << 1)
60#define AF9013_GPIO_O (1 << 2) 96#define AF9013_GPIO_O (1 << 2)
61#define AF9013_GPIO_I (1 << 3) 97#define AF9013_GPIO_I (1 << 3)
62
63#define AF9013_GPIO_LO (AF9013_GPIO_ON|AF9013_GPIO_EN) 98#define AF9013_GPIO_LO (AF9013_GPIO_ON|AF9013_GPIO_EN)
64#define AF9013_GPIO_HI (AF9013_GPIO_ON|AF9013_GPIO_EN|AF9013_GPIO_O) 99#define AF9013_GPIO_HI (AF9013_GPIO_ON|AF9013_GPIO_EN|AF9013_GPIO_O)
65
66#define AF9013_GPIO_TUNER_ON (AF9013_GPIO_ON|AF9013_GPIO_EN) 100#define AF9013_GPIO_TUNER_ON (AF9013_GPIO_ON|AF9013_GPIO_EN)
67#define AF9013_GPIO_TUNER_OFF (AF9013_GPIO_ON|AF9013_GPIO_EN|AF9013_GPIO_O) 101#define AF9013_GPIO_TUNER_OFF (AF9013_GPIO_ON|AF9013_GPIO_EN|AF9013_GPIO_O)
68
69struct af9013_config {
70 /* demodulator's I2C address */
71 u8 demod_address;
72
73 /* frequencies in kHz */
74 u32 adc_clock;
75
76 /* tuner ID */
77 u8 tuner;
78
79 /* tuner IF */
80 u16 tuner_if;
81
82 /* TS data output mode */
83 u8 output_mode:2;
84
85 /* RF spectrum inversion */
86 u8 rf_spec_inv:1;
87
88 /* API version */
89 u8 api_version[4];
90
91 /* GPIOs */
92 u8 gpio[4]; 102 u8 gpio[4];
93}; 103};
94 104
95
96#if defined(CONFIG_DVB_AF9013) || \ 105#if defined(CONFIG_DVB_AF9013) || \
97 (defined(CONFIG_DVB_AF9013_MODULE) && defined(MODULE)) 106 (defined(CONFIG_DVB_AF9013_MODULE) && defined(MODULE))
98extern struct dvb_frontend *af9013_attach(const struct af9013_config *config, 107extern struct dvb_frontend *af9013_attach(const struct af9013_config *config,
@@ -106,4 +115,4 @@ const struct af9013_config *config, struct i2c_adapter *i2c)
106} 115}
107#endif /* CONFIG_DVB_AF9013 */ 116#endif /* CONFIG_DVB_AF9013 */
108 117
109#endif /* _AF9013_H_ */ 118#endif /* AF9013_H */
diff --git a/drivers/media/dvb/frontends/af9013_priv.h b/drivers/media/dvb/frontends/af9013_priv.h
index e00b2a4a2db6..fa848af6e9b4 100644
--- a/drivers/media/dvb/frontends/af9013_priv.h
+++ b/drivers/media/dvb/frontends/af9013_priv.h
@@ -2,6 +2,7 @@
2 * Afatech AF9013 demodulator driver 2 * Afatech AF9013 demodulator driver
3 * 3 *
4 * Copyright (C) 2007 Antti Palosaari <crope@iki.fi> 4 * Copyright (C) 2007 Antti Palosaari <crope@iki.fi>
5 * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
5 * 6 *
6 * Thanks to Afatech who kindly provided information. 7 * Thanks to Afatech who kindly provided information.
7 * 8 *
@@ -21,24 +22,19 @@
21 * 22 *
22 */ 23 */
23 24
24#ifndef _AF9013_PRIV_ 25#ifndef AF9013_PRIV_H
25#define _AF9013_PRIV_ 26#define AF9013_PRIV_H
26 27
27#define LOG_PREFIX "af9013" 28#include "dvb_frontend.h"
28extern int af9013_debug; 29#include "af9013.h"
29 30#include <linux/firmware.h>
30#define dprintk(var, level, args...) \
31 do { if ((var & level)) printk(args); } while (0)
32 31
33#define debug_dump(b, l, func) {\ 32#define LOG_PREFIX "af9013"
34 int loop_; \
35 for (loop_ = 0; loop_ < l; loop_++) \
36 func("%02x ", b[loop_]); \
37 func("\n");\
38}
39
40#define deb_info(args...) dprintk(af9013_debug, 0x01, args)
41 33
34#undef dbg
35#define dbg(f, arg...) \
36 if (af9013_debug) \
37 printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
42#undef err 38#undef err
43#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg) 39#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg)
44#undef info 40#undef info
@@ -48,70 +44,71 @@ extern int af9013_debug;
48 44
49#define AF9013_DEFAULT_FIRMWARE "dvb-fe-af9013.fw" 45#define AF9013_DEFAULT_FIRMWARE "dvb-fe-af9013.fw"
50 46
51struct regdesc { 47struct af9013_reg_bit {
52 u16 addr; 48 u16 addr;
53 u8 pos:4; 49 u8 pos:4;
54 u8 len:4; 50 u8 len:4;
55 u8 val; 51 u8 val;
56}; 52};
57 53
58struct snr_table { 54struct af9013_snr {
59 u32 val; 55 u32 val;
60 u8 snr; 56 u8 snr;
61}; 57};
62 58
63struct coeff { 59struct af9013_coeff {
64 u32 adc_clock; 60 u32 clock;
65 fe_bandwidth_t bw; 61 u32 bandwidth_hz;
66 u8 val[24]; 62 u8 val[24];
67}; 63};
68 64
69/* pre-calculated coeff lookup table */ 65/* pre-calculated coeff lookup table */
70static struct coeff coeff_table[] = { 66static const struct af9013_coeff coeff_lut[] = {
71 /* 28.800 MHz */ 67 /* 28.800 MHz */
72 { 28800, BANDWIDTH_8_MHZ, { 0x02, 0x8a, 0x28, 0xa3, 0x05, 0x14, 68 { 28800000, 8000000, { 0x02, 0x8a, 0x28, 0xa3, 0x05, 0x14,
73 0x51, 0x11, 0x00, 0xa2, 0x8f, 0x3d, 0x00, 0xa2, 0x8a, 69 0x51, 0x11, 0x00, 0xa2, 0x8f, 0x3d, 0x00, 0xa2, 0x8a,
74 0x29, 0x00, 0xa2, 0x85, 0x14, 0x01, 0x45, 0x14, 0x14 } }, 70 0x29, 0x00, 0xa2, 0x85, 0x14, 0x01, 0x45, 0x14, 0x14 } },
75 { 28800, BANDWIDTH_7_MHZ, { 0x02, 0x38, 0xe3, 0x8e, 0x04, 0x71, 71 { 28800000, 7000000, { 0x02, 0x38, 0xe3, 0x8e, 0x04, 0x71,
76 0xc7, 0x07, 0x00, 0x8e, 0x3d, 0x55, 0x00, 0x8e, 0x38, 72 0xc7, 0x07, 0x00, 0x8e, 0x3d, 0x55, 0x00, 0x8e, 0x38,
77 0xe4, 0x00, 0x8e, 0x34, 0x72, 0x01, 0x1c, 0x71, 0x32 } }, 73 0xe4, 0x00, 0x8e, 0x34, 0x72, 0x01, 0x1c, 0x71, 0x32 } },
78 { 28800, BANDWIDTH_6_MHZ, { 0x01, 0xe7, 0x9e, 0x7a, 0x03, 0xcf, 74 { 28800000, 6000000, { 0x01, 0xe7, 0x9e, 0x7a, 0x03, 0xcf,
79 0x3c, 0x3d, 0x00, 0x79, 0xeb, 0x6e, 0x00, 0x79, 0xe7, 75 0x3c, 0x3d, 0x00, 0x79, 0xeb, 0x6e, 0x00, 0x79, 0xe7,
80 0x9e, 0x00, 0x79, 0xe3, 0xcf, 0x00, 0xf3, 0xcf, 0x0f } }, 76 0x9e, 0x00, 0x79, 0xe3, 0xcf, 0x00, 0xf3, 0xcf, 0x0f } },
81 /* 20.480 MHz */ 77 /* 20.480 MHz */
82 { 20480, BANDWIDTH_8_MHZ, { 0x03, 0x92, 0x49, 0x26, 0x07, 0x24, 78 { 20480000, 8000000, { 0x03, 0x92, 0x49, 0x26, 0x07, 0x24,
83 0x92, 0x13, 0x00, 0xe4, 0x99, 0x6e, 0x00, 0xe4, 0x92, 79 0x92, 0x13, 0x00, 0xe4, 0x99, 0x6e, 0x00, 0xe4, 0x92,
84 0x49, 0x00, 0xe4, 0x8b, 0x25, 0x01, 0xc9, 0x24, 0x25 } }, 80 0x49, 0x00, 0xe4, 0x8b, 0x25, 0x01, 0xc9, 0x24, 0x25 } },
85 { 20480, BANDWIDTH_7_MHZ, { 0x03, 0x20, 0x00, 0x01, 0x06, 0x40, 81 { 20480000, 7000000, { 0x03, 0x20, 0x00, 0x01, 0x06, 0x40,
86 0x00, 0x00, 0x00, 0xc8, 0x06, 0x40, 0x00, 0xc8, 0x00, 82 0x00, 0x00, 0x00, 0xc8, 0x06, 0x40, 0x00, 0xc8, 0x00,
87 0x00, 0x00, 0xc7, 0xf9, 0xc0, 0x01, 0x90, 0x00, 0x00 } }, 83 0x00, 0x00, 0xc7, 0xf9, 0xc0, 0x01, 0x90, 0x00, 0x00 } },
88 { 20480, BANDWIDTH_6_MHZ, { 0x02, 0xad, 0xb6, 0xdc, 0x05, 0x5b, 84 { 20480000, 6000000, { 0x02, 0xad, 0xb6, 0xdc, 0x05, 0x5b,
89 0x6d, 0x2e, 0x00, 0xab, 0x73, 0x13, 0x00, 0xab, 0x6d, 85 0x6d, 0x2e, 0x00, 0xab, 0x73, 0x13, 0x00, 0xab, 0x6d,
90 0xb7, 0x00, 0xab, 0x68, 0x5c, 0x01, 0x56, 0xdb, 0x1c } }, 86 0xb7, 0x00, 0xab, 0x68, 0x5c, 0x01, 0x56, 0xdb, 0x1c } },
91 /* 28.000 MHz */ 87 /* 28.000 MHz */
92 { 28000, BANDWIDTH_8_MHZ, { 0x02, 0x9c, 0xbc, 0x15, 0x05, 0x39, 88 { 28000000, 8000000, { 0x02, 0x9c, 0xbc, 0x15, 0x05, 0x39,
93 0x78, 0x0a, 0x00, 0xa7, 0x34, 0x3f, 0x00, 0xa7, 0x2f, 89 0x78, 0x0a, 0x00, 0xa7, 0x34, 0x3f, 0x00, 0xa7, 0x2f,
94 0x05, 0x00, 0xa7, 0x29, 0xcc, 0x01, 0x4e, 0x5e, 0x03 } }, 90 0x05, 0x00, 0xa7, 0x29, 0xcc, 0x01, 0x4e, 0x5e, 0x03 } },
95 { 28000, BANDWIDTH_7_MHZ, { 0x02, 0x49, 0x24, 0x92, 0x04, 0x92, 91 { 28000000, 7000000, { 0x02, 0x49, 0x24, 0x92, 0x04, 0x92,
96 0x49, 0x09, 0x00, 0x92, 0x4d, 0xb7, 0x00, 0x92, 0x49, 92 0x49, 0x09, 0x00, 0x92, 0x4d, 0xb7, 0x00, 0x92, 0x49,
97 0x25, 0x00, 0x92, 0x44, 0x92, 0x01, 0x24, 0x92, 0x12 } }, 93 0x25, 0x00, 0x92, 0x44, 0x92, 0x01, 0x24, 0x92, 0x12 } },
98 { 28000, BANDWIDTH_6_MHZ, { 0x01, 0xf5, 0x8d, 0x10, 0x03, 0xeb, 94 { 28000000, 6000000, { 0x01, 0xf5, 0x8d, 0x10, 0x03, 0xeb,
99 0x1a, 0x08, 0x00, 0x7d, 0x67, 0x2f, 0x00, 0x7d, 0x63, 95 0x1a, 0x08, 0x00, 0x7d, 0x67, 0x2f, 0x00, 0x7d, 0x63,
100 0x44, 0x00, 0x7d, 0x5f, 0x59, 0x00, 0xfa, 0xc6, 0x22 } }, 96 0x44, 0x00, 0x7d, 0x5f, 0x59, 0x00, 0xfa, 0xc6, 0x22 } },
101 /* 25.000 MHz */ 97 /* 25.000 MHz */
102 { 25000, BANDWIDTH_8_MHZ, { 0x02, 0xec, 0xfb, 0x9d, 0x05, 0xd9, 98 { 25000000, 8000000, { 0x02, 0xec, 0xfb, 0x9d, 0x05, 0xd9,
103 0xf7, 0x0e, 0x00, 0xbb, 0x44, 0xc1, 0x00, 0xbb, 0x3e, 99 0xf7, 0x0e, 0x00, 0xbb, 0x44, 0xc1, 0x00, 0xbb, 0x3e,
104 0xe7, 0x00, 0xbb, 0x39, 0x0d, 0x01, 0x76, 0x7d, 0x34 } }, 100 0xe7, 0x00, 0xbb, 0x39, 0x0d, 0x01, 0x76, 0x7d, 0x34 } },
105 { 25000, BANDWIDTH_7_MHZ, { 0x02, 0x8f, 0x5c, 0x29, 0x05, 0x1e, 101 { 25000000, 7000000, { 0x02, 0x8f, 0x5c, 0x29, 0x05, 0x1e,
106 0xb8, 0x14, 0x00, 0xa3, 0xdc, 0x29, 0x00, 0xa3, 0xd7, 102 0xb8, 0x14, 0x00, 0xa3, 0xdc, 0x29, 0x00, 0xa3, 0xd7,
107 0x0a, 0x00, 0xa3, 0xd1, 0xec, 0x01, 0x47, 0xae, 0x05 } }, 103 0x0a, 0x00, 0xa3, 0xd1, 0xec, 0x01, 0x47, 0xae, 0x05 } },
108 { 25000, BANDWIDTH_6_MHZ, { 0x02, 0x31, 0xbc, 0xb5, 0x04, 0x63, 104 { 25000000, 6000000, { 0x02, 0x31, 0xbc, 0xb5, 0x04, 0x63,
109 0x79, 0x1b, 0x00, 0x8c, 0x73, 0x91, 0x00, 0x8c, 0x6f, 105 0x79, 0x1b, 0x00, 0x8c, 0x73, 0x91, 0x00, 0x8c, 0x6f,
110 0x2d, 0x00, 0x8c, 0x6a, 0xca, 0x01, 0x18, 0xde, 0x17 } }, 106 0x2d, 0x00, 0x8c, 0x6a, 0xca, 0x01, 0x18, 0xde, 0x17 } },
111}; 107};
112 108
113/* QPSK SNR lookup table */ 109/* QPSK SNR lookup table */
114static struct snr_table qpsk_snr_table[] = { 110static const struct af9013_snr qpsk_snr_lut[] = {
111 { 0x000000, 0 },
115 { 0x0b4771, 0 }, 112 { 0x0b4771, 0 },
116 { 0x0c1aed, 1 }, 113 { 0x0c1aed, 1 },
117 { 0x0d0d27, 2 }, 114 { 0x0d0d27, 2 },
@@ -131,7 +128,8 @@ static struct snr_table qpsk_snr_table[] = {
131}; 128};
132 129
133/* QAM16 SNR lookup table */ 130/* QAM16 SNR lookup table */
134static struct snr_table qam16_snr_table[] = { 131static const struct af9013_snr qam16_snr_lut[] = {
132 { 0x000000, 0 },
135 { 0x05eb62, 5 }, 133 { 0x05eb62, 5 },
136 { 0x05fecf, 6 }, 134 { 0x05fecf, 6 },
137 { 0x060b80, 7 }, 135 { 0x060b80, 7 },
@@ -151,7 +149,8 @@ static struct snr_table qam16_snr_table[] = {
151}; 149};
152 150
153/* QAM64 SNR lookup table */ 151/* QAM64 SNR lookup table */
154static struct snr_table qam64_snr_table[] = { 152static const struct af9013_snr qam64_snr_lut[] = {
153 { 0x000000, 0 },
155 { 0x03109b, 12 }, 154 { 0x03109b, 12 },
156 { 0x0310d4, 13 }, 155 { 0x0310d4, 13 },
157 { 0x031920, 14 }, 156 { 0x031920, 14 },
@@ -170,7 +169,7 @@ static struct snr_table qam64_snr_table[] = {
170 { 0xffffff, 27 }, 169 { 0xffffff, 27 },
171}; 170};
172 171
173static struct regdesc ofsm_init[] = { 172static const struct af9013_reg_bit ofsm_init[] = {
174 { 0xd73a, 0, 8, 0xa1 }, 173 { 0xd73a, 0, 8, 0xa1 },
175 { 0xd73b, 0, 8, 0x1f }, 174 { 0xd73b, 0, 8, 0x1f },
176 { 0xd73c, 4, 4, 0x0a }, 175 { 0xd73c, 4, 4, 0x0a },
@@ -252,7 +251,7 @@ static struct regdesc ofsm_init[] = {
252 251
253/* Panasonic ENV77H11D5 tuner init 252/* Panasonic ENV77H11D5 tuner init
254 AF9013_TUNER_ENV77H11D5 = 129 */ 253 AF9013_TUNER_ENV77H11D5 = 129 */
255static struct regdesc tuner_init_env77h11d5[] = { 254static const struct af9013_reg_bit tuner_init_env77h11d5[] = {
256 { 0x9bd5, 0, 8, 0x01 }, 255 { 0x9bd5, 0, 8, 0x01 },
257 { 0x9bd6, 0, 8, 0x03 }, 256 { 0x9bd6, 0, 8, 0x03 },
258 { 0x9bbe, 0, 8, 0x01 }, 257 { 0x9bbe, 0, 8, 0x01 },
@@ -318,7 +317,7 @@ static struct regdesc tuner_init_env77h11d5[] = {
318 317
319/* Microtune MT2060 tuner init 318/* Microtune MT2060 tuner init
320 AF9013_TUNER_MT2060 = 130 */ 319 AF9013_TUNER_MT2060 = 130 */
321static struct regdesc tuner_init_mt2060[] = { 320static const struct af9013_reg_bit tuner_init_mt2060[] = {
322 { 0x9bd5, 0, 8, 0x01 }, 321 { 0x9bd5, 0, 8, 0x01 },
323 { 0x9bd6, 0, 8, 0x07 }, 322 { 0x9bd6, 0, 8, 0x07 },
324 { 0xd1a0, 1, 1, 0x01 }, 323 { 0xd1a0, 1, 1, 0x01 },
@@ -395,7 +394,7 @@ static struct regdesc tuner_init_mt2060[] = {
395 394
396/* Microtune MT2060 tuner init 395/* Microtune MT2060 tuner init
397 AF9013_TUNER_MT2060_2 = 147 */ 396 AF9013_TUNER_MT2060_2 = 147 */
398static struct regdesc tuner_init_mt2060_2[] = { 397static const struct af9013_reg_bit tuner_init_mt2060_2[] = {
399 { 0x9bd5, 0, 8, 0x01 }, 398 { 0x9bd5, 0, 8, 0x01 },
400 { 0x9bd6, 0, 8, 0x06 }, 399 { 0x9bd6, 0, 8, 0x06 },
401 { 0x9bbe, 0, 8, 0x01 }, 400 { 0x9bbe, 0, 8, 0x01 },
@@ -462,7 +461,7 @@ static struct regdesc tuner_init_mt2060_2[] = {
462 461
463/* MaxLinear MXL5003 tuner init 462/* MaxLinear MXL5003 tuner init
464 AF9013_TUNER_MXL5003D = 3 */ 463 AF9013_TUNER_MXL5003D = 3 */
465static struct regdesc tuner_init_mxl5003d[] = { 464static const struct af9013_reg_bit tuner_init_mxl5003d[] = {
466 { 0x9bd5, 0, 8, 0x01 }, 465 { 0x9bd5, 0, 8, 0x01 },
467 { 0x9bd6, 0, 8, 0x09 }, 466 { 0x9bd6, 0, 8, 0x09 },
468 { 0xd1a0, 1, 1, 0x01 }, 467 { 0xd1a0, 1, 1, 0x01 },
@@ -534,7 +533,7 @@ static struct regdesc tuner_init_mxl5003d[] = {
534 AF9013_TUNER_MXL5005D = 13 533 AF9013_TUNER_MXL5005D = 13
535 AF9013_TUNER_MXL5005R = 30 534 AF9013_TUNER_MXL5005R = 30
536 AF9013_TUNER_MXL5007T = 177 */ 535 AF9013_TUNER_MXL5007T = 177 */
537static struct regdesc tuner_init_mxl5005[] = { 536static const struct af9013_reg_bit tuner_init_mxl5005[] = {
538 { 0x9bd5, 0, 8, 0x01 }, 537 { 0x9bd5, 0, 8, 0x01 },
539 { 0x9bd6, 0, 8, 0x07 }, 538 { 0x9bd6, 0, 8, 0x07 },
540 { 0xd1a0, 1, 1, 0x01 }, 539 { 0xd1a0, 1, 1, 0x01 },
@@ -613,7 +612,7 @@ static struct regdesc tuner_init_mxl5005[] = {
613/* Quantek QT1010 tuner init 612/* Quantek QT1010 tuner init
614 AF9013_TUNER_QT1010 = 134 613 AF9013_TUNER_QT1010 = 134
615 AF9013_TUNER_QT1010A = 162 */ 614 AF9013_TUNER_QT1010A = 162 */
616static struct regdesc tuner_init_qt1010[] = { 615static const struct af9013_reg_bit tuner_init_qt1010[] = {
617 { 0x9bd5, 0, 8, 0x01 }, 616 { 0x9bd5, 0, 8, 0x01 },
618 { 0x9bd6, 0, 8, 0x09 }, 617 { 0x9bd6, 0, 8, 0x09 },
619 { 0xd1a0, 1, 1, 0x01 }, 618 { 0xd1a0, 1, 1, 0x01 },
@@ -690,7 +689,7 @@ static struct regdesc tuner_init_qt1010[] = {
690 689
691/* Freescale MC44S803 tuner init 690/* Freescale MC44S803 tuner init
692 AF9013_TUNER_MC44S803 = 133 */ 691 AF9013_TUNER_MC44S803 = 133 */
693static struct regdesc tuner_init_mc44s803[] = { 692static const struct af9013_reg_bit tuner_init_mc44s803[] = {
694 { 0x9bd5, 0, 8, 0x01 }, 693 { 0x9bd5, 0, 8, 0x01 },
695 { 0x9bd6, 0, 8, 0x06 }, 694 { 0x9bd6, 0, 8, 0x06 },
696 { 0xd1a0, 1, 1, 0x01 }, 695 { 0xd1a0, 1, 1, 0x01 },
@@ -772,7 +771,7 @@ static struct regdesc tuner_init_mc44s803[] = {
772 771
773/* unknown, probably for tin can tuner, tuner init 772/* unknown, probably for tin can tuner, tuner init
774 AF9013_TUNER_UNKNOWN = 140 */ 773 AF9013_TUNER_UNKNOWN = 140 */
775static struct regdesc tuner_init_unknown[] = { 774static const struct af9013_reg_bit tuner_init_unknown[] = {
776 { 0x9bd5, 0, 8, 0x01 }, 775 { 0x9bd5, 0, 8, 0x01 },
777 { 0x9bd6, 0, 8, 0x02 }, 776 { 0x9bd6, 0, 8, 0x02 },
778 { 0xd1a0, 1, 1, 0x01 }, 777 { 0xd1a0, 1, 1, 0x01 },
@@ -845,7 +844,7 @@ static struct regdesc tuner_init_unknown[] = {
845/* NXP TDA18271 & TDA18218 tuner init 844/* NXP TDA18271 & TDA18218 tuner init
846 AF9013_TUNER_TDA18271 = 156 845 AF9013_TUNER_TDA18271 = 156
847 AF9013_TUNER_TDA18218 = 179 */ 846 AF9013_TUNER_TDA18218 = 179 */
848static struct regdesc tuner_init_tda18271[] = { 847static const struct af9013_reg_bit tuner_init_tda18271[] = {
849 { 0x9bd5, 0, 8, 0x01 }, 848 { 0x9bd5, 0, 8, 0x01 },
850 { 0x9bd6, 0, 8, 0x04 }, 849 { 0x9bd6, 0, 8, 0x04 },
851 { 0xd1a0, 1, 1, 0x01 }, 850 { 0xd1a0, 1, 1, 0x01 },
@@ -920,4 +919,4 @@ static struct regdesc tuner_init_tda18271[] = {
920 { 0x9bee, 0, 1, 0x01 }, 919 { 0x9bee, 0, 1, 0x01 },
921}; 920};
922 921
923#endif /* _AF9013_PRIV_ */ 922#endif /* AF9013_PRIV_H */
diff --git a/drivers/media/dvb/frontends/atbm8830.c b/drivers/media/dvb/frontends/atbm8830.c
index 1539ea1f81ac..a2261ea2cf82 100644
--- a/drivers/media/dvb/frontends/atbm8830.c
+++ b/drivers/media/dvb/frontends/atbm8830.c
@@ -267,8 +267,7 @@ static void atbm8830_release(struct dvb_frontend *fe)
267 kfree(state); 267 kfree(state);
268} 268}
269 269
270static int atbm8830_set_fe(struct dvb_frontend *fe, 270static int atbm8830_set_fe(struct dvb_frontend *fe)
271 struct dvb_frontend_parameters *fe_params)
272{ 271{
273 struct atbm_state *priv = fe->demodulator_priv; 272 struct atbm_state *priv = fe->demodulator_priv;
274 int i; 273 int i;
@@ -279,7 +278,7 @@ static int atbm8830_set_fe(struct dvb_frontend *fe,
279 if (fe->ops.tuner_ops.set_params) { 278 if (fe->ops.tuner_ops.set_params) {
280 if (fe->ops.i2c_gate_ctrl) 279 if (fe->ops.i2c_gate_ctrl)
281 fe->ops.i2c_gate_ctrl(fe, 1); 280 fe->ops.i2c_gate_ctrl(fe, 1);
282 fe->ops.tuner_ops.set_params(fe, fe_params); 281 fe->ops.tuner_ops.set_params(fe);
283 if (fe->ops.i2c_gate_ctrl) 282 if (fe->ops.i2c_gate_ctrl)
284 fe->ops.i2c_gate_ctrl(fe, 0); 283 fe->ops.i2c_gate_ctrl(fe, 0);
285 } 284 }
@@ -298,31 +297,31 @@ static int atbm8830_set_fe(struct dvb_frontend *fe,
298 return 0; 297 return 0;
299} 298}
300 299
301static int atbm8830_get_fe(struct dvb_frontend *fe, 300static int atbm8830_get_fe(struct dvb_frontend *fe)
302 struct dvb_frontend_parameters *fe_params)
303{ 301{
302 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
304 dprintk("%s\n", __func__); 303 dprintk("%s\n", __func__);
305 304
306 /* TODO: get real readings from device */ 305 /* TODO: get real readings from device */
307 /* inversion status */ 306 /* inversion status */
308 fe_params->inversion = INVERSION_OFF; 307 c->inversion = INVERSION_OFF;
309 308
310 /* bandwidth */ 309 /* bandwidth */
311 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; 310 c->bandwidth_hz = 8000000;
312 311
313 fe_params->u.ofdm.code_rate_HP = FEC_AUTO; 312 c->code_rate_HP = FEC_AUTO;
314 fe_params->u.ofdm.code_rate_LP = FEC_AUTO; 313 c->code_rate_LP = FEC_AUTO;
315 314
316 fe_params->u.ofdm.constellation = QAM_AUTO; 315 c->modulation = QAM_AUTO;
317 316
318 /* transmission mode */ 317 /* transmission mode */
319 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO; 318 c->transmission_mode = TRANSMISSION_MODE_AUTO;
320 319
321 /* guard interval */ 320 /* guard interval */
322 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO; 321 c->guard_interval = GUARD_INTERVAL_AUTO;
323 322
324 /* hierarchy */ 323 /* hierarchy */
325 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE; 324 c->hierarchy = HIERARCHY_NONE;
326 325
327 return 0; 326 return 0;
328} 327}
@@ -429,9 +428,9 @@ static int atbm8830_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
429} 428}
430 429
431static struct dvb_frontend_ops atbm8830_ops = { 430static struct dvb_frontend_ops atbm8830_ops = {
431 .delsys = { SYS_DMBTH },
432 .info = { 432 .info = {
433 .name = "AltoBeam ATBM8830/8831 DMB-TH", 433 .name = "AltoBeam ATBM8830/8831 DMB-TH",
434 .type = FE_OFDM,
435 .frequency_min = 474000000, 434 .frequency_min = 474000000,
436 .frequency_max = 858000000, 435 .frequency_max = 858000000,
437 .frequency_stepsize = 10000, 436 .frequency_stepsize = 10000,
diff --git a/drivers/media/dvb/frontends/au8522_dig.c b/drivers/media/dvb/frontends/au8522_dig.c
index 1d572940e243..c688b95df486 100644
--- a/drivers/media/dvb/frontends/au8522_dig.c
+++ b/drivers/media/dvb/frontends/au8522_dig.c
@@ -576,19 +576,19 @@ static int au8522_enable_modulation(struct dvb_frontend *fe,
576} 576}
577 577
578/* Talk to the demod, set the FEC, GUARD, QAM settings etc */ 578/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
579static int au8522_set_frontend(struct dvb_frontend *fe, 579static int au8522_set_frontend(struct dvb_frontend *fe)
580 struct dvb_frontend_parameters *p)
581{ 580{
581 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
582 struct au8522_state *state = fe->demodulator_priv; 582 struct au8522_state *state = fe->demodulator_priv;
583 int ret = -EINVAL; 583 int ret = -EINVAL;
584 584
585 dprintk("%s(frequency=%d)\n", __func__, p->frequency); 585 dprintk("%s(frequency=%d)\n", __func__, c->frequency);
586 586
587 if ((state->current_frequency == p->frequency) && 587 if ((state->current_frequency == c->frequency) &&
588 (state->current_modulation == p->u.vsb.modulation)) 588 (state->current_modulation == c->modulation))
589 return 0; 589 return 0;
590 590
591 au8522_enable_modulation(fe, p->u.vsb.modulation); 591 au8522_enable_modulation(fe, c->modulation);
592 592
593 /* Allow the demod to settle */ 593 /* Allow the demod to settle */
594 msleep(100); 594 msleep(100);
@@ -596,7 +596,7 @@ static int au8522_set_frontend(struct dvb_frontend *fe,
596 if (fe->ops.tuner_ops.set_params) { 596 if (fe->ops.tuner_ops.set_params) {
597 if (fe->ops.i2c_gate_ctrl) 597 if (fe->ops.i2c_gate_ctrl)
598 fe->ops.i2c_gate_ctrl(fe, 1); 598 fe->ops.i2c_gate_ctrl(fe, 1);
599 ret = fe->ops.tuner_ops.set_params(fe, p); 599 ret = fe->ops.tuner_ops.set_params(fe);
600 if (fe->ops.i2c_gate_ctrl) 600 if (fe->ops.i2c_gate_ctrl)
601 fe->ops.i2c_gate_ctrl(fe, 0); 601 fe->ops.i2c_gate_ctrl(fe, 0);
602 } 602 }
@@ -604,7 +604,7 @@ static int au8522_set_frontend(struct dvb_frontend *fe,
604 if (ret < 0) 604 if (ret < 0)
605 return ret; 605 return ret;
606 606
607 state->current_frequency = p->frequency; 607 state->current_frequency = c->frequency;
608 608
609 return 0; 609 return 0;
610} 610}
@@ -862,7 +862,36 @@ static int au8522_read_snr(struct dvb_frontend *fe, u16 *snr)
862static int au8522_read_signal_strength(struct dvb_frontend *fe, 862static int au8522_read_signal_strength(struct dvb_frontend *fe,
863 u16 *signal_strength) 863 u16 *signal_strength)
864{ 864{
865 return au8522_read_snr(fe, signal_strength); 865 /* borrowed from lgdt330x.c
866 *
867 * Calculate strength from SNR up to 35dB
868 * Even though the SNR can go higher than 35dB,
869 * there is some comfort factor in having a range of
870 * strong signals that can show at 100%
871 */
872 u16 snr;
873 u32 tmp;
874 int ret = au8522_read_snr(fe, &snr);
875
876 *signal_strength = 0;
877
878 if (0 == ret) {
879 /* The following calculation method was chosen
880 * purely for the sake of code re-use from the
881 * other demod drivers that use this method */
882
883 /* Convert from SNR in dB * 10 to 8.24 fixed-point */
884 tmp = (snr * ((1 << 24) / 10));
885
886 /* Convert from 8.24 fixed-point to
887 * scale the range 0 - 35*2^24 into 0 - 65535*/
888 if (tmp >= 8960 * 0x10000)
889 *signal_strength = 0xffff;
890 else
891 *signal_strength = tmp / 8960;
892 }
893
894 return ret;
866} 895}
867 896
868static int au8522_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 897static int au8522_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
@@ -882,13 +911,13 @@ static int au8522_read_ber(struct dvb_frontend *fe, u32 *ber)
882 return au8522_read_ucblocks(fe, ber); 911 return au8522_read_ucblocks(fe, ber);
883} 912}
884 913
885static int au8522_get_frontend(struct dvb_frontend *fe, 914static int au8522_get_frontend(struct dvb_frontend *fe)
886 struct dvb_frontend_parameters *p)
887{ 915{
916 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
888 struct au8522_state *state = fe->demodulator_priv; 917 struct au8522_state *state = fe->demodulator_priv;
889 918
890 p->frequency = state->current_frequency; 919 c->frequency = state->current_frequency;
891 p->u.vsb.modulation = state->current_modulation; 920 c->modulation = state->current_modulation;
892 921
893 return 0; 922 return 0;
894} 923}
@@ -981,10 +1010,9 @@ error:
981EXPORT_SYMBOL(au8522_attach); 1010EXPORT_SYMBOL(au8522_attach);
982 1011
983static struct dvb_frontend_ops au8522_ops = { 1012static struct dvb_frontend_ops au8522_ops = {
984 1013 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
985 .info = { 1014 .info = {
986 .name = "Auvitek AU8522 QAM/8VSB Frontend", 1015 .name = "Auvitek AU8522 QAM/8VSB Frontend",
987 .type = FE_ATSC,
988 .frequency_min = 54000000, 1016 .frequency_min = 54000000,
989 .frequency_max = 858000000, 1017 .frequency_max = 858000000,
990 .frequency_stepsize = 62500, 1018 .frequency_stepsize = 62500,
diff --git a/drivers/media/dvb/frontends/bcm3510.c b/drivers/media/dvb/frontends/bcm3510.c
index 8aff5868a5e1..033cd7ad3ca2 100644
--- a/drivers/media/dvb/frontends/bcm3510.c
+++ b/drivers/media/dvb/frontends/bcm3510.c
@@ -479,16 +479,16 @@ static int bcm3510_set_freq(struct bcm3510_state* st,u32 freq)
479 return -EINVAL; 479 return -EINVAL;
480} 480}
481 481
482static int bcm3510_set_frontend(struct dvb_frontend* fe, 482static int bcm3510_set_frontend(struct dvb_frontend *fe)
483 struct dvb_frontend_parameters *p)
484{ 483{
484 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
485 struct bcm3510_state* st = fe->demodulator_priv; 485 struct bcm3510_state* st = fe->demodulator_priv;
486 struct bcm3510_hab_cmd_ext_acquire cmd; 486 struct bcm3510_hab_cmd_ext_acquire cmd;
487 struct bcm3510_hab_cmd_bert_control bert; 487 struct bcm3510_hab_cmd_bert_control bert;
488 int ret; 488 int ret;
489 489
490 memset(&cmd,0,sizeof(cmd)); 490 memset(&cmd,0,sizeof(cmd));
491 switch (p->u.vsb.modulation) { 491 switch (c->modulation) {
492 case QAM_256: 492 case QAM_256:
493 cmd.ACQUIRE0.MODE = 0x1; 493 cmd.ACQUIRE0.MODE = 0x1;
494 cmd.ACQUIRE1.SYM_RATE = 0x1; 494 cmd.ACQUIRE1.SYM_RATE = 0x1;
@@ -499,7 +499,8 @@ static int bcm3510_set_frontend(struct dvb_frontend* fe,
499 cmd.ACQUIRE1.SYM_RATE = 0x2; 499 cmd.ACQUIRE1.SYM_RATE = 0x2;
500 cmd.ACQUIRE1.IF_FREQ = 0x1; 500 cmd.ACQUIRE1.IF_FREQ = 0x1;
501 break; 501 break;
502/* case QAM_256: 502#if 0
503 case QAM_256:
503 cmd.ACQUIRE0.MODE = 0x3; 504 cmd.ACQUIRE0.MODE = 0x3;
504 break; 505 break;
505 case QAM_128: 506 case QAM_128:
@@ -513,7 +514,8 @@ static int bcm3510_set_frontend(struct dvb_frontend* fe,
513 break; 514 break;
514 case QAM_16: 515 case QAM_16:
515 cmd.ACQUIRE0.MODE = 0x7; 516 cmd.ACQUIRE0.MODE = 0x7;
516 break;*/ 517 break;
518#endif
517 case VSB_8: 519 case VSB_8:
518 cmd.ACQUIRE0.MODE = 0x8; 520 cmd.ACQUIRE0.MODE = 0x8;
519 cmd.ACQUIRE1.SYM_RATE = 0x0; 521 cmd.ACQUIRE1.SYM_RATE = 0x0;
@@ -552,7 +554,8 @@ static int bcm3510_set_frontend(struct dvb_frontend* fe,
552 554
553 bcm3510_bert_reset(st); 555 bcm3510_bert_reset(st);
554 556
555 if ((ret = bcm3510_set_freq(st,p->frequency)) < 0) 557 ret = bcm3510_set_freq(st, c->frequency);
558 if (ret < 0)
556 return ret; 559 return ret;
557 560
558 memset(&st->status1,0,sizeof(st->status1)); 561 memset(&st->status1,0,sizeof(st->status1));
@@ -819,10 +822,9 @@ error:
819EXPORT_SYMBOL(bcm3510_attach); 822EXPORT_SYMBOL(bcm3510_attach);
820 823
821static struct dvb_frontend_ops bcm3510_ops = { 824static struct dvb_frontend_ops bcm3510_ops = {
822 825 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
823 .info = { 826 .info = {
824 .name = "Broadcom BCM3510 VSB/QAM frontend", 827 .name = "Broadcom BCM3510 VSB/QAM frontend",
825 .type = FE_ATSC,
826 .frequency_min = 54000000, 828 .frequency_min = 54000000,
827 .frequency_max = 803000000, 829 .frequency_max = 803000000,
828 /* stepsize is just a guess */ 830 /* stepsize is just a guess */
diff --git a/drivers/media/dvb/frontends/bsbe1.h b/drivers/media/dvb/frontends/bsbe1.h
index 5e431ebd089b..53e4d0dbb745 100644
--- a/drivers/media/dvb/frontends/bsbe1.h
+++ b/drivers/media/dvb/frontends/bsbe1.h
@@ -69,18 +69,19 @@ static int alps_bsbe1_set_symbol_rate(struct dvb_frontend* fe, u32 srate, u32 ra
69 return 0; 69 return 0;
70} 70}
71 71
72static int alps_bsbe1_tuner_set_params(struct dvb_frontend* fe, struct dvb_frontend_parameters *params) 72static int alps_bsbe1_tuner_set_params(struct dvb_frontend *fe)
73{ 73{
74 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
74 int ret; 75 int ret;
75 u8 data[4]; 76 u8 data[4];
76 u32 div; 77 u32 div;
77 struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) }; 78 struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) };
78 struct i2c_adapter *i2c = fe->tuner_priv; 79 struct i2c_adapter *i2c = fe->tuner_priv;
79 80
80 if ((params->frequency < 950000) || (params->frequency > 2150000)) 81 if ((p->frequency < 950000) || (p->frequency > 2150000))
81 return -EINVAL; 82 return -EINVAL;
82 83
83 div = params->frequency / 1000; 84 div = p->frequency / 1000;
84 data[0] = (div >> 8) & 0x7f; 85 data[0] = (div >> 8) & 0x7f;
85 data[1] = div & 0xff; 86 data[1] = div & 0xff;
86 data[2] = 0x80 | ((div & 0x18000) >> 10) | 0x1; 87 data[2] = 0x80 | ((div & 0x18000) >> 10) | 0x1;
diff --git a/drivers/media/dvb/frontends/bsru6.h b/drivers/media/dvb/frontends/bsru6.h
index c480c839b302..c2a578e1314d 100644
--- a/drivers/media/dvb/frontends/bsru6.h
+++ b/drivers/media/dvb/frontends/bsru6.h
@@ -101,23 +101,24 @@ static int alps_bsru6_set_symbol_rate(struct dvb_frontend *fe, u32 srate, u32 ra
101 return 0; 101 return 0;
102} 102}
103 103
104static int alps_bsru6_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) 104static int alps_bsru6_tuner_set_params(struct dvb_frontend *fe)
105{ 105{
106 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
106 u8 buf[4]; 107 u8 buf[4];
107 u32 div; 108 u32 div;
108 struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = buf, .len = sizeof(buf) }; 109 struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = buf, .len = sizeof(buf) };
109 struct i2c_adapter *i2c = fe->tuner_priv; 110 struct i2c_adapter *i2c = fe->tuner_priv;
110 111
111 if ((params->frequency < 950000) || (params->frequency > 2150000)) 112 if ((p->frequency < 950000) || (p->frequency > 2150000))
112 return -EINVAL; 113 return -EINVAL;
113 114
114 div = (params->frequency + (125 - 1)) / 125; // round correctly 115 div = (p->frequency + (125 - 1)) / 125; /* round correctly */
115 buf[0] = (div >> 8) & 0x7f; 116 buf[0] = (div >> 8) & 0x7f;
116 buf[1] = div & 0xff; 117 buf[1] = div & 0xff;
117 buf[2] = 0x80 | ((div & 0x18000) >> 10) | 4; 118 buf[2] = 0x80 | ((div & 0x18000) >> 10) | 4;
118 buf[3] = 0xC4; 119 buf[3] = 0xC4;
119 120
120 if (params->frequency > 1530000) 121 if (p->frequency > 1530000)
121 buf[3] = 0xc0; 122 buf[3] = 0xc0;
122 123
123 if (fe->ops.i2c_gate_ctrl) 124 if (fe->ops.i2c_gate_ctrl)
diff --git a/drivers/media/dvb/frontends/cx22700.c b/drivers/media/dvb/frontends/cx22700.c
index 0142214b0133..f2a90f990ce3 100644
--- a/drivers/media/dvb/frontends/cx22700.c
+++ b/drivers/media/dvb/frontends/cx22700.c
@@ -121,7 +121,8 @@ static int cx22700_set_inversion (struct cx22700_state* state, int inversion)
121 } 121 }
122} 122}
123 123
124static int cx22700_set_tps (struct cx22700_state *state, struct dvb_ofdm_parameters *p) 124static int cx22700_set_tps(struct cx22700_state *state,
125 struct dtv_frontend_properties *p)
125{ 126{
126 static const u8 qam_tab [4] = { 0, 1, 0, 2 }; 127 static const u8 qam_tab [4] = { 0, 1, 0, 2 };
127 static const u8 fec_tab [6] = { 0, 1, 2, 0, 3, 4 }; 128 static const u8 fec_tab [6] = { 0, 1, 2, 0, 3, 4 };
@@ -146,25 +147,25 @@ static int cx22700_set_tps (struct cx22700_state *state, struct dvb_ofdm_paramet
146 p->transmission_mode != TRANSMISSION_MODE_8K) 147 p->transmission_mode != TRANSMISSION_MODE_8K)
147 return -EINVAL; 148 return -EINVAL;
148 149
149 if (p->constellation != QPSK && 150 if (p->modulation != QPSK &&
150 p->constellation != QAM_16 && 151 p->modulation != QAM_16 &&
151 p->constellation != QAM_64) 152 p->modulation != QAM_64)
152 return -EINVAL; 153 return -EINVAL;
153 154
154 if (p->hierarchy_information < HIERARCHY_NONE || 155 if (p->hierarchy < HIERARCHY_NONE ||
155 p->hierarchy_information > HIERARCHY_4) 156 p->hierarchy > HIERARCHY_4)
156 return -EINVAL; 157 return -EINVAL;
157 158
158 if (p->bandwidth < BANDWIDTH_8_MHZ || p->bandwidth > BANDWIDTH_6_MHZ) 159 if (p->bandwidth_hz > 8000000 || p->bandwidth_hz < 6000000)
159 return -EINVAL; 160 return -EINVAL;
160 161
161 if (p->bandwidth == BANDWIDTH_7_MHZ) 162 if (p->bandwidth_hz == 7000000)
162 cx22700_writereg (state, 0x09, cx22700_readreg (state, 0x09 | 0x10)); 163 cx22700_writereg (state, 0x09, cx22700_readreg (state, 0x09 | 0x10));
163 else 164 else
164 cx22700_writereg (state, 0x09, cx22700_readreg (state, 0x09 & ~0x10)); 165 cx22700_writereg (state, 0x09, cx22700_readreg (state, 0x09 & ~0x10));
165 166
166 val = qam_tab[p->constellation - QPSK]; 167 val = qam_tab[p->modulation - QPSK];
167 val |= p->hierarchy_information - HIERARCHY_NONE; 168 val |= p->hierarchy - HIERARCHY_NONE;
168 169
169 cx22700_writereg (state, 0x04, val); 170 cx22700_writereg (state, 0x04, val);
170 171
@@ -184,7 +185,8 @@ static int cx22700_set_tps (struct cx22700_state *state, struct dvb_ofdm_paramet
184 return 0; 185 return 0;
185} 186}
186 187
187static int cx22700_get_tps (struct cx22700_state* state, struct dvb_ofdm_parameters *p) 188static int cx22700_get_tps(struct cx22700_state *state,
189 struct dtv_frontend_properties *p)
188{ 190{
189 static const fe_modulation_t qam_tab [3] = { QPSK, QAM_16, QAM_64 }; 191 static const fe_modulation_t qam_tab [3] = { QPSK, QAM_16, QAM_64 };
190 static const fe_code_rate_t fec_tab [5] = { FEC_1_2, FEC_2_3, FEC_3_4, 192 static const fe_code_rate_t fec_tab [5] = { FEC_1_2, FEC_2_3, FEC_3_4,
@@ -199,14 +201,14 @@ static int cx22700_get_tps (struct cx22700_state* state, struct dvb_ofdm_paramet
199 val = cx22700_readreg (state, 0x01); 201 val = cx22700_readreg (state, 0x01);
200 202
201 if ((val & 0x7) > 4) 203 if ((val & 0x7) > 4)
202 p->hierarchy_information = HIERARCHY_AUTO; 204 p->hierarchy = HIERARCHY_AUTO;
203 else 205 else
204 p->hierarchy_information = HIERARCHY_NONE + (val & 0x7); 206 p->hierarchy = HIERARCHY_NONE + (val & 0x7);
205 207
206 if (((val >> 3) & 0x3) > 2) 208 if (((val >> 3) & 0x3) > 2)
207 p->constellation = QAM_AUTO; 209 p->modulation = QAM_AUTO;
208 else 210 else
209 p->constellation = qam_tab[(val >> 3) & 0x3]; 211 p->modulation = qam_tab[(val >> 3) & 0x3];
210 212
211 val = cx22700_readreg (state, 0x02); 213 val = cx22700_readreg (state, 0x02);
212 214
@@ -318,33 +320,35 @@ static int cx22700_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
318 return 0; 320 return 0;
319} 321}
320 322
321static int cx22700_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 323static int cx22700_set_frontend(struct dvb_frontend *fe)
322{ 324{
325 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
323 struct cx22700_state* state = fe->demodulator_priv; 326 struct cx22700_state* state = fe->demodulator_priv;
324 327
325 cx22700_writereg (state, 0x00, 0x02); /* XXX CHECKME: soft reset*/ 328 cx22700_writereg (state, 0x00, 0x02); /* XXX CHECKME: soft reset*/
326 cx22700_writereg (state, 0x00, 0x00); 329 cx22700_writereg (state, 0x00, 0x00);
327 330
328 if (fe->ops.tuner_ops.set_params) { 331 if (fe->ops.tuner_ops.set_params) {
329 fe->ops.tuner_ops.set_params(fe, p); 332 fe->ops.tuner_ops.set_params(fe);
330 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 333 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
331 } 334 }
332 335
333 cx22700_set_inversion (state, p->inversion); 336 cx22700_set_inversion(state, c->inversion);
334 cx22700_set_tps (state, &p->u.ofdm); 337 cx22700_set_tps(state, c);
335 cx22700_writereg (state, 0x37, 0x01); /* PAL loop filter off */ 338 cx22700_writereg (state, 0x37, 0x01); /* PAL loop filter off */
336 cx22700_writereg (state, 0x00, 0x01); /* restart acquire */ 339 cx22700_writereg (state, 0x00, 0x01); /* restart acquire */
337 340
338 return 0; 341 return 0;
339} 342}
340 343
341static int cx22700_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 344static int cx22700_get_frontend(struct dvb_frontend *fe)
342{ 345{
346 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
343 struct cx22700_state* state = fe->demodulator_priv; 347 struct cx22700_state* state = fe->demodulator_priv;
344 u8 reg09 = cx22700_readreg (state, 0x09); 348 u8 reg09 = cx22700_readreg (state, 0x09);
345 349
346 p->inversion = reg09 & 0x1 ? INVERSION_ON : INVERSION_OFF; 350 c->inversion = reg09 & 0x1 ? INVERSION_ON : INVERSION_OFF;
347 return cx22700_get_tps (state, &p->u.ofdm); 351 return cx22700_get_tps(state, c);
348} 352}
349 353
350static int cx22700_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) 354static int cx22700_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
@@ -401,10 +405,9 @@ error:
401} 405}
402 406
403static struct dvb_frontend_ops cx22700_ops = { 407static struct dvb_frontend_ops cx22700_ops = {
404 408 .delsys = { SYS_DVBT },
405 .info = { 409 .info = {
406 .name = "Conexant CX22700 DVB-T", 410 .name = "Conexant CX22700 DVB-T",
407 .type = FE_OFDM,
408 .frequency_min = 470000000, 411 .frequency_min = 470000000,
409 .frequency_max = 860000000, 412 .frequency_max = 860000000,
410 .frequency_stepsize = 166667, 413 .frequency_stepsize = 166667,
diff --git a/drivers/media/dvb/frontends/cx22702.c b/drivers/media/dvb/frontends/cx22702.c
index 3139558148ba..faba82485086 100644
--- a/drivers/media/dvb/frontends/cx22702.c
+++ b/drivers/media/dvb/frontends/cx22702.c
@@ -146,7 +146,7 @@ static int cx22702_set_inversion(struct cx22702_state *state, int inversion)
146 146
147/* Retrieve the demod settings */ 147/* Retrieve the demod settings */
148static int cx22702_get_tps(struct cx22702_state *state, 148static int cx22702_get_tps(struct cx22702_state *state,
149 struct dvb_ofdm_parameters *p) 149 struct dtv_frontend_properties *p)
150{ 150{
151 u8 val; 151 u8 val;
152 152
@@ -157,27 +157,27 @@ static int cx22702_get_tps(struct cx22702_state *state,
157 val = cx22702_readreg(state, 0x01); 157 val = cx22702_readreg(state, 0x01);
158 switch ((val & 0x18) >> 3) { 158 switch ((val & 0x18) >> 3) {
159 case 0: 159 case 0:
160 p->constellation = QPSK; 160 p->modulation = QPSK;
161 break; 161 break;
162 case 1: 162 case 1:
163 p->constellation = QAM_16; 163 p->modulation = QAM_16;
164 break; 164 break;
165 case 2: 165 case 2:
166 p->constellation = QAM_64; 166 p->modulation = QAM_64;
167 break; 167 break;
168 } 168 }
169 switch (val & 0x07) { 169 switch (val & 0x07) {
170 case 0: 170 case 0:
171 p->hierarchy_information = HIERARCHY_NONE; 171 p->hierarchy = HIERARCHY_NONE;
172 break; 172 break;
173 case 1: 173 case 1:
174 p->hierarchy_information = HIERARCHY_1; 174 p->hierarchy = HIERARCHY_1;
175 break; 175 break;
176 case 2: 176 case 2:
177 p->hierarchy_information = HIERARCHY_2; 177 p->hierarchy = HIERARCHY_2;
178 break; 178 break;
179 case 3: 179 case 3:
180 p->hierarchy_information = HIERARCHY_4; 180 p->hierarchy = HIERARCHY_4;
181 break; 181 break;
182 } 182 }
183 183
@@ -260,14 +260,14 @@ static int cx22702_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
260} 260}
261 261
262/* Talk to the demod, set the FEC, GUARD, QAM settings etc */ 262/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
263static int cx22702_set_tps(struct dvb_frontend *fe, 263static int cx22702_set_tps(struct dvb_frontend *fe)
264 struct dvb_frontend_parameters *p)
265{ 264{
265 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
266 u8 val; 266 u8 val;
267 struct cx22702_state *state = fe->demodulator_priv; 267 struct cx22702_state *state = fe->demodulator_priv;
268 268
269 if (fe->ops.tuner_ops.set_params) { 269 if (fe->ops.tuner_ops.set_params) {
270 fe->ops.tuner_ops.set_params(fe, p); 270 fe->ops.tuner_ops.set_params(fe);
271 if (fe->ops.i2c_gate_ctrl) 271 if (fe->ops.i2c_gate_ctrl)
272 fe->ops.i2c_gate_ctrl(fe, 0); 272 fe->ops.i2c_gate_ctrl(fe, 0);
273 } 273 }
@@ -277,14 +277,14 @@ static int cx22702_set_tps(struct dvb_frontend *fe,
277 277
278 /* set bandwidth */ 278 /* set bandwidth */
279 val = cx22702_readreg(state, 0x0C) & 0xcf; 279 val = cx22702_readreg(state, 0x0C) & 0xcf;
280 switch (p->u.ofdm.bandwidth) { 280 switch (p->bandwidth_hz) {
281 case BANDWIDTH_6_MHZ: 281 case 6000000:
282 val |= 0x20; 282 val |= 0x20;
283 break; 283 break;
284 case BANDWIDTH_7_MHZ: 284 case 7000000:
285 val |= 0x10; 285 val |= 0x10;
286 break; 286 break;
287 case BANDWIDTH_8_MHZ: 287 case 8000000:
288 break; 288 break;
289 default: 289 default:
290 dprintk("%s: invalid bandwidth\n", __func__); 290 dprintk("%s: invalid bandwidth\n", __func__);
@@ -292,15 +292,15 @@ static int cx22702_set_tps(struct dvb_frontend *fe,
292 } 292 }
293 cx22702_writereg(state, 0x0C, val); 293 cx22702_writereg(state, 0x0C, val);
294 294
295 p->u.ofdm.code_rate_LP = FEC_AUTO; /* temp hack as manual not working */ 295 p->code_rate_LP = FEC_AUTO; /* temp hack as manual not working */
296 296
297 /* use auto configuration? */ 297 /* use auto configuration? */
298 if ((p->u.ofdm.hierarchy_information == HIERARCHY_AUTO) || 298 if ((p->hierarchy == HIERARCHY_AUTO) ||
299 (p->u.ofdm.constellation == QAM_AUTO) || 299 (p->modulation == QAM_AUTO) ||
300 (p->u.ofdm.code_rate_HP == FEC_AUTO) || 300 (p->code_rate_HP == FEC_AUTO) ||
301 (p->u.ofdm.code_rate_LP == FEC_AUTO) || 301 (p->code_rate_LP == FEC_AUTO) ||
302 (p->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO) || 302 (p->guard_interval == GUARD_INTERVAL_AUTO) ||
303 (p->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO)) { 303 (p->transmission_mode == TRANSMISSION_MODE_AUTO)) {
304 304
305 /* TPS Source - use hardware driven values */ 305 /* TPS Source - use hardware driven values */
306 cx22702_writereg(state, 0x06, 0x10); 306 cx22702_writereg(state, 0x06, 0x10);
@@ -316,7 +316,7 @@ static int cx22702_set_tps(struct dvb_frontend *fe,
316 } 316 }
317 317
318 /* manually programmed values */ 318 /* manually programmed values */
319 switch (p->u.ofdm.constellation) { /* mask 0x18 */ 319 switch (p->modulation) { /* mask 0x18 */
320 case QPSK: 320 case QPSK:
321 val = 0x00; 321 val = 0x00;
322 break; 322 break;
@@ -327,10 +327,10 @@ static int cx22702_set_tps(struct dvb_frontend *fe,
327 val = 0x10; 327 val = 0x10;
328 break; 328 break;
329 default: 329 default:
330 dprintk("%s: invalid constellation\n", __func__); 330 dprintk("%s: invalid modulation\n", __func__);
331 return -EINVAL; 331 return -EINVAL;
332 } 332 }
333 switch (p->u.ofdm.hierarchy_information) { /* mask 0x07 */ 333 switch (p->hierarchy) { /* mask 0x07 */
334 case HIERARCHY_NONE: 334 case HIERARCHY_NONE:
335 break; 335 break;
336 case HIERARCHY_1: 336 case HIERARCHY_1:
@@ -348,7 +348,7 @@ static int cx22702_set_tps(struct dvb_frontend *fe,
348 } 348 }
349 cx22702_writereg(state, 0x06, val); 349 cx22702_writereg(state, 0x06, val);
350 350
351 switch (p->u.ofdm.code_rate_HP) { /* mask 0x38 */ 351 switch (p->code_rate_HP) { /* mask 0x38 */
352 case FEC_NONE: 352 case FEC_NONE:
353 case FEC_1_2: 353 case FEC_1_2:
354 val = 0x00; 354 val = 0x00;
@@ -369,7 +369,7 @@ static int cx22702_set_tps(struct dvb_frontend *fe,
369 dprintk("%s: invalid code_rate_HP\n", __func__); 369 dprintk("%s: invalid code_rate_HP\n", __func__);
370 return -EINVAL; 370 return -EINVAL;
371 } 371 }
372 switch (p->u.ofdm.code_rate_LP) { /* mask 0x07 */ 372 switch (p->code_rate_LP) { /* mask 0x07 */
373 case FEC_NONE: 373 case FEC_NONE:
374 case FEC_1_2: 374 case FEC_1_2:
375 break; 375 break;
@@ -391,7 +391,7 @@ static int cx22702_set_tps(struct dvb_frontend *fe,
391 } 391 }
392 cx22702_writereg(state, 0x07, val); 392 cx22702_writereg(state, 0x07, val);
393 393
394 switch (p->u.ofdm.guard_interval) { /* mask 0x0c */ 394 switch (p->guard_interval) { /* mask 0x0c */
395 case GUARD_INTERVAL_1_32: 395 case GUARD_INTERVAL_1_32:
396 val = 0x00; 396 val = 0x00;
397 break; 397 break;
@@ -408,7 +408,7 @@ static int cx22702_set_tps(struct dvb_frontend *fe,
408 dprintk("%s: invalid guard_interval\n", __func__); 408 dprintk("%s: invalid guard_interval\n", __func__);
409 return -EINVAL; 409 return -EINVAL;
410 } 410 }
411 switch (p->u.ofdm.transmission_mode) { /* mask 0x03 */ 411 switch (p->transmission_mode) { /* mask 0x03 */
412 case TRANSMISSION_MODE_2K: 412 case TRANSMISSION_MODE_2K:
413 break; 413 break;
414 case TRANSMISSION_MODE_8K: 414 case TRANSMISSION_MODE_8K:
@@ -546,15 +546,15 @@ static int cx22702_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
546 return 0; 546 return 0;
547} 547}
548 548
549static int cx22702_get_frontend(struct dvb_frontend *fe, 549static int cx22702_get_frontend(struct dvb_frontend *fe)
550 struct dvb_frontend_parameters *p)
551{ 550{
551 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
552 struct cx22702_state *state = fe->demodulator_priv; 552 struct cx22702_state *state = fe->demodulator_priv;
553 553
554 u8 reg0C = cx22702_readreg(state, 0x0C); 554 u8 reg0C = cx22702_readreg(state, 0x0C);
555 555
556 p->inversion = reg0C & 0x1 ? INVERSION_ON : INVERSION_OFF; 556 c->inversion = reg0C & 0x1 ? INVERSION_ON : INVERSION_OFF;
557 return cx22702_get_tps(state, &p->u.ofdm); 557 return cx22702_get_tps(state, c);
558} 558}
559 559
560static int cx22702_get_tune_settings(struct dvb_frontend *fe, 560static int cx22702_get_tune_settings(struct dvb_frontend *fe,
@@ -603,10 +603,9 @@ error:
603EXPORT_SYMBOL(cx22702_attach); 603EXPORT_SYMBOL(cx22702_attach);
604 604
605static const struct dvb_frontend_ops cx22702_ops = { 605static const struct dvb_frontend_ops cx22702_ops = {
606 606 .delsys = { SYS_DVBT },
607 .info = { 607 .info = {
608 .name = "Conexant CX22702 DVB-T", 608 .name = "Conexant CX22702 DVB-T",
609 .type = FE_OFDM,
610 .frequency_min = 177000000, 609 .frequency_min = 177000000,
611 .frequency_max = 858000000, 610 .frequency_max = 858000000,
612 .frequency_stepsize = 166666, 611 .frequency_stepsize = 166666,
diff --git a/drivers/media/dvb/frontends/cx24110.c b/drivers/media/dvb/frontends/cx24110.c
index bf9c999aa470..5101f10f2d7a 100644
--- a/drivers/media/dvb/frontends/cx24110.c
+++ b/drivers/media/dvb/frontends/cx24110.c
@@ -531,26 +531,27 @@ static int cx24110_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
531 return 0; 531 return 0;
532} 532}
533 533
534static int cx24110_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 534static int cx24110_set_frontend(struct dvb_frontend *fe)
535{ 535{
536 struct cx24110_state *state = fe->demodulator_priv; 536 struct cx24110_state *state = fe->demodulator_priv;
537 537 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
538 538
539 if (fe->ops.tuner_ops.set_params) { 539 if (fe->ops.tuner_ops.set_params) {
540 fe->ops.tuner_ops.set_params(fe, p); 540 fe->ops.tuner_ops.set_params(fe);
541 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 541 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
542 } 542 }
543 543
544 cx24110_set_inversion (state, p->inversion); 544 cx24110_set_inversion(state, p->inversion);
545 cx24110_set_fec (state, p->u.qpsk.fec_inner); 545 cx24110_set_fec(state, p->fec_inner);
546 cx24110_set_symbolrate (state, p->u.qpsk.symbol_rate); 546 cx24110_set_symbolrate(state, p->symbol_rate);
547 cx24110_writereg(state,0x04,0x05); /* start acquisition */ 547 cx24110_writereg(state,0x04,0x05); /* start acquisition */
548 548
549 return 0; 549 return 0;
550} 550}
551 551
552static int cx24110_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 552static int cx24110_get_frontend(struct dvb_frontend *fe)
553{ 553{
554 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
554 struct cx24110_state *state = fe->demodulator_priv; 555 struct cx24110_state *state = fe->demodulator_priv;
555 s32 afc; unsigned sclk; 556 s32 afc; unsigned sclk;
556 557
@@ -571,7 +572,7 @@ static int cx24110_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
571 p->frequency += afc; 572 p->frequency += afc;
572 p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ? 573 p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ?
573 INVERSION_ON : INVERSION_OFF; 574 INVERSION_ON : INVERSION_OFF;
574 p->u.qpsk.fec_inner = cx24110_get_fec (state); 575 p->fec_inner = cx24110_get_fec(state);
575 576
576 return 0; 577 return 0;
577} 578}
@@ -623,10 +624,9 @@ error:
623} 624}
624 625
625static struct dvb_frontend_ops cx24110_ops = { 626static struct dvb_frontend_ops cx24110_ops = {
626 627 .delsys = { SYS_DVBS },
627 .info = { 628 .info = {
628 .name = "Conexant CX24110 DVB-S", 629 .name = "Conexant CX24110 DVB-S",
629 .type = FE_QPSK,
630 .frequency_min = 950000, 630 .frequency_min = 950000,
631 .frequency_max = 2150000, 631 .frequency_max = 2150000,
632 .frequency_stepsize = 1011, /* kHz for QPSK frontends */ 632 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
diff --git a/drivers/media/dvb/frontends/cx24113.c b/drivers/media/dvb/frontends/cx24113.c
index c341d57d5e81..3883c3b31aef 100644
--- a/drivers/media/dvb/frontends/cx24113.c
+++ b/drivers/media/dvb/frontends/cx24113.c
@@ -476,21 +476,21 @@ static int cx24113_init(struct dvb_frontend *fe)
476 return ret; 476 return ret;
477} 477}
478 478
479static int cx24113_set_params(struct dvb_frontend *fe, 479static int cx24113_set_params(struct dvb_frontend *fe)
480 struct dvb_frontend_parameters *p)
481{ 480{
481 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
482 struct cx24113_state *state = fe->tuner_priv; 482 struct cx24113_state *state = fe->tuner_priv;
483 /* for a ROLL-OFF factor of 0.35, 0.2: 600, 0.25: 625 */ 483 /* for a ROLL-OFF factor of 0.35, 0.2: 600, 0.25: 625 */
484 u32 roll_off = 675; 484 u32 roll_off = 675;
485 u32 bw; 485 u32 bw;
486 486
487 bw = ((p->u.qpsk.symbol_rate/100) * roll_off) / 1000; 487 bw = ((c->symbol_rate/100) * roll_off) / 1000;
488 bw += (10000000/100) + 5; 488 bw += (10000000/100) + 5;
489 bw /= 10; 489 bw /= 10;
490 bw += 1000; 490 bw += 1000;
491 cx24113_set_bandwidth(state, bw); 491 cx24113_set_bandwidth(state, bw);
492 492
493 cx24113_set_frequency(state, p->frequency); 493 cx24113_set_frequency(state, c->frequency);
494 msleep(5); 494 msleep(5);
495 return cx24113_get_status(fe, &bw); 495 return cx24113_get_status(fe, &bw);
496} 496}
@@ -547,11 +547,9 @@ static const struct dvb_tuner_ops cx24113_tuner_ops = {
547 .release = cx24113_release, 547 .release = cx24113_release,
548 548
549 .init = cx24113_init, 549 .init = cx24113_init,
550 .sleep = NULL,
551 550
552 .set_params = cx24113_set_params, 551 .set_params = cx24113_set_params,
553 .get_frequency = cx24113_get_frequency, 552 .get_frequency = cx24113_get_frequency,
554 .get_bandwidth = NULL,
555 .get_status = cx24113_get_status, 553 .get_status = cx24113_get_status,
556}; 554};
557 555
diff --git a/drivers/media/dvb/frontends/cx24116.c b/drivers/media/dvb/frontends/cx24116.c
index ccd05255d527..b48879186537 100644
--- a/drivers/media/dvb/frontends/cx24116.c
+++ b/drivers/media/dvb/frontends/cx24116.c
@@ -1212,25 +1212,10 @@ static int cx24116_sleep(struct dvb_frontend *fe)
1212 return 0; 1212 return 0;
1213} 1213}
1214 1214
1215static int cx24116_set_property(struct dvb_frontend *fe,
1216 struct dtv_property *tvp)
1217{
1218 dprintk("%s(..)\n", __func__);
1219 return 0;
1220}
1221
1222static int cx24116_get_property(struct dvb_frontend *fe,
1223 struct dtv_property *tvp)
1224{
1225 dprintk("%s(..)\n", __func__);
1226 return 0;
1227}
1228
1229/* dvb-core told us to tune, the tv property cache will be complete, 1215/* dvb-core told us to tune, the tv property cache will be complete,
1230 * it's safe for is to pull values and use them for tuning purposes. 1216 * it's safe for is to pull values and use them for tuning purposes.
1231 */ 1217 */
1232static int cx24116_set_frontend(struct dvb_frontend *fe, 1218static int cx24116_set_frontend(struct dvb_frontend *fe)
1233 struct dvb_frontend_parameters *p)
1234{ 1219{
1235 struct cx24116_state *state = fe->demodulator_priv; 1220 struct cx24116_state *state = fe->demodulator_priv;
1236 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1221 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
@@ -1455,12 +1440,20 @@ tuned: /* Set/Reset B/W */
1455 return cx24116_cmd_execute(fe, &cmd); 1440 return cx24116_cmd_execute(fe, &cmd);
1456} 1441}
1457 1442
1458static int cx24116_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *params, 1443static int cx24116_tune(struct dvb_frontend *fe, bool re_tune,
1459 unsigned int mode_flags, unsigned int *delay, fe_status_t *status) 1444 unsigned int mode_flags, unsigned int *delay, fe_status_t *status)
1460{ 1445{
1446 /*
1447 * It is safe to discard "params" here, as the DVB core will sync
1448 * fe->dtv_property_cache with fepriv->parameters_in, where the
1449 * DVBv3 params are stored. The only practical usage for it indicate
1450 * that re-tuning is needed, e. g. (fepriv->state & FESTATE_RETUNE) is
1451 * true.
1452 */
1453
1461 *delay = HZ / 5; 1454 *delay = HZ / 5;
1462 if (params) { 1455 if (re_tune) {
1463 int ret = cx24116_set_frontend(fe, params); 1456 int ret = cx24116_set_frontend(fe);
1464 if (ret) 1457 if (ret)
1465 return ret; 1458 return ret;
1466 } 1459 }
@@ -1473,10 +1466,9 @@ static int cx24116_get_algo(struct dvb_frontend *fe)
1473} 1466}
1474 1467
1475static struct dvb_frontend_ops cx24116_ops = { 1468static struct dvb_frontend_ops cx24116_ops = {
1476 1469 .delsys = { SYS_DVBS, SYS_DVBS2 },
1477 .info = { 1470 .info = {
1478 .name = "Conexant CX24116/CX24118", 1471 .name = "Conexant CX24116/CX24118",
1479 .type = FE_QPSK,
1480 .frequency_min = 950000, 1472 .frequency_min = 950000,
1481 .frequency_max = 2150000, 1473 .frequency_max = 2150000,
1482 .frequency_stepsize = 1011, /* kHz for QPSK frontends */ 1474 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
@@ -1507,8 +1499,6 @@ static struct dvb_frontend_ops cx24116_ops = {
1507 .get_frontend_algo = cx24116_get_algo, 1499 .get_frontend_algo = cx24116_get_algo,
1508 .tune = cx24116_tune, 1500 .tune = cx24116_tune,
1509 1501
1510 .set_property = cx24116_set_property,
1511 .get_property = cx24116_get_property,
1512 .set_frontend = cx24116_set_frontend, 1502 .set_frontend = cx24116_set_frontend,
1513}; 1503};
1514 1504
diff --git a/drivers/media/dvb/frontends/cx24123.c b/drivers/media/dvb/frontends/cx24123.c
index b1dd8acc607a..7e28b4ee7d4f 100644
--- a/drivers/media/dvb/frontends/cx24123.c
+++ b/drivers/media/dvb/frontends/cx24123.c
@@ -526,9 +526,9 @@ static int cx24123_set_symbolrate(struct cx24123_state *state, u32 srate)
526 * to be configured and the correct band selected. 526 * to be configured and the correct band selected.
527 * Calculate those values. 527 * Calculate those values.
528 */ 528 */
529static int cx24123_pll_calculate(struct dvb_frontend *fe, 529static int cx24123_pll_calculate(struct dvb_frontend *fe)
530 struct dvb_frontend_parameters *p)
531{ 530{
531 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
532 struct cx24123_state *state = fe->demodulator_priv; 532 struct cx24123_state *state = fe->demodulator_priv;
533 u32 ndiv = 0, adiv = 0, vco_div = 0; 533 u32 ndiv = 0, adiv = 0, vco_div = 0;
534 int i = 0; 534 int i = 0;
@@ -548,8 +548,8 @@ static int cx24123_pll_calculate(struct dvb_frontend *fe,
548 * FILTUNE programming bits */ 548 * FILTUNE programming bits */
549 for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++) { 549 for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++) {
550 agcv = &cx24123_AGC_vals[i]; 550 agcv = &cx24123_AGC_vals[i];
551 if ((agcv->symbolrate_low <= p->u.qpsk.symbol_rate) && 551 if ((agcv->symbolrate_low <= p->symbol_rate) &&
552 (agcv->symbolrate_high >= p->u.qpsk.symbol_rate)) { 552 (agcv->symbolrate_high >= p->symbol_rate)) {
553 state->VCAarg = agcv->VCAprogdata; 553 state->VCAarg = agcv->VCAprogdata;
554 state->VGAarg = agcv->VGAprogdata; 554 state->VGAarg = agcv->VGAprogdata;
555 state->FILTune = agcv->FILTune; 555 state->FILTune = agcv->FILTune;
@@ -601,8 +601,7 @@ static int cx24123_pll_calculate(struct dvb_frontend *fe,
601 * Tuner cx24109 is written through a dedicated 3wire interface 601 * Tuner cx24109 is written through a dedicated 3wire interface
602 * on the demod chip. 602 * on the demod chip.
603 */ 603 */
604static int cx24123_pll_writereg(struct dvb_frontend *fe, 604static int cx24123_pll_writereg(struct dvb_frontend *fe, u32 data)
605 struct dvb_frontend_parameters *p, u32 data)
606{ 605{
607 struct cx24123_state *state = fe->demodulator_priv; 606 struct cx24123_state *state = fe->demodulator_priv;
608 unsigned long timeout; 607 unsigned long timeout;
@@ -659,26 +658,26 @@ static int cx24123_pll_writereg(struct dvb_frontend *fe,
659 return 0; 658 return 0;
660} 659}
661 660
662static int cx24123_pll_tune(struct dvb_frontend *fe, 661static int cx24123_pll_tune(struct dvb_frontend *fe)
663 struct dvb_frontend_parameters *p)
664{ 662{
663 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
665 struct cx24123_state *state = fe->demodulator_priv; 664 struct cx24123_state *state = fe->demodulator_priv;
666 u8 val; 665 u8 val;
667 666
668 dprintk("frequency=%i\n", p->frequency); 667 dprintk("frequency=%i\n", p->frequency);
669 668
670 if (cx24123_pll_calculate(fe, p) != 0) { 669 if (cx24123_pll_calculate(fe) != 0) {
671 err("%s: cx24123_pll_calcutate failed\n", __func__); 670 err("%s: cx24123_pll_calcutate failed\n", __func__);
672 return -EINVAL; 671 return -EINVAL;
673 } 672 }
674 673
675 /* Write the new VCO/VGA */ 674 /* Write the new VCO/VGA */
676 cx24123_pll_writereg(fe, p, state->VCAarg); 675 cx24123_pll_writereg(fe, state->VCAarg);
677 cx24123_pll_writereg(fe, p, state->VGAarg); 676 cx24123_pll_writereg(fe, state->VGAarg);
678 677
679 /* Write the new bandselect and pll args */ 678 /* Write the new bandselect and pll args */
680 cx24123_pll_writereg(fe, p, state->bandselectarg); 679 cx24123_pll_writereg(fe, state->bandselectarg);
681 cx24123_pll_writereg(fe, p, state->pllarg); 680 cx24123_pll_writereg(fe, state->pllarg);
682 681
683 /* set the FILTUNE voltage */ 682 /* set the FILTUNE voltage */
684 val = cx24123_readreg(state, 0x28) & ~0x3; 683 val = cx24123_readreg(state, 0x28) & ~0x3;
@@ -925,10 +924,10 @@ static int cx24123_read_snr(struct dvb_frontend *fe, u16 *snr)
925 return 0; 924 return 0;
926} 925}
927 926
928static int cx24123_set_frontend(struct dvb_frontend *fe, 927static int cx24123_set_frontend(struct dvb_frontend *fe)
929 struct dvb_frontend_parameters *p)
930{ 928{
931 struct cx24123_state *state = fe->demodulator_priv; 929 struct cx24123_state *state = fe->demodulator_priv;
930 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
932 931
933 dprintk("\n"); 932 dprintk("\n");
934 933
@@ -936,16 +935,16 @@ static int cx24123_set_frontend(struct dvb_frontend *fe,
936 state->config->set_ts_params(fe, 0); 935 state->config->set_ts_params(fe, 0);
937 936
938 state->currentfreq = p->frequency; 937 state->currentfreq = p->frequency;
939 state->currentsymbolrate = p->u.qpsk.symbol_rate; 938 state->currentsymbolrate = p->symbol_rate;
940 939
941 cx24123_set_inversion(state, p->inversion); 940 cx24123_set_inversion(state, p->inversion);
942 cx24123_set_fec(state, p->u.qpsk.fec_inner); 941 cx24123_set_fec(state, p->fec_inner);
943 cx24123_set_symbolrate(state, p->u.qpsk.symbol_rate); 942 cx24123_set_symbolrate(state, p->symbol_rate);
944 943
945 if (!state->config->dont_use_pll) 944 if (!state->config->dont_use_pll)
946 cx24123_pll_tune(fe, p); 945 cx24123_pll_tune(fe);
947 else if (fe->ops.tuner_ops.set_params) 946 else if (fe->ops.tuner_ops.set_params)
948 fe->ops.tuner_ops.set_params(fe, p); 947 fe->ops.tuner_ops.set_params(fe);
949 else 948 else
950 err("it seems I don't have a tuner..."); 949 err("it seems I don't have a tuner...");
951 950
@@ -960,9 +959,9 @@ static int cx24123_set_frontend(struct dvb_frontend *fe,
960 return 0; 959 return 0;
961} 960}
962 961
963static int cx24123_get_frontend(struct dvb_frontend *fe, 962static int cx24123_get_frontend(struct dvb_frontend *fe)
964 struct dvb_frontend_parameters *p)
965{ 963{
964 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
966 struct cx24123_state *state = fe->demodulator_priv; 965 struct cx24123_state *state = fe->demodulator_priv;
967 966
968 dprintk("\n"); 967 dprintk("\n");
@@ -971,12 +970,12 @@ static int cx24123_get_frontend(struct dvb_frontend *fe,
971 err("%s: Failed to get inversion status\n", __func__); 970 err("%s: Failed to get inversion status\n", __func__);
972 return -EREMOTEIO; 971 return -EREMOTEIO;
973 } 972 }
974 if (cx24123_get_fec(state, &p->u.qpsk.fec_inner) != 0) { 973 if (cx24123_get_fec(state, &p->fec_inner) != 0) {
975 err("%s: Failed to get fec status\n", __func__); 974 err("%s: Failed to get fec status\n", __func__);
976 return -EREMOTEIO; 975 return -EREMOTEIO;
977 } 976 }
978 p->frequency = state->currentfreq; 977 p->frequency = state->currentfreq;
979 p->u.qpsk.symbol_rate = state->currentsymbolrate; 978 p->symbol_rate = state->currentsymbolrate;
980 979
981 return 0; 980 return 0;
982} 981}
@@ -1007,15 +1006,15 @@ static int cx24123_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
1007} 1006}
1008 1007
1009static int cx24123_tune(struct dvb_frontend *fe, 1008static int cx24123_tune(struct dvb_frontend *fe,
1010 struct dvb_frontend_parameters *params, 1009 bool re_tune,
1011 unsigned int mode_flags, 1010 unsigned int mode_flags,
1012 unsigned int *delay, 1011 unsigned int *delay,
1013 fe_status_t *status) 1012 fe_status_t *status)
1014{ 1013{
1015 int retval = 0; 1014 int retval = 0;
1016 1015
1017 if (params != NULL) 1016 if (re_tune)
1018 retval = cx24123_set_frontend(fe, params); 1017 retval = cx24123_set_frontend(fe);
1019 1018
1020 if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) 1019 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
1021 cx24123_read_status(fe, status); 1020 cx24123_read_status(fe, status);
@@ -1126,10 +1125,9 @@ error:
1126EXPORT_SYMBOL(cx24123_attach); 1125EXPORT_SYMBOL(cx24123_attach);
1127 1126
1128static struct dvb_frontend_ops cx24123_ops = { 1127static struct dvb_frontend_ops cx24123_ops = {
1129 1128 .delsys = { SYS_DVBS },
1130 .info = { 1129 .info = {
1131 .name = "Conexant CX24123/CX24109", 1130 .name = "Conexant CX24123/CX24109",
1132 .type = FE_QPSK,
1133 .frequency_min = 950000, 1131 .frequency_min = 950000,
1134 .frequency_max = 2150000, 1132 .frequency_max = 2150000,
1135 .frequency_stepsize = 1011, /* kHz for QPSK frontends */ 1133 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
diff --git a/drivers/media/dvb/frontends/cxd2820r.h b/drivers/media/dvb/frontends/cxd2820r.h
index 03cab7b547fb..cf0f546aa1d1 100644
--- a/drivers/media/dvb/frontends/cxd2820r.h
+++ b/drivers/media/dvb/frontends/cxd2820r.h
@@ -63,19 +63,6 @@ struct cxd2820r_config {
63 */ 63 */
64 bool spec_inv; 64 bool spec_inv;
65 65
66 /* IFs for all used modes.
67 * Default: none, must set
68 * Values: <kHz>
69 */
70 u16 if_dvbt_6;
71 u16 if_dvbt_7;
72 u16 if_dvbt_8;
73 u16 if_dvbt2_5;
74 u16 if_dvbt2_6;
75 u16 if_dvbt2_7;
76 u16 if_dvbt2_8;
77 u16 if_dvbc;
78
79 /* GPIOs for all used modes. 66 /* GPIOs for all used modes.
80 * Default: none, disabled 67 * Default: none, disabled
81 * Values: <see above> 68 * Values: <see above>
diff --git a/drivers/media/dvb/frontends/cxd2820r_c.c b/drivers/media/dvb/frontends/cxd2820r_c.c
index b85f5011e344..945404991529 100644
--- a/drivers/media/dvb/frontends/cxd2820r_c.c
+++ b/drivers/media/dvb/frontends/cxd2820r_c.c
@@ -21,13 +21,13 @@
21 21
22#include "cxd2820r_priv.h" 22#include "cxd2820r_priv.h"
23 23
24int cxd2820r_set_frontend_c(struct dvb_frontend *fe, 24int cxd2820r_set_frontend_c(struct dvb_frontend *fe)
25 struct dvb_frontend_parameters *params)
26{ 25{
27 struct cxd2820r_priv *priv = fe->demodulator_priv; 26 struct cxd2820r_priv *priv = fe->demodulator_priv;
28 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 27 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
29 int ret, i; 28 int ret, i;
30 u8 buf[2]; 29 u8 buf[2];
30 u32 if_freq;
31 u16 if_ctl; 31 u16 if_ctl;
32 u64 num; 32 u64 num;
33 struct reg_val_mask tab[] = { 33 struct reg_val_mask tab[] = {
@@ -56,9 +56,9 @@ int cxd2820r_set_frontend_c(struct dvb_frontend *fe,
56 56
57 /* program tuner */ 57 /* program tuner */
58 if (fe->ops.tuner_ops.set_params) 58 if (fe->ops.tuner_ops.set_params)
59 fe->ops.tuner_ops.set_params(fe, params); 59 fe->ops.tuner_ops.set_params(fe);
60 60
61 if (priv->delivery_system != SYS_DVBC_ANNEX_AC) { 61 if (priv->delivery_system != SYS_DVBC_ANNEX_A) {
62 for (i = 0; i < ARRAY_SIZE(tab); i++) { 62 for (i = 0; i < ARRAY_SIZE(tab); i++) {
63 ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, 63 ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
64 tab[i].val, tab[i].mask); 64 tab[i].val, tab[i].mask);
@@ -67,10 +67,20 @@ int cxd2820r_set_frontend_c(struct dvb_frontend *fe,
67 } 67 }
68 } 68 }
69 69
70 priv->delivery_system = SYS_DVBC_ANNEX_AC; 70 priv->delivery_system = SYS_DVBC_ANNEX_A;
71 priv->ber_running = 0; /* tune stops BER counter */ 71 priv->ber_running = 0; /* tune stops BER counter */
72 72
73 num = priv->cfg.if_dvbc; 73 /* program IF frequency */
74 if (fe->ops.tuner_ops.get_if_frequency) {
75 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
76 if (ret)
77 goto error;
78 } else
79 if_freq = 0;
80
81 dbg("%s: if_freq=%d", __func__, if_freq);
82
83 num = if_freq / 1000; /* Hz => kHz */
74 num *= 0x4000; 84 num *= 0x4000;
75 if_ctl = cxd2820r_div_u64_round_closest(num, 41000); 85 if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
76 buf[0] = (if_ctl >> 8) & 0x3f; 86 buf[0] = (if_ctl >> 8) & 0x3f;
@@ -94,8 +104,7 @@ error:
94 return ret; 104 return ret;
95} 105}
96 106
97int cxd2820r_get_frontend_c(struct dvb_frontend *fe, 107int cxd2820r_get_frontend_c(struct dvb_frontend *fe)
98 struct dvb_frontend_parameters *p)
99{ 108{
100 struct cxd2820r_priv *priv = fe->demodulator_priv; 109 struct cxd2820r_priv *priv = fe->demodulator_priv;
101 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 110 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
diff --git a/drivers/media/dvb/frontends/cxd2820r_core.c b/drivers/media/dvb/frontends/cxd2820r_core.c
index 036480f967b7..93e1b12e7907 100644
--- a/drivers/media/dvb/frontends/cxd2820r_core.c
+++ b/drivers/media/dvb/frontends/cxd2820r_core.c
@@ -240,422 +240,234 @@ error:
240 return ret; 240 return ret;
241} 241}
242 242
243/* lock FE */
244static int cxd2820r_lock(struct cxd2820r_priv *priv, int active_fe)
245{
246 int ret = 0;
247 dbg("%s: active_fe=%d", __func__, active_fe);
248
249 mutex_lock(&priv->fe_lock);
250
251 /* -1=NONE, 0=DVB-T/T2, 1=DVB-C */
252 if (priv->active_fe == active_fe)
253 ;
254 else if (priv->active_fe == -1)
255 priv->active_fe = active_fe;
256 else
257 ret = -EBUSY;
258
259 mutex_unlock(&priv->fe_lock);
260
261 return ret;
262}
263
264/* unlock FE */
265static void cxd2820r_unlock(struct cxd2820r_priv *priv, int active_fe)
266{
267 dbg("%s: active_fe=%d", __func__, active_fe);
268
269 mutex_lock(&priv->fe_lock);
270
271 /* -1=NONE, 0=DVB-T/T2, 1=DVB-C */
272 if (priv->active_fe == active_fe)
273 priv->active_fe = -1;
274
275 mutex_unlock(&priv->fe_lock);
276
277 return;
278}
279
280/* 64 bit div with round closest, like DIV_ROUND_CLOSEST but 64 bit */ 243/* 64 bit div with round closest, like DIV_ROUND_CLOSEST but 64 bit */
281u32 cxd2820r_div_u64_round_closest(u64 dividend, u32 divisor) 244u32 cxd2820r_div_u64_round_closest(u64 dividend, u32 divisor)
282{ 245{
283 return div_u64(dividend + (divisor / 2), divisor); 246 return div_u64(dividend + (divisor / 2), divisor);
284} 247}
285 248
286static int cxd2820r_set_frontend(struct dvb_frontend *fe, 249static int cxd2820r_set_frontend(struct dvb_frontend *fe)
287 struct dvb_frontend_parameters *p)
288{ 250{
289 struct cxd2820r_priv *priv = fe->demodulator_priv;
290 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 251 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
291 int ret; 252 int ret;
292 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
293 253
294 if (fe->ops.info.type == FE_OFDM) { 254 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
295 /* DVB-T/T2 */ 255 switch (c->delivery_system) {
296 ret = cxd2820r_lock(priv, 0); 256 case SYS_DVBT:
297 if (ret) 257 ret = cxd2820r_init_t(fe);
298 return ret; 258 if (ret < 0)
299 259 goto err;
300 switch (priv->delivery_system) { 260 ret = cxd2820r_set_frontend_t(fe);
301 case SYS_UNDEFINED: 261 if (ret < 0)
302 if (c->delivery_system == SYS_DVBT) { 262 goto err;
303 /* SLEEP => DVB-T */ 263 break;
304 ret = cxd2820r_set_frontend_t(fe, p); 264 case SYS_DVBT2:
305 } else { 265 ret = cxd2820r_init_t(fe);
306 /* SLEEP => DVB-T2 */ 266 if (ret < 0)
307 ret = cxd2820r_set_frontend_t2(fe, p); 267 goto err;
308 } 268 ret = cxd2820r_set_frontend_t2(fe);
309 break; 269 if (ret < 0)
310 case SYS_DVBT: 270 goto err;
311 if (c->delivery_system == SYS_DVBT) { 271 break;
312 /* DVB-T => DVB-T */ 272 case SYS_DVBC_ANNEX_A:
313 ret = cxd2820r_set_frontend_t(fe, p); 273 ret = cxd2820r_init_c(fe);
314 } else if (c->delivery_system == SYS_DVBT2) { 274 if (ret < 0)
315 /* DVB-T => DVB-T2 */ 275 goto err;
316 ret = cxd2820r_sleep_t(fe); 276 ret = cxd2820r_set_frontend_c(fe);
317 if (ret) 277 if (ret < 0)
318 break; 278 goto err;
319 ret = cxd2820r_set_frontend_t2(fe, p); 279 break;
320 } 280 default:
321 break; 281 dbg("%s: error state=%d", __func__, fe->dtv_property_cache.delivery_system);
322 case SYS_DVBT2: 282 ret = -EINVAL;
323 if (c->delivery_system == SYS_DVBT2) { 283 break;
324 /* DVB-T2 => DVB-T2 */
325 ret = cxd2820r_set_frontend_t2(fe, p);
326 } else if (c->delivery_system == SYS_DVBT) {
327 /* DVB-T2 => DVB-T */
328 ret = cxd2820r_sleep_t2(fe);
329 if (ret)
330 break;
331 ret = cxd2820r_set_frontend_t(fe, p);
332 }
333 break;
334 default:
335 dbg("%s: error state=%d", __func__,
336 priv->delivery_system);
337 ret = -EINVAL;
338 }
339 } else {
340 /* DVB-C */
341 ret = cxd2820r_lock(priv, 1);
342 if (ret)
343 return ret;
344
345 ret = cxd2820r_set_frontend_c(fe, p);
346 } 284 }
347 285err:
348 return ret; 286 return ret;
349} 287}
350
351static int cxd2820r_read_status(struct dvb_frontend *fe, fe_status_t *status) 288static int cxd2820r_read_status(struct dvb_frontend *fe, fe_status_t *status)
352{ 289{
353 struct cxd2820r_priv *priv = fe->demodulator_priv;
354 int ret; 290 int ret;
355 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
356
357 if (fe->ops.info.type == FE_OFDM) {
358 /* DVB-T/T2 */
359 ret = cxd2820r_lock(priv, 0);
360 if (ret)
361 return ret;
362
363 switch (fe->dtv_property_cache.delivery_system) {
364 case SYS_DVBT:
365 ret = cxd2820r_read_status_t(fe, status);
366 break;
367 case SYS_DVBT2:
368 ret = cxd2820r_read_status_t2(fe, status);
369 break;
370 default:
371 ret = -EINVAL;
372 }
373 } else {
374 /* DVB-C */
375 ret = cxd2820r_lock(priv, 1);
376 if (ret)
377 return ret;
378 291
292 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
293 switch (fe->dtv_property_cache.delivery_system) {
294 case SYS_DVBT:
295 ret = cxd2820r_read_status_t(fe, status);
296 break;
297 case SYS_DVBT2:
298 ret = cxd2820r_read_status_t2(fe, status);
299 break;
300 case SYS_DVBC_ANNEX_A:
379 ret = cxd2820r_read_status_c(fe, status); 301 ret = cxd2820r_read_status_c(fe, status);
302 break;
303 default:
304 ret = -EINVAL;
305 break;
380 } 306 }
381
382 return ret; 307 return ret;
383} 308}
384 309
385static int cxd2820r_get_frontend(struct dvb_frontend *fe, 310static int cxd2820r_get_frontend(struct dvb_frontend *fe)
386 struct dvb_frontend_parameters *p)
387{ 311{
388 struct cxd2820r_priv *priv = fe->demodulator_priv;
389 int ret; 312 int ret;
390 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
391 313
392 if (fe->ops.info.type == FE_OFDM) { 314 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
393 /* DVB-T/T2 */ 315 switch (fe->dtv_property_cache.delivery_system) {
394 ret = cxd2820r_lock(priv, 0); 316 case SYS_DVBT:
395 if (ret) 317 ret = cxd2820r_get_frontend_t(fe);
396 return ret; 318 break;
397 319 case SYS_DVBT2:
398 switch (fe->dtv_property_cache.delivery_system) { 320 ret = cxd2820r_get_frontend_t2(fe);
399 case SYS_DVBT: 321 break;
400 ret = cxd2820r_get_frontend_t(fe, p); 322 case SYS_DVBC_ANNEX_A:
401 break; 323 ret = cxd2820r_get_frontend_c(fe);
402 case SYS_DVBT2: 324 break;
403 ret = cxd2820r_get_frontend_t2(fe, p); 325 default:
404 break; 326 ret = -EINVAL;
405 default: 327 break;
406 ret = -EINVAL;
407 }
408 } else {
409 /* DVB-C */
410 ret = cxd2820r_lock(priv, 1);
411 if (ret)
412 return ret;
413
414 ret = cxd2820r_get_frontend_c(fe, p);
415 } 328 }
416
417 return ret; 329 return ret;
418} 330}
419 331
420static int cxd2820r_read_ber(struct dvb_frontend *fe, u32 *ber) 332static int cxd2820r_read_ber(struct dvb_frontend *fe, u32 *ber)
421{ 333{
422 struct cxd2820r_priv *priv = fe->demodulator_priv;
423 int ret; 334 int ret;
424 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
425
426 if (fe->ops.info.type == FE_OFDM) {
427 /* DVB-T/T2 */
428 ret = cxd2820r_lock(priv, 0);
429 if (ret)
430 return ret;
431
432 switch (fe->dtv_property_cache.delivery_system) {
433 case SYS_DVBT:
434 ret = cxd2820r_read_ber_t(fe, ber);
435 break;
436 case SYS_DVBT2:
437 ret = cxd2820r_read_ber_t2(fe, ber);
438 break;
439 default:
440 ret = -EINVAL;
441 }
442 } else {
443 /* DVB-C */
444 ret = cxd2820r_lock(priv, 1);
445 if (ret)
446 return ret;
447 335
336 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
337 switch (fe->dtv_property_cache.delivery_system) {
338 case SYS_DVBT:
339 ret = cxd2820r_read_ber_t(fe, ber);
340 break;
341 case SYS_DVBT2:
342 ret = cxd2820r_read_ber_t2(fe, ber);
343 break;
344 case SYS_DVBC_ANNEX_A:
448 ret = cxd2820r_read_ber_c(fe, ber); 345 ret = cxd2820r_read_ber_c(fe, ber);
346 break;
347 default:
348 ret = -EINVAL;
349 break;
449 } 350 }
450
451 return ret; 351 return ret;
452} 352}
453 353
454static int cxd2820r_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 354static int cxd2820r_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
455{ 355{
456 struct cxd2820r_priv *priv = fe->demodulator_priv;
457 int ret; 356 int ret;
458 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
459
460 if (fe->ops.info.type == FE_OFDM) {
461 /* DVB-T/T2 */
462 ret = cxd2820r_lock(priv, 0);
463 if (ret)
464 return ret;
465
466 switch (fe->dtv_property_cache.delivery_system) {
467 case SYS_DVBT:
468 ret = cxd2820r_read_signal_strength_t(fe, strength);
469 break;
470 case SYS_DVBT2:
471 ret = cxd2820r_read_signal_strength_t2(fe, strength);
472 break;
473 default:
474 ret = -EINVAL;
475 }
476 } else {
477 /* DVB-C */
478 ret = cxd2820r_lock(priv, 1);
479 if (ret)
480 return ret;
481 357
358 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
359 switch (fe->dtv_property_cache.delivery_system) {
360 case SYS_DVBT:
361 ret = cxd2820r_read_signal_strength_t(fe, strength);
362 break;
363 case SYS_DVBT2:
364 ret = cxd2820r_read_signal_strength_t2(fe, strength);
365 break;
366 case SYS_DVBC_ANNEX_A:
482 ret = cxd2820r_read_signal_strength_c(fe, strength); 367 ret = cxd2820r_read_signal_strength_c(fe, strength);
368 break;
369 default:
370 ret = -EINVAL;
371 break;
483 } 372 }
484
485 return ret; 373 return ret;
486} 374}
487 375
488static int cxd2820r_read_snr(struct dvb_frontend *fe, u16 *snr) 376static int cxd2820r_read_snr(struct dvb_frontend *fe, u16 *snr)
489{ 377{
490 struct cxd2820r_priv *priv = fe->demodulator_priv;
491 int ret; 378 int ret;
492 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
493
494 if (fe->ops.info.type == FE_OFDM) {
495 /* DVB-T/T2 */
496 ret = cxd2820r_lock(priv, 0);
497 if (ret)
498 return ret;
499
500 switch (fe->dtv_property_cache.delivery_system) {
501 case SYS_DVBT:
502 ret = cxd2820r_read_snr_t(fe, snr);
503 break;
504 case SYS_DVBT2:
505 ret = cxd2820r_read_snr_t2(fe, snr);
506 break;
507 default:
508 ret = -EINVAL;
509 }
510 } else {
511 /* DVB-C */
512 ret = cxd2820r_lock(priv, 1);
513 if (ret)
514 return ret;
515 379
380 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
381 switch (fe->dtv_property_cache.delivery_system) {
382 case SYS_DVBT:
383 ret = cxd2820r_read_snr_t(fe, snr);
384 break;
385 case SYS_DVBT2:
386 ret = cxd2820r_read_snr_t2(fe, snr);
387 break;
388 case SYS_DVBC_ANNEX_A:
516 ret = cxd2820r_read_snr_c(fe, snr); 389 ret = cxd2820r_read_snr_c(fe, snr);
390 break;
391 default:
392 ret = -EINVAL;
393 break;
517 } 394 }
518
519 return ret; 395 return ret;
520} 396}
521 397
522static int cxd2820r_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 398static int cxd2820r_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
523{ 399{
524 struct cxd2820r_priv *priv = fe->demodulator_priv;
525 int ret; 400 int ret;
526 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
527
528 if (fe->ops.info.type == FE_OFDM) {
529 /* DVB-T/T2 */
530 ret = cxd2820r_lock(priv, 0);
531 if (ret)
532 return ret;
533
534 switch (fe->dtv_property_cache.delivery_system) {
535 case SYS_DVBT:
536 ret = cxd2820r_read_ucblocks_t(fe, ucblocks);
537 break;
538 case SYS_DVBT2:
539 ret = cxd2820r_read_ucblocks_t2(fe, ucblocks);
540 break;
541 default:
542 ret = -EINVAL;
543 }
544 } else {
545 /* DVB-C */
546 ret = cxd2820r_lock(priv, 1);
547 if (ret)
548 return ret;
549 401
402 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
403 switch (fe->dtv_property_cache.delivery_system) {
404 case SYS_DVBT:
405 ret = cxd2820r_read_ucblocks_t(fe, ucblocks);
406 break;
407 case SYS_DVBT2:
408 ret = cxd2820r_read_ucblocks_t2(fe, ucblocks);
409 break;
410 case SYS_DVBC_ANNEX_A:
550 ret = cxd2820r_read_ucblocks_c(fe, ucblocks); 411 ret = cxd2820r_read_ucblocks_c(fe, ucblocks);
412 break;
413 default:
414 ret = -EINVAL;
415 break;
551 } 416 }
552
553 return ret; 417 return ret;
554} 418}
555 419
556static int cxd2820r_init(struct dvb_frontend *fe) 420static int cxd2820r_init(struct dvb_frontend *fe)
557{ 421{
558 struct cxd2820r_priv *priv = fe->demodulator_priv; 422 return 0;
559 int ret;
560 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
561
562 priv->delivery_system = SYS_UNDEFINED;
563 /* delivery system is unknown at that (init) phase */
564
565 if (fe->ops.info.type == FE_OFDM) {
566 /* DVB-T/T2 */
567 ret = cxd2820r_lock(priv, 0);
568 if (ret)
569 return ret;
570
571 ret = cxd2820r_init_t(fe);
572 } else {
573 /* DVB-C */
574 ret = cxd2820r_lock(priv, 1);
575 if (ret)
576 return ret;
577
578 ret = cxd2820r_init_c(fe);
579 }
580
581 return ret;
582} 423}
583 424
584static int cxd2820r_sleep(struct dvb_frontend *fe) 425static int cxd2820r_sleep(struct dvb_frontend *fe)
585{ 426{
586 struct cxd2820r_priv *priv = fe->demodulator_priv;
587 int ret; 427 int ret;
588 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
589
590 if (fe->ops.info.type == FE_OFDM) {
591 /* DVB-T/T2 */
592 ret = cxd2820r_lock(priv, 0);
593 if (ret)
594 return ret;
595
596 switch (fe->dtv_property_cache.delivery_system) {
597 case SYS_DVBT:
598 ret = cxd2820r_sleep_t(fe);
599 break;
600 case SYS_DVBT2:
601 ret = cxd2820r_sleep_t2(fe);
602 break;
603 default:
604 ret = -EINVAL;
605 }
606
607 cxd2820r_unlock(priv, 0);
608 } else {
609 /* DVB-C */
610 ret = cxd2820r_lock(priv, 1);
611 if (ret)
612 return ret;
613 428
429 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
430 switch (fe->dtv_property_cache.delivery_system) {
431 case SYS_DVBT:
432 ret = cxd2820r_sleep_t(fe);
433 break;
434 case SYS_DVBT2:
435 ret = cxd2820r_sleep_t2(fe);
436 break;
437 case SYS_DVBC_ANNEX_A:
614 ret = cxd2820r_sleep_c(fe); 438 ret = cxd2820r_sleep_c(fe);
615 439 break;
616 cxd2820r_unlock(priv, 1); 440 default:
441 ret = -EINVAL;
442 break;
617 } 443 }
618
619 return ret; 444 return ret;
620} 445}
621 446
622static int cxd2820r_get_tune_settings(struct dvb_frontend *fe, 447static int cxd2820r_get_tune_settings(struct dvb_frontend *fe,
623 struct dvb_frontend_tune_settings *s) 448 struct dvb_frontend_tune_settings *s)
624{ 449{
625 struct cxd2820r_priv *priv = fe->demodulator_priv;
626 int ret; 450 int ret;
627 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
628
629 if (fe->ops.info.type == FE_OFDM) {
630 /* DVB-T/T2 */
631 ret = cxd2820r_lock(priv, 0);
632 if (ret)
633 return ret;
634
635 switch (fe->dtv_property_cache.delivery_system) {
636 case SYS_DVBT:
637 ret = cxd2820r_get_tune_settings_t(fe, s);
638 break;
639 case SYS_DVBT2:
640 ret = cxd2820r_get_tune_settings_t2(fe, s);
641 break;
642 default:
643 ret = -EINVAL;
644 }
645 } else {
646 /* DVB-C */
647 ret = cxd2820r_lock(priv, 1);
648 if (ret)
649 return ret;
650 451
452 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
453 switch (fe->dtv_property_cache.delivery_system) {
454 case SYS_DVBT:
455 ret = cxd2820r_get_tune_settings_t(fe, s);
456 break;
457 case SYS_DVBT2:
458 ret = cxd2820r_get_tune_settings_t2(fe, s);
459 break;
460 case SYS_DVBC_ANNEX_A:
651 ret = cxd2820r_get_tune_settings_c(fe, s); 461 ret = cxd2820r_get_tune_settings_c(fe, s);
462 break;
463 default:
464 ret = -EINVAL;
465 break;
652 } 466 }
653
654 return ret; 467 return ret;
655} 468}
656 469
657static enum dvbfe_search cxd2820r_search(struct dvb_frontend *fe, 470static enum dvbfe_search cxd2820r_search(struct dvb_frontend *fe)
658 struct dvb_frontend_parameters *p)
659{ 471{
660 struct cxd2820r_priv *priv = fe->demodulator_priv; 472 struct cxd2820r_priv *priv = fe->demodulator_priv;
661 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 473 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
@@ -664,7 +476,7 @@ static enum dvbfe_search cxd2820r_search(struct dvb_frontend *fe,
664 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); 476 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
665 477
666 /* switch between DVB-T and DVB-T2 when tune fails */ 478 /* switch between DVB-T and DVB-T2 when tune fails */
667 if (priv->last_tune_failed) { 479 if (priv->last_tune_failed && (priv->delivery_system != SYS_DVBC_ANNEX_A)) {
668 if (priv->delivery_system == SYS_DVBT) 480 if (priv->delivery_system == SYS_DVBT)
669 c->delivery_system = SYS_DVBT2; 481 c->delivery_system = SYS_DVBT2;
670 else 482 else
@@ -672,7 +484,7 @@ static enum dvbfe_search cxd2820r_search(struct dvb_frontend *fe,
672 } 484 }
673 485
674 /* set frontend */ 486 /* set frontend */
675 ret = cxd2820r_set_frontend(fe, p); 487 ret = cxd2820r_set_frontend(fe);
676 if (ret) 488 if (ret)
677 goto error; 489 goto error;
678 490
@@ -727,9 +539,7 @@ static void cxd2820r_release(struct dvb_frontend *fe)
727 struct cxd2820r_priv *priv = fe->demodulator_priv; 539 struct cxd2820r_priv *priv = fe->demodulator_priv;
728 dbg("%s", __func__); 540 dbg("%s", __func__);
729 541
730 if (fe->ops.info.type == FE_OFDM) 542 kfree(priv);
731 kfree(priv);
732
733 return; 543 return;
734} 544}
735 545
@@ -742,128 +552,79 @@ static int cxd2820r_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
742 return cxd2820r_wr_reg_mask(priv, 0xdb, enable ? 1 : 0, 0x1); 552 return cxd2820r_wr_reg_mask(priv, 0xdb, enable ? 1 : 0, 0x1);
743} 553}
744 554
745static const struct dvb_frontend_ops cxd2820r_ops[2]; 555static const struct dvb_frontend_ops cxd2820r_ops = {
556 .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
557 /* default: DVB-T/T2 */
558 .info = {
559 .name = "Sony CXD2820R (DVB-T/T2)",
560
561 .caps = FE_CAN_FEC_1_2 |
562 FE_CAN_FEC_2_3 |
563 FE_CAN_FEC_3_4 |
564 FE_CAN_FEC_5_6 |
565 FE_CAN_FEC_7_8 |
566 FE_CAN_FEC_AUTO |
567 FE_CAN_QPSK |
568 FE_CAN_QAM_16 |
569 FE_CAN_QAM_64 |
570 FE_CAN_QAM_256 |
571 FE_CAN_QAM_AUTO |
572 FE_CAN_TRANSMISSION_MODE_AUTO |
573 FE_CAN_GUARD_INTERVAL_AUTO |
574 FE_CAN_HIERARCHY_AUTO |
575 FE_CAN_MUTE_TS |
576 FE_CAN_2G_MODULATION
577 },
746 578
747struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *cfg, 579 .release = cxd2820r_release,
748 struct i2c_adapter *i2c, struct dvb_frontend *fe) 580 .init = cxd2820r_init,
749{ 581 .sleep = cxd2820r_sleep,
750 int ret;
751 struct cxd2820r_priv *priv = NULL;
752 u8 tmp;
753 582
754 if (fe == NULL) { 583 .get_tune_settings = cxd2820r_get_tune_settings,
755 /* FE0 */ 584 .i2c_gate_ctrl = cxd2820r_i2c_gate_ctrl,
756 /* allocate memory for the internal priv */
757 priv = kzalloc(sizeof(struct cxd2820r_priv), GFP_KERNEL);
758 if (priv == NULL)
759 goto error;
760 585
761 /* setup the priv */ 586 .get_frontend = cxd2820r_get_frontend,
762 priv->i2c = i2c;
763 memcpy(&priv->cfg, cfg, sizeof(struct cxd2820r_config));
764 mutex_init(&priv->fe_lock);
765 587
766 priv->active_fe = -1; /* NONE */ 588 .get_frontend_algo = cxd2820r_get_frontend_algo,
589 .search = cxd2820r_search,
767 590
768 /* check if the demod is there */ 591 .read_status = cxd2820r_read_status,
769 priv->bank[0] = priv->bank[1] = 0xff; 592 .read_snr = cxd2820r_read_snr,
770 ret = cxd2820r_rd_reg(priv, 0x000fd, &tmp); 593 .read_ber = cxd2820r_read_ber,
771 dbg("%s: chip id=%02x", __func__, tmp); 594 .read_ucblocks = cxd2820r_read_ucblocks,
772 if (ret || tmp != 0xe1) 595 .read_signal_strength = cxd2820r_read_signal_strength,
773 goto error; 596};
774 597
775 /* create frontends */ 598struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *cfg,
776 memcpy(&priv->fe[0].ops, &cxd2820r_ops[0], 599 struct i2c_adapter *i2c,
777 sizeof(struct dvb_frontend_ops)); 600 struct dvb_frontend *fe)
778 memcpy(&priv->fe[1].ops, &cxd2820r_ops[1], 601{
779 sizeof(struct dvb_frontend_ops)); 602 struct cxd2820r_priv *priv = NULL;
603 int ret;
604 u8 tmp;
780 605
781 priv->fe[0].demodulator_priv = priv; 606 priv = kzalloc(sizeof (struct cxd2820r_priv), GFP_KERNEL);
782 priv->fe[1].demodulator_priv = priv; 607 if (!priv)
608 goto error;
783 609
784 return &priv->fe[0]; 610 priv->i2c = i2c;
611 memcpy(&priv->cfg, cfg, sizeof (struct cxd2820r_config));
785 612
786 } else { 613 priv->bank[0] = priv->bank[1] = 0xff;
787 /* FE1: FE0 given as pointer, just return FE1 we have 614 ret = cxd2820r_rd_reg(priv, 0x000fd, &tmp);
788 * already created */ 615 dbg("%s: chip id=%02x", __func__, tmp);
789 priv = fe->demodulator_priv; 616 if (ret || tmp != 0xe1)
790 return &priv->fe[1]; 617 goto error;
791 }
792 618
619 memcpy(&priv->fe.ops, &cxd2820r_ops, sizeof (struct dvb_frontend_ops));
620 priv->fe.demodulator_priv = priv;
621 return &priv->fe;
793error: 622error:
794 kfree(priv); 623 kfree(priv);
795 return NULL; 624 return NULL;
796} 625}
797EXPORT_SYMBOL(cxd2820r_attach); 626EXPORT_SYMBOL(cxd2820r_attach);
798 627
799static const struct dvb_frontend_ops cxd2820r_ops[2] = {
800 {
801 /* DVB-T/T2 */
802 .info = {
803 .name = "Sony CXD2820R (DVB-T/T2)",
804 .type = FE_OFDM,
805 .caps =
806 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
807 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
808 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
809 FE_CAN_QPSK | FE_CAN_QAM_16 |
810 FE_CAN_QAM_64 | FE_CAN_QAM_256 |
811 FE_CAN_QAM_AUTO |
812 FE_CAN_TRANSMISSION_MODE_AUTO |
813 FE_CAN_GUARD_INTERVAL_AUTO |
814 FE_CAN_HIERARCHY_AUTO |
815 FE_CAN_MUTE_TS |
816 FE_CAN_2G_MODULATION
817 },
818
819 .release = cxd2820r_release,
820 .init = cxd2820r_init,
821 .sleep = cxd2820r_sleep,
822
823 .get_tune_settings = cxd2820r_get_tune_settings,
824 .i2c_gate_ctrl = cxd2820r_i2c_gate_ctrl,
825
826 .get_frontend = cxd2820r_get_frontend,
827
828 .get_frontend_algo = cxd2820r_get_frontend_algo,
829 .search = cxd2820r_search,
830
831 .read_status = cxd2820r_read_status,
832 .read_snr = cxd2820r_read_snr,
833 .read_ber = cxd2820r_read_ber,
834 .read_ucblocks = cxd2820r_read_ucblocks,
835 .read_signal_strength = cxd2820r_read_signal_strength,
836 },
837 {
838 /* DVB-C */
839 .info = {
840 .name = "Sony CXD2820R (DVB-C)",
841 .type = FE_QAM,
842 .caps =
843 FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
844 FE_CAN_QAM_128 | FE_CAN_QAM_256 |
845 FE_CAN_FEC_AUTO
846 },
847
848 .release = cxd2820r_release,
849 .init = cxd2820r_init,
850 .sleep = cxd2820r_sleep,
851
852 .get_tune_settings = cxd2820r_get_tune_settings,
853 .i2c_gate_ctrl = cxd2820r_i2c_gate_ctrl,
854
855 .set_frontend = cxd2820r_set_frontend,
856 .get_frontend = cxd2820r_get_frontend,
857
858 .read_status = cxd2820r_read_status,
859 .read_snr = cxd2820r_read_snr,
860 .read_ber = cxd2820r_read_ber,
861 .read_ucblocks = cxd2820r_read_ucblocks,
862 .read_signal_strength = cxd2820r_read_signal_strength,
863 },
864};
865
866
867MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); 628MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
868MODULE_DESCRIPTION("Sony CXD2820R demodulator driver"); 629MODULE_DESCRIPTION("Sony CXD2820R demodulator driver");
869MODULE_LICENSE("GPL"); 630MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/cxd2820r_priv.h b/drivers/media/dvb/frontends/cxd2820r_priv.h
index 95539134efdb..9a9822cad9cd 100644
--- a/drivers/media/dvb/frontends/cxd2820r_priv.h
+++ b/drivers/media/dvb/frontends/cxd2820r_priv.h
@@ -48,12 +48,9 @@ struct reg_val_mask {
48 48
49struct cxd2820r_priv { 49struct cxd2820r_priv {
50 struct i2c_adapter *i2c; 50 struct i2c_adapter *i2c;
51 struct dvb_frontend fe[2]; 51 struct dvb_frontend fe;
52 struct cxd2820r_config cfg; 52 struct cxd2820r_config cfg;
53 53
54 struct mutex fe_lock; /* FE lock */
55 int active_fe:2; /* FE lock, -1=NONE, 0=DVB-T/T2, 1=DVB-C */
56
57 bool ber_running; 54 bool ber_running;
58 55
59 u8 bank[2]; 56 u8 bank[2];
@@ -89,11 +86,9 @@ int cxd2820r_rd_reg(struct cxd2820r_priv *priv, u32 reg, u8 *val);
89 86
90/* cxd2820r_c.c */ 87/* cxd2820r_c.c */
91 88
92int cxd2820r_get_frontend_c(struct dvb_frontend *fe, 89int cxd2820r_get_frontend_c(struct dvb_frontend *fe);
93 struct dvb_frontend_parameters *p);
94 90
95int cxd2820r_set_frontend_c(struct dvb_frontend *fe, 91int cxd2820r_set_frontend_c(struct dvb_frontend *fe);
96 struct dvb_frontend_parameters *params);
97 92
98int cxd2820r_read_status_c(struct dvb_frontend *fe, fe_status_t *status); 93int cxd2820r_read_status_c(struct dvb_frontend *fe, fe_status_t *status);
99 94
@@ -114,11 +109,9 @@ int cxd2820r_get_tune_settings_c(struct dvb_frontend *fe,
114 109
115/* cxd2820r_t.c */ 110/* cxd2820r_t.c */
116 111
117int cxd2820r_get_frontend_t(struct dvb_frontend *fe, 112int cxd2820r_get_frontend_t(struct dvb_frontend *fe);
118 struct dvb_frontend_parameters *p);
119 113
120int cxd2820r_set_frontend_t(struct dvb_frontend *fe, 114int cxd2820r_set_frontend_t(struct dvb_frontend *fe);
121 struct dvb_frontend_parameters *params);
122 115
123int cxd2820r_read_status_t(struct dvb_frontend *fe, fe_status_t *status); 116int cxd2820r_read_status_t(struct dvb_frontend *fe, fe_status_t *status);
124 117
@@ -139,11 +132,9 @@ int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
139 132
140/* cxd2820r_t2.c */ 133/* cxd2820r_t2.c */
141 134
142int cxd2820r_get_frontend_t2(struct dvb_frontend *fe, 135int cxd2820r_get_frontend_t2(struct dvb_frontend *fe);
143 struct dvb_frontend_parameters *p);
144 136
145int cxd2820r_set_frontend_t2(struct dvb_frontend *fe, 137int cxd2820r_set_frontend_t2(struct dvb_frontend *fe);
146 struct dvb_frontend_parameters *params);
147 138
148int cxd2820r_read_status_t2(struct dvb_frontend *fe, fe_status_t *status); 139int cxd2820r_read_status_t2(struct dvb_frontend *fe, fe_status_t *status);
149 140
diff --git a/drivers/media/dvb/frontends/cxd2820r_t.c b/drivers/media/dvb/frontends/cxd2820r_t.c
index a04f9c810101..1a026239cdcc 100644
--- a/drivers/media/dvb/frontends/cxd2820r_t.c
+++ b/drivers/media/dvb/frontends/cxd2820r_t.c
@@ -21,13 +21,12 @@
21 21
22#include "cxd2820r_priv.h" 22#include "cxd2820r_priv.h"
23 23
24int cxd2820r_set_frontend_t(struct dvb_frontend *fe, 24int cxd2820r_set_frontend_t(struct dvb_frontend *fe)
25 struct dvb_frontend_parameters *p)
26{ 25{
27 struct cxd2820r_priv *priv = fe->demodulator_priv; 26 struct cxd2820r_priv *priv = fe->demodulator_priv;
28 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 27 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
29 int ret, i; 28 int ret, i, bw_i;
30 u32 if_khz, if_ctl; 29 u32 if_freq, if_ctl;
31 u64 num; 30 u64 num;
32 u8 buf[3], bw_param; 31 u8 buf[3], bw_param;
33 u8 bw_params1[][5] = { 32 u8 bw_params1[][5] = {
@@ -57,6 +56,23 @@ int cxd2820r_set_frontend_t(struct dvb_frontend *fe,
57 56
58 dbg("%s: RF=%d BW=%d", __func__, c->frequency, c->bandwidth_hz); 57 dbg("%s: RF=%d BW=%d", __func__, c->frequency, c->bandwidth_hz);
59 58
59 switch (c->bandwidth_hz) {
60 case 6000000:
61 bw_i = 0;
62 bw_param = 2;
63 break;
64 case 7000000:
65 bw_i = 1;
66 bw_param = 1;
67 break;
68 case 8000000:
69 bw_i = 2;
70 bw_param = 0;
71 break;
72 default:
73 return -EINVAL;
74 }
75
60 /* update GPIOs */ 76 /* update GPIOs */
61 ret = cxd2820r_gpio(fe); 77 ret = cxd2820r_gpio(fe);
62 if (ret) 78 if (ret)
@@ -64,7 +80,7 @@ int cxd2820r_set_frontend_t(struct dvb_frontend *fe,
64 80
65 /* program tuner */ 81 /* program tuner */
66 if (fe->ops.tuner_ops.set_params) 82 if (fe->ops.tuner_ops.set_params)
67 fe->ops.tuner_ops.set_params(fe, p); 83 fe->ops.tuner_ops.set_params(fe);
68 84
69 if (priv->delivery_system != SYS_DVBT) { 85 if (priv->delivery_system != SYS_DVBT) {
70 for (i = 0; i < ARRAY_SIZE(tab); i++) { 86 for (i = 0; i < ARRAY_SIZE(tab); i++) {
@@ -78,27 +94,17 @@ int cxd2820r_set_frontend_t(struct dvb_frontend *fe,
78 priv->delivery_system = SYS_DVBT; 94 priv->delivery_system = SYS_DVBT;
79 priv->ber_running = 0; /* tune stops BER counter */ 95 priv->ber_running = 0; /* tune stops BER counter */
80 96
81 switch (c->bandwidth_hz) { 97 /* program IF frequency */
82 case 6000000: 98 if (fe->ops.tuner_ops.get_if_frequency) {
83 if_khz = priv->cfg.if_dvbt_6; 99 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
84 i = 0; 100 if (ret)
85 bw_param = 2; 101 goto error;
86 break; 102 } else
87 case 7000000: 103 if_freq = 0;
88 if_khz = priv->cfg.if_dvbt_7; 104
89 i = 1; 105 dbg("%s: if_freq=%d", __func__, if_freq);
90 bw_param = 1;
91 break;
92 case 8000000:
93 if_khz = priv->cfg.if_dvbt_8;
94 i = 2;
95 bw_param = 0;
96 break;
97 default:
98 return -EINVAL;
99 }
100 106
101 num = if_khz; 107 num = if_freq / 1000; /* Hz => kHz */
102 num *= 0x1000000; 108 num *= 0x1000000;
103 if_ctl = cxd2820r_div_u64_round_closest(num, 41000); 109 if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
104 buf[0] = ((if_ctl >> 16) & 0xff); 110 buf[0] = ((if_ctl >> 16) & 0xff);
@@ -109,7 +115,7 @@ int cxd2820r_set_frontend_t(struct dvb_frontend *fe,
109 if (ret) 115 if (ret)
110 goto error; 116 goto error;
111 117
112 ret = cxd2820r_wr_regs(priv, 0x0009f, bw_params1[i], 5); 118 ret = cxd2820r_wr_regs(priv, 0x0009f, bw_params1[bw_i], 5);
113 if (ret) 119 if (ret)
114 goto error; 120 goto error;
115 121
@@ -117,7 +123,7 @@ int cxd2820r_set_frontend_t(struct dvb_frontend *fe,
117 if (ret) 123 if (ret)
118 goto error; 124 goto error;
119 125
120 ret = cxd2820r_wr_regs(priv, 0x000d9, bw_params2[i], 2); 126 ret = cxd2820r_wr_regs(priv, 0x000d9, bw_params2[bw_i], 2);
121 if (ret) 127 if (ret)
122 goto error; 128 goto error;
123 129
@@ -135,8 +141,7 @@ error:
135 return ret; 141 return ret;
136} 142}
137 143
138int cxd2820r_get_frontend_t(struct dvb_frontend *fe, 144int cxd2820r_get_frontend_t(struct dvb_frontend *fe)
139 struct dvb_frontend_parameters *p)
140{ 145{
141 struct cxd2820r_priv *priv = fe->demodulator_priv; 146 struct cxd2820r_priv *priv = fe->demodulator_priv;
142 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 147 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
diff --git a/drivers/media/dvb/frontends/cxd2820r_t2.c b/drivers/media/dvb/frontends/cxd2820r_t2.c
index 6548588309f7..3a5759e0d235 100644
--- a/drivers/media/dvb/frontends/cxd2820r_t2.c
+++ b/drivers/media/dvb/frontends/cxd2820r_t2.c
@@ -21,13 +21,12 @@
21 21
22#include "cxd2820r_priv.h" 22#include "cxd2820r_priv.h"
23 23
24int cxd2820r_set_frontend_t2(struct dvb_frontend *fe, 24int cxd2820r_set_frontend_t2(struct dvb_frontend *fe)
25 struct dvb_frontend_parameters *params)
26{ 25{
27 struct cxd2820r_priv *priv = fe->demodulator_priv; 26 struct cxd2820r_priv *priv = fe->demodulator_priv;
28 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 27 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
29 int ret, i; 28 int ret, i, bw_i;
30 u32 if_khz, if_ctl; 29 u32 if_freq, if_ctl;
31 u64 num; 30 u64 num;
32 u8 buf[3], bw_param; 31 u8 buf[3], bw_param;
33 u8 bw_params1[][5] = { 32 u8 bw_params1[][5] = {
@@ -71,6 +70,27 @@ int cxd2820r_set_frontend_t2(struct dvb_frontend *fe,
71 70
72 dbg("%s: RF=%d BW=%d", __func__, c->frequency, c->bandwidth_hz); 71 dbg("%s: RF=%d BW=%d", __func__, c->frequency, c->bandwidth_hz);
73 72
73 switch (c->bandwidth_hz) {
74 case 5000000:
75 bw_i = 0;
76 bw_param = 3;
77 break;
78 case 6000000:
79 bw_i = 1;
80 bw_param = 2;
81 break;
82 case 7000000:
83 bw_i = 2;
84 bw_param = 1;
85 break;
86 case 8000000:
87 bw_i = 3;
88 bw_param = 0;
89 break;
90 default:
91 return -EINVAL;
92 }
93
74 /* update GPIOs */ 94 /* update GPIOs */
75 ret = cxd2820r_gpio(fe); 95 ret = cxd2820r_gpio(fe);
76 if (ret) 96 if (ret)
@@ -78,7 +98,7 @@ int cxd2820r_set_frontend_t2(struct dvb_frontend *fe,
78 98
79 /* program tuner */ 99 /* program tuner */
80 if (fe->ops.tuner_ops.set_params) 100 if (fe->ops.tuner_ops.set_params)
81 fe->ops.tuner_ops.set_params(fe, params); 101 fe->ops.tuner_ops.set_params(fe);
82 102
83 if (priv->delivery_system != SYS_DVBT2) { 103 if (priv->delivery_system != SYS_DVBT2) {
84 for (i = 0; i < ARRAY_SIZE(tab); i++) { 104 for (i = 0; i < ARRAY_SIZE(tab); i++) {
@@ -91,32 +111,17 @@ int cxd2820r_set_frontend_t2(struct dvb_frontend *fe,
91 111
92 priv->delivery_system = SYS_DVBT2; 112 priv->delivery_system = SYS_DVBT2;
93 113
94 switch (c->bandwidth_hz) { 114 /* program IF frequency */
95 case 5000000: 115 if (fe->ops.tuner_ops.get_if_frequency) {
96 if_khz = priv->cfg.if_dvbt2_5; 116 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
97 i = 0; 117 if (ret)
98 bw_param = 3; 118 goto error;
99 break; 119 } else
100 case 6000000: 120 if_freq = 0;
101 if_khz = priv->cfg.if_dvbt2_6; 121
102 i = 1; 122 dbg("%s: if_freq=%d", __func__, if_freq);
103 bw_param = 2;
104 break;
105 case 7000000:
106 if_khz = priv->cfg.if_dvbt2_7;
107 i = 2;
108 bw_param = 1;
109 break;
110 case 8000000:
111 if_khz = priv->cfg.if_dvbt2_8;
112 i = 3;
113 bw_param = 0;
114 break;
115 default:
116 return -EINVAL;
117 }
118 123
119 num = if_khz; 124 num = if_freq / 1000; /* Hz => kHz */
120 num *= 0x1000000; 125 num *= 0x1000000;
121 if_ctl = cxd2820r_div_u64_round_closest(num, 41000); 126 if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
122 buf[0] = ((if_ctl >> 16) & 0xff); 127 buf[0] = ((if_ctl >> 16) & 0xff);
@@ -127,7 +132,7 @@ int cxd2820r_set_frontend_t2(struct dvb_frontend *fe,
127 if (ret) 132 if (ret)
128 goto error; 133 goto error;
129 134
130 ret = cxd2820r_wr_regs(priv, 0x0209f, bw_params1[i], 5); 135 ret = cxd2820r_wr_regs(priv, 0x0209f, bw_params1[bw_i], 5);
131 if (ret) 136 if (ret)
132 goto error; 137 goto error;
133 138
@@ -150,8 +155,7 @@ error:
150 155
151} 156}
152 157
153int cxd2820r_get_frontend_t2(struct dvb_frontend *fe, 158int cxd2820r_get_frontend_t2(struct dvb_frontend *fe)
154 struct dvb_frontend_parameters *p)
155{ 159{
156 struct cxd2820r_priv *priv = fe->demodulator_priv; 160 struct cxd2820r_priv *priv = fe->demodulator_priv;
157 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 161 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
diff --git a/drivers/media/dvb/frontends/dib0070.c b/drivers/media/dvb/frontends/dib0070.c
index dc1cb17a6ea7..3b024bfe980a 100644
--- a/drivers/media/dvb/frontends/dib0070.c
+++ b/drivers/media/dvb/frontends/dib0070.c
@@ -150,7 +150,7 @@ static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
150 } \ 150 } \
151} while (0) 151} while (0)
152 152
153static int dib0070_set_bandwidth(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch) 153static int dib0070_set_bandwidth(struct dvb_frontend *fe)
154{ 154{
155 struct dib0070_state *state = fe->tuner_priv; 155 struct dib0070_state *state = fe->tuner_priv;
156 u16 tmp = dib0070_read_reg(state, 0x02) & 0x3fff; 156 u16 tmp = dib0070_read_reg(state, 0x02) & 0x3fff;
@@ -335,7 +335,7 @@ static const struct dib0070_lna_match dib0070_lna[] = {
335}; 335};
336 336
337#define LPF 100 337#define LPF 100
338static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch) 338static int dib0070_tune_digital(struct dvb_frontend *fe)
339{ 339{
340 struct dib0070_state *state = fe->tuner_priv; 340 struct dib0070_state *state = fe->tuner_priv;
341 341
@@ -507,7 +507,7 @@ static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_par
507 507
508 *tune_state = CT_TUNER_STEP_5; 508 *tune_state = CT_TUNER_STEP_5;
509 } else if (*tune_state == CT_TUNER_STEP_5) { 509 } else if (*tune_state == CT_TUNER_STEP_5) {
510 dib0070_set_bandwidth(fe, ch); 510 dib0070_set_bandwidth(fe);
511 *tune_state = CT_TUNER_STOP; 511 *tune_state = CT_TUNER_STOP;
512 } else { 512 } else {
513 ret = FE_CALLBACK_TIME_NEVER; /* tuner finished, time to call again infinite */ 513 ret = FE_CALLBACK_TIME_NEVER; /* tuner finished, time to call again infinite */
@@ -516,7 +516,7 @@ static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_par
516} 516}
517 517
518 518
519static int dib0070_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) 519static int dib0070_tune(struct dvb_frontend *fe)
520{ 520{
521 struct dib0070_state *state = fe->tuner_priv; 521 struct dib0070_state *state = fe->tuner_priv;
522 uint32_t ret; 522 uint32_t ret;
@@ -524,7 +524,7 @@ static int dib0070_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters
524 state->tune_state = CT_TUNER_START; 524 state->tune_state = CT_TUNER_START;
525 525
526 do { 526 do {
527 ret = dib0070_tune_digital(fe, p); 527 ret = dib0070_tune_digital(fe);
528 if (ret != FE_CALLBACK_TIME_NEVER) 528 if (ret != FE_CALLBACK_TIME_NEVER)
529 msleep(ret/10); 529 msleep(ret/10);
530 else 530 else
diff --git a/drivers/media/dvb/frontends/dib0090.c b/drivers/media/dvb/frontends/dib0090.c
index b174d1c78583..224d81e85091 100644
--- a/drivers/media/dvb/frontends/dib0090.c
+++ b/drivers/media/dvb/frontends/dib0090.c
@@ -717,6 +717,34 @@ static const u16 rf_ramp_pwm_cband_7090[] = {
717 (0 << 10) | 109, /* RF_RAMP4, LNA 4 */ 717 (0 << 10) | 109, /* RF_RAMP4, LNA 4 */
718}; 718};
719 719
720static const uint16_t rf_ramp_pwm_cband_7090e_sensitivity[] = {
721 186,
722 40,
723 746,
724 (10 << 10) | 345,
725 (0 << 10) | 746,
726 (0 << 10) | 0,
727 (0 << 10) | 0,
728 (28 << 10) | 200,
729 (0 << 10) | 345,
730 (20 << 10) | 0,
731 (0 << 10) | 200,
732};
733
734static const uint16_t rf_ramp_pwm_cband_7090e_aci[] = {
735 86,
736 40,
737 345,
738 (0 << 10) | 0,
739 (0 << 10) | 0,
740 (0 << 10) | 0,
741 (0 << 10) | 0,
742 (28 << 10) | 200,
743 (0 << 10) | 345,
744 (20 << 10) | 0,
745 (0 << 10) | 200,
746};
747
720static const u16 rf_ramp_pwm_cband_8090[] = { 748static const u16 rf_ramp_pwm_cband_8090[] = {
721 345, /* max RF gain in 10th of dB */ 749 345, /* max RF gain in 10th of dB */
722 29, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */ 750 29, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
@@ -1076,8 +1104,16 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
1076 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs); 1104 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
1077 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1) 1105 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
1078 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_8090); 1106 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_8090);
1079 else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1) 1107 else if (state->identity.version == SOC_7090_P1G_11R1
1080 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_7090); 1108 || state->identity.version == SOC_7090_P1G_21R1) {
1109 if (state->config->is_dib7090e) {
1110 if (state->rf_ramp == NULL)
1111 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_7090e_sensitivity);
1112 else
1113 dib0090_set_rframp_pwm(state, state->rf_ramp);
1114 } else
1115 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_7090);
1116 }
1081 } else { 1117 } else {
1082 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband); 1118 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband);
1083 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); 1119 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
@@ -1112,13 +1148,21 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
1112 else 1148 else
1113 dib0090_write_reg(state, 0x32, (0 << 11)); 1149 dib0090_write_reg(state, 0x32, (0 << 11));
1114 1150
1115 dib0090_write_reg(state, 0x04, 0x01); 1151 dib0090_write_reg(state, 0x04, 0x03);
1116 dib0090_write_reg(state, 0x39, (1 << 10)); 1152 dib0090_write_reg(state, 0x39, (1 << 10));
1117 } 1153 }
1118} 1154}
1119 1155
1120EXPORT_SYMBOL(dib0090_pwm_gain_reset); 1156EXPORT_SYMBOL(dib0090_pwm_gain_reset);
1121 1157
1158void dib0090_set_dc_servo(struct dvb_frontend *fe, u8 DC_servo_cutoff)
1159{
1160 struct dib0090_state *state = fe->tuner_priv;
1161 if (DC_servo_cutoff < 4)
1162 dib0090_write_reg(state, 0x04, DC_servo_cutoff);
1163}
1164EXPORT_SYMBOL(dib0090_set_dc_servo);
1165
1122static u32 dib0090_get_slow_adc_val(struct dib0090_state *state) 1166static u32 dib0090_get_slow_adc_val(struct dib0090_state *state)
1123{ 1167{
1124 u16 adc_val = dib0090_read_reg(state, 0x1d); 1168 u16 adc_val = dib0090_read_reg(state, 0x1d);
@@ -1305,7 +1349,7 @@ void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 *
1305 1349
1306EXPORT_SYMBOL(dib0090_get_current_gain); 1350EXPORT_SYMBOL(dib0090_get_current_gain);
1307 1351
1308u16 dib0090_get_wbd_offset(struct dvb_frontend *fe) 1352u16 dib0090_get_wbd_target(struct dvb_frontend *fe)
1309{ 1353{
1310 struct dib0090_state *state = fe->tuner_priv; 1354 struct dib0090_state *state = fe->tuner_priv;
1311 u32 f_MHz = state->fe->dtv_property_cache.frequency / 1000000; 1355 u32 f_MHz = state->fe->dtv_property_cache.frequency / 1000000;
@@ -1342,9 +1386,57 @@ u16 dib0090_get_wbd_offset(struct dvb_frontend *fe)
1342 1386
1343 return state->wbd_offset + wbd_tcold; 1387 return state->wbd_offset + wbd_tcold;
1344} 1388}
1389EXPORT_SYMBOL(dib0090_get_wbd_target);
1345 1390
1391u16 dib0090_get_wbd_offset(struct dvb_frontend *fe)
1392{
1393 struct dib0090_state *state = fe->tuner_priv;
1394 return state->wbd_offset;
1395}
1346EXPORT_SYMBOL(dib0090_get_wbd_offset); 1396EXPORT_SYMBOL(dib0090_get_wbd_offset);
1347 1397
1398int dib0090_set_switch(struct dvb_frontend *fe, u8 sw1, u8 sw2, u8 sw3)
1399{
1400 struct dib0090_state *state = fe->tuner_priv;
1401
1402 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xfff8)
1403 | ((sw3 & 1) << 2) | ((sw2 & 1) << 1) | (sw1 & 1));
1404
1405 return 0;
1406}
1407EXPORT_SYMBOL(dib0090_set_switch);
1408
1409int dib0090_set_vga(struct dvb_frontend *fe, u8 onoff)
1410{
1411 struct dib0090_state *state = fe->tuner_priv;
1412
1413 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x7fff)
1414 | ((onoff & 1) << 15));
1415 return 0;
1416}
1417EXPORT_SYMBOL(dib0090_set_vga);
1418
1419int dib0090_update_rframp_7090(struct dvb_frontend *fe, u8 cfg_sensitivity)
1420{
1421 struct dib0090_state *state = fe->tuner_priv;
1422
1423 if ((!state->identity.p1g) || (!state->identity.in_soc)
1424 || ((state->identity.version != SOC_7090_P1G_21R1)
1425 && (state->identity.version != SOC_7090_P1G_11R1))) {
1426 dprintk("%s() function can only be used for dib7090P", __func__);
1427 return -ENODEV;
1428 }
1429
1430 if (cfg_sensitivity)
1431 state->rf_ramp = (const u16 *)&rf_ramp_pwm_cband_7090e_sensitivity;
1432 else
1433 state->rf_ramp = (const u16 *)&rf_ramp_pwm_cband_7090e_aci;
1434 dib0090_pwm_gain_reset(fe);
1435
1436 return 0;
1437}
1438EXPORT_SYMBOL(dib0090_update_rframp_7090);
1439
1348static const u16 dib0090_defaults[] = { 1440static const u16 dib0090_defaults[] = {
1349 1441
1350 25, 0x01, 1442 25, 0x01,
@@ -1430,7 +1522,7 @@ static void dib0090_set_default_config(struct dib0090_state *state, const u16 *
1430#define POLY_MIN (u8) 0 1522#define POLY_MIN (u8) 0
1431#define POLY_MAX (u8) 8 1523#define POLY_MAX (u8) 8
1432 1524
1433void dib0090_set_EFUSE(struct dib0090_state *state) 1525static void dib0090_set_EFUSE(struct dib0090_state *state)
1434{ 1526{
1435 u8 c, h, n; 1527 u8 c, h, n;
1436 u16 e2, e4; 1528 u16 e2, e4;
@@ -1505,7 +1597,10 @@ static int dib0090_reset(struct dvb_frontend *fe)
1505 dib0090_set_EFUSE(state); 1597 dib0090_set_EFUSE(state);
1506 1598
1507 /* Congigure in function of the crystal */ 1599 /* Congigure in function of the crystal */
1508 if (state->config->io.clock_khz >= 24000) 1600 if (state->config->force_crystal_mode != 0)
1601 dib0090_write_reg(state, 0x14,
1602 state->config->force_crystal_mode & 3);
1603 else if (state->config->io.clock_khz >= 24000)
1509 dib0090_write_reg(state, 0x14, 1); 1604 dib0090_write_reg(state, 0x14, 1);
1510 else 1605 else
1511 dib0090_write_reg(state, 0x14, 2); 1606 dib0090_write_reg(state, 0x14, 2);
@@ -1951,6 +2046,52 @@ static const struct dib0090_tuning dib0090_tuning_table_cband_7090[] = {
1951#endif 2046#endif
1952}; 2047};
1953 2048
2049static const struct dib0090_tuning dib0090_tuning_table_cband_7090e_sensitivity[] = {
2050#ifdef CONFIG_BAND_CBAND
2051 { 300000, 0 , 3, 0x8105, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
2052 { 380000, 0 , 10, 0x810F, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
2053 { 600000, 0 , 10, 0x815E, 0x280, 0x2d12, 0xb84e, EN_CAB },
2054 { 660000, 0 , 5, 0x85E3, 0x280, 0x2d12, 0xb84e, EN_CAB },
2055 { 720000, 0 , 5, 0x852E, 0x280, 0x2d12, 0xb84e, EN_CAB },
2056 { 860000, 0 , 4, 0x85E5, 0x280, 0x2d12, 0xb84e, EN_CAB },
2057#endif
2058};
2059
2060int dib0090_update_tuning_table_7090(struct dvb_frontend *fe,
2061 u8 cfg_sensitivity)
2062{
2063 struct dib0090_state *state = fe->tuner_priv;
2064 const struct dib0090_tuning *tune =
2065 dib0090_tuning_table_cband_7090e_sensitivity;
2066 const struct dib0090_tuning dib0090_tuning_table_cband_7090e_aci[] = {
2067 { 300000, 0 , 3, 0x8165, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
2068 { 650000, 0 , 4, 0x815B, 0x280, 0x2d12, 0xb84e, EN_CAB },
2069 { 860000, 0 , 5, 0x84EF, 0x280, 0x2d12, 0xb84e, EN_CAB },
2070 };
2071
2072 if ((!state->identity.p1g) || (!state->identity.in_soc)
2073 || ((state->identity.version != SOC_7090_P1G_21R1)
2074 && (state->identity.version != SOC_7090_P1G_11R1))) {
2075 dprintk("%s() function can only be used for dib7090", __func__);
2076 return -ENODEV;
2077 }
2078
2079 if (cfg_sensitivity)
2080 tune = dib0090_tuning_table_cband_7090e_sensitivity;
2081 else
2082 tune = dib0090_tuning_table_cband_7090e_aci;
2083
2084 while (state->rf_request > tune->max_freq)
2085 tune++;
2086
2087 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x8000)
2088 | (tune->lna_bias & 0x7fff));
2089 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xf83f)
2090 | ((tune->lna_tune << 6) & 0x07c0));
2091 return 0;
2092}
2093EXPORT_SYMBOL(dib0090_update_tuning_table_7090);
2094
1954static int dib0090_captrim_search(struct dib0090_state *state, enum frontend_tune_state *tune_state) 2095static int dib0090_captrim_search(struct dib0090_state *state, enum frontend_tune_state *tune_state)
1955{ 2096{
1956 int ret = 0; 2097 int ret = 0;
@@ -2199,12 +2340,18 @@ static int dib0090_tune(struct dvb_frontend *fe)
2199 if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF 2340 if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF
2200 || state->current_band & BAND_UHF) { 2341 || state->current_band & BAND_UHF) {
2201 state->current_band = BAND_CBAND; 2342 state->current_band = BAND_CBAND;
2202 tune = dib0090_tuning_table_cband_7090; 2343 if (state->config->is_dib7090e)
2344 tune = dib0090_tuning_table_cband_7090e_sensitivity;
2345 else
2346 tune = dib0090_tuning_table_cband_7090;
2203 } 2347 }
2204 } else { /* Use the CBAND input for all band under UHF */ 2348 } else { /* Use the CBAND input for all band under UHF */
2205 if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF) { 2349 if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF) {
2206 state->current_band = BAND_CBAND; 2350 state->current_band = BAND_CBAND;
2207 tune = dib0090_tuning_table_cband_7090; 2351 if (state->config->is_dib7090e)
2352 tune = dib0090_tuning_table_cband_7090e_sensitivity;
2353 else
2354 tune = dib0090_tuning_table_cband_7090;
2208 } 2355 }
2209 } 2356 }
2210 } else 2357 } else
@@ -2419,7 +2566,7 @@ static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
2419 return 0; 2566 return 0;
2420} 2567}
2421 2568
2422static int dib0090_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) 2569static int dib0090_set_params(struct dvb_frontend *fe)
2423{ 2570{
2424 struct dib0090_state *state = fe->tuner_priv; 2571 struct dib0090_state *state = fe->tuner_priv;
2425 u32 ret; 2572 u32 ret;
diff --git a/drivers/media/dvb/frontends/dib0090.h b/drivers/media/dvb/frontends/dib0090.h
index 13d85244ec16..781dc49de45b 100644
--- a/drivers/media/dvb/frontends/dib0090.h
+++ b/drivers/media/dvb/frontends/dib0090.h
@@ -71,6 +71,8 @@ struct dib0090_config {
71 u8 fref_clock_ratio; 71 u8 fref_clock_ratio;
72 u16 force_cband_input; 72 u16 force_cband_input;
73 struct dib0090_wbd_slope *wbd; 73 struct dib0090_wbd_slope *wbd;
74 u8 is_dib7090e;
75 u8 force_crystal_mode;
74}; 76};
75 77
76#if defined(CONFIG_DVB_TUNER_DIB0090) || (defined(CONFIG_DVB_TUNER_DIB0090_MODULE) && defined(MODULE)) 78#if defined(CONFIG_DVB_TUNER_DIB0090) || (defined(CONFIG_DVB_TUNER_DIB0090_MODULE) && defined(MODULE))
@@ -78,13 +80,21 @@ extern struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c
78extern struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config); 80extern struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config);
79extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast); 81extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast);
80extern void dib0090_pwm_gain_reset(struct dvb_frontend *fe); 82extern void dib0090_pwm_gain_reset(struct dvb_frontend *fe);
81extern u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner); 83extern u16 dib0090_get_wbd_target(struct dvb_frontend *tuner);
84extern u16 dib0090_get_wbd_offset(struct dvb_frontend *fe);
82extern int dib0090_gain_control(struct dvb_frontend *fe); 85extern int dib0090_gain_control(struct dvb_frontend *fe);
83extern enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe); 86extern enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe);
84extern int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state); 87extern int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state);
85extern void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt); 88extern void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt);
89extern void dib0090_set_dc_servo(struct dvb_frontend *fe, u8 DC_servo_cutoff);
90extern int dib0090_set_switch(struct dvb_frontend *fe, u8 sw1, u8 sw2, u8 sw3);
91extern int dib0090_set_vga(struct dvb_frontend *fe, u8 onoff);
92extern int dib0090_update_rframp_7090(struct dvb_frontend *fe,
93 u8 cfg_sensitivity);
94extern int dib0090_update_tuning_table_7090(struct dvb_frontend *fe,
95 u8 cfg_sensitivity);
86#else 96#else
87static inline struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0090_config *config) 97static inline struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
88{ 98{
89 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 99 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
90 return NULL; 100 return NULL;
@@ -106,7 +116,13 @@ static inline void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
106 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 116 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
107} 117}
108 118
109static inline u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner) 119static inline u16 dib0090_get_wbd_target(struct dvb_frontend *tuner)
120{
121 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
122 return 0;
123}
124
125static inline u16 dib0090_get_wbd_offset(struct dvb_frontend *fe)
110{ 126{
111 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 127 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
112 return 0; 128 return 0;
@@ -134,6 +150,38 @@ static inline void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u
134{ 150{
135 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 151 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
136} 152}
153
154static inline void dib0090_set_dc_servo(struct dvb_frontend *fe, u8 DC_servo_cutoff)
155{
156 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
157}
158
159static inline int dib0090_set_switch(struct dvb_frontend *fe,
160 u8 sw1, u8 sw2, u8 sw3)
161{
162 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
163 return -ENODEV;
164}
165
166static inline int dib0090_set_vga(struct dvb_frontend *fe, u8 onoff)
167{
168 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
169 return -ENODEV;
170}
171
172static inline int dib0090_update_rframp_7090(struct dvb_frontend *fe,
173 u8 cfg_sensitivity)
174{
175 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
176 return -ENODEV;
177}
178
179static inline int dib0090_update_tuning_table_7090(struct dvb_frontend *fe,
180 u8 cfg_sensitivity)
181{
182 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
183 return -ENODEV;
184}
137#endif 185#endif
138 186
139#endif 187#endif
diff --git a/drivers/media/dvb/frontends/dib3000mb.c b/drivers/media/dvb/frontends/dib3000mb.c
index 437904cbf3e6..af91e0c92339 100644
--- a/drivers/media/dvb/frontends/dib3000mb.c
+++ b/drivers/media/dvb/frontends/dib3000mb.c
@@ -112,39 +112,37 @@ static u16 dib3000_seq[2][2][2] = /* fft,gua, inv */
112 } 112 }
113 }; 113 };
114 114
115static int dib3000mb_get_frontend(struct dvb_frontend* fe, 115static int dib3000mb_get_frontend(struct dvb_frontend* fe);
116 struct dvb_frontend_parameters *fep);
117 116
118static int dib3000mb_set_frontend(struct dvb_frontend* fe, 117static int dib3000mb_set_frontend(struct dvb_frontend *fe, int tuner)
119 struct dvb_frontend_parameters *fep, int tuner)
120{ 118{
121 struct dib3000_state* state = fe->demodulator_priv; 119 struct dib3000_state* state = fe->demodulator_priv;
122 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm; 120 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
123 fe_code_rate_t fe_cr = FEC_NONE; 121 fe_code_rate_t fe_cr = FEC_NONE;
124 int search_state, seq; 122 int search_state, seq;
125 123
126 if (tuner && fe->ops.tuner_ops.set_params) { 124 if (tuner && fe->ops.tuner_ops.set_params) {
127 fe->ops.tuner_ops.set_params(fe, fep); 125 fe->ops.tuner_ops.set_params(fe);
128 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 126 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
129 127
130 deb_setf("bandwidth: "); 128 deb_setf("bandwidth: ");
131 switch (ofdm->bandwidth) { 129 switch (c->bandwidth_hz) {
132 case BANDWIDTH_8_MHZ: 130 case 8000000:
133 deb_setf("8 MHz\n"); 131 deb_setf("8 MHz\n");
134 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]); 132 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
135 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz); 133 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
136 break; 134 break;
137 case BANDWIDTH_7_MHZ: 135 case 7000000:
138 deb_setf("7 MHz\n"); 136 deb_setf("7 MHz\n");
139 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]); 137 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]);
140 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz); 138 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz);
141 break; 139 break;
142 case BANDWIDTH_6_MHZ: 140 case 6000000:
143 deb_setf("6 MHz\n"); 141 deb_setf("6 MHz\n");
144 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]); 142 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]);
145 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz); 143 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz);
146 break; 144 break;
147 case BANDWIDTH_AUTO: 145 case 0:
148 return -EOPNOTSUPP; 146 return -EOPNOTSUPP;
149 default: 147 default:
150 err("unknown bandwidth value."); 148 err("unknown bandwidth value.");
@@ -154,7 +152,7 @@ static int dib3000mb_set_frontend(struct dvb_frontend* fe,
154 wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4); 152 wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
155 153
156 deb_setf("transmission mode: "); 154 deb_setf("transmission mode: ");
157 switch (ofdm->transmission_mode) { 155 switch (c->transmission_mode) {
158 case TRANSMISSION_MODE_2K: 156 case TRANSMISSION_MODE_2K:
159 deb_setf("2k\n"); 157 deb_setf("2k\n");
160 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K); 158 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
@@ -171,7 +169,7 @@ static int dib3000mb_set_frontend(struct dvb_frontend* fe,
171 } 169 }
172 170
173 deb_setf("guard: "); 171 deb_setf("guard: ");
174 switch (ofdm->guard_interval) { 172 switch (c->guard_interval) {
175 case GUARD_INTERVAL_1_32: 173 case GUARD_INTERVAL_1_32:
176 deb_setf("1_32\n"); 174 deb_setf("1_32\n");
177 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32); 175 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
@@ -196,7 +194,7 @@ static int dib3000mb_set_frontend(struct dvb_frontend* fe,
196 } 194 }
197 195
198 deb_setf("inversion: "); 196 deb_setf("inversion: ");
199 switch (fep->inversion) { 197 switch (c->inversion) {
200 case INVERSION_OFF: 198 case INVERSION_OFF:
201 deb_setf("off\n"); 199 deb_setf("off\n");
202 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF); 200 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
@@ -212,8 +210,8 @@ static int dib3000mb_set_frontend(struct dvb_frontend* fe,
212 return -EINVAL; 210 return -EINVAL;
213 } 211 }
214 212
215 deb_setf("constellation: "); 213 deb_setf("modulation: ");
216 switch (ofdm->constellation) { 214 switch (c->modulation) {
217 case QPSK: 215 case QPSK:
218 deb_setf("qpsk\n"); 216 deb_setf("qpsk\n");
219 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK); 217 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
@@ -232,7 +230,7 @@ static int dib3000mb_set_frontend(struct dvb_frontend* fe,
232 return -EINVAL; 230 return -EINVAL;
233 } 231 }
234 deb_setf("hierarchy: "); 232 deb_setf("hierarchy: ");
235 switch (ofdm->hierarchy_information) { 233 switch (c->hierarchy) {
236 case HIERARCHY_NONE: 234 case HIERARCHY_NONE:
237 deb_setf("none "); 235 deb_setf("none ");
238 /* fall through */ 236 /* fall through */
@@ -256,16 +254,16 @@ static int dib3000mb_set_frontend(struct dvb_frontend* fe,
256 } 254 }
257 255
258 deb_setf("hierarchy: "); 256 deb_setf("hierarchy: ");
259 if (ofdm->hierarchy_information == HIERARCHY_NONE) { 257 if (c->hierarchy == HIERARCHY_NONE) {
260 deb_setf("none\n"); 258 deb_setf("none\n");
261 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF); 259 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
262 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP); 260 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
263 fe_cr = ofdm->code_rate_HP; 261 fe_cr = c->code_rate_HP;
264 } else if (ofdm->hierarchy_information != HIERARCHY_AUTO) { 262 } else if (c->hierarchy != HIERARCHY_AUTO) {
265 deb_setf("on\n"); 263 deb_setf("on\n");
266 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON); 264 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
267 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP); 265 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
268 fe_cr = ofdm->code_rate_LP; 266 fe_cr = c->code_rate_LP;
269 } 267 }
270 deb_setf("fec: "); 268 deb_setf("fec: ");
271 switch (fe_cr) { 269 switch (fe_cr) {
@@ -300,9 +298,9 @@ static int dib3000mb_set_frontend(struct dvb_frontend* fe,
300 } 298 }
301 299
302 seq = dib3000_seq 300 seq = dib3000_seq
303 [ofdm->transmission_mode == TRANSMISSION_MODE_AUTO] 301 [c->transmission_mode == TRANSMISSION_MODE_AUTO]
304 [ofdm->guard_interval == GUARD_INTERVAL_AUTO] 302 [c->guard_interval == GUARD_INTERVAL_AUTO]
305 [fep->inversion == INVERSION_AUTO]; 303 [c->inversion == INVERSION_AUTO];
306 304
307 deb_setf("seq? %d\n", seq); 305 deb_setf("seq? %d\n", seq);
308 306
@@ -310,8 +308,8 @@ static int dib3000mb_set_frontend(struct dvb_frontend* fe,
310 308
311 wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE); 309 wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
312 310
313 if (ofdm->transmission_mode == TRANSMISSION_MODE_2K) { 311 if (c->transmission_mode == TRANSMISSION_MODE_2K) {
314 if (ofdm->guard_interval == GUARD_INTERVAL_1_8) { 312 if (c->guard_interval == GUARD_INTERVAL_1_8) {
315 wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8); 313 wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8);
316 } else { 314 } else {
317 wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT); 315 wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT);
@@ -339,10 +337,10 @@ static int dib3000mb_set_frontend(struct dvb_frontend* fe,
339 wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low); 337 wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
340 338
341 /* something has to be auto searched */ 339 /* something has to be auto searched */
342 if (ofdm->constellation == QAM_AUTO || 340 if (c->modulation == QAM_AUTO ||
343 ofdm->hierarchy_information == HIERARCHY_AUTO || 341 c->hierarchy == HIERARCHY_AUTO ||
344 fe_cr == FEC_AUTO || 342 fe_cr == FEC_AUTO ||
345 fep->inversion == INVERSION_AUTO) { 343 c->inversion == INVERSION_AUTO) {
346 int as_count=0; 344 int as_count=0;
347 345
348 deb_setf("autosearch enabled.\n"); 346 deb_setf("autosearch enabled.\n");
@@ -361,10 +359,9 @@ static int dib3000mb_set_frontend(struct dvb_frontend* fe,
361 deb_setf("search_state after autosearch %d after %d checks\n",search_state,as_count); 359 deb_setf("search_state after autosearch %d after %d checks\n",search_state,as_count);
362 360
363 if (search_state == 1) { 361 if (search_state == 1) {
364 struct dvb_frontend_parameters feps; 362 if (dib3000mb_get_frontend(fe) == 0) {
365 if (dib3000mb_get_frontend(fe, &feps) == 0) {
366 deb_setf("reading tuning data from frontend succeeded.\n"); 363 deb_setf("reading tuning data from frontend succeeded.\n");
367 return dib3000mb_set_frontend(fe, &feps, 0); 364 return dib3000mb_set_frontend(fe, 0);
368 } 365 }
369 } 366 }
370 367
@@ -453,11 +450,10 @@ static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
453 return 0; 450 return 0;
454} 451}
455 452
456static int dib3000mb_get_frontend(struct dvb_frontend* fe, 453static int dib3000mb_get_frontend(struct dvb_frontend* fe)
457 struct dvb_frontend_parameters *fep)
458{ 454{
455 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
459 struct dib3000_state* state = fe->demodulator_priv; 456 struct dib3000_state* state = fe->demodulator_priv;
460 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
461 fe_code_rate_t *cr; 457 fe_code_rate_t *cr;
462 u16 tps_val; 458 u16 tps_val;
463 int inv_test1,inv_test2; 459 int inv_test1,inv_test2;
@@ -484,25 +480,25 @@ static int dib3000mb_get_frontend(struct dvb_frontend* fe,
484 else 480 else
485 inv_test2 = 2; 481 inv_test2 = 2;
486 482
487 fep->inversion = 483 c->inversion =
488 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) || 484 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
489 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ? 485 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
490 INVERSION_ON : INVERSION_OFF; 486 INVERSION_ON : INVERSION_OFF;
491 487
492 deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, fep->inversion); 488 deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, c->inversion);
493 489
494 switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) { 490 switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
495 case DIB3000_CONSTELLATION_QPSK: 491 case DIB3000_CONSTELLATION_QPSK:
496 deb_getf("QPSK "); 492 deb_getf("QPSK ");
497 ofdm->constellation = QPSK; 493 c->modulation = QPSK;
498 break; 494 break;
499 case DIB3000_CONSTELLATION_16QAM: 495 case DIB3000_CONSTELLATION_16QAM:
500 deb_getf("QAM16 "); 496 deb_getf("QAM16 ");
501 ofdm->constellation = QAM_16; 497 c->modulation = QAM_16;
502 break; 498 break;
503 case DIB3000_CONSTELLATION_64QAM: 499 case DIB3000_CONSTELLATION_64QAM:
504 deb_getf("QAM64 "); 500 deb_getf("QAM64 ");
505 ofdm->constellation = QAM_64; 501 c->modulation = QAM_64;
506 break; 502 break;
507 default: 503 default:
508 err("Unexpected constellation returned by TPS (%d)", tps_val); 504 err("Unexpected constellation returned by TPS (%d)", tps_val);
@@ -512,24 +508,24 @@ static int dib3000mb_get_frontend(struct dvb_frontend* fe,
512 508
513 if (rd(DIB3000MB_REG_TPS_HRCH)) { 509 if (rd(DIB3000MB_REG_TPS_HRCH)) {
514 deb_getf("HRCH ON\n"); 510 deb_getf("HRCH ON\n");
515 cr = &ofdm->code_rate_LP; 511 cr = &c->code_rate_LP;
516 ofdm->code_rate_HP = FEC_NONE; 512 c->code_rate_HP = FEC_NONE;
517 switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) { 513 switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
518 case DIB3000_ALPHA_0: 514 case DIB3000_ALPHA_0:
519 deb_getf("HIERARCHY_NONE "); 515 deb_getf("HIERARCHY_NONE ");
520 ofdm->hierarchy_information = HIERARCHY_NONE; 516 c->hierarchy = HIERARCHY_NONE;
521 break; 517 break;
522 case DIB3000_ALPHA_1: 518 case DIB3000_ALPHA_1:
523 deb_getf("HIERARCHY_1 "); 519 deb_getf("HIERARCHY_1 ");
524 ofdm->hierarchy_information = HIERARCHY_1; 520 c->hierarchy = HIERARCHY_1;
525 break; 521 break;
526 case DIB3000_ALPHA_2: 522 case DIB3000_ALPHA_2:
527 deb_getf("HIERARCHY_2 "); 523 deb_getf("HIERARCHY_2 ");
528 ofdm->hierarchy_information = HIERARCHY_2; 524 c->hierarchy = HIERARCHY_2;
529 break; 525 break;
530 case DIB3000_ALPHA_4: 526 case DIB3000_ALPHA_4:
531 deb_getf("HIERARCHY_4 "); 527 deb_getf("HIERARCHY_4 ");
532 ofdm->hierarchy_information = HIERARCHY_4; 528 c->hierarchy = HIERARCHY_4;
533 break; 529 break;
534 default: 530 default:
535 err("Unexpected ALPHA value returned by TPS (%d)", tps_val); 531 err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
@@ -540,9 +536,9 @@ static int dib3000mb_get_frontend(struct dvb_frontend* fe,
540 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP); 536 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
541 } else { 537 } else {
542 deb_getf("HRCH OFF\n"); 538 deb_getf("HRCH OFF\n");
543 cr = &ofdm->code_rate_HP; 539 cr = &c->code_rate_HP;
544 ofdm->code_rate_LP = FEC_NONE; 540 c->code_rate_LP = FEC_NONE;
545 ofdm->hierarchy_information = HIERARCHY_NONE; 541 c->hierarchy = HIERARCHY_NONE;
546 542
547 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP); 543 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
548 } 544 }
@@ -577,19 +573,19 @@ static int dib3000mb_get_frontend(struct dvb_frontend* fe,
577 switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) { 573 switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
578 case DIB3000_GUARD_TIME_1_32: 574 case DIB3000_GUARD_TIME_1_32:
579 deb_getf("GUARD_INTERVAL_1_32 "); 575 deb_getf("GUARD_INTERVAL_1_32 ");
580 ofdm->guard_interval = GUARD_INTERVAL_1_32; 576 c->guard_interval = GUARD_INTERVAL_1_32;
581 break; 577 break;
582 case DIB3000_GUARD_TIME_1_16: 578 case DIB3000_GUARD_TIME_1_16:
583 deb_getf("GUARD_INTERVAL_1_16 "); 579 deb_getf("GUARD_INTERVAL_1_16 ");
584 ofdm->guard_interval = GUARD_INTERVAL_1_16; 580 c->guard_interval = GUARD_INTERVAL_1_16;
585 break; 581 break;
586 case DIB3000_GUARD_TIME_1_8: 582 case DIB3000_GUARD_TIME_1_8:
587 deb_getf("GUARD_INTERVAL_1_8 "); 583 deb_getf("GUARD_INTERVAL_1_8 ");
588 ofdm->guard_interval = GUARD_INTERVAL_1_8; 584 c->guard_interval = GUARD_INTERVAL_1_8;
589 break; 585 break;
590 case DIB3000_GUARD_TIME_1_4: 586 case DIB3000_GUARD_TIME_1_4:
591 deb_getf("GUARD_INTERVAL_1_4 "); 587 deb_getf("GUARD_INTERVAL_1_4 ");
592 ofdm->guard_interval = GUARD_INTERVAL_1_4; 588 c->guard_interval = GUARD_INTERVAL_1_4;
593 break; 589 break;
594 default: 590 default:
595 err("Unexpected Guard Time returned by TPS (%d)", tps_val); 591 err("Unexpected Guard Time returned by TPS (%d)", tps_val);
@@ -600,11 +596,11 @@ static int dib3000mb_get_frontend(struct dvb_frontend* fe,
600 switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) { 596 switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
601 case DIB3000_TRANSMISSION_MODE_2K: 597 case DIB3000_TRANSMISSION_MODE_2K:
602 deb_getf("TRANSMISSION_MODE_2K "); 598 deb_getf("TRANSMISSION_MODE_2K ");
603 ofdm->transmission_mode = TRANSMISSION_MODE_2K; 599 c->transmission_mode = TRANSMISSION_MODE_2K;
604 break; 600 break;
605 case DIB3000_TRANSMISSION_MODE_8K: 601 case DIB3000_TRANSMISSION_MODE_8K:
606 deb_getf("TRANSMISSION_MODE_8K "); 602 deb_getf("TRANSMISSION_MODE_8K ");
607 ofdm->transmission_mode = TRANSMISSION_MODE_8K; 603 c->transmission_mode = TRANSMISSION_MODE_8K;
608 break; 604 break;
609 default: 605 default:
610 err("unexpected transmission mode return by TPS (%d)", tps_val); 606 err("unexpected transmission mode return by TPS (%d)", tps_val);
@@ -701,9 +697,9 @@ static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe)
701 return dib3000mb_fe_init(fe, 0); 697 return dib3000mb_fe_init(fe, 0);
702} 698}
703 699
704static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend* fe, struct dvb_frontend_parameters *fep) 700static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend *fe)
705{ 701{
706 return dib3000mb_set_frontend(fe, fep, 1); 702 return dib3000mb_set_frontend(fe, 1);
707} 703}
708 704
709static void dib3000mb_release(struct dvb_frontend* fe) 705static void dib3000mb_release(struct dvb_frontend* fe)
@@ -794,10 +790,9 @@ error:
794} 790}
795 791
796static struct dvb_frontend_ops dib3000mb_ops = { 792static struct dvb_frontend_ops dib3000mb_ops = {
797 793 .delsys = { SYS_DVBT },
798 .info = { 794 .info = {
799 .name = "DiBcom 3000M-B DVB-T", 795 .name = "DiBcom 3000M-B DVB-T",
800 .type = FE_OFDM,
801 .frequency_min = 44250000, 796 .frequency_min = 44250000,
802 .frequency_max = 867250000, 797 .frequency_max = 867250000,
803 .frequency_stepsize = 62500, 798 .frequency_stepsize = 62500,
diff --git a/drivers/media/dvb/frontends/dib3000mb_priv.h b/drivers/media/dvb/frontends/dib3000mb_priv.h
index 16c526591f36..9dc235aa44b7 100644
--- a/drivers/media/dvb/frontends/dib3000mb_priv.h
+++ b/drivers/media/dvb/frontends/dib3000mb_priv.h
@@ -98,7 +98,7 @@ struct dib3000_state {
98 int timing_offset; 98 int timing_offset;
99 int timing_offset_comp_done; 99 int timing_offset_comp_done;
100 100
101 fe_bandwidth_t last_tuned_bw; 101 u32 last_tuned_bw;
102 u32 last_tuned_freq; 102 u32 last_tuned_freq;
103}; 103};
104 104
diff --git a/drivers/media/dvb/frontends/dib3000mc.c b/drivers/media/dvb/frontends/dib3000mc.c
index 088e7fadbe3d..ffad181a9692 100644
--- a/drivers/media/dvb/frontends/dib3000mc.c
+++ b/drivers/media/dvb/frontends/dib3000mc.c
@@ -40,7 +40,7 @@ struct dib3000mc_state {
40 40
41 u32 timf; 41 u32 timf;
42 42
43 fe_bandwidth_t current_bandwidth; 43 u32 current_bandwidth;
44 44
45 u16 dev_id; 45 u16 dev_id;
46 46
@@ -438,11 +438,14 @@ static void dib3000mc_set_adp_cfg(struct dib3000mc_state *state, s16 qam)
438 dib3000mc_write_word(state, reg, cfg[reg - 129]); 438 dib3000mc_write_word(state, reg, cfg[reg - 129]);
439} 439}
440 440
441static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dvb_frontend_parameters *ch, u16 seq) 441static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state,
442 struct dtv_frontend_properties *ch, u16 seq)
442{ 443{
443 u16 value; 444 u16 value;
444 dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)); 445 u32 bw = BANDWIDTH_TO_KHZ(ch->bandwidth_hz);
445 dib3000mc_set_timing(state, ch->u.ofdm.transmission_mode, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth), 0); 446
447 dib3000mc_set_bandwidth(state, bw);
448 dib3000mc_set_timing(state, ch->transmission_mode, bw, 0);
446 449
447// if (boost) 450// if (boost)
448// dib3000mc_write_word(state, 100, (11 << 6) + 6); 451// dib3000mc_write_word(state, 100, (11 << 6) + 6);
@@ -471,22 +474,22 @@ static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dvb_
471 dib3000mc_write_word(state, 97,0); 474 dib3000mc_write_word(state, 97,0);
472 dib3000mc_write_word(state, 98,0); 475 dib3000mc_write_word(state, 98,0);
473 476
474 dib3000mc_set_impulse_noise(state, 0, ch->u.ofdm.transmission_mode); 477 dib3000mc_set_impulse_noise(state, 0, ch->transmission_mode);
475 478
476 value = 0; 479 value = 0;
477 switch (ch->u.ofdm.transmission_mode) { 480 switch (ch->transmission_mode) {
478 case TRANSMISSION_MODE_2K: value |= (0 << 7); break; 481 case TRANSMISSION_MODE_2K: value |= (0 << 7); break;
479 default: 482 default:
480 case TRANSMISSION_MODE_8K: value |= (1 << 7); break; 483 case TRANSMISSION_MODE_8K: value |= (1 << 7); break;
481 } 484 }
482 switch (ch->u.ofdm.guard_interval) { 485 switch (ch->guard_interval) {
483 case GUARD_INTERVAL_1_32: value |= (0 << 5); break; 486 case GUARD_INTERVAL_1_32: value |= (0 << 5); break;
484 case GUARD_INTERVAL_1_16: value |= (1 << 5); break; 487 case GUARD_INTERVAL_1_16: value |= (1 << 5); break;
485 case GUARD_INTERVAL_1_4: value |= (3 << 5); break; 488 case GUARD_INTERVAL_1_4: value |= (3 << 5); break;
486 default: 489 default:
487 case GUARD_INTERVAL_1_8: value |= (2 << 5); break; 490 case GUARD_INTERVAL_1_8: value |= (2 << 5); break;
488 } 491 }
489 switch (ch->u.ofdm.constellation) { 492 switch (ch->modulation) {
490 case QPSK: value |= (0 << 3); break; 493 case QPSK: value |= (0 << 3); break;
491 case QAM_16: value |= (1 << 3); break; 494 case QAM_16: value |= (1 << 3); break;
492 default: 495 default:
@@ -502,11 +505,11 @@ static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dvb_
502 dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4)); 505 dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4));
503 506
504 value = 0; 507 value = 0;
505 if (ch->u.ofdm.hierarchy_information == 1) 508 if (ch->hierarchy == 1)
506 value |= (1 << 4); 509 value |= (1 << 4);
507 if (1 == 1) 510 if (1 == 1)
508 value |= 1; 511 value |= 1;
509 switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) { 512 switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
510 case FEC_2_3: value |= (2 << 1); break; 513 case FEC_2_3: value |= (2 << 1); break;
511 case FEC_3_4: value |= (3 << 1); break; 514 case FEC_3_4: value |= (3 << 1); break;
512 case FEC_5_6: value |= (5 << 1); break; 515 case FEC_5_6: value |= (5 << 1); break;
@@ -517,12 +520,12 @@ static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dvb_
517 dib3000mc_write_word(state, 181, value); 520 dib3000mc_write_word(state, 181, value);
518 521
519 // diversity synchro delay add 50% SFN margin 522 // diversity synchro delay add 50% SFN margin
520 switch (ch->u.ofdm.transmission_mode) { 523 switch (ch->transmission_mode) {
521 case TRANSMISSION_MODE_8K: value = 256; break; 524 case TRANSMISSION_MODE_8K: value = 256; break;
522 case TRANSMISSION_MODE_2K: 525 case TRANSMISSION_MODE_2K:
523 default: value = 64; break; 526 default: value = 64; break;
524 } 527 }
525 switch (ch->u.ofdm.guard_interval) { 528 switch (ch->guard_interval) {
526 case GUARD_INTERVAL_1_16: value *= 2; break; 529 case GUARD_INTERVAL_1_16: value *= 2; break;
527 case GUARD_INTERVAL_1_8: value *= 4; break; 530 case GUARD_INTERVAL_1_8: value *= 4; break;
528 case GUARD_INTERVAL_1_4: value *= 8; break; 531 case GUARD_INTERVAL_1_4: value *= 8; break;
@@ -540,27 +543,28 @@ static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dvb_
540 543
541 msleep(30); 544 msleep(30);
542 545
543 dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, ch->u.ofdm.transmission_mode); 546 dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, ch->transmission_mode);
544} 547}
545 548
546static int dib3000mc_autosearch_start(struct dvb_frontend *demod, struct dvb_frontend_parameters *chan) 549static int dib3000mc_autosearch_start(struct dvb_frontend *demod)
547{ 550{
551 struct dtv_frontend_properties *chan = &demod->dtv_property_cache;
548 struct dib3000mc_state *state = demod->demodulator_priv; 552 struct dib3000mc_state *state = demod->demodulator_priv;
549 u16 reg; 553 u16 reg;
550// u32 val; 554// u32 val;
551 struct dvb_frontend_parameters schan; 555 struct dtv_frontend_properties schan;
552 556
553 schan = *chan; 557 schan = *chan;
554 558
555 /* TODO what is that ? */ 559 /* TODO what is that ? */
556 560
557 /* a channel for autosearch */ 561 /* a channel for autosearch */
558 schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; 562 schan.transmission_mode = TRANSMISSION_MODE_8K;
559 schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32; 563 schan.guard_interval = GUARD_INTERVAL_1_32;
560 schan.u.ofdm.constellation = QAM_64; 564 schan.modulation = QAM_64;
561 schan.u.ofdm.code_rate_HP = FEC_2_3; 565 schan.code_rate_HP = FEC_2_3;
562 schan.u.ofdm.code_rate_LP = FEC_2_3; 566 schan.code_rate_LP = FEC_2_3;
563 schan.u.ofdm.hierarchy_information = 0; 567 schan.hierarchy = 0;
564 568
565 dib3000mc_set_channel_cfg(state, &schan, 11); 569 dib3000mc_set_channel_cfg(state, &schan, 11);
566 570
@@ -586,8 +590,9 @@ static int dib3000mc_autosearch_is_irq(struct dvb_frontend *demod)
586 return 0; // still pending 590 return 0; // still pending
587} 591}
588 592
589static int dib3000mc_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch) 593static int dib3000mc_tune(struct dvb_frontend *demod)
590{ 594{
595 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
591 struct dib3000mc_state *state = demod->demodulator_priv; 596 struct dib3000mc_state *state = demod->demodulator_priv;
592 597
593 // ** configure demod ** 598 // ** configure demod **
@@ -603,8 +608,8 @@ static int dib3000mc_tune(struct dvb_frontend *demod, struct dvb_frontend_parame
603 dib3000mc_write_word(state, 108, 0x0000); // P_pha3_force_pha_shift 608 dib3000mc_write_word(state, 108, 0x0000); // P_pha3_force_pha_shift
604 } 609 }
605 610
606 dib3000mc_set_adp_cfg(state, (u8)ch->u.ofdm.constellation); 611 dib3000mc_set_adp_cfg(state, (u8)ch->modulation);
607 if (ch->u.ofdm.transmission_mode == TRANSMISSION_MODE_8K) { 612 if (ch->transmission_mode == TRANSMISSION_MODE_8K) {
608 dib3000mc_write_word(state, 26, 38528); 613 dib3000mc_write_word(state, 26, 38528);
609 dib3000mc_write_word(state, 33, 8); 614 dib3000mc_write_word(state, 33, 8);
610 } else { 615 } else {
@@ -613,7 +618,8 @@ static int dib3000mc_tune(struct dvb_frontend *demod, struct dvb_frontend_parame
613 } 618 }
614 619
615 if (dib3000mc_read_word(state, 509) & 0x80) 620 if (dib3000mc_read_word(state, 509) & 0x80)
616 dib3000mc_set_timing(state, ch->u.ofdm.transmission_mode, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth), 1); 621 dib3000mc_set_timing(state, ch->transmission_mode,
622 BANDWIDTH_TO_KHZ(ch->bandwidth_hz), 1);
617 623
618 return 0; 624 return 0;
619} 625}
@@ -626,87 +632,87 @@ struct i2c_adapter * dib3000mc_get_tuner_i2c_master(struct dvb_frontend *demod,
626 632
627EXPORT_SYMBOL(dib3000mc_get_tuner_i2c_master); 633EXPORT_SYMBOL(dib3000mc_get_tuner_i2c_master);
628 634
629static int dib3000mc_get_frontend(struct dvb_frontend* fe, 635static int dib3000mc_get_frontend(struct dvb_frontend* fe)
630 struct dvb_frontend_parameters *fep)
631{ 636{
637 struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
632 struct dib3000mc_state *state = fe->demodulator_priv; 638 struct dib3000mc_state *state = fe->demodulator_priv;
633 u16 tps = dib3000mc_read_word(state,458); 639 u16 tps = dib3000mc_read_word(state,458);
634 640
635 fep->inversion = INVERSION_AUTO; 641 fep->inversion = INVERSION_AUTO;
636 642
637 fep->u.ofdm.bandwidth = state->current_bandwidth; 643 fep->bandwidth_hz = state->current_bandwidth;
638 644
639 switch ((tps >> 8) & 0x1) { 645 switch ((tps >> 8) & 0x1) {
640 case 0: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; break; 646 case 0: fep->transmission_mode = TRANSMISSION_MODE_2K; break;
641 case 1: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; break; 647 case 1: fep->transmission_mode = TRANSMISSION_MODE_8K; break;
642 } 648 }
643 649
644 switch (tps & 0x3) { 650 switch (tps & 0x3) {
645 case 0: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; break; 651 case 0: fep->guard_interval = GUARD_INTERVAL_1_32; break;
646 case 1: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; break; 652 case 1: fep->guard_interval = GUARD_INTERVAL_1_16; break;
647 case 2: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; break; 653 case 2: fep->guard_interval = GUARD_INTERVAL_1_8; break;
648 case 3: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; break; 654 case 3: fep->guard_interval = GUARD_INTERVAL_1_4; break;
649 } 655 }
650 656
651 switch ((tps >> 13) & 0x3) { 657 switch ((tps >> 13) & 0x3) {
652 case 0: fep->u.ofdm.constellation = QPSK; break; 658 case 0: fep->modulation = QPSK; break;
653 case 1: fep->u.ofdm.constellation = QAM_16; break; 659 case 1: fep->modulation = QAM_16; break;
654 case 2: 660 case 2:
655 default: fep->u.ofdm.constellation = QAM_64; break; 661 default: fep->modulation = QAM_64; break;
656 } 662 }
657 663
658 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */ 664 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
659 /* (tps >> 12) & 0x1 == hrch is used, (tps >> 9) & 0x7 == alpha */ 665 /* (tps >> 12) & 0x1 == hrch is used, (tps >> 9) & 0x7 == alpha */
660 666
661 fep->u.ofdm.hierarchy_information = HIERARCHY_NONE; 667 fep->hierarchy = HIERARCHY_NONE;
662 switch ((tps >> 5) & 0x7) { 668 switch ((tps >> 5) & 0x7) {
663 case 1: fep->u.ofdm.code_rate_HP = FEC_1_2; break; 669 case 1: fep->code_rate_HP = FEC_1_2; break;
664 case 2: fep->u.ofdm.code_rate_HP = FEC_2_3; break; 670 case 2: fep->code_rate_HP = FEC_2_3; break;
665 case 3: fep->u.ofdm.code_rate_HP = FEC_3_4; break; 671 case 3: fep->code_rate_HP = FEC_3_4; break;
666 case 5: fep->u.ofdm.code_rate_HP = FEC_5_6; break; 672 case 5: fep->code_rate_HP = FEC_5_6; break;
667 case 7: 673 case 7:
668 default: fep->u.ofdm.code_rate_HP = FEC_7_8; break; 674 default: fep->code_rate_HP = FEC_7_8; break;
669 675
670 } 676 }
671 677
672 switch ((tps >> 2) & 0x7) { 678 switch ((tps >> 2) & 0x7) {
673 case 1: fep->u.ofdm.code_rate_LP = FEC_1_2; break; 679 case 1: fep->code_rate_LP = FEC_1_2; break;
674 case 2: fep->u.ofdm.code_rate_LP = FEC_2_3; break; 680 case 2: fep->code_rate_LP = FEC_2_3; break;
675 case 3: fep->u.ofdm.code_rate_LP = FEC_3_4; break; 681 case 3: fep->code_rate_LP = FEC_3_4; break;
676 case 5: fep->u.ofdm.code_rate_LP = FEC_5_6; break; 682 case 5: fep->code_rate_LP = FEC_5_6; break;
677 case 7: 683 case 7:
678 default: fep->u.ofdm.code_rate_LP = FEC_7_8; break; 684 default: fep->code_rate_LP = FEC_7_8; break;
679 } 685 }
680 686
681 return 0; 687 return 0;
682} 688}
683 689
684static int dib3000mc_set_frontend(struct dvb_frontend* fe, 690static int dib3000mc_set_frontend(struct dvb_frontend *fe)
685 struct dvb_frontend_parameters *fep)
686{ 691{
692 struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
687 struct dib3000mc_state *state = fe->demodulator_priv; 693 struct dib3000mc_state *state = fe->demodulator_priv;
688 int ret; 694 int ret;
689 695
690 dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z); 696 dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z);
691 697
692 state->current_bandwidth = fep->u.ofdm.bandwidth; 698 state->current_bandwidth = fep->bandwidth_hz;
693 dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->u.ofdm.bandwidth)); 699 dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz));
694 700
695 /* maybe the parameter has been changed */ 701 /* maybe the parameter has been changed */
696 state->sfn_workaround_active = buggy_sfn_workaround; 702 state->sfn_workaround_active = buggy_sfn_workaround;
697 703
698 if (fe->ops.tuner_ops.set_params) { 704 if (fe->ops.tuner_ops.set_params) {
699 fe->ops.tuner_ops.set_params(fe, fep); 705 fe->ops.tuner_ops.set_params(fe);
700 msleep(100); 706 msleep(100);
701 } 707 }
702 708
703 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO || 709 if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
704 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || 710 fep->guard_interval == GUARD_INTERVAL_AUTO ||
705 fep->u.ofdm.constellation == QAM_AUTO || 711 fep->modulation == QAM_AUTO ||
706 fep->u.ofdm.code_rate_HP == FEC_AUTO) { 712 fep->code_rate_HP == FEC_AUTO) {
707 int i = 1000, found; 713 int i = 1000, found;
708 714
709 dib3000mc_autosearch_start(fe, fep); 715 dib3000mc_autosearch_start(fe);
710 do { 716 do {
711 msleep(1); 717 msleep(1);
712 found = dib3000mc_autosearch_is_irq(fe); 718 found = dib3000mc_autosearch_is_irq(fe);
@@ -716,14 +722,14 @@ static int dib3000mc_set_frontend(struct dvb_frontend* fe,
716 if (found == 0 || found == 1) 722 if (found == 0 || found == 1)
717 return 0; // no channel found 723 return 0; // no channel found
718 724
719 dib3000mc_get_frontend(fe, fep); 725 dib3000mc_get_frontend(fe);
720 } 726 }
721 727
722 ret = dib3000mc_tune(fe, fep); 728 ret = dib3000mc_tune(fe);
723 729
724 /* make this a config parameter */ 730 /* make this a config parameter */
725 dib3000mc_set_output_mode(state, OUTMODE_MPEG2_FIFO); 731 dib3000mc_set_output_mode(state, OUTMODE_MPEG2_FIFO);
726 return ret; 732 return ret;
727} 733}
728 734
729static int dib3000mc_read_status(struct dvb_frontend *fe, fe_status_t *stat) 735static int dib3000mc_read_status(struct dvb_frontend *fe, fe_status_t *stat)
@@ -897,9 +903,9 @@ error:
897EXPORT_SYMBOL(dib3000mc_attach); 903EXPORT_SYMBOL(dib3000mc_attach);
898 904
899static struct dvb_frontend_ops dib3000mc_ops = { 905static struct dvb_frontend_ops dib3000mc_ops = {
906 .delsys = { SYS_DVBT },
900 .info = { 907 .info = {
901 .name = "DiBcom 3000MC/P", 908 .name = "DiBcom 3000MC/P",
902 .type = FE_OFDM,
903 .frequency_min = 44250000, 909 .frequency_min = 44250000,
904 .frequency_max = 867250000, 910 .frequency_max = 867250000,
905 .frequency_stepsize = 62500, 911 .frequency_stepsize = 62500,
diff --git a/drivers/media/dvb/frontends/dib7000m.c b/drivers/media/dvb/frontends/dib7000m.c
index dbb76d75c932..148bf79236fb 100644
--- a/drivers/media/dvb/frontends/dib7000m.c
+++ b/drivers/media/dvb/frontends/dib7000m.c
@@ -38,7 +38,7 @@ struct dib7000m_state {
38 u16 wbd_ref; 38 u16 wbd_ref;
39 39
40 u8 current_band; 40 u8 current_band;
41 fe_bandwidth_t current_bandwidth; 41 u32 current_bandwidth;
42 struct dibx000_agc_config *current_agc; 42 struct dibx000_agc_config *current_agc;
43 u32 timf; 43 u32 timf;
44 u32 timf_default; 44 u32 timf_default;
@@ -313,6 +313,9 @@ static int dib7000m_set_bandwidth(struct dib7000m_state *state, u32 bw)
313{ 313{
314 u32 timf; 314 u32 timf;
315 315
316 if (!bw)
317 bw = 8000;
318
316 // store the current bandwidth for later use 319 // store the current bandwidth for later use
317 state->current_bandwidth = bw; 320 state->current_bandwidth = bw;
318 321
@@ -742,8 +745,9 @@ static void dib7000m_update_timf(struct dib7000m_state *state)
742 dprintk( "updated timf_frequency: %d (default: %d)",state->timf, state->timf_default); 745 dprintk( "updated timf_frequency: %d (default: %d)",state->timf, state->timf_default);
743} 746}
744 747
745static int dib7000m_agc_startup(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch) 748static int dib7000m_agc_startup(struct dvb_frontend *demod)
746{ 749{
750 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
747 struct dib7000m_state *state = demod->demodulator_priv; 751 struct dib7000m_state *state = demod->demodulator_priv;
748 u16 cfg_72 = dib7000m_read_word(state, 72); 752 u16 cfg_72 = dib7000m_read_word(state, 72);
749 int ret = -1; 753 int ret = -1;
@@ -832,28 +836,29 @@ static int dib7000m_agc_startup(struct dvb_frontend *demod, struct dvb_frontend_
832 return ret; 836 return ret;
833} 837}
834 838
835static void dib7000m_set_channel(struct dib7000m_state *state, struct dvb_frontend_parameters *ch, u8 seq) 839static void dib7000m_set_channel(struct dib7000m_state *state, struct dtv_frontend_properties *ch,
840 u8 seq)
836{ 841{
837 u16 value, est[4]; 842 u16 value, est[4];
838 843
839 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)); 844 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
840 845
841 /* nfft, guard, qam, alpha */ 846 /* nfft, guard, qam, alpha */
842 value = 0; 847 value = 0;
843 switch (ch->u.ofdm.transmission_mode) { 848 switch (ch->transmission_mode) {
844 case TRANSMISSION_MODE_2K: value |= (0 << 7); break; 849 case TRANSMISSION_MODE_2K: value |= (0 << 7); break;
845 case TRANSMISSION_MODE_4K: value |= (2 << 7); break; 850 case TRANSMISSION_MODE_4K: value |= (2 << 7); break;
846 default: 851 default:
847 case TRANSMISSION_MODE_8K: value |= (1 << 7); break; 852 case TRANSMISSION_MODE_8K: value |= (1 << 7); break;
848 } 853 }
849 switch (ch->u.ofdm.guard_interval) { 854 switch (ch->guard_interval) {
850 case GUARD_INTERVAL_1_32: value |= (0 << 5); break; 855 case GUARD_INTERVAL_1_32: value |= (0 << 5); break;
851 case GUARD_INTERVAL_1_16: value |= (1 << 5); break; 856 case GUARD_INTERVAL_1_16: value |= (1 << 5); break;
852 case GUARD_INTERVAL_1_4: value |= (3 << 5); break; 857 case GUARD_INTERVAL_1_4: value |= (3 << 5); break;
853 default: 858 default:
854 case GUARD_INTERVAL_1_8: value |= (2 << 5); break; 859 case GUARD_INTERVAL_1_8: value |= (2 << 5); break;
855 } 860 }
856 switch (ch->u.ofdm.constellation) { 861 switch (ch->modulation) {
857 case QPSK: value |= (0 << 3); break; 862 case QPSK: value |= (0 << 3); break;
858 case QAM_16: value |= (1 << 3); break; 863 case QAM_16: value |= (1 << 3); break;
859 default: 864 default:
@@ -872,11 +877,11 @@ static void dib7000m_set_channel(struct dib7000m_state *state, struct dvb_fronte
872 value = 0; 877 value = 0;
873 if (1 != 0) 878 if (1 != 0)
874 value |= (1 << 6); 879 value |= (1 << 6);
875 if (ch->u.ofdm.hierarchy_information == 1) 880 if (ch->hierarchy == 1)
876 value |= (1 << 4); 881 value |= (1 << 4);
877 if (1 == 1) 882 if (1 == 1)
878 value |= 1; 883 value |= 1;
879 switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) { 884 switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
880 case FEC_2_3: value |= (2 << 1); break; 885 case FEC_2_3: value |= (2 << 1); break;
881 case FEC_3_4: value |= (3 << 1); break; 886 case FEC_3_4: value |= (3 << 1); break;
882 case FEC_5_6: value |= (5 << 1); break; 887 case FEC_5_6: value |= (5 << 1); break;
@@ -901,13 +906,13 @@ static void dib7000m_set_channel(struct dib7000m_state *state, struct dvb_fronte
901 dib7000m_write_word(state, 33, (0 << 4) | 0x5); 906 dib7000m_write_word(state, 33, (0 << 4) | 0x5);
902 907
903 /* P_dvsy_sync_wait */ 908 /* P_dvsy_sync_wait */
904 switch (ch->u.ofdm.transmission_mode) { 909 switch (ch->transmission_mode) {
905 case TRANSMISSION_MODE_8K: value = 256; break; 910 case TRANSMISSION_MODE_8K: value = 256; break;
906 case TRANSMISSION_MODE_4K: value = 128; break; 911 case TRANSMISSION_MODE_4K: value = 128; break;
907 case TRANSMISSION_MODE_2K: 912 case TRANSMISSION_MODE_2K:
908 default: value = 64; break; 913 default: value = 64; break;
909 } 914 }
910 switch (ch->u.ofdm.guard_interval) { 915 switch (ch->guard_interval) {
911 case GUARD_INTERVAL_1_16: value *= 2; break; 916 case GUARD_INTERVAL_1_16: value *= 2; break;
912 case GUARD_INTERVAL_1_8: value *= 4; break; 917 case GUARD_INTERVAL_1_8: value *= 4; break;
913 case GUARD_INTERVAL_1_4: value *= 8; break; 918 case GUARD_INTERVAL_1_4: value *= 8; break;
@@ -925,7 +930,7 @@ static void dib7000m_set_channel(struct dib7000m_state *state, struct dvb_fronte
925 dib7000m_set_diversity_in(&state->demod, state->div_state); 930 dib7000m_set_diversity_in(&state->demod, state->div_state);
926 931
927 /* channel estimation fine configuration */ 932 /* channel estimation fine configuration */
928 switch (ch->u.ofdm.constellation) { 933 switch (ch->modulation) {
929 case QAM_64: 934 case QAM_64:
930 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */ 935 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
931 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */ 936 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
@@ -952,25 +957,26 @@ static void dib7000m_set_channel(struct dib7000m_state *state, struct dvb_fronte
952 dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD); 957 dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD);
953} 958}
954 959
955static int dib7000m_autosearch_start(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch) 960static int dib7000m_autosearch_start(struct dvb_frontend *demod)
956{ 961{
962 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
957 struct dib7000m_state *state = demod->demodulator_priv; 963 struct dib7000m_state *state = demod->demodulator_priv;
958 struct dvb_frontend_parameters schan; 964 struct dtv_frontend_properties schan;
959 int ret = 0; 965 int ret = 0;
960 u32 value, factor; 966 u32 value, factor;
961 967
962 schan = *ch; 968 schan = *ch;
963 969
964 schan.u.ofdm.constellation = QAM_64; 970 schan.modulation = QAM_64;
965 schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32; 971 schan.guard_interval = GUARD_INTERVAL_1_32;
966 schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; 972 schan.transmission_mode = TRANSMISSION_MODE_8K;
967 schan.u.ofdm.code_rate_HP = FEC_2_3; 973 schan.code_rate_HP = FEC_2_3;
968 schan.u.ofdm.code_rate_LP = FEC_3_4; 974 schan.code_rate_LP = FEC_3_4;
969 schan.u.ofdm.hierarchy_information = 0; 975 schan.hierarchy = 0;
970 976
971 dib7000m_set_channel(state, &schan, 7); 977 dib7000m_set_channel(state, &schan, 7);
972 978
973 factor = BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth); 979 factor = BANDWIDTH_TO_KHZ(schan.bandwidth_hz);
974 if (factor >= 5000) 980 if (factor >= 5000)
975 factor = 1; 981 factor = 1;
976 else 982 else
@@ -1027,8 +1033,9 @@ static int dib7000m_autosearch_is_irq(struct dvb_frontend *demod)
1027 return dib7000m_autosearch_irq(state, 537); 1033 return dib7000m_autosearch_irq(state, 537);
1028} 1034}
1029 1035
1030static int dib7000m_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch) 1036static int dib7000m_tune(struct dvb_frontend *demod)
1031{ 1037{
1038 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
1032 struct dib7000m_state *state = demod->demodulator_priv; 1039 struct dib7000m_state *state = demod->demodulator_priv;
1033 int ret = 0; 1040 int ret = 0;
1034 u16 value; 1041 u16 value;
@@ -1055,7 +1062,7 @@ static int dib7000m_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
1055 //dump_reg(state); 1062 //dump_reg(state);
1056 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */ 1063 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
1057 value = (6 << 8) | 0x80; 1064 value = (6 << 8) | 0x80;
1058 switch (ch->u.ofdm.transmission_mode) { 1065 switch (ch->transmission_mode) {
1059 case TRANSMISSION_MODE_2K: value |= (7 << 12); break; 1066 case TRANSMISSION_MODE_2K: value |= (7 << 12); break;
1060 case TRANSMISSION_MODE_4K: value |= (8 << 12); break; 1067 case TRANSMISSION_MODE_4K: value |= (8 << 12); break;
1061 default: 1068 default:
@@ -1065,7 +1072,7 @@ static int dib7000m_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
1065 1072
1066 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */ 1073 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
1067 value = (0 << 4); 1074 value = (0 << 4);
1068 switch (ch->u.ofdm.transmission_mode) { 1075 switch (ch->transmission_mode) {
1069 case TRANSMISSION_MODE_2K: value |= 0x6; break; 1076 case TRANSMISSION_MODE_2K: value |= 0x6; break;
1070 case TRANSMISSION_MODE_4K: value |= 0x7; break; 1077 case TRANSMISSION_MODE_4K: value |= 0x7; break;
1071 default: 1078 default:
@@ -1075,7 +1082,7 @@ static int dib7000m_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
1075 1082
1076 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */ 1083 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
1077 value = (0 << 4); 1084 value = (0 << 4);
1078 switch (ch->u.ofdm.transmission_mode) { 1085 switch (ch->transmission_mode) {
1079 case TRANSMISSION_MODE_2K: value |= 0x6; break; 1086 case TRANSMISSION_MODE_2K: value |= 0x6; break;
1080 case TRANSMISSION_MODE_4K: value |= 0x7; break; 1087 case TRANSMISSION_MODE_4K: value |= 0x7; break;
1081 default: 1088 default:
@@ -1087,7 +1094,7 @@ static int dib7000m_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
1087 if ((dib7000m_read_word(state, 535) >> 6) & 0x1) 1094 if ((dib7000m_read_word(state, 535) >> 6) & 0x1)
1088 dib7000m_update_timf(state); 1095 dib7000m_update_timf(state);
1089 1096
1090 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)); 1097 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
1091 return ret; 1098 return ret;
1092} 1099}
1093 1100
@@ -1147,57 +1154,57 @@ static int dib7000m_identify(struct dib7000m_state *state)
1147} 1154}
1148 1155
1149 1156
1150static int dib7000m_get_frontend(struct dvb_frontend* fe, 1157static int dib7000m_get_frontend(struct dvb_frontend* fe)
1151 struct dvb_frontend_parameters *fep)
1152{ 1158{
1159 struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
1153 struct dib7000m_state *state = fe->demodulator_priv; 1160 struct dib7000m_state *state = fe->demodulator_priv;
1154 u16 tps = dib7000m_read_word(state,480); 1161 u16 tps = dib7000m_read_word(state,480);
1155 1162
1156 fep->inversion = INVERSION_AUTO; 1163 fep->inversion = INVERSION_AUTO;
1157 1164
1158 fep->u.ofdm.bandwidth = state->current_bandwidth; 1165 fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth);
1159 1166
1160 switch ((tps >> 8) & 0x3) { 1167 switch ((tps >> 8) & 0x3) {
1161 case 0: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; break; 1168 case 0: fep->transmission_mode = TRANSMISSION_MODE_2K; break;
1162 case 1: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; break; 1169 case 1: fep->transmission_mode = TRANSMISSION_MODE_8K; break;
1163 /* case 2: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_4K; break; */ 1170 /* case 2: fep->transmission_mode = TRANSMISSION_MODE_4K; break; */
1164 } 1171 }
1165 1172
1166 switch (tps & 0x3) { 1173 switch (tps & 0x3) {
1167 case 0: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; break; 1174 case 0: fep->guard_interval = GUARD_INTERVAL_1_32; break;
1168 case 1: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; break; 1175 case 1: fep->guard_interval = GUARD_INTERVAL_1_16; break;
1169 case 2: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; break; 1176 case 2: fep->guard_interval = GUARD_INTERVAL_1_8; break;
1170 case 3: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; break; 1177 case 3: fep->guard_interval = GUARD_INTERVAL_1_4; break;
1171 } 1178 }
1172 1179
1173 switch ((tps >> 14) & 0x3) { 1180 switch ((tps >> 14) & 0x3) {
1174 case 0: fep->u.ofdm.constellation = QPSK; break; 1181 case 0: fep->modulation = QPSK; break;
1175 case 1: fep->u.ofdm.constellation = QAM_16; break; 1182 case 1: fep->modulation = QAM_16; break;
1176 case 2: 1183 case 2:
1177 default: fep->u.ofdm.constellation = QAM_64; break; 1184 default: fep->modulation = QAM_64; break;
1178 } 1185 }
1179 1186
1180 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */ 1187 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
1181 /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */ 1188 /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */
1182 1189
1183 fep->u.ofdm.hierarchy_information = HIERARCHY_NONE; 1190 fep->hierarchy = HIERARCHY_NONE;
1184 switch ((tps >> 5) & 0x7) { 1191 switch ((tps >> 5) & 0x7) {
1185 case 1: fep->u.ofdm.code_rate_HP = FEC_1_2; break; 1192 case 1: fep->code_rate_HP = FEC_1_2; break;
1186 case 2: fep->u.ofdm.code_rate_HP = FEC_2_3; break; 1193 case 2: fep->code_rate_HP = FEC_2_3; break;
1187 case 3: fep->u.ofdm.code_rate_HP = FEC_3_4; break; 1194 case 3: fep->code_rate_HP = FEC_3_4; break;
1188 case 5: fep->u.ofdm.code_rate_HP = FEC_5_6; break; 1195 case 5: fep->code_rate_HP = FEC_5_6; break;
1189 case 7: 1196 case 7:
1190 default: fep->u.ofdm.code_rate_HP = FEC_7_8; break; 1197 default: fep->code_rate_HP = FEC_7_8; break;
1191 1198
1192 } 1199 }
1193 1200
1194 switch ((tps >> 2) & 0x7) { 1201 switch ((tps >> 2) & 0x7) {
1195 case 1: fep->u.ofdm.code_rate_LP = FEC_1_2; break; 1202 case 1: fep->code_rate_LP = FEC_1_2; break;
1196 case 2: fep->u.ofdm.code_rate_LP = FEC_2_3; break; 1203 case 2: fep->code_rate_LP = FEC_2_3; break;
1197 case 3: fep->u.ofdm.code_rate_LP = FEC_3_4; break; 1204 case 3: fep->code_rate_LP = FEC_3_4; break;
1198 case 5: fep->u.ofdm.code_rate_LP = FEC_5_6; break; 1205 case 5: fep->code_rate_LP = FEC_5_6; break;
1199 case 7: 1206 case 7:
1200 default: fep->u.ofdm.code_rate_LP = FEC_7_8; break; 1207 default: fep->code_rate_LP = FEC_7_8; break;
1201 } 1208 }
1202 1209
1203 /* native interleaver: (dib7000m_read_word(state, 481) >> 5) & 0x1 */ 1210 /* native interleaver: (dib7000m_read_word(state, 481) >> 5) & 0x1 */
@@ -1205,35 +1212,34 @@ static int dib7000m_get_frontend(struct dvb_frontend* fe,
1205 return 0; 1212 return 0;
1206} 1213}
1207 1214
1208static int dib7000m_set_frontend(struct dvb_frontend* fe, 1215static int dib7000m_set_frontend(struct dvb_frontend *fe)
1209 struct dvb_frontend_parameters *fep)
1210{ 1216{
1217 struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
1211 struct dib7000m_state *state = fe->demodulator_priv; 1218 struct dib7000m_state *state = fe->demodulator_priv;
1212 int time, ret; 1219 int time, ret;
1213 1220
1214 dib7000m_set_output_mode(state, OUTMODE_HIGH_Z); 1221 dib7000m_set_output_mode(state, OUTMODE_HIGH_Z);
1215 1222
1216 state->current_bandwidth = fep->u.ofdm.bandwidth; 1223 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz));
1217 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->u.ofdm.bandwidth));
1218 1224
1219 if (fe->ops.tuner_ops.set_params) 1225 if (fe->ops.tuner_ops.set_params)
1220 fe->ops.tuner_ops.set_params(fe, fep); 1226 fe->ops.tuner_ops.set_params(fe);
1221 1227
1222 /* start up the AGC */ 1228 /* start up the AGC */
1223 state->agc_state = 0; 1229 state->agc_state = 0;
1224 do { 1230 do {
1225 time = dib7000m_agc_startup(fe, fep); 1231 time = dib7000m_agc_startup(fe);
1226 if (time != -1) 1232 if (time != -1)
1227 msleep(time); 1233 msleep(time);
1228 } while (time != -1); 1234 } while (time != -1);
1229 1235
1230 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO || 1236 if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
1231 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || 1237 fep->guard_interval == GUARD_INTERVAL_AUTO ||
1232 fep->u.ofdm.constellation == QAM_AUTO || 1238 fep->modulation == QAM_AUTO ||
1233 fep->u.ofdm.code_rate_HP == FEC_AUTO) { 1239 fep->code_rate_HP == FEC_AUTO) {
1234 int i = 800, found; 1240 int i = 800, found;
1235 1241
1236 dib7000m_autosearch_start(fe, fep); 1242 dib7000m_autosearch_start(fe);
1237 do { 1243 do {
1238 msleep(1); 1244 msleep(1);
1239 found = dib7000m_autosearch_is_irq(fe); 1245 found = dib7000m_autosearch_is_irq(fe);
@@ -1243,10 +1249,10 @@ static int dib7000m_set_frontend(struct dvb_frontend* fe,
1243 if (found == 0 || found == 1) 1249 if (found == 0 || found == 1)
1244 return 0; // no channel found 1250 return 0; // no channel found
1245 1251
1246 dib7000m_get_frontend(fe, fep); 1252 dib7000m_get_frontend(fe);
1247 } 1253 }
1248 1254
1249 ret = dib7000m_tune(fe, fep); 1255 ret = dib7000m_tune(fe);
1250 1256
1251 /* make this a config parameter */ 1257 /* make this a config parameter */
1252 dib7000m_set_output_mode(state, OUTMODE_MPEG2_FIFO); 1258 dib7000m_set_output_mode(state, OUTMODE_MPEG2_FIFO);
@@ -1430,9 +1436,9 @@ error:
1430EXPORT_SYMBOL(dib7000m_attach); 1436EXPORT_SYMBOL(dib7000m_attach);
1431 1437
1432static struct dvb_frontend_ops dib7000m_ops = { 1438static struct dvb_frontend_ops dib7000m_ops = {
1439 .delsys = { SYS_DVBT },
1433 .info = { 1440 .info = {
1434 .name = "DiBcom 7000MA/MB/PA/PB/MC", 1441 .name = "DiBcom 7000MA/MB/PA/PB/MC",
1435 .type = FE_OFDM,
1436 .frequency_min = 44250000, 1442 .frequency_min = 44250000,
1437 .frequency_max = 867250000, 1443 .frequency_max = 867250000,
1438 .frequency_stepsize = 62500, 1444 .frequency_stepsize = 62500,
diff --git a/drivers/media/dvb/frontends/dib7000p.c b/drivers/media/dvb/frontends/dib7000p.c
index ce8534ff142e..5ceadc285b3a 100644
--- a/drivers/media/dvb/frontends/dib7000p.c
+++ b/drivers/media/dvb/frontends/dib7000p.c
@@ -70,6 +70,8 @@ struct dib7000p_state {
70 u8 i2c_write_buffer[4]; 70 u8 i2c_write_buffer[4];
71 u8 i2c_read_buffer[2]; 71 u8 i2c_read_buffer[2];
72 struct mutex i2c_buffer_lock; 72 struct mutex i2c_buffer_lock;
73
74 u8 input_mode_mpeg;
73}; 75};
74 76
75enum dib7000p_power_mode { 77enum dib7000p_power_mode {
@@ -78,8 +80,11 @@ enum dib7000p_power_mode {
78 DIB7000P_POWER_INTERFACE_ONLY, 80 DIB7000P_POWER_INTERFACE_ONLY,
79}; 81};
80 82
83/* dib7090 specific fonctions */
81static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode); 84static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode);
82static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff); 85static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff);
86static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode);
87static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode);
83 88
84static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg) 89static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg)
85{ 90{
@@ -276,17 +281,23 @@ static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_p
276 dib7000p_write_word(state, 774, reg_774); 281 dib7000p_write_word(state, 774, reg_774);
277 dib7000p_write_word(state, 775, reg_775); 282 dib7000p_write_word(state, 775, reg_775);
278 dib7000p_write_word(state, 776, reg_776); 283 dib7000p_write_word(state, 776, reg_776);
279 dib7000p_write_word(state, 899, reg_899);
280 dib7000p_write_word(state, 1280, reg_1280); 284 dib7000p_write_word(state, 1280, reg_1280);
285 if (state->version != SOC7090)
286 dib7000p_write_word(state, 899, reg_899);
281 287
282 return 0; 288 return 0;
283} 289}
284 290
285static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no) 291static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no)
286{ 292{
287 u16 reg_908 = dib7000p_read_word(state, 908), reg_909 = dib7000p_read_word(state, 909); 293 u16 reg_908 = 0, reg_909 = 0;
288 u16 reg; 294 u16 reg;
289 295
296 if (state->version != SOC7090) {
297 reg_908 = dib7000p_read_word(state, 908);
298 reg_909 = dib7000p_read_word(state, 909);
299 }
300
290 switch (no) { 301 switch (no) {
291 case DIBX000_SLOW_ADC_ON: 302 case DIBX000_SLOW_ADC_ON:
292 if (state->version == SOC7090) { 303 if (state->version == SOC7090) {
@@ -342,8 +353,10 @@ static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_ad
342 reg_909 |= (state->cfg.disable_sample_and_hold & 1) << 4; 353 reg_909 |= (state->cfg.disable_sample_and_hold & 1) << 4;
343 reg_908 |= (state->cfg.enable_current_mirror & 1) << 7; 354 reg_908 |= (state->cfg.enable_current_mirror & 1) << 7;
344 355
345 dib7000p_write_word(state, 908, reg_908); 356 if (state->version != SOC7090) {
346 dib7000p_write_word(state, 909, reg_909); 357 dib7000p_write_word(state, 908, reg_908);
358 dib7000p_write_word(state, 909, reg_909);
359 }
347} 360}
348 361
349static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw) 362static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
@@ -398,6 +411,24 @@ int dib7000p_set_wbd_ref(struct dvb_frontend *demod, u16 value)
398} 411}
399EXPORT_SYMBOL(dib7000p_set_wbd_ref); 412EXPORT_SYMBOL(dib7000p_set_wbd_ref);
400 413
414int dib7000p_get_agc_values(struct dvb_frontend *fe,
415 u16 *agc_global, u16 *agc1, u16 *agc2, u16 *wbd)
416{
417 struct dib7000p_state *state = fe->demodulator_priv;
418
419 if (agc_global != NULL)
420 *agc_global = dib7000p_read_word(state, 394);
421 if (agc1 != NULL)
422 *agc1 = dib7000p_read_word(state, 392);
423 if (agc2 != NULL)
424 *agc2 = dib7000p_read_word(state, 393);
425 if (wbd != NULL)
426 *wbd = dib7000p_read_word(state, 397);
427
428 return 0;
429}
430EXPORT_SYMBOL(dib7000p_get_agc_values);
431
401static void dib7000p_reset_pll(struct dib7000p_state *state) 432static void dib7000p_reset_pll(struct dib7000p_state *state)
402{ 433{
403 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0]; 434 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];
@@ -519,7 +550,7 @@ static u16 dib7000p_defaults[] = {
519 // auto search configuration 550 // auto search configuration
520 3, 2, 551 3, 2,
521 0x0004, 552 0x0004,
522 0x1000, 553 (1<<3)|(1<<11)|(1<<12)|(1<<13),
523 0x0814, /* Equal Lock */ 554 0x0814, /* Equal Lock */
524 555
525 12, 6, 556 12, 6,
@@ -595,13 +626,6 @@ static u16 dib7000p_defaults[] = {
595 1, 235, 626 1, 235,
596 0x0062, 627 0x0062,
597 628
598 2, 901,
599 0x0006,
600 (3 << 10) | (1 << 6),
601
602 1, 905,
603 0x2c8e,
604
605 0, 629 0,
606}; 630};
607 631
@@ -618,15 +642,18 @@ static int dib7000p_demod_reset(struct dib7000p_state *state)
618 dib7000p_write_word(state, 770, 0xffff); 642 dib7000p_write_word(state, 770, 0xffff);
619 dib7000p_write_word(state, 771, 0xffff); 643 dib7000p_write_word(state, 771, 0xffff);
620 dib7000p_write_word(state, 772, 0x001f); 644 dib7000p_write_word(state, 772, 0x001f);
621 dib7000p_write_word(state, 898, 0x0003);
622 dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3))); 645 dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3)));
623 646
624 dib7000p_write_word(state, 770, 0); 647 dib7000p_write_word(state, 770, 0);
625 dib7000p_write_word(state, 771, 0); 648 dib7000p_write_word(state, 771, 0);
626 dib7000p_write_word(state, 772, 0); 649 dib7000p_write_word(state, 772, 0);
627 dib7000p_write_word(state, 898, 0);
628 dib7000p_write_word(state, 1280, 0); 650 dib7000p_write_word(state, 1280, 0);
629 651
652 if (state->version != SOC7090) {
653 dib7000p_write_word(state, 898, 0x0003);
654 dib7000p_write_word(state, 898, 0);
655 }
656
630 /* default */ 657 /* default */
631 dib7000p_reset_pll(state); 658 dib7000p_reset_pll(state);
632 659
@@ -640,7 +667,7 @@ static int dib7000p_demod_reset(struct dib7000p_state *state)
640 dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */ 667 dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */
641 dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */ 668 dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */
642 dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */ 669 dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */
643 dib7000p_write_word(state, 273, (1<<6) | 30); 670 dib7000p_write_word(state, 273, (0<<6) | 30);
644 } 671 }
645 if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0) 672 if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
646 dprintk("OUTPUT_MODE could not be reset."); 673 dprintk("OUTPUT_MODE could not be reset.");
@@ -655,7 +682,7 @@ static int dib7000p_demod_reset(struct dib7000p_state *state)
655 dib7000p_set_bandwidth(state, 8000); 682 dib7000p_set_bandwidth(state, 8000);
656 683
657 if (state->version == SOC7090) { 684 if (state->version == SOC7090) {
658 dib7000p_write_word(state, 36, 0x5755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */ 685 dib7000p_write_word(state, 36, 0x0755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */
659 } else { 686 } else {
660 if (state->cfg.tuner_is_baseband) 687 if (state->cfg.tuner_is_baseband)
661 dib7000p_write_word(state, 36, 0x0755); 688 dib7000p_write_word(state, 36, 0x0755);
@@ -664,6 +691,11 @@ static int dib7000p_demod_reset(struct dib7000p_state *state)
664 } 691 }
665 692
666 dib7000p_write_tab(state, dib7000p_defaults); 693 dib7000p_write_tab(state, dib7000p_defaults);
694 if (state->version != SOC7090) {
695 dib7000p_write_word(state, 901, 0x0006);
696 dib7000p_write_word(state, 902, (3 << 10) | (1 << 6));
697 dib7000p_write_word(state, 905, 0x2c8e);
698 }
667 699
668 dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); 700 dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
669 701
@@ -780,8 +812,9 @@ static void dib7000p_set_dds(struct dib7000p_state *state, s32 offset_khz)
780 } 812 }
781} 813}
782 814
783static int dib7000p_agc_startup(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch) 815static int dib7000p_agc_startup(struct dvb_frontend *demod)
784{ 816{
817 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
785 struct dib7000p_state *state = demod->demodulator_priv; 818 struct dib7000p_state *state = demod->demodulator_priv;
786 int ret = -1; 819 int ret = -1;
787 u8 *agc_state = &state->agc_state; 820 u8 *agc_state = &state->agc_state;
@@ -904,15 +937,16 @@ u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
904} 937}
905EXPORT_SYMBOL(dib7000p_ctrl_timf); 938EXPORT_SYMBOL(dib7000p_ctrl_timf);
906 939
907static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_frontend_parameters *ch, u8 seq) 940static void dib7000p_set_channel(struct dib7000p_state *state,
941 struct dtv_frontend_properties *ch, u8 seq)
908{ 942{
909 u16 value, est[4]; 943 u16 value, est[4];
910 944
911 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)); 945 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
912 946
913 /* nfft, guard, qam, alpha */ 947 /* nfft, guard, qam, alpha */
914 value = 0; 948 value = 0;
915 switch (ch->u.ofdm.transmission_mode) { 949 switch (ch->transmission_mode) {
916 case TRANSMISSION_MODE_2K: 950 case TRANSMISSION_MODE_2K:
917 value |= (0 << 7); 951 value |= (0 << 7);
918 break; 952 break;
@@ -924,7 +958,7 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
924 value |= (1 << 7); 958 value |= (1 << 7);
925 break; 959 break;
926 } 960 }
927 switch (ch->u.ofdm.guard_interval) { 961 switch (ch->guard_interval) {
928 case GUARD_INTERVAL_1_32: 962 case GUARD_INTERVAL_1_32:
929 value |= (0 << 5); 963 value |= (0 << 5);
930 break; 964 break;
@@ -939,7 +973,7 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
939 value |= (2 << 5); 973 value |= (2 << 5);
940 break; 974 break;
941 } 975 }
942 switch (ch->u.ofdm.constellation) { 976 switch (ch->modulation) {
943 case QPSK: 977 case QPSK:
944 value |= (0 << 3); 978 value |= (0 << 3);
945 break; 979 break;
@@ -970,11 +1004,11 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
970 value = 0; 1004 value = 0;
971 if (1 != 0) 1005 if (1 != 0)
972 value |= (1 << 6); 1006 value |= (1 << 6);
973 if (ch->u.ofdm.hierarchy_information == 1) 1007 if (ch->hierarchy == 1)
974 value |= (1 << 4); 1008 value |= (1 << 4);
975 if (1 == 1) 1009 if (1 == 1)
976 value |= 1; 1010 value |= 1;
977 switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) { 1011 switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
978 case FEC_2_3: 1012 case FEC_2_3:
979 value |= (2 << 1); 1013 value |= (2 << 1);
980 break; 1014 break;
@@ -1001,7 +1035,7 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
1001 dib7000p_write_word(state, 33, 0x0005); 1035 dib7000p_write_word(state, 33, 0x0005);
1002 1036
1003 /* P_dvsy_sync_wait */ 1037 /* P_dvsy_sync_wait */
1004 switch (ch->u.ofdm.transmission_mode) { 1038 switch (ch->transmission_mode) {
1005 case TRANSMISSION_MODE_8K: 1039 case TRANSMISSION_MODE_8K:
1006 value = 256; 1040 value = 256;
1007 break; 1041 break;
@@ -1013,7 +1047,7 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
1013 value = 64; 1047 value = 64;
1014 break; 1048 break;
1015 } 1049 }
1016 switch (ch->u.ofdm.guard_interval) { 1050 switch (ch->guard_interval) {
1017 case GUARD_INTERVAL_1_16: 1051 case GUARD_INTERVAL_1_16:
1018 value *= 2; 1052 value *= 2;
1019 break; 1053 break;
@@ -1034,11 +1068,11 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
1034 state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay; 1068 state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay;
1035 1069
1036 /* deactive the possibility of diversity reception if extended interleaver */ 1070 /* deactive the possibility of diversity reception if extended interleaver */
1037 state->div_force_off = !1 && ch->u.ofdm.transmission_mode != TRANSMISSION_MODE_8K; 1071 state->div_force_off = !1 && ch->transmission_mode != TRANSMISSION_MODE_8K;
1038 dib7000p_set_diversity_in(&state->demod, state->div_state); 1072 dib7000p_set_diversity_in(&state->demod, state->div_state);
1039 1073
1040 /* channel estimation fine configuration */ 1074 /* channel estimation fine configuration */
1041 switch (ch->u.ofdm.constellation) { 1075 switch (ch->modulation) {
1042 case QAM_64: 1076 case QAM_64:
1043 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */ 1077 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
1044 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */ 1078 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
@@ -1062,27 +1096,31 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
1062 dib7000p_write_word(state, 187 + value, est[value]); 1096 dib7000p_write_word(state, 187 + value, est[value]);
1063} 1097}
1064 1098
1065static int dib7000p_autosearch_start(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch) 1099static int dib7000p_autosearch_start(struct dvb_frontend *demod)
1066{ 1100{
1101 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
1067 struct dib7000p_state *state = demod->demodulator_priv; 1102 struct dib7000p_state *state = demod->demodulator_priv;
1068 struct dvb_frontend_parameters schan; 1103 struct dtv_frontend_properties schan;
1069 u32 value, factor; 1104 u32 value, factor;
1070 u32 internal = dib7000p_get_internal_freq(state); 1105 u32 internal = dib7000p_get_internal_freq(state);
1071 1106
1072 schan = *ch; 1107 schan = *ch;
1073 schan.u.ofdm.constellation = QAM_64; 1108 schan.modulation = QAM_64;
1074 schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32; 1109 schan.guard_interval = GUARD_INTERVAL_1_32;
1075 schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; 1110 schan.transmission_mode = TRANSMISSION_MODE_8K;
1076 schan.u.ofdm.code_rate_HP = FEC_2_3; 1111 schan.code_rate_HP = FEC_2_3;
1077 schan.u.ofdm.code_rate_LP = FEC_3_4; 1112 schan.code_rate_LP = FEC_3_4;
1078 schan.u.ofdm.hierarchy_information = 0; 1113 schan.hierarchy = 0;
1079 1114
1080 dib7000p_set_channel(state, &schan, 7); 1115 dib7000p_set_channel(state, &schan, 7);
1081 1116
1082 factor = BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth); 1117 factor = BANDWIDTH_TO_KHZ(ch->bandwidth_hz);
1083 if (factor >= 5000) 1118 if (factor >= 5000) {
1084 factor = 1; 1119 if (state->version == SOC7090)
1085 else 1120 factor = 2;
1121 else
1122 factor = 1;
1123 } else
1086 factor = 6; 1124 factor = 6;
1087 1125
1088 value = 30 * internal * factor; 1126 value = 30 * internal * factor;
@@ -1205,8 +1243,9 @@ static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32
1205 dib7000p_write_word(state, 143, 0); 1243 dib7000p_write_word(state, 143, 0);
1206} 1244}
1207 1245
1208static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch) 1246static int dib7000p_tune(struct dvb_frontend *demod)
1209{ 1247{
1248 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
1210 struct dib7000p_state *state = demod->demodulator_priv; 1249 struct dib7000p_state *state = demod->demodulator_priv;
1211 u16 tmp = 0; 1250 u16 tmp = 0;
1212 1251
@@ -1239,7 +1278,7 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
1239 1278
1240 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */ 1279 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
1241 tmp = (6 << 8) | 0x80; 1280 tmp = (6 << 8) | 0x80;
1242 switch (ch->u.ofdm.transmission_mode) { 1281 switch (ch->transmission_mode) {
1243 case TRANSMISSION_MODE_2K: 1282 case TRANSMISSION_MODE_2K:
1244 tmp |= (2 << 12); 1283 tmp |= (2 << 12);
1245 break; 1284 break;
@@ -1255,7 +1294,7 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
1255 1294
1256 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */ 1295 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
1257 tmp = (0 << 4); 1296 tmp = (0 << 4);
1258 switch (ch->u.ofdm.transmission_mode) { 1297 switch (ch->transmission_mode) {
1259 case TRANSMISSION_MODE_2K: 1298 case TRANSMISSION_MODE_2K:
1260 tmp |= 0x6; 1299 tmp |= 0x6;
1261 break; 1300 break;
@@ -1271,7 +1310,7 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
1271 1310
1272 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */ 1311 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
1273 tmp = (0 << 4); 1312 tmp = (0 << 4);
1274 switch (ch->u.ofdm.transmission_mode) { 1313 switch (ch->transmission_mode) {
1275 case TRANSMISSION_MODE_2K: 1314 case TRANSMISSION_MODE_2K:
1276 tmp |= 0x6; 1315 tmp |= 0x6;
1277 break; 1316 break;
@@ -1303,9 +1342,9 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
1303 } 1342 }
1304 1343
1305 if (state->cfg.spur_protect) 1344 if (state->cfg.spur_protect)
1306 dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)); 1345 dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
1307 1346
1308 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)); 1347 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
1309 return 0; 1348 return 0;
1310} 1349}
1311 1350
@@ -1323,7 +1362,7 @@ static int dib7000p_sleep(struct dvb_frontend *demod)
1323{ 1362{
1324 struct dib7000p_state *state = demod->demodulator_priv; 1363 struct dib7000p_state *state = demod->demodulator_priv;
1325 if (state->version == SOC7090) 1364 if (state->version == SOC7090)
1326 return dib7090_set_output_mode(demod, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); 1365 return dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
1327 return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); 1366 return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
1328} 1367}
1329 1368
@@ -1345,93 +1384,94 @@ static int dib7000p_identify(struct dib7000p_state *st)
1345 return 0; 1384 return 0;
1346} 1385}
1347 1386
1348static int dib7000p_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep) 1387static int dib7000p_get_frontend(struct dvb_frontend *fe)
1349{ 1388{
1389 struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
1350 struct dib7000p_state *state = fe->demodulator_priv; 1390 struct dib7000p_state *state = fe->demodulator_priv;
1351 u16 tps = dib7000p_read_word(state, 463); 1391 u16 tps = dib7000p_read_word(state, 463);
1352 1392
1353 fep->inversion = INVERSION_AUTO; 1393 fep->inversion = INVERSION_AUTO;
1354 1394
1355 fep->u.ofdm.bandwidth = BANDWIDTH_TO_INDEX(state->current_bandwidth); 1395 fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth);
1356 1396
1357 switch ((tps >> 8) & 0x3) { 1397 switch ((tps >> 8) & 0x3) {
1358 case 0: 1398 case 0:
1359 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; 1399 fep->transmission_mode = TRANSMISSION_MODE_2K;
1360 break; 1400 break;
1361 case 1: 1401 case 1:
1362 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; 1402 fep->transmission_mode = TRANSMISSION_MODE_8K;
1363 break; 1403 break;
1364 /* case 2: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_4K; break; */ 1404 /* case 2: fep->transmission_mode = TRANSMISSION_MODE_4K; break; */
1365 } 1405 }
1366 1406
1367 switch (tps & 0x3) { 1407 switch (tps & 0x3) {
1368 case 0: 1408 case 0:
1369 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; 1409 fep->guard_interval = GUARD_INTERVAL_1_32;
1370 break; 1410 break;
1371 case 1: 1411 case 1:
1372 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; 1412 fep->guard_interval = GUARD_INTERVAL_1_16;
1373 break; 1413 break;
1374 case 2: 1414 case 2:
1375 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; 1415 fep->guard_interval = GUARD_INTERVAL_1_8;
1376 break; 1416 break;
1377 case 3: 1417 case 3:
1378 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; 1418 fep->guard_interval = GUARD_INTERVAL_1_4;
1379 break; 1419 break;
1380 } 1420 }
1381 1421
1382 switch ((tps >> 14) & 0x3) { 1422 switch ((tps >> 14) & 0x3) {
1383 case 0: 1423 case 0:
1384 fep->u.ofdm.constellation = QPSK; 1424 fep->modulation = QPSK;
1385 break; 1425 break;
1386 case 1: 1426 case 1:
1387 fep->u.ofdm.constellation = QAM_16; 1427 fep->modulation = QAM_16;
1388 break; 1428 break;
1389 case 2: 1429 case 2:
1390 default: 1430 default:
1391 fep->u.ofdm.constellation = QAM_64; 1431 fep->modulation = QAM_64;
1392 break; 1432 break;
1393 } 1433 }
1394 1434
1395 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */ 1435 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
1396 /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */ 1436 /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */
1397 1437
1398 fep->u.ofdm.hierarchy_information = HIERARCHY_NONE; 1438 fep->hierarchy = HIERARCHY_NONE;
1399 switch ((tps >> 5) & 0x7) { 1439 switch ((tps >> 5) & 0x7) {
1400 case 1: 1440 case 1:
1401 fep->u.ofdm.code_rate_HP = FEC_1_2; 1441 fep->code_rate_HP = FEC_1_2;
1402 break; 1442 break;
1403 case 2: 1443 case 2:
1404 fep->u.ofdm.code_rate_HP = FEC_2_3; 1444 fep->code_rate_HP = FEC_2_3;
1405 break; 1445 break;
1406 case 3: 1446 case 3:
1407 fep->u.ofdm.code_rate_HP = FEC_3_4; 1447 fep->code_rate_HP = FEC_3_4;
1408 break; 1448 break;
1409 case 5: 1449 case 5:
1410 fep->u.ofdm.code_rate_HP = FEC_5_6; 1450 fep->code_rate_HP = FEC_5_6;
1411 break; 1451 break;
1412 case 7: 1452 case 7:
1413 default: 1453 default:
1414 fep->u.ofdm.code_rate_HP = FEC_7_8; 1454 fep->code_rate_HP = FEC_7_8;
1415 break; 1455 break;
1416 1456
1417 } 1457 }
1418 1458
1419 switch ((tps >> 2) & 0x7) { 1459 switch ((tps >> 2) & 0x7) {
1420 case 1: 1460 case 1:
1421 fep->u.ofdm.code_rate_LP = FEC_1_2; 1461 fep->code_rate_LP = FEC_1_2;
1422 break; 1462 break;
1423 case 2: 1463 case 2:
1424 fep->u.ofdm.code_rate_LP = FEC_2_3; 1464 fep->code_rate_LP = FEC_2_3;
1425 break; 1465 break;
1426 case 3: 1466 case 3:
1427 fep->u.ofdm.code_rate_LP = FEC_3_4; 1467 fep->code_rate_LP = FEC_3_4;
1428 break; 1468 break;
1429 case 5: 1469 case 5:
1430 fep->u.ofdm.code_rate_LP = FEC_5_6; 1470 fep->code_rate_LP = FEC_5_6;
1431 break; 1471 break;
1432 case 7: 1472 case 7:
1433 default: 1473 default:
1434 fep->u.ofdm.code_rate_LP = FEC_7_8; 1474 fep->code_rate_LP = FEC_7_8;
1435 break; 1475 break;
1436 } 1476 }
1437 1477
@@ -1440,36 +1480,36 @@ static int dib7000p_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_pa
1440 return 0; 1480 return 0;
1441} 1481}
1442 1482
1443static int dib7000p_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep) 1483static int dib7000p_set_frontend(struct dvb_frontend *fe)
1444{ 1484{
1485 struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
1445 struct dib7000p_state *state = fe->demodulator_priv; 1486 struct dib7000p_state *state = fe->demodulator_priv;
1446 int time, ret; 1487 int time, ret;
1447 1488
1448 if (state->version == SOC7090) { 1489 if (state->version == SOC7090)
1449 dib7090_set_diversity_in(fe, 0); 1490 dib7090_set_diversity_in(fe, 0);
1450 dib7090_set_output_mode(fe, OUTMODE_HIGH_Z); 1491 else
1451 } else
1452 dib7000p_set_output_mode(state, OUTMODE_HIGH_Z); 1492 dib7000p_set_output_mode(state, OUTMODE_HIGH_Z);
1453 1493
1454 /* maybe the parameter has been changed */ 1494 /* maybe the parameter has been changed */
1455 state->sfn_workaround_active = buggy_sfn_workaround; 1495 state->sfn_workaround_active = buggy_sfn_workaround;
1456 1496
1457 if (fe->ops.tuner_ops.set_params) 1497 if (fe->ops.tuner_ops.set_params)
1458 fe->ops.tuner_ops.set_params(fe, fep); 1498 fe->ops.tuner_ops.set_params(fe);
1459 1499
1460 /* start up the AGC */ 1500 /* start up the AGC */
1461 state->agc_state = 0; 1501 state->agc_state = 0;
1462 do { 1502 do {
1463 time = dib7000p_agc_startup(fe, fep); 1503 time = dib7000p_agc_startup(fe);
1464 if (time != -1) 1504 if (time != -1)
1465 msleep(time); 1505 msleep(time);
1466 } while (time != -1); 1506 } while (time != -1);
1467 1507
1468 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO || 1508 if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
1469 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) { 1509 fep->guard_interval == GUARD_INTERVAL_AUTO || fep->modulation == QAM_AUTO || fep->code_rate_HP == FEC_AUTO) {
1470 int i = 800, found; 1510 int i = 800, found;
1471 1511
1472 dib7000p_autosearch_start(fe, fep); 1512 dib7000p_autosearch_start(fe);
1473 do { 1513 do {
1474 msleep(1); 1514 msleep(1);
1475 found = dib7000p_autosearch_is_irq(fe); 1515 found = dib7000p_autosearch_is_irq(fe);
@@ -1479,15 +1519,19 @@ static int dib7000p_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_pa
1479 if (found == 0 || found == 1) 1519 if (found == 0 || found == 1)
1480 return 0; 1520 return 0;
1481 1521
1482 dib7000p_get_frontend(fe, fep); 1522 dib7000p_get_frontend(fe);
1483 } 1523 }
1484 1524
1485 ret = dib7000p_tune(fe, fep); 1525 ret = dib7000p_tune(fe);
1486 1526
1487 /* make this a config parameter */ 1527 /* make this a config parameter */
1488 if (state->version == SOC7090) 1528 if (state->version == SOC7090) {
1489 dib7090_set_output_mode(fe, state->cfg.output_mode); 1529 dib7090_set_output_mode(fe, state->cfg.output_mode);
1490 else 1530 if (state->cfg.enMpegOutput == 0) {
1531 dib7090_setDibTxMux(state, MPEG_ON_DIBTX);
1532 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1533 }
1534 } else
1491 dib7000p_set_output_mode(state, state->cfg.output_mode); 1535 dib7000p_set_output_mode(state, state->cfg.output_mode);
1492 1536
1493 return ret; 1537 return ret;
@@ -1831,7 +1875,8 @@ static int w7090p_tuner_rw_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg m
1831 return num; 1875 return num;
1832} 1876}
1833 1877
1834int dib7090p_rw_on_apb(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num, u16 apb_address) 1878static int dib7090p_rw_on_apb(struct i2c_adapter *i2c_adap,
1879 struct i2c_msg msg[], int num, u16 apb_address)
1835{ 1880{
1836 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap); 1881 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1837 u16 word; 1882 u16 word;
@@ -1933,10 +1978,10 @@ static int dib7090_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[]
1933 apb_address = 915; 1978 apb_address = 915;
1934 break; 1979 break;
1935 case 0x27: 1980 case 0x27:
1936 apb_address = 916; 1981 apb_address = 917;
1937 break; 1982 break;
1938 case 0x28: 1983 case 0x28:
1939 apb_address = 917; 1984 apb_address = 916;
1940 break; 1985 break;
1941 case 0x1d: 1986 case 0x1d:
1942 i = ((dib7000p_read_word(state, 72) >> 12) & 0x3); 1987 i = ((dib7000p_read_word(state, 72) >> 12) & 0x3);
@@ -2031,12 +2076,7 @@ static u32 dib7090_calcSyncFreq(u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32
2031 2076
2032static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize) 2077static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize)
2033{ 2078{
2034 u8 index_buf;
2035 u16 rx_copy_buf[22];
2036
2037 dprintk("Configure DibStream Tx"); 2079 dprintk("Configure DibStream Tx");
2038 for (index_buf = 0; index_buf < 22; index_buf++)
2039 rx_copy_buf[index_buf] = dib7000p_read_word(state, 1536+index_buf);
2040 2080
2041 dib7000p_write_word(state, 1615, 1); 2081 dib7000p_write_word(state, 1615, 1);
2042 dib7000p_write_word(state, 1603, P_Kin); 2082 dib7000p_write_word(state, 1603, P_Kin);
@@ -2048,9 +2088,6 @@ static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout
2048 dib7000p_write_word(state, 1612, syncSize); 2088 dib7000p_write_word(state, 1612, syncSize);
2049 dib7000p_write_word(state, 1615, 0); 2089 dib7000p_write_word(state, 1615, 0);
2050 2090
2051 for (index_buf = 0; index_buf < 22; index_buf++)
2052 dib7000p_write_word(state, 1536+index_buf, rx_copy_buf[index_buf]);
2053
2054 return 0; 2091 return 0;
2055} 2092}
2056 2093
@@ -2077,109 +2114,121 @@ static int dib7090_cfg_DibRx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout
2077 return 0; 2114 return 0;
2078} 2115}
2079 2116
2080static int dib7090_enDivOnHostBus(struct dib7000p_state *state) 2117static void dib7090_enMpegMux(struct dib7000p_state *state, int onoff)
2081{
2082 u16 reg;
2083
2084 dprintk("Enable Diversity on host bus");
2085 reg = (1 << 8) | (1 << 5);
2086 dib7000p_write_word(state, 1288, reg);
2087
2088 return dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
2089}
2090
2091static int dib7090_enAdcOnHostBus(struct dib7000p_state *state)
2092{
2093 u16 reg;
2094
2095 dprintk("Enable ADC on host bus");
2096 reg = (1 << 7) | (1 << 5);
2097 dib7000p_write_word(state, 1288, reg);
2098
2099 return dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
2100}
2101
2102static int dib7090_enMpegOnHostBus(struct dib7000p_state *state)
2103{ 2118{
2104 u16 reg; 2119 u16 reg_1287 = dib7000p_read_word(state, 1287);
2105
2106 dprintk("Enable Mpeg on host bus");
2107 reg = (1 << 9) | (1 << 5);
2108 dib7000p_write_word(state, 1288, reg);
2109 2120
2110 return dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0); 2121 switch (onoff) {
2111} 2122 case 1:
2123 reg_1287 &= ~(1<<7);
2124 break;
2125 case 0:
2126 reg_1287 |= (1<<7);
2127 break;
2128 }
2112 2129
2113static int dib7090_enMpegInput(struct dib7000p_state *state) 2130 dib7000p_write_word(state, 1287, reg_1287);
2114{
2115 dprintk("Enable Mpeg input");
2116 return dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); /*outputRate = 8 */
2117} 2131}
2118 2132
2119static int dib7090_enMpegMux(struct dib7000p_state *state, u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2) 2133static void dib7090_configMpegMux(struct dib7000p_state *state,
2134 u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
2120{ 2135{
2121 u16 reg = (1 << 7) | ((pulseWidth & 0x1f) << 2) | ((enSerialMode & 0x1) << 1) | (enSerialClkDiv2 & 0x1);
2122
2123 dprintk("Enable Mpeg mux"); 2136 dprintk("Enable Mpeg mux");
2124 dib7000p_write_word(state, 1287, reg);
2125 2137
2126 reg &= ~(1 << 7); 2138 dib7090_enMpegMux(state, 0);
2127 dib7000p_write_word(state, 1287, reg);
2128 2139
2129 reg = (1 << 4); 2140 /* If the input mode is MPEG do not divide the serial clock */
2130 dib7000p_write_word(state, 1288, reg); 2141 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
2142 enSerialClkDiv2 = 0;
2131 2143
2132 return 0; 2144 dib7000p_write_word(state, 1287, ((pulseWidth & 0x1f) << 2)
2145 | ((enSerialMode & 0x1) << 1)
2146 | (enSerialClkDiv2 & 0x1));
2147
2148 dib7090_enMpegMux(state, 1);
2133} 2149}
2134 2150
2135static int dib7090_disableMpegMux(struct dib7000p_state *state) 2151static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode)
2136{ 2152{
2137 u16 reg; 2153 u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 7);
2138
2139 dprintk("Disable Mpeg mux");
2140 dib7000p_write_word(state, 1288, 0);
2141
2142 reg = dib7000p_read_word(state, 1287);
2143 reg &= ~(1 << 7);
2144 dib7000p_write_word(state, 1287, reg);
2145 2154
2146 return 0; 2155 switch (mode) {
2156 case MPEG_ON_DIBTX:
2157 dprintk("SET MPEG ON DIBSTREAM TX");
2158 dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
2159 reg_1288 |= (1<<9);
2160 break;
2161 case DIV_ON_DIBTX:
2162 dprintk("SET DIV_OUT ON DIBSTREAM TX");
2163 dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
2164 reg_1288 |= (1<<8);
2165 break;
2166 case ADC_ON_DIBTX:
2167 dprintk("SET ADC_OUT ON DIBSTREAM TX");
2168 dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
2169 reg_1288 |= (1<<7);
2170 break;
2171 default:
2172 break;
2173 }
2174 dib7000p_write_word(state, 1288, reg_1288);
2147} 2175}
2148 2176
2149static int dib7090_set_input_mode(struct dvb_frontend *fe, int mode) 2177static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode)
2150{ 2178{
2151 struct dib7000p_state *state = fe->demodulator_priv; 2179 u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 4);
2152 2180
2153 switch (mode) { 2181 switch (mode) {
2154 case INPUT_MODE_DIVERSITY: 2182 case DEMOUT_ON_HOSTBUS:
2155 dprintk("Enable diversity INPUT"); 2183 dprintk("SET DEM OUT OLD INTERF ON HOST BUS");
2156 dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0); 2184 dib7090_enMpegMux(state, 0);
2185 reg_1288 |= (1<<6);
2186 break;
2187 case DIBTX_ON_HOSTBUS:
2188 dprintk("SET DIBSTREAM TX ON HOST BUS");
2189 dib7090_enMpegMux(state, 0);
2190 reg_1288 |= (1<<5);
2157 break; 2191 break;
2158 case INPUT_MODE_MPEG: 2192 case MPEG_ON_HOSTBUS:
2159 dprintk("Enable Mpeg INPUT"); 2193 dprintk("SET MPEG MUX ON HOST BUS");
2160 dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); /*outputRate = 8 */ 2194 reg_1288 |= (1<<4);
2161 break; 2195 break;
2162 case INPUT_MODE_OFF:
2163 default: 2196 default:
2164 dprintk("Disable INPUT");
2165 dib7090_cfg_DibRx(state, 0, 0, 0, 0, 0, 0, 0);
2166 break; 2197 break;
2167 } 2198 }
2168 return 0; 2199 dib7000p_write_word(state, 1288, reg_1288);
2169} 2200}
2170 2201
2171static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff) 2202int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff)
2172{ 2203{
2204 struct dib7000p_state *state = fe->demodulator_priv;
2205 u16 reg_1287;
2206
2173 switch (onoff) { 2207 switch (onoff) {
2174 case 0: /* only use the internal way - not the diversity input */ 2208 case 0: /* only use the internal way - not the diversity input */
2175 dib7090_set_input_mode(fe, INPUT_MODE_MPEG); 2209 dprintk("%s mode OFF : by default Enable Mpeg INPUT", __func__);
2176 break; 2210 dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
2177 case 1: /* both ways */ 2211
2178 case 2: /* only the diversity input */ 2212 /* Do not divide the serial clock of MPEG MUX */
2179 dib7090_set_input_mode(fe, INPUT_MODE_DIVERSITY); 2213 /* in SERIAL MODE in case input mode MPEG is used */
2180 break; 2214 reg_1287 = dib7000p_read_word(state, 1287);
2215 /* enSerialClkDiv2 == 1 ? */
2216 if ((reg_1287 & 0x1) == 1) {
2217 /* force enSerialClkDiv2 = 0 */
2218 reg_1287 &= ~0x1;
2219 dib7000p_write_word(state, 1287, reg_1287);
2220 }
2221 state->input_mode_mpeg = 1;
2222 break;
2223 case 1: /* both ways */
2224 case 2: /* only the diversity input */
2225 dprintk("%s ON : Enable diversity INPUT", __func__);
2226 dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
2227 state->input_mode_mpeg = 0;
2228 break;
2181 } 2229 }
2182 2230
2231 dib7000p_set_diversity_in(&state->demod, onoff);
2183 return 0; 2232 return 0;
2184} 2233}
2185 2234
@@ -2204,69 +2253,63 @@ static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode)
2204 2253
2205 case OUTMODE_MPEG2_SERIAL: 2254 case OUTMODE_MPEG2_SERIAL:
2206 if (prefer_mpeg_mux_use) { 2255 if (prefer_mpeg_mux_use) {
2207 dprintk("Sip 7090P setting output mode TS_SERIAL using Mpeg Mux"); 2256 dprintk("setting output mode TS_SERIAL using Mpeg Mux");
2208 dib7090_enMpegOnHostBus(state); 2257 dib7090_configMpegMux(state, 3, 1, 1);
2209 dib7090_enMpegInput(state); 2258 dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS);
2210 if (state->cfg.enMpegOutput == 1) 2259 } else {/* Use Smooth block */
2211 dib7090_enMpegMux(state, 3, 1, 1); 2260 dprintk("setting output mode TS_SERIAL using Smooth bloc");
2212 2261 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2213 } else { /* Use Smooth block */ 2262 outreg |= (2<<6) | (0 << 1);
2214 dprintk("Sip 7090P setting output mode TS_SERIAL using Smooth bloc");
2215 dib7090_disableMpegMux(state);
2216 dib7000p_write_word(state, 1288, (1 << 6));
2217 outreg |= (2 << 6) | (0 << 1);
2218 } 2263 }
2219 break; 2264 break;
2220 2265
2221 case OUTMODE_MPEG2_PAR_GATED_CLK: 2266 case OUTMODE_MPEG2_PAR_GATED_CLK:
2222 if (prefer_mpeg_mux_use) { 2267 if (prefer_mpeg_mux_use) {
2223 dprintk("Sip 7090P setting output mode TS_PARALLEL_GATED using Mpeg Mux"); 2268 dprintk("setting output mode TS_PARALLEL_GATED using Mpeg Mux");
2224 dib7090_enMpegOnHostBus(state); 2269 dib7090_configMpegMux(state, 2, 0, 0);
2225 dib7090_enMpegInput(state); 2270 dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS);
2226 if (state->cfg.enMpegOutput == 1) 2271 } else { /* Use Smooth block */
2227 dib7090_enMpegMux(state, 2, 0, 0); 2272 dprintk("setting output mode TS_PARALLEL_GATED using Smooth block");
2228 } else { /* Use Smooth block */ 2273 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2229 dprintk("Sip 7090P setting output mode TS_PARALLEL_GATED using Smooth block"); 2274 outreg |= (0<<6);
2230 dib7090_disableMpegMux(state);
2231 dib7000p_write_word(state, 1288, (1 << 6));
2232 outreg |= (0 << 6);
2233 } 2275 }
2234 break; 2276 break;
2235 2277
2236 case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */ 2278 case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
2237 dprintk("Sip 7090P setting output mode TS_PARALLEL_CONT using Smooth block"); 2279 dprintk("setting output mode TS_PARALLEL_CONT using Smooth block");
2238 dib7090_disableMpegMux(state); 2280 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2239 dib7000p_write_word(state, 1288, (1 << 6)); 2281 outreg |= (1<<6);
2240 outreg |= (1 << 6);
2241 break; 2282 break;
2242 2283
2243 case OUTMODE_MPEG2_FIFO: /* Using Smooth block because not supported by new Mpeg Mux bloc */ 2284 case OUTMODE_MPEG2_FIFO: /* Using Smooth block because not supported by new Mpeg Mux bloc */
2244 dprintk("Sip 7090P setting output mode TS_FIFO using Smooth block"); 2285 dprintk("setting output mode TS_FIFO using Smooth block");
2245 dib7090_disableMpegMux(state); 2286 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2246 dib7000p_write_word(state, 1288, (1 << 6)); 2287 outreg |= (5<<6);
2247 outreg |= (5 << 6);
2248 smo_mode |= (3 << 1); 2288 smo_mode |= (3 << 1);
2249 fifo_threshold = 512; 2289 fifo_threshold = 512;
2250 break; 2290 break;
2251 2291
2252 case OUTMODE_DIVERSITY: 2292 case OUTMODE_DIVERSITY:
2253 dprintk("Sip 7090P setting output mode MODE_DIVERSITY"); 2293 dprintk("setting output mode MODE_DIVERSITY");
2254 dib7090_disableMpegMux(state); 2294 dib7090_setDibTxMux(state, DIV_ON_DIBTX);
2255 dib7090_enDivOnHostBus(state); 2295 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
2256 break; 2296 break;
2257 2297
2258 case OUTMODE_ANALOG_ADC: 2298 case OUTMODE_ANALOG_ADC:
2259 dprintk("Sip 7090P setting output mode MODE_ANALOG_ADC"); 2299 dprintk("setting output mode MODE_ANALOG_ADC");
2260 dib7090_enAdcOnHostBus(state); 2300 dib7090_setDibTxMux(state, ADC_ON_DIBTX);
2301 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
2261 break; 2302 break;
2262 } 2303 }
2304 if (mode != OUTMODE_HIGH_Z)
2305 outreg |= (1 << 10);
2263 2306
2264 if (state->cfg.output_mpeg2_in_188_bytes) 2307 if (state->cfg.output_mpeg2_in_188_bytes)
2265 smo_mode |= (1 << 5); 2308 smo_mode |= (1 << 5);
2266 2309
2267 ret |= dib7000p_write_word(state, 235, smo_mode); 2310 ret |= dib7000p_write_word(state, 235, smo_mode);
2268 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */ 2311 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
2269 ret |= dib7000p_write_word(state, 1286, outreg | (1 << 10)); /* allways set Dout active = 1 !!! */ 2312 ret |= dib7000p_write_word(state, 1286, outreg);
2270 2313
2271 return ret; 2314 return ret;
2272} 2315}
@@ -2296,13 +2339,6 @@ int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
2296} 2339}
2297EXPORT_SYMBOL(dib7090_tuner_sleep); 2340EXPORT_SYMBOL(dib7090_tuner_sleep);
2298 2341
2299int dib7090_agc_restart(struct dvb_frontend *fe, u8 restart)
2300{
2301 dprintk("AGC restart callback: %d", restart);
2302 return 0;
2303}
2304EXPORT_SYMBOL(dib7090_agc_restart);
2305
2306int dib7090_get_adc_power(struct dvb_frontend *fe) 2342int dib7090_get_adc_power(struct dvb_frontend *fe)
2307{ 2343{
2308 return dib7000p_get_adc_power(fe); 2344 return dib7000p_get_adc_power(fe);
@@ -2391,9 +2427,9 @@ error:
2391EXPORT_SYMBOL(dib7000p_attach); 2427EXPORT_SYMBOL(dib7000p_attach);
2392 2428
2393static struct dvb_frontend_ops dib7000p_ops = { 2429static struct dvb_frontend_ops dib7000p_ops = {
2430 .delsys = { SYS_DVBT },
2394 .info = { 2431 .info = {
2395 .name = "DiBcom 7000PC", 2432 .name = "DiBcom 7000PC",
2396 .type = FE_OFDM,
2397 .frequency_min = 44250000, 2433 .frequency_min = 44250000,
2398 .frequency_max = 867250000, 2434 .frequency_max = 867250000,
2399 .frequency_stepsize = 62500, 2435 .frequency_stepsize = 62500,
diff --git a/drivers/media/dvb/frontends/dib7000p.h b/drivers/media/dvb/frontends/dib7000p.h
index 0179f9474bac..b61b03a6e1ed 100644
--- a/drivers/media/dvb/frontends/dib7000p.h
+++ b/drivers/media/dvb/frontends/dib7000p.h
@@ -56,11 +56,12 @@ extern int dib7000p_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff);
56extern int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff); 56extern int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff);
57extern int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw); 57extern int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw);
58extern u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf); 58extern u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf);
59extern int dib7090_agc_restart(struct dvb_frontend *fe, u8 restart);
60extern int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff); 59extern int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff);
61extern int dib7090_get_adc_power(struct dvb_frontend *fe); 60extern int dib7090_get_adc_power(struct dvb_frontend *fe);
62extern struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe); 61extern struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe);
63extern int dib7090_slave_reset(struct dvb_frontend *fe); 62extern int dib7090_slave_reset(struct dvb_frontend *fe);
63extern int dib7000p_get_agc_values(struct dvb_frontend *fe,
64 u16 *agc_global, u16 *agc1, u16 *agc2, u16 *wbd);
64#else 65#else
65static inline struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg) 66static inline struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
66{ 67{
@@ -122,12 +123,6 @@ static inline u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
122 return 0; 123 return 0;
123} 124}
124 125
125static inline int dib7090_agc_restart(struct dvb_frontend *fe, u8 restart)
126{
127 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
128 return -ENODEV;
129}
130
131static inline int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff) 126static inline int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
132{ 127{
133 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 128 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
@@ -151,6 +146,13 @@ static inline int dib7090_slave_reset(struct dvb_frontend *fe)
151 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 146 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
152 return -ENODEV; 147 return -ENODEV;
153} 148}
149
150static inline int dib7000p_get_agc_values(struct dvb_frontend *fe,
151 u16 *agc_global, u16 *agc1, u16 *agc2, u16 *wbd)
152{
153 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
154 return -ENODEV;
155}
154#endif 156#endif
155 157
156#endif 158#endif
diff --git a/drivers/media/dvb/frontends/dib8000.c b/drivers/media/dvb/frontends/dib8000.c
index fe284d5292f5..9ca34f495009 100644
--- a/drivers/media/dvb/frontends/dib8000.c
+++ b/drivers/media/dvb/frontends/dib8000.c
@@ -81,11 +81,15 @@ struct dib8000_state {
81 u8 i2c_write_buffer[4]; 81 u8 i2c_write_buffer[4];
82 u8 i2c_read_buffer[2]; 82 u8 i2c_read_buffer[2];
83 struct mutex i2c_buffer_lock; 83 struct mutex i2c_buffer_lock;
84 u8 input_mode_mpeg;
85
86 u16 tuner_enable;
87 struct i2c_adapter dib8096p_tuner_adap;
84}; 88};
85 89
86enum dib8000_power_mode { 90enum dib8000_power_mode {
87 DIB8000M_POWER_ALL = 0, 91 DIB8000_POWER_ALL = 0,
88 DIB8000M_POWER_INTERFACE_ONLY, 92 DIB8000_POWER_INTERFACE_ONLY,
89}; 93};
90 94
91static u16 dib8000_i2c_read16(struct i2c_device *i2c, u16 reg) 95static u16 dib8000_i2c_read16(struct i2c_device *i2c, u16 reg)
@@ -428,20 +432,31 @@ static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_pow
428 /* by default everything is going to be powered off */ 432 /* by default everything is going to be powered off */
429 u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff, 433 u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff,
430 reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3, 434 reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3,
435 reg_1280;
436
437 if (state->revision != 0x8090)
431 reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00; 438 reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
439 else
440 reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80;
432 441
433 /* now, depending on the requested mode, we power on */ 442 /* now, depending on the requested mode, we power on */
434 switch (mode) { 443 switch (mode) {
435 /* power up everything in the demod */ 444 /* power up everything in the demod */
436 case DIB8000M_POWER_ALL: 445 case DIB8000_POWER_ALL:
437 reg_774 = 0x0000; 446 reg_774 = 0x0000;
438 reg_775 = 0x0000; 447 reg_775 = 0x0000;
439 reg_776 = 0x0000; 448 reg_776 = 0x0000;
440 reg_900 &= 0xfffc; 449 reg_900 &= 0xfffc;
441 reg_1280 &= 0x00ff; 450 if (state->revision != 0x8090)
451 reg_1280 &= 0x00ff;
452 else
453 reg_1280 &= 0x707f;
442 break; 454 break;
443 case DIB8000M_POWER_INTERFACE_ONLY: 455 case DIB8000_POWER_INTERFACE_ONLY:
444 reg_1280 &= 0x00ff; 456 if (state->revision != 0x8090)
457 reg_1280 &= 0x00ff;
458 else
459 reg_1280 &= 0xfa7b;
445 break; 460 break;
446 } 461 }
447 462
@@ -453,19 +468,67 @@ static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_pow
453 dib8000_write_word(state, 1280, reg_1280); 468 dib8000_write_word(state, 1280, reg_1280);
454} 469}
455 470
471static int dib8000_init_sdram(struct dib8000_state *state)
472{
473 u16 reg = 0;
474 dprintk("Init sdram");
475
476 reg = dib8000_read_word(state, 274)&0xfff0;
477 /* P_dintlv_delay_ram = 7 because of MobileSdram */
478 dib8000_write_word(state, 274, reg | 0x7);
479
480 dib8000_write_word(state, 1803, (7<<2));
481
482 reg = dib8000_read_word(state, 1280);
483 /* force restart P_restart_sdram */
484 dib8000_write_word(state, 1280, reg | (1<<2));
485
486 /* release restart P_restart_sdram */
487 dib8000_write_word(state, 1280, reg);
488
489 return 0;
490}
491
456static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no) 492static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no)
457{ 493{
458 int ret = 0; 494 int ret = 0;
459 u16 reg_907 = dib8000_read_word(state, 907), reg_908 = dib8000_read_word(state, 908); 495 u16 reg, reg_907 = dib8000_read_word(state, 907);
496 u16 reg_908 = dib8000_read_word(state, 908);
460 497
461 switch (no) { 498 switch (no) {
462 case DIBX000_SLOW_ADC_ON: 499 case DIBX000_SLOW_ADC_ON:
463 reg_908 |= (1 << 1) | (1 << 0); 500 if (state->revision != 0x8090) {
464 ret |= dib8000_write_word(state, 908, reg_908); 501 reg_908 |= (1 << 1) | (1 << 0);
465 reg_908 &= ~(1 << 1); 502 ret |= dib8000_write_word(state, 908, reg_908);
503 reg_908 &= ~(1 << 1);
504 } else {
505 reg = dib8000_read_word(state, 1925);
506 /* en_slowAdc = 1 & reset_sladc = 1 */
507 dib8000_write_word(state, 1925, reg |
508 (1<<4) | (1<<2));
509
510 /* read acces to make it works... strange ... */
511 reg = dib8000_read_word(state, 1925);
512 msleep(20);
513 /* en_slowAdc = 1 & reset_sladc = 0 */
514 dib8000_write_word(state, 1925, reg & ~(1<<4));
515
516 reg = dib8000_read_word(state, 921) & ~((0x3 << 14)
517 | (0x3 << 12));
518 /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ;
519 (Vin2 = Vcm) */
520 dib8000_write_word(state, 921, reg | (1 << 14)
521 | (3 << 12));
522 }
466 break; 523 break;
467 524
468 case DIBX000_SLOW_ADC_OFF: 525 case DIBX000_SLOW_ADC_OFF:
526 if (state->revision == 0x8090) {
527 reg = dib8000_read_word(state, 1925);
528 /* reset_sladc = 1 en_slowAdc = 0 */
529 dib8000_write_word(state, 1925,
530 (reg & ~(1<<2)) | (1<<4));
531 }
469 reg_908 |= (1 << 1) | (1 << 0); 532 reg_908 |= (1 << 1) | (1 << 0);
470 break; 533 break;
471 534
@@ -521,7 +584,12 @@ static int dib8000_set_bandwidth(struct dvb_frontend *fe, u32 bw)
521 584
522static int dib8000_sad_calib(struct dib8000_state *state) 585static int dib8000_sad_calib(struct dib8000_state *state)
523{ 586{
524/* internal */ 587 if (state->revision == 0x8090) {
588 dprintk("%s: the sad calibration is not needed for the dib8096P",
589 __func__);
590 return 0;
591 }
592 /* internal */
525 dib8000_write_word(state, 923, (0 << 1) | (0 << 0)); 593 dib8000_write_word(state, 923, (0 << 1) | (0 << 0));
526 dib8000_write_word(state, 924, 776); // 0.625*3.3 / 4096 594 dib8000_write_word(state, 924, 776); // 0.625*3.3 / 4096
527 595
@@ -546,48 +614,129 @@ EXPORT_SYMBOL(dib8000_set_wbd_ref);
546static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_config *bw) 614static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_config *bw)
547{ 615{
548 dprintk("ifreq: %d %x, inversion: %d", bw->ifreq, bw->ifreq, bw->ifreq >> 25); 616 dprintk("ifreq: %d %x, inversion: %d", bw->ifreq, bw->ifreq, bw->ifreq >> 25);
549 dib8000_write_word(state, 23, (u16) (((bw->internal * 1000) >> 16) & 0xffff)); /* P_sec_len */ 617 if (state->revision != 0x8090) {
550 dib8000_write_word(state, 24, (u16) ((bw->internal * 1000) & 0xffff)); 618 dib8000_write_word(state, 23,
619 (u16) (((bw->internal * 1000) >> 16) & 0xffff));
620 dib8000_write_word(state, 24,
621 (u16) ((bw->internal * 1000) & 0xffff));
622 } else {
623 dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff));
624 dib8000_write_word(state, 24,
625 (u16) ((bw->internal / 2 * 1000) & 0xffff));
626 }
551 dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff)); 627 dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff));
552 dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff)); 628 dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff));
553 dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003)); 629 dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003));
554 630
555 dib8000_write_word(state, 922, bw->sad_cfg); 631 if (state->revision != 0x8090)
632 dib8000_write_word(state, 922, bw->sad_cfg);
556} 633}
557 634
558static void dib8000_reset_pll(struct dib8000_state *state) 635static void dib8000_reset_pll(struct dib8000_state *state)
559{ 636{
560 const struct dibx000_bandwidth_config *pll = state->cfg.pll; 637 const struct dibx000_bandwidth_config *pll = state->cfg.pll;
561 u16 clk_cfg1; 638 u16 clk_cfg1, reg;
562 639
563 // clk_cfg0 640 if (state->revision != 0x8090) {
564 dib8000_write_word(state, 901, (pll->pll_prediv << 8) | (pll->pll_ratio << 0)); 641 dib8000_write_word(state, 901,
565 642 (pll->pll_prediv << 8) | (pll->pll_ratio << 0));
566 // clk_cfg1 643
567 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) | 644 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |
568 (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | (1 << 3) | 645 (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) |
569 (pll->pll_range << 1) | (pll->pll_reset << 0); 646 (1 << 3) | (pll->pll_range << 1) |
570 647 (pll->pll_reset << 0);
571 dib8000_write_word(state, 902, clk_cfg1); 648
572 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3); 649 dib8000_write_word(state, 902, clk_cfg1);
573 dib8000_write_word(state, 902, clk_cfg1); 650 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3);
574 651 dib8000_write_word(state, 902, clk_cfg1);
575 dprintk("clk_cfg1: 0x%04x", clk_cfg1); /* 0x507 1 0 1 000 0 0 11 1 */ 652
576 653 dprintk("clk_cfg1: 0x%04x", clk_cfg1);
577 /* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */ 654
578 if (state->cfg.pll->ADClkSrc == 0) 655 /* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */
579 dib8000_write_word(state, 904, (0 << 15) | (0 << 12) | (0 << 10) | 656 if (state->cfg.pll->ADClkSrc == 0)
580 (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1)); 657 dib8000_write_word(state, 904,
581 else if (state->cfg.refclksel != 0) 658 (0 << 15) | (0 << 12) | (0 << 10) |
582 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | 659 (pll->modulo << 8) |
583 ((state->cfg.refclksel & 0x3) << 10) | (pll->modulo << 8) | 660 (pll->ADClkSrc << 7) | (0 << 1));
584 (pll->ADClkSrc << 7) | (0 << 1)); 661 else if (state->cfg.refclksel != 0)
585 else 662 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
586 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | (3 << 10) | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1)); 663 ((state->cfg.refclksel & 0x3) << 10) |
664 (pll->modulo << 8) |
665 (pll->ADClkSrc << 7) | (0 << 1));
666 else
667 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
668 (3 << 10) | (pll->modulo << 8) |
669 (pll->ADClkSrc << 7) | (0 << 1));
670 } else {
671 dib8000_write_word(state, 1856, (!pll->pll_reset<<13) |
672 (pll->pll_range<<12) | (pll->pll_ratio<<6) |
673 (pll->pll_prediv));
674
675 reg = dib8000_read_word(state, 1857);
676 dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15));
677
678 reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */
679 dib8000_write_word(state, 1858, reg | 1);
680
681 dib8000_write_word(state, 904, (pll->modulo << 8));
682 }
587 683
588 dib8000_reset_pll_common(state, pll); 684 dib8000_reset_pll_common(state, pll);
589} 685}
590 686
687int dib8000_update_pll(struct dvb_frontend *fe,
688 struct dibx000_bandwidth_config *pll)
689{
690 struct dib8000_state *state = fe->demodulator_priv;
691 u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856);
692 u8 loopdiv, prediv;
693 u32 internal, xtal;
694
695 /* get back old values */
696 prediv = reg_1856 & 0x3f;
697 loopdiv = (reg_1856 >> 6) & 0x3f;
698
699 if ((pll != NULL) && (pll->pll_prediv != prediv ||
700 pll->pll_ratio != loopdiv)) {
701 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio);
702 reg_1856 &= 0xf000;
703 reg_1857 = dib8000_read_word(state, 1857);
704 /* disable PLL */
705 dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15));
706
707 dib8000_write_word(state, 1856, reg_1856 |
708 ((pll->pll_ratio & 0x3f) << 6) |
709 (pll->pll_prediv & 0x3f));
710
711 /* write new system clk into P_sec_len */
712 internal = dib8000_read32(state, 23) / 1000;
713 dprintk("Old Internal = %d", internal);
714 xtal = 2 * (internal / loopdiv) * prediv;
715 internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio;
716 dprintk("Xtal = %d , New Fmem = %d New Fdemod = %d, New Fsampling = %d", xtal, internal/1000, internal/2000, internal/8000);
717 dprintk("New Internal = %d", internal);
718
719 dib8000_write_word(state, 23,
720 (u16) (((internal / 2) >> 16) & 0xffff));
721 dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff));
722 /* enable PLL */
723 dib8000_write_word(state, 1857, reg_1857 | (1 << 15));
724
725 while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1)
726 dprintk("Waiting for PLL to lock");
727
728 /* verify */
729 reg_1856 = dib8000_read_word(state, 1856);
730 dprintk("PLL Updated with prediv = %d and loopdiv = %d",
731 reg_1856&0x3f, (reg_1856>>6)&0x3f);
732
733 return 0;
734 }
735 return -EINVAL;
736}
737EXPORT_SYMBOL(dib8000_update_pll);
738
739
591static int dib8000_reset_gpio(struct dib8000_state *st) 740static int dib8000_reset_gpio(struct dib8000_state *st)
592{ 741{
593 /* reset the GPIOs */ 742 /* reset the GPIOs */
@@ -721,9 +870,6 @@ static const u16 dib8000_defaults[] = {
721 (3 << 5) | /* P_ctrl_pre_freq_step=3 */ 870 (3 << 5) | /* P_ctrl_pre_freq_step=3 */
722 (1 << 0), /* P_pre_freq_win_len=1 */ 871 (1 << 0), /* P_pre_freq_win_len=1 */
723 872
724 1, 903,
725 (0 << 4) | 2, // P_divclksel=0 P_divbitsel=2 (was clk=3,bit=1 for MPW)
726
727 0, 873 0,
728}; 874};
729 875
@@ -740,7 +886,8 @@ static u16 dib8000_identify(struct i2c_device *client)
740 } 886 }
741 887
742 value = dib8000_i2c_read16(client, 897); 888 value = dib8000_i2c_read16(client, 897);
743 if (value != 0x8000 && value != 0x8001 && value != 0x8002) { 889 if (value != 0x8000 && value != 0x8001 &&
890 value != 0x8002 && value != 0x8090) {
744 dprintk("wrong Device ID (%x)", value); 891 dprintk("wrong Device ID (%x)", value);
745 return 0; 892 return 0;
746 } 893 }
@@ -755,6 +902,9 @@ static u16 dib8000_identify(struct i2c_device *client)
755 case 0x8002: 902 case 0x8002:
756 dprintk("found DiB8000C"); 903 dprintk("found DiB8000C");
757 break; 904 break;
905 case 0x8090:
906 dprintk("found DiB8096P");
907 break;
758 } 908 }
759 return value; 909 return value;
760} 910}
@@ -763,17 +913,19 @@ static int dib8000_reset(struct dvb_frontend *fe)
763{ 913{
764 struct dib8000_state *state = fe->demodulator_priv; 914 struct dib8000_state *state = fe->demodulator_priv;
765 915
766 dib8000_write_word(state, 1287, 0x0003); /* sram lead in, rdy */
767
768 if ((state->revision = dib8000_identify(&state->i2c)) == 0) 916 if ((state->revision = dib8000_identify(&state->i2c)) == 0)
769 return -EINVAL; 917 return -EINVAL;
770 918
919 /* sram lead in, rdy */
920 if (state->revision != 0x8090)
921 dib8000_write_word(state, 1287, 0x0003);
922
771 if (state->revision == 0x8000) 923 if (state->revision == 0x8000)
772 dprintk("error : dib8000 MA not supported"); 924 dprintk("error : dib8000 MA not supported");
773 925
774 dibx000_reset_i2c_master(&state->i2c_master); 926 dibx000_reset_i2c_master(&state->i2c_master);
775 927
776 dib8000_set_power_mode(state, DIB8000M_POWER_ALL); 928 dib8000_set_power_mode(state, DIB8000_POWER_ALL);
777 929
778 /* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */ 930 /* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */
779 dib8000_set_adc_state(state, DIBX000_VBG_ENABLE); 931 dib8000_set_adc_state(state, DIBX000_VBG_ENABLE);
@@ -782,8 +934,10 @@ static int dib8000_reset(struct dvb_frontend *fe)
782 dib8000_write_word(state, 770, 0xffff); 934 dib8000_write_word(state, 770, 0xffff);
783 dib8000_write_word(state, 771, 0xffff); 935 dib8000_write_word(state, 771, 0xffff);
784 dib8000_write_word(state, 772, 0xfffc); 936 dib8000_write_word(state, 772, 0xfffc);
785 dib8000_write_word(state, 898, 0x000c); // sad 937 if (state->revision == 0x8090)
786 dib8000_write_word(state, 1280, 0x004d); 938 dib8000_write_word(state, 1280, 0x0045);
939 else
940 dib8000_write_word(state, 1280, 0x004d);
787 dib8000_write_word(state, 1281, 0x000c); 941 dib8000_write_word(state, 1281, 0x000c);
788 942
789 dib8000_write_word(state, 770, 0x0000); 943 dib8000_write_word(state, 770, 0x0000);
@@ -794,19 +948,25 @@ static int dib8000_reset(struct dvb_frontend *fe)
794 dib8000_write_word(state, 1281, 0x0000); 948 dib8000_write_word(state, 1281, 0x0000);
795 949
796 /* drives */ 950 /* drives */
797 if (state->cfg.drives) 951 if (state->revision != 0x8090) {
798 dib8000_write_word(state, 906, state->cfg.drives); 952 if (state->cfg.drives)
799 else { 953 dib8000_write_word(state, 906, state->cfg.drives);
800 dprintk("using standard PAD-drive-settings, please adjust settings in config-struct to be optimal."); 954 else {
801 dib8000_write_word(state, 906, 0x2d98); // min drive SDRAM - not optimal - adjust 955 dprintk("using standard PAD-drive-settings, please adjust settings in config-struct to be optimal.");
956 /* min drive SDRAM - not optimal - adjust */
957 dib8000_write_word(state, 906, 0x2d98);
958 }
802 } 959 }
803 960
804 dib8000_reset_pll(state); 961 dib8000_reset_pll(state);
962 if (state->revision != 0x8090)
963 dib8000_write_word(state, 898, 0x0004);
805 964
806 if (dib8000_reset_gpio(state) != 0) 965 if (dib8000_reset_gpio(state) != 0)
807 dprintk("GPIO reset was not successful."); 966 dprintk("GPIO reset was not successful.");
808 967
809 if (dib8000_set_output_mode(fe, OUTMODE_HIGH_Z) != 0) 968 if ((state->revision != 0x8090) &&
969 (dib8000_set_output_mode(fe, OUTMODE_HIGH_Z) != 0))
810 dprintk("OUTPUT_MODE could not be resetted."); 970 dprintk("OUTPUT_MODE could not be resetted.");
811 971
812 state->current_agc = NULL; 972 state->current_agc = NULL;
@@ -832,6 +992,8 @@ static int dib8000_reset(struct dvb_frontend *fe)
832 l = *n++; 992 l = *n++;
833 } 993 }
834 } 994 }
995 if (state->revision != 0x8090)
996 dib8000_write_word(state, 903, (0 << 4) | 2);
835 state->isdbt_cfg_loaded = 0; 997 state->isdbt_cfg_loaded = 0;
836 998
837 //div_cfg override for special configs 999 //div_cfg override for special configs
@@ -844,10 +1006,12 @@ static int dib8000_reset(struct dvb_frontend *fe)
844 dib8000_set_bandwidth(fe, 6000); 1006 dib8000_set_bandwidth(fe, 6000);
845 1007
846 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON); 1008 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON);
847 dib8000_sad_calib(state); 1009 if (state->revision != 0x8090) {
848 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF); 1010 dib8000_sad_calib(state);
1011 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
1012 }
849 1013
850 dib8000_set_power_mode(state, DIB8000M_POWER_INTERFACE_ONLY); 1014 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
851 1015
852 return 0; 1016 return 0;
853} 1017}
@@ -879,6 +1043,8 @@ static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)
879{ 1043{
880 struct dibx000_agc_config *agc = NULL; 1044 struct dibx000_agc_config *agc = NULL;
881 int i; 1045 int i;
1046 u16 reg;
1047
882 if (state->current_band == band && state->current_agc != NULL) 1048 if (state->current_band == band && state->current_agc != NULL)
883 return 0; 1049 return 0;
884 state->current_band = band; 1050 state->current_band = band;
@@ -914,6 +1080,12 @@ static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)
914 dib8000_write_word(state, 106, state->wbd_ref); 1080 dib8000_write_word(state, 106, state->wbd_ref);
915 else // use default 1081 else // use default
916 dib8000_write_word(state, 106, agc->wbd_ref); 1082 dib8000_write_word(state, 106, agc->wbd_ref);
1083
1084 if (state->revision == 0x8090) {
1085 reg = dib8000_read_word(state, 922) & (0x3 << 2);
1086 dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2));
1087 }
1088
917 dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8)); 1089 dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
918 dib8000_write_word(state, 108, agc->agc1_max); 1090 dib8000_write_word(state, 108, agc->agc1_max);
919 dib8000_write_word(state, 109, agc->agc1_min); 1091 dib8000_write_word(state, 109, agc->agc1_min);
@@ -925,7 +1097,10 @@ static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)
925 dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2); 1097 dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
926 1098
927 dib8000_write_word(state, 75, agc->agc1_pt3); 1099 dib8000_write_word(state, 75, agc->agc1_pt3);
928 dib8000_write_word(state, 923, (dib8000_read_word(state, 923) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2)); /*LB : 929 -> 923 */ 1100 if (state->revision != 0x8090)
1101 dib8000_write_word(state, 923,
1102 (dib8000_read_word(state, 923) & 0xffe3) |
1103 (agc->wbd_inv << 4) | (agc->wbd_sel << 2));
929 1104
930 return 0; 1105 return 0;
931} 1106}
@@ -968,14 +1143,30 @@ static int dib8000_agc_startup(struct dvb_frontend *fe)
968{ 1143{
969 struct dib8000_state *state = fe->demodulator_priv; 1144 struct dib8000_state *state = fe->demodulator_priv;
970 enum frontend_tune_state *tune_state = &state->tune_state; 1145 enum frontend_tune_state *tune_state = &state->tune_state;
971
972 int ret = 0; 1146 int ret = 0;
1147 u16 reg, upd_demod_gain_period = 0x8000;
973 1148
974 switch (*tune_state) { 1149 switch (*tune_state) {
975 case CT_AGC_START: 1150 case CT_AGC_START:
976 // set power-up level: interf+analog+AGC 1151 // set power-up level: interf+analog+AGC
977 1152
978 dib8000_set_adc_state(state, DIBX000_ADC_ON); 1153 if (state->revision != 0x8090)
1154 dib8000_set_adc_state(state, DIBX000_ADC_ON);
1155 else {
1156 dib8000_set_power_mode(state, DIB8000_POWER_ALL);
1157
1158 reg = dib8000_read_word(state, 1947)&0xff00;
1159 dib8000_write_word(state, 1946,
1160 upd_demod_gain_period & 0xFFFF);
1161 /* bit 14 = enDemodGain */
1162 dib8000_write_word(state, 1947, reg | (1<<14) |
1163 ((upd_demod_gain_period >> 16) & 0xFF));
1164
1165 /* enable adc i & q */
1166 reg = dib8000_read_word(state, 1920);
1167 dib8000_write_word(state, 1920, (reg | 0x3) &
1168 (~(1 << 7)));
1169 }
979 1170
980 if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) { 1171 if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) {
981 *tune_state = CT_AGC_STOP; 1172 *tune_state = CT_AGC_STOP;
@@ -1026,6 +1217,579 @@ static int dib8000_agc_startup(struct dvb_frontend *fe)
1026 1217
1027} 1218}
1028 1219
1220static void dib8096p_host_bus_drive(struct dib8000_state *state, u8 drive)
1221{
1222 u16 reg;
1223
1224 drive &= 0x7;
1225
1226 /* drive host bus 2, 3, 4 */
1227 reg = dib8000_read_word(state, 1798) &
1228 ~(0x7 | (0x7 << 6) | (0x7 << 12));
1229 reg |= (drive<<12) | (drive<<6) | drive;
1230 dib8000_write_word(state, 1798, reg);
1231
1232 /* drive host bus 5,6 */
1233 reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
1234 reg |= (drive<<8) | (drive<<2);
1235 dib8000_write_word(state, 1799, reg);
1236
1237 /* drive host bus 7, 8, 9 */
1238 reg = dib8000_read_word(state, 1800) &
1239 ~(0x7 | (0x7 << 6) | (0x7 << 12));
1240 reg |= (drive<<12) | (drive<<6) | drive;
1241 dib8000_write_word(state, 1800, reg);
1242
1243 /* drive host bus 10, 11 */
1244 reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
1245 reg |= (drive<<8) | (drive<<2);
1246 dib8000_write_word(state, 1801, reg);
1247
1248 /* drive host bus 12, 13, 14 */
1249 reg = dib8000_read_word(state, 1802) &
1250 ~(0x7 | (0x7 << 6) | (0x7 << 12));
1251 reg |= (drive<<12) | (drive<<6) | drive;
1252 dib8000_write_word(state, 1802, reg);
1253}
1254
1255static u32 dib8096p_calcSyncFreq(u32 P_Kin, u32 P_Kout,
1256 u32 insertExtSynchro, u32 syncSize)
1257{
1258 u32 quantif = 3;
1259 u32 nom = (insertExtSynchro * P_Kin+syncSize);
1260 u32 denom = P_Kout;
1261 u32 syncFreq = ((nom << quantif) / denom);
1262
1263 if ((syncFreq & ((1 << quantif) - 1)) != 0)
1264 syncFreq = (syncFreq >> quantif) + 1;
1265 else
1266 syncFreq = (syncFreq >> quantif);
1267
1268 if (syncFreq != 0)
1269 syncFreq = syncFreq - 1;
1270
1271 return syncFreq;
1272}
1273
1274static void dib8096p_cfg_DibTx(struct dib8000_state *state, u32 P_Kin,
1275 u32 P_Kout, u32 insertExtSynchro, u32 synchroMode,
1276 u32 syncWord, u32 syncSize)
1277{
1278 dprintk("Configure DibStream Tx");
1279
1280 dib8000_write_word(state, 1615, 1);
1281 dib8000_write_word(state, 1603, P_Kin);
1282 dib8000_write_word(state, 1605, P_Kout);
1283 dib8000_write_word(state, 1606, insertExtSynchro);
1284 dib8000_write_word(state, 1608, synchroMode);
1285 dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff);
1286 dib8000_write_word(state, 1610, syncWord & 0xffff);
1287 dib8000_write_word(state, 1612, syncSize);
1288 dib8000_write_word(state, 1615, 0);
1289}
1290
1291static void dib8096p_cfg_DibRx(struct dib8000_state *state, u32 P_Kin,
1292 u32 P_Kout, u32 synchroMode, u32 insertExtSynchro,
1293 u32 syncWord, u32 syncSize, u32 dataOutRate)
1294{
1295 u32 syncFreq;
1296
1297 dprintk("Configure DibStream Rx synchroMode = %d", synchroMode);
1298
1299 if ((P_Kin != 0) && (P_Kout != 0)) {
1300 syncFreq = dib8096p_calcSyncFreq(P_Kin, P_Kout,
1301 insertExtSynchro, syncSize);
1302 dib8000_write_word(state, 1542, syncFreq);
1303 }
1304
1305 dib8000_write_word(state, 1554, 1);
1306 dib8000_write_word(state, 1536, P_Kin);
1307 dib8000_write_word(state, 1537, P_Kout);
1308 dib8000_write_word(state, 1539, synchroMode);
1309 dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff);
1310 dib8000_write_word(state, 1541, syncWord & 0xffff);
1311 dib8000_write_word(state, 1543, syncSize);
1312 dib8000_write_word(state, 1544, dataOutRate);
1313 dib8000_write_word(state, 1554, 0);
1314}
1315
1316static void dib8096p_enMpegMux(struct dib8000_state *state, int onoff)
1317{
1318 u16 reg_1287;
1319
1320 reg_1287 = dib8000_read_word(state, 1287);
1321
1322 switch (onoff) {
1323 case 1:
1324 reg_1287 &= ~(1 << 8);
1325 break;
1326 case 0:
1327 reg_1287 |= (1 << 8);
1328 break;
1329 }
1330
1331 dib8000_write_word(state, 1287, reg_1287);
1332}
1333
1334static void dib8096p_configMpegMux(struct dib8000_state *state,
1335 u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
1336{
1337 u16 reg_1287;
1338
1339 dprintk("Enable Mpeg mux");
1340
1341 dib8096p_enMpegMux(state, 0);
1342
1343 /* If the input mode is MPEG do not divide the serial clock */
1344 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
1345 enSerialClkDiv2 = 0;
1346
1347 reg_1287 = ((pulseWidth & 0x1f) << 3) |
1348 ((enSerialMode & 0x1) << 2) | (enSerialClkDiv2 & 0x1);
1349 dib8000_write_word(state, 1287, reg_1287);
1350
1351 dib8096p_enMpegMux(state, 1);
1352}
1353
1354static void dib8096p_setDibTxMux(struct dib8000_state *state, int mode)
1355{
1356 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7);
1357
1358 switch (mode) {
1359 case MPEG_ON_DIBTX:
1360 dprintk("SET MPEG ON DIBSTREAM TX");
1361 dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
1362 reg_1288 |= (1 << 9); break;
1363 case DIV_ON_DIBTX:
1364 dprintk("SET DIV_OUT ON DIBSTREAM TX");
1365 dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
1366 reg_1288 |= (1 << 8); break;
1367 case ADC_ON_DIBTX:
1368 dprintk("SET ADC_OUT ON DIBSTREAM TX");
1369 dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
1370 reg_1288 |= (1 << 7); break;
1371 default:
1372 break;
1373 }
1374 dib8000_write_word(state, 1288, reg_1288);
1375}
1376
1377static void dib8096p_setHostBusMux(struct dib8000_state *state, int mode)
1378{
1379 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4);
1380
1381 switch (mode) {
1382 case DEMOUT_ON_HOSTBUS:
1383 dprintk("SET DEM OUT OLD INTERF ON HOST BUS");
1384 dib8096p_enMpegMux(state, 0);
1385 reg_1288 |= (1 << 6);
1386 break;
1387 case DIBTX_ON_HOSTBUS:
1388 dprintk("SET DIBSTREAM TX ON HOST BUS");
1389 dib8096p_enMpegMux(state, 0);
1390 reg_1288 |= (1 << 5);
1391 break;
1392 case MPEG_ON_HOSTBUS:
1393 dprintk("SET MPEG MUX ON HOST BUS");
1394 reg_1288 |= (1 << 4);
1395 break;
1396 default:
1397 break;
1398 }
1399 dib8000_write_word(state, 1288, reg_1288);
1400}
1401
1402static int dib8096p_set_diversity_in(struct dvb_frontend *fe, int onoff)
1403{
1404 struct dib8000_state *state = fe->demodulator_priv;
1405 u16 reg_1287;
1406
1407 switch (onoff) {
1408 case 0: /* only use the internal way - not the diversity input */
1409 dprintk("%s mode OFF : by default Enable Mpeg INPUT",
1410 __func__);
1411 /* outputRate = 8 */
1412 dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
1413
1414 /* Do not divide the serial clock of MPEG MUX in
1415 SERIAL MODE in case input mode MPEG is used */
1416 reg_1287 = dib8000_read_word(state, 1287);
1417 /* enSerialClkDiv2 == 1 ? */
1418 if ((reg_1287 & 0x1) == 1) {
1419 /* force enSerialClkDiv2 = 0 */
1420 reg_1287 &= ~0x1;
1421 dib8000_write_word(state, 1287, reg_1287);
1422 }
1423 state->input_mode_mpeg = 1;
1424 break;
1425 case 1: /* both ways */
1426 case 2: /* only the diversity input */
1427 dprintk("%s ON : Enable diversity INPUT", __func__);
1428 dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
1429 state->input_mode_mpeg = 0;
1430 break;
1431 }
1432
1433 dib8000_set_diversity_in(state->fe[0], onoff);
1434 return 0;
1435}
1436
1437static int dib8096p_set_output_mode(struct dvb_frontend *fe, int mode)
1438{
1439 struct dib8000_state *state = fe->demodulator_priv;
1440 u16 outreg, smo_mode, fifo_threshold;
1441 u8 prefer_mpeg_mux_use = 1;
1442 int ret = 0;
1443
1444 dib8096p_host_bus_drive(state, 1);
1445
1446 fifo_threshold = 1792;
1447 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
1448 outreg = dib8000_read_word(state, 1286) &
1449 ~((1 << 10) | (0x7 << 6) | (1 << 1));
1450
1451 switch (mode) {
1452 case OUTMODE_HIGH_Z:
1453 outreg = 0;
1454 break;
1455
1456 case OUTMODE_MPEG2_SERIAL:
1457 if (prefer_mpeg_mux_use) {
1458 dprintk("dib8096P setting output mode TS_SERIAL using Mpeg Mux");
1459 dib8096p_configMpegMux(state, 3, 1, 1);
1460 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
1461 } else {/* Use Smooth block */
1462 dprintk("dib8096P setting output mode TS_SERIAL using Smooth bloc");
1463 dib8096p_setHostBusMux(state,
1464 DEMOUT_ON_HOSTBUS);
1465 outreg |= (2 << 6) | (0 << 1);
1466 }
1467 break;
1468
1469 case OUTMODE_MPEG2_PAR_GATED_CLK:
1470 if (prefer_mpeg_mux_use) {
1471 dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Mpeg Mux");
1472 dib8096p_configMpegMux(state, 2, 0, 0);
1473 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
1474 } else { /* Use Smooth block */
1475 dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Smooth block");
1476 dib8096p_setHostBusMux(state,
1477 DEMOUT_ON_HOSTBUS);
1478 outreg |= (0 << 6);
1479 }
1480 break;
1481
1482 case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
1483 dprintk("dib8096P setting output mode TS_PARALLEL_CONT using Smooth block");
1484 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
1485 outreg |= (1 << 6);
1486 break;
1487
1488 case OUTMODE_MPEG2_FIFO:
1489 /* Using Smooth block because not supported
1490 by new Mpeg Mux bloc */
1491 dprintk("dib8096P setting output mode TS_FIFO using Smooth block");
1492 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
1493 outreg |= (5 << 6);
1494 smo_mode |= (3 << 1);
1495 fifo_threshold = 512;
1496 break;
1497
1498 case OUTMODE_DIVERSITY:
1499 dprintk("dib8096P setting output mode MODE_DIVERSITY");
1500 dib8096p_setDibTxMux(state, DIV_ON_DIBTX);
1501 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1502 break;
1503
1504 case OUTMODE_ANALOG_ADC:
1505 dprintk("dib8096P setting output mode MODE_ANALOG_ADC");
1506 dib8096p_setDibTxMux(state, ADC_ON_DIBTX);
1507 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1508 break;
1509 }
1510
1511 if (mode != OUTMODE_HIGH_Z)
1512 outreg |= (1<<10);
1513
1514 dprintk("output_mpeg2_in_188_bytes = %d",
1515 state->cfg.output_mpeg2_in_188_bytes);
1516 if (state->cfg.output_mpeg2_in_188_bytes)
1517 smo_mode |= (1 << 5);
1518
1519 ret |= dib8000_write_word(state, 299, smo_mode);
1520 /* synchronous fread */
1521 ret |= dib8000_write_word(state, 299 + 1, fifo_threshold);
1522 ret |= dib8000_write_word(state, 1286, outreg);
1523
1524 return ret;
1525}
1526
1527static int map_addr_to_serpar_number(struct i2c_msg *msg)
1528{
1529 if (msg->buf[0] <= 15)
1530 msg->buf[0] -= 1;
1531 else if (msg->buf[0] == 17)
1532 msg->buf[0] = 15;
1533 else if (msg->buf[0] == 16)
1534 msg->buf[0] = 17;
1535 else if (msg->buf[0] == 19)
1536 msg->buf[0] = 16;
1537 else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
1538 msg->buf[0] -= 3;
1539 else if (msg->buf[0] == 28)
1540 msg->buf[0] = 23;
1541 else if (msg->buf[0] == 99)
1542 msg->buf[0] = 99;
1543 else
1544 return -EINVAL;
1545 return 0;
1546}
1547
1548static int dib8096p_tuner_write_serpar(struct i2c_adapter *i2c_adap,
1549 struct i2c_msg msg[], int num)
1550{
1551 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1552 u8 n_overflow = 1;
1553 u16 i = 1000;
1554 u16 serpar_num = msg[0].buf[0];
1555
1556 while (n_overflow == 1 && i) {
1557 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
1558 i--;
1559 if (i == 0)
1560 dprintk("Tuner ITF: write busy (overflow)");
1561 }
1562 dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
1563 dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
1564
1565 return num;
1566}
1567
1568static int dib8096p_tuner_read_serpar(struct i2c_adapter *i2c_adap,
1569 struct i2c_msg msg[], int num)
1570{
1571 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1572 u8 n_overflow = 1, n_empty = 1;
1573 u16 i = 1000;
1574 u16 serpar_num = msg[0].buf[0];
1575 u16 read_word;
1576
1577 while (n_overflow == 1 && i) {
1578 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
1579 i--;
1580 if (i == 0)
1581 dprintk("TunerITF: read busy (overflow)");
1582 }
1583 dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f));
1584
1585 i = 1000;
1586 while (n_empty == 1 && i) {
1587 n_empty = dib8000_read_word(state, 1984)&0x1;
1588 i--;
1589 if (i == 0)
1590 dprintk("TunerITF: read busy (empty)");
1591 }
1592
1593 read_word = dib8000_read_word(state, 1987);
1594 msg[1].buf[0] = (read_word >> 8) & 0xff;
1595 msg[1].buf[1] = (read_word) & 0xff;
1596
1597 return num;
1598}
1599
1600static int dib8096p_tuner_rw_serpar(struct i2c_adapter *i2c_adap,
1601 struct i2c_msg msg[], int num)
1602{
1603 if (map_addr_to_serpar_number(&msg[0]) == 0) {
1604 if (num == 1) /* write */
1605 return dib8096p_tuner_write_serpar(i2c_adap, msg, 1);
1606 else /* read */
1607 return dib8096p_tuner_read_serpar(i2c_adap, msg, 2);
1608 }
1609 return num;
1610}
1611
1612static int dib8096p_rw_on_apb(struct i2c_adapter *i2c_adap,
1613 struct i2c_msg msg[], int num, u16 apb_address)
1614{
1615 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1616 u16 word;
1617
1618 if (num == 1) { /* write */
1619 dib8000_write_word(state, apb_address,
1620 ((msg[0].buf[1] << 8) | (msg[0].buf[2])));
1621 } else {
1622 word = dib8000_read_word(state, apb_address);
1623 msg[1].buf[0] = (word >> 8) & 0xff;
1624 msg[1].buf[1] = (word) & 0xff;
1625 }
1626 return num;
1627}
1628
1629static int dib8096p_tuner_xfer(struct i2c_adapter *i2c_adap,
1630 struct i2c_msg msg[], int num)
1631{
1632 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1633 u16 apb_address = 0, word;
1634 int i = 0;
1635
1636 switch (msg[0].buf[0]) {
1637 case 0x12:
1638 apb_address = 1920;
1639 break;
1640 case 0x14:
1641 apb_address = 1921;
1642 break;
1643 case 0x24:
1644 apb_address = 1922;
1645 break;
1646 case 0x1a:
1647 apb_address = 1923;
1648 break;
1649 case 0x22:
1650 apb_address = 1924;
1651 break;
1652 case 0x33:
1653 apb_address = 1926;
1654 break;
1655 case 0x34:
1656 apb_address = 1927;
1657 break;
1658 case 0x35:
1659 apb_address = 1928;
1660 break;
1661 case 0x36:
1662 apb_address = 1929;
1663 break;
1664 case 0x37:
1665 apb_address = 1930;
1666 break;
1667 case 0x38:
1668 apb_address = 1931;
1669 break;
1670 case 0x39:
1671 apb_address = 1932;
1672 break;
1673 case 0x2a:
1674 apb_address = 1935;
1675 break;
1676 case 0x2b:
1677 apb_address = 1936;
1678 break;
1679 case 0x2c:
1680 apb_address = 1937;
1681 break;
1682 case 0x2d:
1683 apb_address = 1938;
1684 break;
1685 case 0x2e:
1686 apb_address = 1939;
1687 break;
1688 case 0x2f:
1689 apb_address = 1940;
1690 break;
1691 case 0x30:
1692 apb_address = 1941;
1693 break;
1694 case 0x31:
1695 apb_address = 1942;
1696 break;
1697 case 0x32:
1698 apb_address = 1943;
1699 break;
1700 case 0x3e:
1701 apb_address = 1944;
1702 break;
1703 case 0x3f:
1704 apb_address = 1945;
1705 break;
1706 case 0x40:
1707 apb_address = 1948;
1708 break;
1709 case 0x25:
1710 apb_address = 936;
1711 break;
1712 case 0x26:
1713 apb_address = 937;
1714 break;
1715 case 0x27:
1716 apb_address = 938;
1717 break;
1718 case 0x28:
1719 apb_address = 939;
1720 break;
1721 case 0x1d:
1722 /* get sad sel request */
1723 i = ((dib8000_read_word(state, 921) >> 12)&0x3);
1724 word = dib8000_read_word(state, 924+i);
1725 msg[1].buf[0] = (word >> 8) & 0xff;
1726 msg[1].buf[1] = (word) & 0xff;
1727 return num;
1728 case 0x1f:
1729 if (num == 1) { /* write */
1730 word = (u16) ((msg[0].buf[1] << 8) |
1731 msg[0].buf[2]);
1732 /* in the VGAMODE Sel are located on bit 0/1 */
1733 word &= 0x3;
1734 word = (dib8000_read_word(state, 921) &
1735 ~(3<<12)) | (word<<12);
1736 /* Set the proper input */
1737 dib8000_write_word(state, 921, word);
1738 return num;
1739 }
1740 }
1741
1742 if (apb_address != 0) /* R/W acces via APB */
1743 return dib8096p_rw_on_apb(i2c_adap, msg, num, apb_address);
1744 else /* R/W access via SERPAR */
1745 return dib8096p_tuner_rw_serpar(i2c_adap, msg, num);
1746
1747 return 0;
1748}
1749
1750static u32 dib8096p_i2c_func(struct i2c_adapter *adapter)
1751{
1752 return I2C_FUNC_I2C;
1753}
1754
1755static struct i2c_algorithm dib8096p_tuner_xfer_algo = {
1756 .master_xfer = dib8096p_tuner_xfer,
1757 .functionality = dib8096p_i2c_func,
1758};
1759
1760struct i2c_adapter *dib8096p_get_i2c_tuner(struct dvb_frontend *fe)
1761{
1762 struct dib8000_state *st = fe->demodulator_priv;
1763 return &st->dib8096p_tuner_adap;
1764}
1765EXPORT_SYMBOL(dib8096p_get_i2c_tuner);
1766
1767int dib8096p_tuner_sleep(struct dvb_frontend *fe, int onoff)
1768{
1769 struct dib8000_state *state = fe->demodulator_priv;
1770 u16 en_cur_state;
1771
1772 dprintk("sleep dib8096p: %d", onoff);
1773
1774 en_cur_state = dib8000_read_word(state, 1922);
1775
1776 /* LNAs and MIX are ON and therefore it is a valid configuration */
1777 if (en_cur_state > 0xff)
1778 state->tuner_enable = en_cur_state ;
1779
1780 if (onoff)
1781 en_cur_state &= 0x00ff;
1782 else {
1783 if (state->tuner_enable != 0)
1784 en_cur_state = state->tuner_enable;
1785 }
1786
1787 dib8000_write_word(state, 1922, en_cur_state);
1788
1789 return 0;
1790}
1791EXPORT_SYMBOL(dib8096p_tuner_sleep);
1792
1029static const s32 lut_1000ln_mant[] = 1793static const s32 lut_1000ln_mant[] =
1030{ 1794{
1031 908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600 1795 908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600
@@ -1051,6 +1815,26 @@ s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
1051} 1815}
1052EXPORT_SYMBOL(dib8000_get_adc_power); 1816EXPORT_SYMBOL(dib8000_get_adc_power);
1053 1817
1818int dib8090p_get_dc_power(struct dvb_frontend *fe, u8 IQ)
1819{
1820 struct dib8000_state *state = fe->demodulator_priv;
1821 int val = 0;
1822
1823 switch (IQ) {
1824 case 1:
1825 val = dib8000_read_word(state, 403);
1826 break;
1827 case 0:
1828 val = dib8000_read_word(state, 404);
1829 break;
1830 }
1831 if (val & 0x200)
1832 val -= 1024;
1833
1834 return val;
1835}
1836EXPORT_SYMBOL(dib8090p_get_dc_power);
1837
1054static void dib8000_update_timf(struct dib8000_state *state) 1838static void dib8000_update_timf(struct dib8000_state *state)
1055{ 1839{
1056 u32 timf = state->timf = dib8000_read32(state, 435); 1840 u32 timf = state->timf = dib8000_read32(state, 435);
@@ -1060,6 +1844,26 @@ static void dib8000_update_timf(struct dib8000_state *state)
1060 dprintk("Updated timing frequency: %d (default: %d)", state->timf, state->timf_default); 1844 dprintk("Updated timing frequency: %d (default: %d)", state->timf, state->timf_default);
1061} 1845}
1062 1846
1847u32 dib8000_ctrl_timf(struct dvb_frontend *fe, uint8_t op, uint32_t timf)
1848{
1849 struct dib8000_state *state = fe->demodulator_priv;
1850
1851 switch (op) {
1852 case DEMOD_TIMF_SET:
1853 state->timf = timf;
1854 break;
1855 case DEMOD_TIMF_UPDATE:
1856 dib8000_update_timf(state);
1857 break;
1858 case DEMOD_TIMF_GET:
1859 break;
1860 }
1861 dib8000_set_bandwidth(state->fe[0], 6000);
1862
1863 return state->timf;
1864}
1865EXPORT_SYMBOL(dib8000_ctrl_timf);
1866
1063static const u16 adc_target_16dB[11] = { 1867static const u16 adc_target_16dB[11] = {
1064 (1 << 13) - 825 - 117, 1868 (1 << 13) - 825 - 117,
1065 (1 << 13) - 837 - 117, 1869 (1 << 13) - 837 - 117,
@@ -1086,6 +1890,9 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1086 u16 init_prbs = 0xfff; 1890 u16 init_prbs = 0xfff;
1087 u16 ana_gain = 0; 1891 u16 ana_gain = 0;
1088 1892
1893 if (state->revision == 0x8090)
1894 dib8000_init_sdram(state);
1895
1089 if (state->ber_monitored_layer != LAYER_ALL) 1896 if (state->ber_monitored_layer != LAYER_ALL)
1090 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & 0x60) | state->ber_monitored_layer); 1897 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & 0x60) | state->ber_monitored_layer);
1091 else 1898 else
@@ -1418,7 +2225,10 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1418 dprintk("nbseg_diff = %X (%d)", seg_diff_mask, seg_diff_mask); 2225 dprintk("nbseg_diff = %X (%d)", seg_diff_mask, seg_diff_mask);
1419 2226
1420 state->differential_constellation = (seg_diff_mask != 0); 2227 state->differential_constellation = (seg_diff_mask != 0);
1421 dib8000_set_diversity_in(state->fe[0], state->diversity_onoff); 2228 if (state->revision != 0x8090)
2229 dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);
2230 else
2231 dib8096p_set_diversity_in(state->fe[0], state->diversity_onoff);
1422 2232
1423 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { 2233 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
1424 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1) 2234 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1)
@@ -1870,7 +2680,7 @@ static int dib8000_tune(struct dvb_frontend *fe)
1870{ 2680{
1871 struct dib8000_state *state = fe->demodulator_priv; 2681 struct dib8000_state *state = fe->demodulator_priv;
1872 int ret = 0; 2682 int ret = 0;
1873 u16 value, mode = fft_to_mode(state); 2683 u16 lock, value, mode = fft_to_mode(state);
1874 2684
1875 // we are already tuned - just resuming from suspend 2685 // we are already tuned - just resuming from suspend
1876 if (state == NULL) 2686 if (state == NULL)
@@ -1924,7 +2734,11 @@ static int dib8000_tune(struct dvb_frontend *fe)
1924 } 2734 }
1925 2735
1926 // we achieved a coff_cpil_lock - it's time to update the timf 2736 // we achieved a coff_cpil_lock - it's time to update the timf
1927 if ((dib8000_read_word(state, 568) >> 11) & 0x1) 2737 if (state->revision != 0x8090)
2738 lock = dib8000_read_word(state, 568);
2739 else
2740 lock = dib8000_read_word(state, 570);
2741 if ((lock >> 11) & 0x1)
1928 dib8000_update_timf(state); 2742 dib8000_update_timf(state);
1929 2743
1930 //now that tune is finished, lock0 should lock on fec_mpeg to output this lock on MP_LOCK. It's changed in autosearch start 2744 //now that tune is finished, lock0 should lock on fec_mpeg to output this lock on MP_LOCK. It's changed in autosearch start
@@ -1946,11 +2760,14 @@ static int dib8000_wakeup(struct dvb_frontend *fe)
1946 u8 index_frontend; 2760 u8 index_frontend;
1947 int ret; 2761 int ret;
1948 2762
1949 dib8000_set_power_mode(state, DIB8000M_POWER_ALL); 2763 dib8000_set_power_mode(state, DIB8000_POWER_ALL);
1950 dib8000_set_adc_state(state, DIBX000_ADC_ON); 2764 dib8000_set_adc_state(state, DIBX000_ADC_ON);
1951 if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0) 2765 if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
1952 dprintk("could not start Slow ADC"); 2766 dprintk("could not start Slow ADC");
1953 2767
2768 if (state->revision != 0x8090)
2769 dib8000_sad_calib(state);
2770
1954 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { 2771 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1955 ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]); 2772 ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]);
1956 if (ret < 0) 2773 if (ret < 0)
@@ -1972,8 +2789,9 @@ static int dib8000_sleep(struct dvb_frontend *fe)
1972 return ret; 2789 return ret;
1973 } 2790 }
1974 2791
1975 dib8000_set_output_mode(fe, OUTMODE_HIGH_Z); 2792 if (state->revision != 0x8090)
1976 dib8000_set_power_mode(state, DIB8000M_POWER_INTERFACE_ONLY); 2793 dib8000_set_output_mode(fe, OUTMODE_HIGH_Z);
2794 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
1977 return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_ADC_OFF); 2795 return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_ADC_OFF);
1978} 2796}
1979 2797
@@ -1992,7 +2810,7 @@ int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tun
1992} 2810}
1993EXPORT_SYMBOL(dib8000_set_tune_state); 2811EXPORT_SYMBOL(dib8000_set_tune_state);
1994 2812
1995static int dib8000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep) 2813static int dib8000_get_frontend(struct dvb_frontend *fe)
1996{ 2814{
1997 struct dib8000_state *state = fe->demodulator_priv; 2815 struct dib8000_state *state = fe->demodulator_priv;
1998 u16 i, val = 0; 2816 u16 i, val = 0;
@@ -2006,7 +2824,7 @@ static int dib8000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
2006 if (stat&FE_HAS_SYNC) { 2824 if (stat&FE_HAS_SYNC) {
2007 dprintk("TMCC lock on the slave%i", index_frontend); 2825 dprintk("TMCC lock on the slave%i", index_frontend);
2008 /* synchronize the cache with the other frontends */ 2826 /* synchronize the cache with the other frontends */
2009 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], fep); 2827 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend]);
2010 for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) { 2828 for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
2011 if (sub_index_frontend != index_frontend) { 2829 if (sub_index_frontend != index_frontend) {
2012 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode; 2830 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
@@ -2028,7 +2846,10 @@ static int dib8000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
2028 2846
2029 fe->dtv_property_cache.isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1; 2847 fe->dtv_property_cache.isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;
2030 2848
2031 val = dib8000_read_word(state, 570); 2849 if (state->revision == 0x8090)
2850 val = dib8000_read_word(state, 572);
2851 else
2852 val = dib8000_read_word(state, 570);
2032 fe->dtv_property_cache.inversion = (val & 0x40) >> 6; 2853 fe->dtv_property_cache.inversion = (val & 0x40) >> 6;
2033 switch ((val & 0x30) >> 4) { 2854 switch ((val & 0x30) >> 4) {
2034 case 1: 2855 case 1:
@@ -2135,7 +2956,7 @@ static int dib8000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
2135 return 0; 2956 return 0;
2136} 2957}
2137 2958
2138static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep) 2959static int dib8000_set_frontend(struct dvb_frontend *fe)
2139{ 2960{
2140 struct dib8000_state *state = fe->demodulator_priv; 2961 struct dib8000_state *state = fe->demodulator_priv;
2141 u8 nbr_pending, exit_condition, index_frontend; 2962 u8 nbr_pending, exit_condition, index_frontend;
@@ -2158,9 +2979,14 @@ static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
2158 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT; 2979 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT;
2159 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties)); 2980 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
2160 2981
2161 dib8000_set_output_mode(state->fe[index_frontend], OUTMODE_HIGH_Z); 2982 if (state->revision != 0x8090)
2983 dib8000_set_output_mode(state->fe[index_frontend],
2984 OUTMODE_HIGH_Z);
2985 else
2986 dib8096p_set_output_mode(state->fe[index_frontend],
2987 OUTMODE_HIGH_Z);
2162 if (state->fe[index_frontend]->ops.tuner_ops.set_params) 2988 if (state->fe[index_frontend]->ops.tuner_ops.set_params)
2163 state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend], fep); 2989 state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]);
2164 2990
2165 dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START); 2991 dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START);
2166 } 2992 }
@@ -2215,7 +3041,7 @@ static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
2215 ((state->fe[0]->dtv_property_cache.layer[1].segment_count == 0) || 3041 ((state->fe[0]->dtv_property_cache.layer[1].segment_count == 0) ||
2216 ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (2 << 0)) == 0)) && 3042 ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (2 << 0)) == 0)) &&
2217 ((state->fe[0]->dtv_property_cache.layer[2].segment_count == 0) || ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (3 << 0)) == 0)))) { 3043 ((state->fe[0]->dtv_property_cache.layer[2].segment_count == 0) || ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (3 << 0)) == 0)))) {
2218 int i = 80000; 3044 int i = 100;
2219 u8 found = 0; 3045 u8 found = 0;
2220 u8 tune_failed = 0; 3046 u8 tune_failed = 0;
2221 3047
@@ -2243,6 +3069,7 @@ static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
2243 default: 3069 default:
2244 dprintk("unhandled autosearch result"); 3070 dprintk("unhandled autosearch result");
2245 case 1: 3071 case 1:
3072 tune_failed |= (1 << index_frontend);
2246 dprintk("autosearch failed for the frontend%i", index_frontend); 3073 dprintk("autosearch failed for the frontend%i", index_frontend);
2247 break; 3074 break;
2248 } 3075 }
@@ -2261,21 +3088,44 @@ static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
2261 3088
2262 dprintk("tune success on frontend%i", index_frontend_success); 3089 dprintk("tune success on frontend%i", index_frontend_success);
2263 3090
2264 dib8000_get_frontend(fe, fep); 3091 dib8000_get_frontend(fe);
2265 } 3092 }
2266 3093
2267 for (index_frontend = 0, ret = 0; (ret >= 0) && (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) 3094 for (index_frontend = 0, ret = 0; (ret >= 0) && (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2268 ret = dib8000_tune(state->fe[index_frontend]); 3095 ret = dib8000_tune(state->fe[index_frontend]);
2269 3096
2270 /* set output mode and diversity input */ 3097 /* set output mode and diversity input */
2271 dib8000_set_output_mode(state->fe[0], state->cfg.output_mode); 3098 if (state->revision != 0x8090) {
2272 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { 3099 dib8000_set_output_mode(state->fe[0], state->cfg.output_mode);
2273 dib8000_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY); 3100 for (index_frontend = 1;
2274 dib8000_set_diversity_in(state->fe[index_frontend-1], 1); 3101 (index_frontend < MAX_NUMBER_OF_FRONTENDS) &&
2275 } 3102 (state->fe[index_frontend] != NULL);
3103 index_frontend++) {
3104 dib8000_set_output_mode(state->fe[index_frontend],
3105 OUTMODE_DIVERSITY);
3106 dib8000_set_diversity_in(state->fe[index_frontend-1], 1);
3107 }
2276 3108
2277 /* turn off the diversity of the last chip */ 3109 /* turn off the diversity of the last chip */
2278 dib8000_set_diversity_in(state->fe[index_frontend-1], 0); 3110 dib8000_set_diversity_in(state->fe[index_frontend-1], 0);
3111 } else {
3112 dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode);
3113 if (state->cfg.enMpegOutput == 0) {
3114 dib8096p_setDibTxMux(state, MPEG_ON_DIBTX);
3115 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
3116 }
3117 for (index_frontend = 1;
3118 (index_frontend < MAX_NUMBER_OF_FRONTENDS) &&
3119 (state->fe[index_frontend] != NULL);
3120 index_frontend++) {
3121 dib8096p_set_output_mode(state->fe[index_frontend],
3122 OUTMODE_DIVERSITY);
3123 dib8096p_set_diversity_in(state->fe[index_frontend-1], 1);
3124 }
3125
3126 /* turn off the diversity of the last chip */
3127 dib8096p_set_diversity_in(state->fe[index_frontend-1], 0);
3128 }
2279 3129
2280 return ret; 3130 return ret;
2281} 3131}
@@ -2284,15 +3134,22 @@ static u16 dib8000_read_lock(struct dvb_frontend *fe)
2284{ 3134{
2285 struct dib8000_state *state = fe->demodulator_priv; 3135 struct dib8000_state *state = fe->demodulator_priv;
2286 3136
3137 if (state->revision == 0x8090)
3138 return dib8000_read_word(state, 570);
2287 return dib8000_read_word(state, 568); 3139 return dib8000_read_word(state, 568);
2288} 3140}
2289 3141
2290static int dib8000_read_status(struct dvb_frontend *fe, fe_status_t * stat) 3142static int dib8000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
2291{ 3143{
2292 struct dib8000_state *state = fe->demodulator_priv; 3144 struct dib8000_state *state = fe->demodulator_priv;
2293 u16 lock_slave = 0, lock = dib8000_read_word(state, 568); 3145 u16 lock_slave = 0, lock;
2294 u8 index_frontend; 3146 u8 index_frontend;
2295 3147
3148 if (state->revision == 0x8090)
3149 lock = dib8000_read_word(state, 570);
3150 else
3151 lock = dib8000_read_word(state, 568);
3152
2296 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) 3153 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2297 lock_slave |= dib8000_read_lock(state->fe[index_frontend]); 3154 lock_slave |= dib8000_read_lock(state->fe[index_frontend]);
2298 3155
@@ -2330,14 +3187,26 @@ static int dib8000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
2330static int dib8000_read_ber(struct dvb_frontend *fe, u32 * ber) 3187static int dib8000_read_ber(struct dvb_frontend *fe, u32 * ber)
2331{ 3188{
2332 struct dib8000_state *state = fe->demodulator_priv; 3189 struct dib8000_state *state = fe->demodulator_priv;
2333 *ber = (dib8000_read_word(state, 560) << 16) | dib8000_read_word(state, 561); // 13 segments 3190
3191 /* 13 segments */
3192 if (state->revision == 0x8090)
3193 *ber = (dib8000_read_word(state, 562) << 16) |
3194 dib8000_read_word(state, 563);
3195 else
3196 *ber = (dib8000_read_word(state, 560) << 16) |
3197 dib8000_read_word(state, 561);
2334 return 0; 3198 return 0;
2335} 3199}
2336 3200
2337static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc) 3201static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
2338{ 3202{
2339 struct dib8000_state *state = fe->demodulator_priv; 3203 struct dib8000_state *state = fe->demodulator_priv;
2340 *unc = dib8000_read_word(state, 565); // packet error on 13 seg 3204
3205 /* packet error on 13 seg */
3206 if (state->revision == 0x8090)
3207 *unc = dib8000_read_word(state, 567);
3208 else
3209 *unc = dib8000_read_word(state, 565);
2341 return 0; 3210 return 0;
2342} 3211}
2343 3212
@@ -2370,14 +3239,20 @@ static u32 dib8000_get_snr(struct dvb_frontend *fe)
2370 u32 n, s, exp; 3239 u32 n, s, exp;
2371 u16 val; 3240 u16 val;
2372 3241
2373 val = dib8000_read_word(state, 542); 3242 if (state->revision != 0x8090)
3243 val = dib8000_read_word(state, 542);
3244 else
3245 val = dib8000_read_word(state, 544);
2374 n = (val >> 6) & 0xff; 3246 n = (val >> 6) & 0xff;
2375 exp = (val & 0x3f); 3247 exp = (val & 0x3f);
2376 if ((exp & 0x20) != 0) 3248 if ((exp & 0x20) != 0)
2377 exp -= 0x40; 3249 exp -= 0x40;
2378 n <<= exp+16; 3250 n <<= exp+16;
2379 3251
2380 val = dib8000_read_word(state, 543); 3252 if (state->revision != 0x8090)
3253 val = dib8000_read_word(state, 543);
3254 else
3255 val = dib8000_read_word(state, 545);
2381 s = (val >> 6) & 0xff; 3256 s = (val >> 6) & 0xff;
2382 exp = (val & 0x3f); 3257 exp = (val & 0x3f);
2383 if ((exp & 0x20) != 0) 3258 if ((exp & 0x20) != 0)
@@ -2401,7 +3276,7 @@ static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr)
2401 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) 3276 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2402 snr_master += dib8000_get_snr(state->fe[index_frontend]); 3277 snr_master += dib8000_get_snr(state->fe[index_frontend]);
2403 3278
2404 if (snr_master != 0) { 3279 if ((snr_master >> 16) != 0) {
2405 snr_master = 10*intlog10(snr_master>>16); 3280 snr_master = 10*intlog10(snr_master>>16);
2406 *snr = snr_master / ((1 << 24) / 10); 3281 *snr = snr_master / ((1 << 24) / 10);
2407 } 3282 }
@@ -2458,7 +3333,8 @@ struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int sla
2458EXPORT_SYMBOL(dib8000_get_slave_frontend); 3333EXPORT_SYMBOL(dib8000_get_slave_frontend);
2459 3334
2460 3335
2461int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr) 3336int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods,
3337 u8 default_addr, u8 first_addr, u8 is_dib8096p)
2462{ 3338{
2463 int k = 0, ret = 0; 3339 int k = 0, ret = 0;
2464 u8 new_addr = 0; 3340 u8 new_addr = 0;
@@ -2488,9 +3364,12 @@ int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 defau
2488 new_addr = first_addr + (k << 1); 3364 new_addr = first_addr + (k << 1);
2489 3365
2490 client.addr = new_addr; 3366 client.addr = new_addr;
2491 dib8000_i2c_write16(&client, 1287, 0x0003); /* sram lead in, rdy */ 3367 if (!is_dib8096p)
2492 if (dib8000_identify(&client) == 0) {
2493 dib8000_i2c_write16(&client, 1287, 0x0003); /* sram lead in, rdy */ 3368 dib8000_i2c_write16(&client, 1287, 0x0003); /* sram lead in, rdy */
3369 if (dib8000_identify(&client) == 0) {
3370 /* sram lead in, rdy */
3371 if (!is_dib8096p)
3372 dib8000_i2c_write16(&client, 1287, 0x0003);
2494 client.addr = default_addr; 3373 client.addr = default_addr;
2495 if (dib8000_identify(&client) == 0) { 3374 if (dib8000_identify(&client) == 0) {
2496 dprintk("#%d: not identified", k); 3375 dprintk("#%d: not identified", k);
@@ -2549,6 +3428,7 @@ static void dib8000_release(struct dvb_frontend *fe)
2549 dvb_frontend_detach(st->fe[index_frontend]); 3428 dvb_frontend_detach(st->fe[index_frontend]);
2550 3429
2551 dibx000_exit_i2c_master(&st->i2c_master); 3430 dibx000_exit_i2c_master(&st->i2c_master);
3431 i2c_del_adapter(&st->dib8096p_tuner_adap);
2552 kfree(st->fe[0]); 3432 kfree(st->fe[0]);
2553 kfree(st); 3433 kfree(st);
2554} 3434}
@@ -2581,9 +3461,9 @@ int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
2581EXPORT_SYMBOL(dib8000_pid_filter); 3461EXPORT_SYMBOL(dib8000_pid_filter);
2582 3462
2583static const struct dvb_frontend_ops dib8000_ops = { 3463static const struct dvb_frontend_ops dib8000_ops = {
3464 .delsys = { SYS_ISDBT },
2584 .info = { 3465 .info = {
2585 .name = "DiBcom 8000 ISDB-T", 3466 .name = "DiBcom 8000 ISDB-T",
2586 .type = FE_OFDM,
2587 .frequency_min = 44250000, 3467 .frequency_min = 44250000,
2588 .frequency_max = 867250000, 3468 .frequency_max = 867250000,
2589 .frequency_stepsize = 62500, 3469 .frequency_stepsize = 62500,
@@ -2651,6 +3531,15 @@ struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, s
2651 3531
2652 dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr); 3532 dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr);
2653 3533
3534 /* init 8096p tuner adapter */
3535 strncpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface",
3536 sizeof(state->dib8096p_tuner_adap.name));
3537 state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo;
3538 state->dib8096p_tuner_adap.algo_data = NULL;
3539 state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent;
3540 i2c_set_adapdata(&state->dib8096p_tuner_adap, state);
3541 i2c_add_adapter(&state->dib8096p_tuner_adap);
3542
2654 dib8000_reset(fe); 3543 dib8000_reset(fe);
2655 3544
2656 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len = 3 */ 3545 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len = 3 */
diff --git a/drivers/media/dvb/frontends/dib8000.h b/drivers/media/dvb/frontends/dib8000.h
index 617f9eba3a09..39591bb172c1 100644
--- a/drivers/media/dvb/frontends/dib8000.h
+++ b/drivers/media/dvb/frontends/dib8000.h
@@ -32,6 +32,7 @@ struct dib8000_config {
32 u8 div_cfg; 32 u8 div_cfg;
33 u8 output_mode; 33 u8 output_mode;
34 u8 refclksel; 34 u8 refclksel;
35 u8 enMpegOutput:1;
35}; 36};
36 37
37#define DEFAULT_DIB8000_I2C_ADDRESS 18 38#define DEFAULT_DIB8000_I2C_ADDRESS 18
@@ -40,7 +41,8 @@ struct dib8000_config {
40extern struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg); 41extern struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg);
41extern struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *, enum dibx000_i2c_interface, int); 42extern struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *, enum dibx000_i2c_interface, int);
42 43
43extern int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr); 44extern int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods,
45 u8 default_addr, u8 first_addr, u8 is_dib8096p);
44 46
45extern int dib8000_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val); 47extern int dib8000_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val);
46extern int dib8000_set_wbd_ref(struct dvb_frontend *, u16 value); 48extern int dib8000_set_wbd_ref(struct dvb_frontend *, u16 value);
@@ -50,6 +52,13 @@ extern int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_st
50extern enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe); 52extern enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe);
51extern void dib8000_pwm_agc_reset(struct dvb_frontend *fe); 53extern void dib8000_pwm_agc_reset(struct dvb_frontend *fe);
52extern s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode); 54extern s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode);
55extern struct i2c_adapter *dib8096p_get_i2c_tuner(struct dvb_frontend *fe);
56extern int dib8096p_tuner_sleep(struct dvb_frontend *fe, int onoff);
57extern int dib8090p_get_dc_power(struct dvb_frontend *fe, u8 IQ);
58extern u32 dib8000_ctrl_timf(struct dvb_frontend *fe,
59 uint8_t op, uint32_t timf);
60extern int dib8000_update_pll(struct dvb_frontend *fe,
61 struct dibx000_bandwidth_config *pll);
53extern int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave); 62extern int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave);
54extern int dib8000_remove_slave_frontend(struct dvb_frontend *fe); 63extern int dib8000_remove_slave_frontend(struct dvb_frontend *fe);
55extern struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index); 64extern struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index);
@@ -66,7 +75,9 @@ static inline struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe
66 return NULL; 75 return NULL;
67} 76}
68 77
69static inline int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr) 78static inline int dib8000_i2c_enumeration(struct i2c_adapter *host,
79 int no_of_demods, u8 default_addr, u8 first_addr,
80 u8 is_dib8096p)
70{ 81{
71 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 82 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
72 return -ENODEV; 83 return -ENODEV;
@@ -109,11 +120,38 @@ static inline void dib8000_pwm_agc_reset(struct dvb_frontend *fe)
109{ 120{
110 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 121 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
111} 122}
123static inline struct i2c_adapter *dib8096p_get_i2c_tuner(struct dvb_frontend *fe)
124{
125 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
126 return NULL;
127}
128static inline int dib8096p_tuner_sleep(struct dvb_frontend *fe, int onoff)
129{
130 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
131 return 0;
132}
112static inline s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode) 133static inline s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
113{ 134{
114 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 135 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
115 return 0; 136 return 0;
116} 137}
138static inline int dib8090p_get_dc_power(struct dvb_frontend *fe, u8 IQ)
139{
140 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
141 return 0;
142}
143static inline u32 dib8000_ctrl_timf(struct dvb_frontend *fe,
144 uint8_t op, uint32_t timf)
145{
146 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
147 return 0;
148}
149static inline int dib8000_update_pll(struct dvb_frontend *fe,
150 struct dibx000_bandwidth_config *pll)
151{
152 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
153 return -ENODEV;
154}
117static inline int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave) 155static inline int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
118{ 156{
119 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 157 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
diff --git a/drivers/media/dvb/frontends/dib9000.c b/drivers/media/dvb/frontends/dib9000.c
index 660f80661ed4..863ef3cfab9f 100644
--- a/drivers/media/dvb/frontends/dib9000.c
+++ b/drivers/media/dvb/frontends/dib9000.c
@@ -1136,7 +1136,7 @@ static int dib9000_fw_init(struct dib9000_state *state)
1136 return 0; 1136 return 0;
1137} 1137}
1138 1138
1139static void dib9000_fw_set_channel_head(struct dib9000_state *state, struct dvb_frontend_parameters *ch) 1139static void dib9000_fw_set_channel_head(struct dib9000_state *state)
1140{ 1140{
1141 u8 b[9]; 1141 u8 b[9];
1142 u32 freq = state->fe[0]->dtv_property_cache.frequency / 1000; 1142 u32 freq = state->fe[0]->dtv_property_cache.frequency / 1000;
@@ -1157,7 +1157,7 @@ static void dib9000_fw_set_channel_head(struct dib9000_state *state, struct dvb_
1157 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_HEAD, b); 1157 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_HEAD, b);
1158} 1158}
1159 1159
1160static int dib9000_fw_get_channel(struct dvb_frontend *fe, struct dvb_frontend_parameters *channel) 1160static int dib9000_fw_get_channel(struct dvb_frontend *fe)
1161{ 1161{
1162 struct dib9000_state *state = fe->demodulator_priv; 1162 struct dib9000_state *state = fe->demodulator_priv;
1163 struct dibDVBTChannel { 1163 struct dibDVBTChannel {
@@ -1309,7 +1309,7 @@ error:
1309 return ret; 1309 return ret;
1310} 1310}
1311 1311
1312static int dib9000_fw_set_channel_union(struct dvb_frontend *fe, struct dvb_frontend_parameters *channel) 1312static int dib9000_fw_set_channel_union(struct dvb_frontend *fe)
1313{ 1313{
1314 struct dib9000_state *state = fe->demodulator_priv; 1314 struct dib9000_state *state = fe->demodulator_priv;
1315 struct dibDVBTChannel { 1315 struct dibDVBTChannel {
@@ -1454,7 +1454,7 @@ static int dib9000_fw_set_channel_union(struct dvb_frontend *fe, struct dvb_fron
1454 return 0; 1454 return 0;
1455} 1455}
1456 1456
1457static int dib9000_fw_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch) 1457static int dib9000_fw_tune(struct dvb_frontend *fe)
1458{ 1458{
1459 struct dib9000_state *state = fe->demodulator_priv; 1459 struct dib9000_state *state = fe->demodulator_priv;
1460 int ret = 10, search = state->channel_status.status == CHANNEL_STATUS_PARAMETERS_UNKNOWN; 1460 int ret = 10, search = state->channel_status.status == CHANNEL_STATUS_PARAMETERS_UNKNOWN;
@@ -1462,7 +1462,7 @@ static int dib9000_fw_tune(struct dvb_frontend *fe, struct dvb_frontend_paramete
1462 1462
1463 switch (state->tune_state) { 1463 switch (state->tune_state) {
1464 case CT_DEMOD_START: 1464 case CT_DEMOD_START:
1465 dib9000_fw_set_channel_head(state, ch); 1465 dib9000_fw_set_channel_head(state);
1466 1466
1467 /* write the channel context - a channel is initialized to 0, so it is OK */ 1467 /* write the channel context - a channel is initialized to 0, so it is OK */
1468 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_CONTEXT, (u8 *) fe_info); 1468 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_CONTEXT, (u8 *) fe_info);
@@ -1471,7 +1471,7 @@ static int dib9000_fw_tune(struct dvb_frontend *fe, struct dvb_frontend_paramete
1471 if (search) 1471 if (search)
1472 dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_SEARCH, NULL, 0); 1472 dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_SEARCH, NULL, 0);
1473 else { 1473 else {
1474 dib9000_fw_set_channel_union(fe, ch); 1474 dib9000_fw_set_channel_union(fe);
1475 dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_TUNE, NULL, 0); 1475 dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_TUNE, NULL, 0);
1476 } 1476 }
1477 state->tune_state = CT_DEMOD_STEP_1; 1477 state->tune_state = CT_DEMOD_STEP_1;
@@ -1867,7 +1867,7 @@ static int dib9000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_fron
1867 return 0; 1867 return 0;
1868} 1868}
1869 1869
1870static int dib9000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep) 1870static int dib9000_get_frontend(struct dvb_frontend *fe)
1871{ 1871{
1872 struct dib9000_state *state = fe->demodulator_priv; 1872 struct dib9000_state *state = fe->demodulator_priv;
1873 u8 index_frontend, sub_index_frontend; 1873 u8 index_frontend, sub_index_frontend;
@@ -1883,7 +1883,7 @@ static int dib9000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
1883 dprintk("TPS lock on the slave%i", index_frontend); 1883 dprintk("TPS lock on the slave%i", index_frontend);
1884 1884
1885 /* synchronize the cache with the other frontends */ 1885 /* synchronize the cache with the other frontends */
1886 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], fep); 1886 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend]);
1887 for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); 1887 for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL);
1888 sub_index_frontend++) { 1888 sub_index_frontend++) {
1889 if (sub_index_frontend != index_frontend) { 1889 if (sub_index_frontend != index_frontend) {
@@ -1911,7 +1911,7 @@ static int dib9000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
1911 } 1911 }
1912 1912
1913 /* get the channel from master chip */ 1913 /* get the channel from master chip */
1914 ret = dib9000_fw_get_channel(fe, fep); 1914 ret = dib9000_fw_get_channel(fe);
1915 if (ret != 0) 1915 if (ret != 0)
1916 goto return_value; 1916 goto return_value;
1917 1917
@@ -1958,7 +1958,7 @@ static int dib9000_set_channel_status(struct dvb_frontend *fe, struct dvb_fronte
1958 return 0; 1958 return 0;
1959} 1959}
1960 1960
1961static int dib9000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep) 1961static int dib9000_set_frontend(struct dvb_frontend *fe)
1962{ 1962{
1963 struct dib9000_state *state = fe->demodulator_priv; 1963 struct dib9000_state *state = fe->demodulator_priv;
1964 int sleep_time, sleep_time_slave; 1964 int sleep_time, sleep_time_slave;
@@ -1983,8 +1983,10 @@ static int dib9000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
1983 fe->dtv_property_cache.delivery_system = SYS_DVBT; 1983 fe->dtv_property_cache.delivery_system = SYS_DVBT;
1984 1984
1985 /* set the master status */ 1985 /* set the master status */
1986 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO || 1986 if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO ||
1987 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) { 1987 state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO ||
1988 state->fe[0]->dtv_property_cache.modulation == QAM_AUTO ||
1989 state->fe[0]->dtv_property_cache.code_rate_HP == FEC_AUTO) {
1988 /* no channel specified, autosearch the channel */ 1990 /* no channel specified, autosearch the channel */
1989 state->channel_status.status = CHANNEL_STATUS_PARAMETERS_UNKNOWN; 1991 state->channel_status.status = CHANNEL_STATUS_PARAMETERS_UNKNOWN;
1990 } else 1992 } else
@@ -2008,9 +2010,9 @@ static int dib9000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
2008 exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */ 2010 exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */
2009 index_frontend_success = 0; 2011 index_frontend_success = 0;
2010 do { 2012 do {
2011 sleep_time = dib9000_fw_tune(state->fe[0], NULL); 2013 sleep_time = dib9000_fw_tune(state->fe[0]);
2012 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { 2014 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2013 sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL); 2015 sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend]);
2014 if (sleep_time == FE_CALLBACK_TIME_NEVER) 2016 if (sleep_time == FE_CALLBACK_TIME_NEVER)
2015 sleep_time = sleep_time_slave; 2017 sleep_time = sleep_time_slave;
2016 else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time)) 2018 else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
@@ -2052,7 +2054,7 @@ static int dib9000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
2052 2054
2053 /* synchronize all the channel cache */ 2055 /* synchronize all the channel cache */
2054 state->get_frontend_internal = 1; 2056 state->get_frontend_internal = 1;
2055 dib9000_get_frontend(state->fe[0], fep); 2057 dib9000_get_frontend(state->fe[0]);
2056 state->get_frontend_internal = 0; 2058 state->get_frontend_internal = 0;
2057 2059
2058 /* retune the other frontends with the found channel */ 2060 /* retune the other frontends with the found channel */
@@ -2068,7 +2070,7 @@ static int dib9000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
2068 sleep_time = FE_CALLBACK_TIME_NEVER; 2070 sleep_time = FE_CALLBACK_TIME_NEVER;
2069 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { 2071 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2070 if (index_frontend != index_frontend_success) { 2072 if (index_frontend != index_frontend_success) {
2071 sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL); 2073 sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend]);
2072 if (sleep_time == FE_CALLBACK_TIME_NEVER) 2074 if (sleep_time == FE_CALLBACK_TIME_NEVER)
2073 sleep_time = sleep_time_slave; 2075 sleep_time = sleep_time_slave;
2074 else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time)) 2076 else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
@@ -2495,9 +2497,9 @@ error:
2495EXPORT_SYMBOL(dib9000_attach); 2497EXPORT_SYMBOL(dib9000_attach);
2496 2498
2497static struct dvb_frontend_ops dib9000_ops = { 2499static struct dvb_frontend_ops dib9000_ops = {
2500 .delsys = { SYS_DVBT },
2498 .info = { 2501 .info = {
2499 .name = "DiBcom 9000", 2502 .name = "DiBcom 9000",
2500 .type = FE_OFDM,
2501 .frequency_min = 44250000, 2503 .frequency_min = 44250000,
2502 .frequency_max = 867250000, 2504 .frequency_max = 867250000,
2503 .frequency_stepsize = 62500, 2505 .frequency_stepsize = 62500,
diff --git a/drivers/media/dvb/frontends/dibx000_common.h b/drivers/media/dvb/frontends/dibx000_common.h
index 5e011474be43..5f484881d7b1 100644
--- a/drivers/media/dvb/frontends/dibx000_common.h
+++ b/drivers/media/dvb/frontends/dibx000_common.h
@@ -146,14 +146,8 @@ enum dibx000_adc_states {
146 DIBX000_VBG_DISABLE, 146 DIBX000_VBG_DISABLE,
147}; 147};
148 148
149#define BANDWIDTH_TO_KHZ(v) ((v) == BANDWIDTH_8_MHZ ? 8000 : \ 149#define BANDWIDTH_TO_KHZ(v) ((v) / 1000)
150 (v) == BANDWIDTH_7_MHZ ? 7000 : \ 150#define BANDWIDTH_TO_HZ(v) ((v) * 1000)
151 (v) == BANDWIDTH_6_MHZ ? 6000 : 8000)
152
153#define BANDWIDTH_TO_INDEX(v) ( \
154 (v) == 8000 ? BANDWIDTH_8_MHZ : \
155 (v) == 7000 ? BANDWIDTH_7_MHZ : \
156 (v) == 6000 ? BANDWIDTH_6_MHZ : BANDWIDTH_8_MHZ )
157 151
158/* Chip output mode. */ 152/* Chip output mode. */
159#define OUTMODE_HIGH_Z 0 153#define OUTMODE_HIGH_Z 0
@@ -276,4 +270,11 @@ struct dibSubbandSelection {
276#define DEMOD_TIMF_GET 0x01 270#define DEMOD_TIMF_GET 0x01
277#define DEMOD_TIMF_UPDATE 0x02 271#define DEMOD_TIMF_UPDATE 0x02
278 272
273#define MPEG_ON_DIBTX 1
274#define DIV_ON_DIBTX 2
275#define ADC_ON_DIBTX 3
276#define DEMOUT_ON_HOSTBUS 4
277#define DIBTX_ON_HOSTBUS 5
278#define MPEG_ON_HOSTBUS 6
279
279#endif 280#endif
diff --git a/drivers/media/dvb/frontends/drxd.h b/drivers/media/dvb/frontends/drxd.h
index 7113535844f2..34398738f9bc 100644
--- a/drivers/media/dvb/frontends/drxd.h
+++ b/drivers/media/dvb/frontends/drxd.h
@@ -48,8 +48,6 @@ struct drxd_config {
48 u8 disable_i2c_gate_ctrl; 48 u8 disable_i2c_gate_ctrl;
49 49
50 u32 IF; 50 u32 IF;
51 int (*pll_set) (void *priv, void *priv_params,
52 u8 pll_addr, u8 demoda_addr, s32 *off);
53 s16(*osc_deviation) (void *priv, s16 dev, int flag); 51 s16(*osc_deviation) (void *priv, s16 dev, int flag);
54}; 52};
55 53
diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c
index 88e46f4cdbb2..7bf39cda83c5 100644
--- a/drivers/media/dvb/frontends/drxd_hard.c
+++ b/drivers/media/dvb/frontends/drxd_hard.c
@@ -120,7 +120,7 @@ enum EIFFilter {
120struct drxd_state { 120struct drxd_state {
121 struct dvb_frontend frontend; 121 struct dvb_frontend frontend;
122 struct dvb_frontend_ops ops; 122 struct dvb_frontend_ops ops;
123 struct dvb_frontend_parameters param; 123 struct dtv_frontend_properties props;
124 124
125 const struct firmware *fw; 125 const struct firmware *fw;
126 struct device *dev; 126 struct device *dev;
@@ -914,14 +914,13 @@ static int load_firmware(struct drxd_state *state, const char *fw_name)
914 return -EIO; 914 return -EIO;
915 } 915 }
916 916
917 state->microcode = kmalloc(fw->size, GFP_KERNEL); 917 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL);
918 if (state->microcode == NULL) { 918 if (state->microcode == NULL) {
919 release_firmware(fw); 919 release_firmware(fw);
920 printk(KERN_ERR "drxd: firmware load failure: no memory\n"); 920 printk(KERN_ERR "drxd: firmware load failure: no memory\n");
921 return -ENOMEM; 921 return -ENOMEM;
922 } 922 }
923 923
924 memcpy(state->microcode, fw->data, fw->size);
925 state->microcode_length = fw->size; 924 state->microcode_length = fw->size;
926 release_firmware(fw); 925 release_firmware(fw);
927 return 0; 926 return 0;
@@ -1622,14 +1621,14 @@ static int CorrectSysClockDeviation(struct drxd_state *state)
1622 break; 1621 break;
1623 } 1622 }
1624 1623
1625 switch (state->param.u.ofdm.bandwidth) { 1624 switch (state->props.bandwidth_hz) {
1626 case BANDWIDTH_8_MHZ: 1625 case 8000000:
1627 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ; 1626 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1628 break; 1627 break;
1629 case BANDWIDTH_7_MHZ: 1628 case 7000000:
1630 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ; 1629 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1631 break; 1630 break;
1632 case BANDWIDTH_6_MHZ: 1631 case 6000000:
1633 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ; 1632 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1634 break; 1633 break;
1635 default: 1634 default:
@@ -1804,7 +1803,7 @@ static int StartDiversity(struct drxd_state *state)
1804 status = WriteTable(state, state->m_StartDiversityEnd); 1803 status = WriteTable(state, state->m_StartDiversityEnd);
1805 if (status < 0) 1804 if (status < 0)
1806 break; 1805 break;
1807 if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) { 1806 if (state->props.bandwidth_hz == 8000000) {
1808 status = WriteTable(state, state->m_DiversityDelay8MHZ); 1807 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1809 if (status < 0) 1808 if (status < 0)
1810 break; 1809 break;
@@ -1906,7 +1905,7 @@ static int SetCfgNoiseCalibration(struct drxd_state *state,
1906 1905
1907static int DRX_Start(struct drxd_state *state, s32 off) 1906static int DRX_Start(struct drxd_state *state, s32 off)
1908{ 1907{
1909 struct dvb_ofdm_parameters *p = &state->param.u.ofdm; 1908 struct dtv_frontend_properties *p = &state->props;
1910 int status; 1909 int status;
1911 1910
1912 u16 transmissionParams = 0; 1911 u16 transmissionParams = 0;
@@ -1971,7 +1970,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
1971 if (status < 0) 1970 if (status < 0)
1972 break; 1971 break;
1973 1972
1974 mirrorFreqSpect = (state->param.inversion == INVERSION_ON); 1973 mirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1975 1974
1976 switch (p->transmission_mode) { 1975 switch (p->transmission_mode) {
1977 default: /* Not set, detect it automatically */ 1976 default: /* Not set, detect it automatically */
@@ -2021,7 +2020,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2021 break; 2020 break;
2022 } 2021 }
2023 2022
2024 switch (p->hierarchy_information) { 2023 switch (p->hierarchy) {
2025 case HIERARCHY_1: 2024 case HIERARCHY_1:
2026 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1; 2025 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
2027 if (state->type_A) { 2026 if (state->type_A) {
@@ -2147,7 +2146,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2147 if (status < 0) 2146 if (status < 0)
2148 break; 2147 break;
2149 2148
2150 switch (p->constellation) { 2149 switch (p->modulation) {
2151 default: 2150 default:
2152 operationMode |= SC_RA_RAM_OP_AUTO_CONST__M; 2151 operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2153 /* fall through , try first guess 2152 /* fall through , try first guess
@@ -2331,9 +2330,11 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2331 by SC for fix for some 8K,1/8 guard but is restored by 2330 by SC for fix for some 8K,1/8 guard but is restored by
2332 InitEC and ResetEC 2331 InitEC and ResetEC
2333 functions */ 2332 functions */
2334 switch (p->bandwidth) { 2333 switch (p->bandwidth_hz) {
2335 case BANDWIDTH_AUTO: 2334 case 0:
2336 case BANDWIDTH_8_MHZ: 2335 p->bandwidth_hz = 8000000;
2336 /* fall through */
2337 case 8000000:
2337 /* (64/7)*(8/8)*1000000 */ 2338 /* (64/7)*(8/8)*1000000 */
2338 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ; 2339 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2339 2340
@@ -2341,14 +2342,14 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2341 status = Write16(state, 2342 status = Write16(state,
2342 FE_AG_REG_IND_DEL__A, 50, 0x0000); 2343 FE_AG_REG_IND_DEL__A, 50, 0x0000);
2343 break; 2344 break;
2344 case BANDWIDTH_7_MHZ: 2345 case 7000000:
2345 /* (64/7)*(7/8)*1000000 */ 2346 /* (64/7)*(7/8)*1000000 */
2346 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ; 2347 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
2347 bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */ 2348 bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
2348 status = Write16(state, 2349 status = Write16(state,
2349 FE_AG_REG_IND_DEL__A, 59, 0x0000); 2350 FE_AG_REG_IND_DEL__A, 59, 0x0000);
2350 break; 2351 break;
2351 case BANDWIDTH_6_MHZ: 2352 case 6000000:
2352 /* (64/7)*(6/8)*1000000 */ 2353 /* (64/7)*(6/8)*1000000 */
2353 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ; 2354 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
2354 bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */ 2355 bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
@@ -2887,41 +2888,26 @@ static int drxd_sleep(struct dvb_frontend *fe)
2887 return 0; 2888 return 0;
2888} 2889}
2889 2890
2890static int drxd_get_frontend(struct dvb_frontend *fe,
2891 struct dvb_frontend_parameters *param)
2892{
2893 return 0;
2894}
2895
2896static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 2891static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2897{ 2892{
2898 return drxd_config_i2c(fe, enable); 2893 return drxd_config_i2c(fe, enable);
2899} 2894}
2900 2895
2901static int drxd_set_frontend(struct dvb_frontend *fe, 2896static int drxd_set_frontend(struct dvb_frontend *fe)
2902 struct dvb_frontend_parameters *param)
2903{ 2897{
2898 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2904 struct drxd_state *state = fe->demodulator_priv; 2899 struct drxd_state *state = fe->demodulator_priv;
2905 s32 off = 0; 2900 s32 off = 0;
2906 2901
2907 state->param = *param; 2902 state->props = *p;
2908 DRX_Stop(state); 2903 DRX_Stop(state);
2909 2904
2910 if (fe->ops.tuner_ops.set_params) { 2905 if (fe->ops.tuner_ops.set_params) {
2911 fe->ops.tuner_ops.set_params(fe, param); 2906 fe->ops.tuner_ops.set_params(fe);
2912 if (fe->ops.i2c_gate_ctrl) 2907 if (fe->ops.i2c_gate_ctrl)
2913 fe->ops.i2c_gate_ctrl(fe, 0); 2908 fe->ops.i2c_gate_ctrl(fe, 0);
2914 } 2909 }
2915 2910
2916 /* FIXME: move PLL drivers */
2917 if (state->config.pll_set &&
2918 state->config.pll_set(state->priv, param,
2919 state->config.pll_address,
2920 state->config.demoda_address, &off) < 0) {
2921 printk(KERN_ERR "Error in pll_set\n");
2922 return -1;
2923 }
2924
2925 msleep(200); 2911 msleep(200);
2926 2912
2927 return DRX_Start(state, off); 2913 return DRX_Start(state, off);
@@ -2935,10 +2921,9 @@ static void drxd_release(struct dvb_frontend *fe)
2935} 2921}
2936 2922
2937static struct dvb_frontend_ops drxd_ops = { 2923static struct dvb_frontend_ops drxd_ops = {
2938 2924 .delsys = { SYS_DVBT},
2939 .info = { 2925 .info = {
2940 .name = "Micronas DRXD DVB-T", 2926 .name = "Micronas DRXD DVB-T",
2941 .type = FE_OFDM,
2942 .frequency_min = 47125000, 2927 .frequency_min = 47125000,
2943 .frequency_max = 855250000, 2928 .frequency_max = 855250000,
2944 .frequency_stepsize = 166667, 2929 .frequency_stepsize = 166667,
@@ -2958,7 +2943,6 @@ static struct dvb_frontend_ops drxd_ops = {
2958 .i2c_gate_ctrl = drxd_i2c_gate_ctrl, 2943 .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2959 2944
2960 .set_frontend = drxd_set_frontend, 2945 .set_frontend = drxd_set_frontend,
2961 .get_frontend = drxd_get_frontend,
2962 .get_tune_settings = drxd_get_tune_settings, 2946 .get_tune_settings = drxd_get_tune_settings,
2963 2947
2964 .read_status = drxd_read_status, 2948 .read_status = drxd_read_status,
diff --git a/drivers/media/dvb/frontends/drxk.h b/drivers/media/dvb/frontends/drxk.h
index 58baf419560c..020981844a86 100644
--- a/drivers/media/dvb/frontends/drxk.h
+++ b/drivers/media/dvb/frontends/drxk.h
@@ -8,6 +8,8 @@
8 * struct drxk_config - Configure the initial parameters for DRX-K 8 * struct drxk_config - Configure the initial parameters for DRX-K
9 * 9 *
10 * adr: I2C Address of the DRX-K 10 * adr: I2C Address of the DRX-K
11 * parallel_ts: true means that the device uses parallel TS,
12 * Serial otherwise.
11 * single_master: Device is on the single master mode 13 * single_master: Device is on the single master mode
12 * no_i2c_bridge: Don't switch the I2C bridge to talk with tuner 14 * no_i2c_bridge: Don't switch the I2C bridge to talk with tuner
13 * antenna_gpio: GPIO bit used to control the antenna 15 * antenna_gpio: GPIO bit used to control the antenna
@@ -22,22 +24,23 @@ struct drxk_config {
22 u8 adr; 24 u8 adr;
23 bool single_master; 25 bool single_master;
24 bool no_i2c_bridge; 26 bool no_i2c_bridge;
27 bool parallel_ts;
25 28
26 bool antenna_dvbt; 29 bool antenna_dvbt;
27 u16 antenna_gpio; 30 u16 antenna_gpio;
28 31
32 int chunk_size;
33
29 const char *microcode_name; 34 const char *microcode_name;
30}; 35};
31 36
32#if defined(CONFIG_DVB_DRXK) || (defined(CONFIG_DVB_DRXK_MODULE) \ 37#if defined(CONFIG_DVB_DRXK) || (defined(CONFIG_DVB_DRXK_MODULE) \
33 && defined(MODULE)) 38 && defined(MODULE))
34extern struct dvb_frontend *drxk_attach(const struct drxk_config *config, 39extern struct dvb_frontend *drxk_attach(const struct drxk_config *config,
35 struct i2c_adapter *i2c, 40 struct i2c_adapter *i2c);
36 struct dvb_frontend **fe_t);
37#else 41#else
38static inline struct dvb_frontend *drxk_attach(const struct drxk_config *config, 42static inline struct dvb_frontend *drxk_attach(const struct drxk_config *config,
39 struct i2c_adapter *i2c, 43 struct i2c_adapter *i2c)
40 struct dvb_frontend **fe_t)
41{ 44{
42 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 45 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
43 return NULL; 46 return NULL;
diff --git a/drivers/media/dvb/frontends/drxk_hard.c b/drivers/media/dvb/frontends/drxk_hard.c
index f6431ef827dc..6980ed7b8786 100644
--- a/drivers/media/dvb/frontends/drxk_hard.c
+++ b/drivers/media/dvb/frontends/drxk_hard.c
@@ -368,10 +368,10 @@ static int i2c_read(struct i2c_adapter *adap,
368 } 368 }
369 if (debug > 2) { 369 if (debug > 2) {
370 int i; 370 int i;
371 dprintk(2, ": read from "); 371 dprintk(2, ": read from");
372 for (i = 0; i < len; i++) 372 for (i = 0; i < len; i++)
373 printk(KERN_CONT " %02x", msg[i]); 373 printk(KERN_CONT " %02x", msg[i]);
374 printk(KERN_CONT "Value = "); 374 printk(KERN_CONT ", value = ");
375 for (i = 0; i < alen; i++) 375 for (i = 0; i < alen; i++)
376 printk(KERN_CONT " %02x", answ[i]); 376 printk(KERN_CONT " %02x", answ[i]);
377 printk(KERN_CONT "\n"); 377 printk(KERN_CONT "\n");
@@ -660,7 +660,6 @@ static int init_state(struct drxk_state *state)
660 /* io_pad_cfg_mode output mode is drive always */ 660 /* io_pad_cfg_mode output mode is drive always */
661 /* io_pad_cfg_drive is set to power 2 (23 mA) */ 661 /* io_pad_cfg_drive is set to power 2 (23 mA) */
662 u32 ulGPIOCfg = 0x0113; 662 u32 ulGPIOCfg = 0x0113;
663 u32 ulSerialMode = 1;
664 u32 ulInvertTSClock = 0; 663 u32 ulInvertTSClock = 0;
665 u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; 664 u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
666 u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH; 665 u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH;
@@ -681,7 +680,8 @@ static int init_state(struct drxk_state *state)
681 state->m_hasOOB = false; 680 state->m_hasOOB = false;
682 state->m_hasAudio = false; 681 state->m_hasAudio = false;
683 682
684 state->m_ChunkSize = 124; 683 if (!state->m_ChunkSize)
684 state->m_ChunkSize = 124;
685 685
686 state->m_oscClockFreq = 0; 686 state->m_oscClockFreq = 0;
687 state->m_smartAntInverted = false; 687 state->m_smartAntInverted = false;
@@ -810,8 +810,6 @@ static int init_state(struct drxk_state *state)
810 /* MPEG output configuration */ 810 /* MPEG output configuration */
811 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ 811 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
812 state->m_insertRSByte = false; /* If TRUE; insert RS byte */ 812 state->m_insertRSByte = false; /* If TRUE; insert RS byte */
813 state->m_enableParallel = true; /* If TRUE;
814 parallel out otherwise serial */
815 state->m_invertDATA = false; /* If TRUE; invert DATA signals */ 813 state->m_invertDATA = false; /* If TRUE; invert DATA signals */
816 state->m_invertERR = false; /* If TRUE; invert ERR signal */ 814 state->m_invertERR = false; /* If TRUE; invert ERR signal */
817 state->m_invertSTR = false; /* If TRUE; invert STR signals */ 815 state->m_invertSTR = false; /* If TRUE; invert STR signals */
@@ -856,8 +854,6 @@ static int init_state(struct drxk_state *state)
856 state->m_bPowerDown = false; 854 state->m_bPowerDown = false;
857 state->m_currentPowerMode = DRX_POWER_DOWN; 855 state->m_currentPowerMode = DRX_POWER_DOWN;
858 856
859 state->m_enableParallel = (ulSerialMode == 0);
860
861 state->m_rfmirror = (ulRfMirror == 0); 857 state->m_rfmirror = (ulRfMirror == 0);
862 state->m_IfAgcPol = false; 858 state->m_IfAgcPol = false;
863 return 0; 859 return 0;
@@ -946,6 +942,9 @@ static int GetDeviceCapabilities(struct drxk_state *state)
946 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo); 942 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
947 if (status < 0) 943 if (status < 0)
948 goto error; 944 goto error;
945
946printk(KERN_ERR "drxk: status = 0x%08x\n", sioTopJtagidLo);
947
949 /* driver 0.9.0 */ 948 /* driver 0.9.0 */
950 switch ((sioTopJtagidLo >> 29) & 0xF) { 949 switch ((sioTopJtagidLo >> 29) & 0xF) {
951 case 0: 950 case 0:
@@ -963,7 +962,8 @@ static int GetDeviceCapabilities(struct drxk_state *state)
963 default: 962 default:
964 state->m_deviceSpin = DRXK_SPIN_UNKNOWN; 963 state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
965 status = -EINVAL; 964 status = -EINVAL;
966 printk(KERN_ERR "drxk: Spin unknown\n"); 965 printk(KERN_ERR "drxk: Spin %d unknown\n",
966 (sioTopJtagidLo >> 29) & 0xF);
967 goto error2; 967 goto error2;
968 } 968 }
969 switch ((sioTopJtagidLo >> 12) & 0xFF) { 969 switch ((sioTopJtagidLo >> 12) & 0xFF) {
@@ -1190,7 +1190,9 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1190 u16 sioPdrMclkCfg = 0; 1190 u16 sioPdrMclkCfg = 0;
1191 u16 sioPdrMdxCfg = 0; 1191 u16 sioPdrMdxCfg = 0;
1192 1192
1193 dprintk(1, "\n"); 1193 dprintk(1, ": mpeg %s, %s mode\n",
1194 mpegEnable ? "enable" : "disable",
1195 state->m_enableParallel ? "parallel" : "serial");
1194 1196
1195 /* stop lock indicator process */ 1197 /* stop lock indicator process */
1196 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 1198 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
@@ -1846,6 +1848,7 @@ static int SetOperationMode(struct drxk_state *state,
1846 */ 1848 */
1847 switch (oMode) { 1849 switch (oMode) {
1848 case OM_DVBT: 1850 case OM_DVBT:
1851 dprintk(1, ": DVB-T\n");
1849 state->m_OperationMode = oMode; 1852 state->m_OperationMode = oMode;
1850 status = SetDVBTStandard(state, oMode); 1853 status = SetDVBTStandard(state, oMode);
1851 if (status < 0) 1854 if (status < 0)
@@ -1853,6 +1856,8 @@ static int SetOperationMode(struct drxk_state *state,
1853 break; 1856 break;
1854 case OM_QAM_ITU_A: /* fallthrough */ 1857 case OM_QAM_ITU_A: /* fallthrough */
1855 case OM_QAM_ITU_C: 1858 case OM_QAM_ITU_C:
1859 dprintk(1, ": DVB-C Annex %c\n",
1860 (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C');
1856 state->m_OperationMode = oMode; 1861 state->m_OperationMode = oMode;
1857 status = SetQAMStandard(state, oMode); 1862 status = SetQAMStandard(state, oMode);
1858 if (status < 0) 1863 if (status < 0)
@@ -1881,7 +1886,7 @@ static int Start(struct drxk_state *state, s32 offsetFreq,
1881 state->m_DrxkState != DRXK_DTV_STARTED) 1886 state->m_DrxkState != DRXK_DTV_STARTED)
1882 goto error; 1887 goto error;
1883 1888
1884 state->m_bMirrorFreqSpect = (state->param.inversion == INVERSION_ON); 1889 state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1885 1890
1886 if (IntermediateFrequency < 0) { 1891 if (IntermediateFrequency < 0) {
1887 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; 1892 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
@@ -2503,7 +2508,7 @@ static int GetQAMSignalToNoise(struct drxk_state *state,
2503 u16 qamSlErrPower = 0; /* accum. error between 2508 u16 qamSlErrPower = 0; /* accum. error between
2504 raw and sliced symbols */ 2509 raw and sliced symbols */
2505 u32 qamSlSigPower = 0; /* used for MER, depends of 2510 u32 qamSlSigPower = 0; /* used for MER, depends of
2506 QAM constellation */ 2511 QAM modulation */
2507 u32 qamSlMer = 0; /* QAM MER */ 2512 u32 qamSlMer = 0; /* QAM MER */
2508 2513
2509 dprintk(1, "\n"); 2514 dprintk(1, "\n");
@@ -2517,7 +2522,7 @@ static int GetQAMSignalToNoise(struct drxk_state *state,
2517 return -EINVAL; 2522 return -EINVAL;
2518 } 2523 }
2519 2524
2520 switch (state->param.u.qam.modulation) { 2525 switch (state->props.modulation) {
2521 case QAM_16: 2526 case QAM_16:
2522 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; 2527 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2523 break; 2528 break;
@@ -2748,7 +2753,7 @@ static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2748 if (status < 0) 2753 if (status < 0)
2749 break; 2754 break;
2750 2755
2751 switch (state->param.u.qam.modulation) { 2756 switch (state->props.modulation) {
2752 case QAM_16: 2757 case QAM_16:
2753 SignalToNoiseRel = SignalToNoise - 200; 2758 SignalToNoiseRel = SignalToNoise - 200;
2754 break; 2759 break;
@@ -3813,7 +3818,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3813 /*== Write channel settings to device =====================================*/ 3818 /*== Write channel settings to device =====================================*/
3814 3819
3815 /* mode */ 3820 /* mode */
3816 switch (state->param.u.ofdm.transmission_mode) { 3821 switch (state->props.transmission_mode) {
3817 case TRANSMISSION_MODE_AUTO: 3822 case TRANSMISSION_MODE_AUTO:
3818 default: 3823 default:
3819 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; 3824 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
@@ -3827,7 +3832,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3827 } 3832 }
3828 3833
3829 /* guard */ 3834 /* guard */
3830 switch (state->param.u.ofdm.guard_interval) { 3835 switch (state->props.guard_interval) {
3831 default: 3836 default:
3832 case GUARD_INTERVAL_AUTO: 3837 case GUARD_INTERVAL_AUTO:
3833 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; 3838 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
@@ -3847,7 +3852,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3847 } 3852 }
3848 3853
3849 /* hierarchy */ 3854 /* hierarchy */
3850 switch (state->param.u.ofdm.hierarchy_information) { 3855 switch (state->props.hierarchy) {
3851 case HIERARCHY_AUTO: 3856 case HIERARCHY_AUTO:
3852 case HIERARCHY_NONE: 3857 case HIERARCHY_NONE:
3853 default: 3858 default:
@@ -3867,8 +3872,8 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3867 } 3872 }
3868 3873
3869 3874
3870 /* constellation */ 3875 /* modulation */
3871 switch (state->param.u.ofdm.constellation) { 3876 switch (state->props.modulation) {
3872 case QAM_AUTO: 3877 case QAM_AUTO:
3873 default: 3878 default:
3874 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; 3879 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
@@ -3911,7 +3916,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3911#endif 3916#endif
3912 3917
3913 /* coderate */ 3918 /* coderate */
3914 switch (state->param.u.ofdm.code_rate_HP) { 3919 switch (state->props.code_rate_HP) {
3915 case FEC_AUTO: 3920 case FEC_AUTO:
3916 default: 3921 default:
3917 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; 3922 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
@@ -3940,9 +3945,11 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3940 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed 3945 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3941 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC 3946 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3942 functions */ 3947 functions */
3943 switch (state->param.u.ofdm.bandwidth) { 3948 switch (state->props.bandwidth_hz) {
3944 case BANDWIDTH_AUTO: 3949 case 0:
3945 case BANDWIDTH_8_MHZ: 3950 state->props.bandwidth_hz = 8000000;
3951 /* fall though */
3952 case 8000000:
3946 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; 3953 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3947 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052); 3954 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3948 if (status < 0) 3955 if (status < 0)
@@ -3961,7 +3968,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3961 if (status < 0) 3968 if (status < 0)
3962 goto error; 3969 goto error;
3963 break; 3970 break;
3964 case BANDWIDTH_7_MHZ: 3971 case 7000000:
3965 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; 3972 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3966 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491); 3973 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3967 if (status < 0) 3974 if (status < 0)
@@ -3980,7 +3987,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3980 if (status < 0) 3987 if (status < 0)
3981 goto error; 3988 goto error;
3982 break; 3989 break;
3983 case BANDWIDTH_6_MHZ: 3990 case 6000000:
3984 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; 3991 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3985 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073); 3992 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3986 if (status < 0) 3993 if (status < 0)
@@ -4187,7 +4194,7 @@ error:
4187/** 4194/**
4188* \brief Setup of the QAM Measurement intervals for signal quality 4195* \brief Setup of the QAM Measurement intervals for signal quality
4189* \param demod instance of demod. 4196* \param demod instance of demod.
4190* \param constellation current constellation. 4197* \param modulation current modulation.
4191* \return DRXStatus_t. 4198* \return DRXStatus_t.
4192* 4199*
4193* NOTE: 4200* NOTE:
@@ -4196,7 +4203,7 @@ error:
4196* 4203*
4197*/ 4204*/
4198static int SetQAMMeasurement(struct drxk_state *state, 4205static int SetQAMMeasurement(struct drxk_state *state,
4199 enum EDrxkConstellation constellation, 4206 enum EDrxkConstellation modulation,
4200 u32 symbolRate) 4207 u32 symbolRate)
4201{ 4208{
4202 u32 fecBitsDesired = 0; /* BER accounting period */ 4209 u32 fecBitsDesired = 0; /* BER accounting period */
@@ -4210,11 +4217,11 @@ static int SetQAMMeasurement(struct drxk_state *state,
4210 fecRsPrescale = 1; 4217 fecRsPrescale = 1;
4211 /* fecBitsDesired = symbolRate [kHz] * 4218 /* fecBitsDesired = symbolRate [kHz] *
4212 FrameLenght [ms] * 4219 FrameLenght [ms] *
4213 (constellation + 1) * 4220 (modulation + 1) *
4214 SyncLoss (== 1) * 4221 SyncLoss (== 1) *
4215 ViterbiLoss (==1) 4222 ViterbiLoss (==1)
4216 */ 4223 */
4217 switch (constellation) { 4224 switch (modulation) {
4218 case DRX_CONSTELLATION_QAM16: 4225 case DRX_CONSTELLATION_QAM16:
4219 fecBitsDesired = 4 * symbolRate; 4226 fecBitsDesired = 4 * symbolRate;
4220 break; 4227 break;
@@ -5281,12 +5288,12 @@ static int QAMSetSymbolrate(struct drxk_state *state)
5281 /* Select & calculate correct IQM rate */ 5288 /* Select & calculate correct IQM rate */
5282 adcFrequency = (state->m_sysClockFreq * 1000) / 3; 5289 adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5283 ratesel = 0; 5290 ratesel = 0;
5284 /* printk(KERN_DEBUG "drxk: SR %d\n", state->param.u.qam.symbol_rate); */ 5291 /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */
5285 if (state->param.u.qam.symbol_rate <= 1188750) 5292 if (state->props.symbol_rate <= 1188750)
5286 ratesel = 3; 5293 ratesel = 3;
5287 else if (state->param.u.qam.symbol_rate <= 2377500) 5294 else if (state->props.symbol_rate <= 2377500)
5288 ratesel = 2; 5295 ratesel = 2;
5289 else if (state->param.u.qam.symbol_rate <= 4755000) 5296 else if (state->props.symbol_rate <= 4755000)
5290 ratesel = 1; 5297 ratesel = 1;
5291 status = write16(state, IQM_FD_RATESEL__A, ratesel); 5298 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5292 if (status < 0) 5299 if (status < 0)
@@ -5295,7 +5302,7 @@ static int QAMSetSymbolrate(struct drxk_state *state)
5295 /* 5302 /*
5296 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23) 5303 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5297 */ 5304 */
5298 symbFreq = state->param.u.qam.symbol_rate * (1 << ratesel); 5305 symbFreq = state->props.symbol_rate * (1 << ratesel);
5299 if (symbFreq == 0) { 5306 if (symbFreq == 0) {
5300 /* Divide by zero */ 5307 /* Divide by zero */
5301 status = -EINVAL; 5308 status = -EINVAL;
@@ -5311,7 +5318,7 @@ static int QAMSetSymbolrate(struct drxk_state *state)
5311 /* 5318 /*
5312 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) 5319 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
5313 */ 5320 */
5314 symbFreq = state->param.u.qam.symbol_rate; 5321 symbFreq = state->props.symbol_rate;
5315 if (adcFrequency == 0) { 5322 if (adcFrequency == 0) {
5316 /* Divide by zero */ 5323 /* Divide by zero */
5317 status = -EINVAL; 5324 status = -EINVAL;
@@ -5412,7 +5419,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5412 goto error; 5419 goto error;
5413 5420
5414 /* Set params */ 5421 /* Set params */
5415 switch (state->param.u.qam.modulation) { 5422 switch (state->props.modulation) {
5416 case QAM_256: 5423 case QAM_256:
5417 state->m_Constellation = DRX_CONSTELLATION_QAM256; 5424 state->m_Constellation = DRX_CONSTELLATION_QAM256;
5418 break; 5425 break;
@@ -5435,7 +5442,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5435 } 5442 }
5436 if (status < 0) 5443 if (status < 0)
5437 goto error; 5444 goto error;
5438 setParamParameters[0] = state->m_Constellation; /* constellation */ 5445 setParamParameters[0] = state->m_Constellation; /* modulation */
5439 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ 5446 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5440 if (state->m_OperationMode == OM_QAM_ITU_C) 5447 if (state->m_OperationMode == OM_QAM_ITU_C)
5441 setParamParameters[2] = QAM_TOP_ANNEX_C; 5448 setParamParameters[2] = QAM_TOP_ANNEX_C;
@@ -5457,7 +5464,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5457 if (status < 0) 5464 if (status < 0)
5458 goto error; 5465 goto error;
5459 5466
5460 setParamParameters[0] = state->m_Constellation; /* constellation */ 5467 setParamParameters[0] = state->m_Constellation; /* modulation */
5461 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ 5468 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5462 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2, setParamParameters, 1, &cmdResult); 5469 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2, setParamParameters, 1, &cmdResult);
5463 } 5470 }
@@ -5466,7 +5473,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5466 5473
5467 /* 5474 /*
5468 * STEP 3: enable the system in a mode where the ADC provides valid 5475 * STEP 3: enable the system in a mode where the ADC provides valid
5469 * signal setup constellation independent registers 5476 * signal setup modulation independent registers
5470 */ 5477 */
5471#if 0 5478#if 0
5472 status = SetFrequency(channel, tunerFreqOffset)); 5479 status = SetFrequency(channel, tunerFreqOffset));
@@ -5478,7 +5485,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5478 goto error; 5485 goto error;
5479 5486
5480 /* Setup BER measurement */ 5487 /* Setup BER measurement */
5481 status = SetQAMMeasurement(state, state->m_Constellation, state->param.u. qam.symbol_rate); 5488 status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate);
5482 if (status < 0) 5489 if (status < 0)
5483 goto error; 5490 goto error;
5484 5491
@@ -5560,8 +5567,8 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5560 if (status < 0) 5567 if (status < 0)
5561 goto error; 5568 goto error;
5562 5569
5563 /* STEP 4: constellation specific setup */ 5570 /* STEP 4: modulation specific setup */
5564 switch (state->param.u.qam.modulation) { 5571 switch (state->props.modulation) {
5565 case QAM_16: 5572 case QAM_16:
5566 status = SetQAM16(state); 5573 status = SetQAM16(state);
5567 break; 5574 break;
@@ -5591,7 +5598,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5591 goto error; 5598 goto error;
5592 5599
5593 /* Re-configure MPEG output, requires knowledge of channel bitrate */ 5600 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5594 /* extAttr->currentChannel.constellation = channel->constellation; */ 5601 /* extAttr->currentChannel.modulation = channel->modulation; */
5595 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ 5602 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5596 status = MPEGTSDtoSetup(state, state->m_OperationMode); 5603 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5597 if (status < 0) 5604 if (status < 0)
@@ -6167,7 +6174,7 @@ error:
6167 return status; 6174 return status;
6168} 6175}
6169 6176
6170static void drxk_c_release(struct dvb_frontend *fe) 6177static void drxk_release(struct dvb_frontend *fe)
6171{ 6178{
6172 struct drxk_state *state = fe->demodulator_priv; 6179 struct drxk_state *state = fe->demodulator_priv;
6173 6180
@@ -6175,24 +6182,12 @@ static void drxk_c_release(struct dvb_frontend *fe)
6175 kfree(state); 6182 kfree(state);
6176} 6183}
6177 6184
6178static int drxk_c_init(struct dvb_frontend *fe) 6185static int drxk_sleep(struct dvb_frontend *fe)
6179{
6180 struct drxk_state *state = fe->demodulator_priv;
6181
6182 dprintk(1, "\n");
6183 if (mutex_trylock(&state->ctlock) == 0)
6184 return -EBUSY;
6185 SetOperationMode(state, OM_QAM_ITU_A);
6186 return 0;
6187}
6188
6189static int drxk_c_sleep(struct dvb_frontend *fe)
6190{ 6186{
6191 struct drxk_state *state = fe->demodulator_priv; 6187 struct drxk_state *state = fe->demodulator_priv;
6192 6188
6193 dprintk(1, "\n"); 6189 dprintk(1, "\n");
6194 ShutDown(state); 6190 ShutDown(state);
6195 mutex_unlock(&state->ctlock);
6196 return 0; 6191 return 0;
6197} 6192}
6198 6193
@@ -6204,9 +6199,10 @@ static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6204 return ConfigureI2CBridge(state, enable ? true : false); 6199 return ConfigureI2CBridge(state, enable ? true : false);
6205} 6200}
6206 6201
6207static int drxk_set_parameters(struct dvb_frontend *fe, 6202static int drxk_set_parameters(struct dvb_frontend *fe)
6208 struct dvb_frontend_parameters *p)
6209{ 6203{
6204 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6205 u32 delsys = p->delivery_system, old_delsys;
6210 struct drxk_state *state = fe->demodulator_priv; 6206 struct drxk_state *state = fe->demodulator_priv;
6211 u32 IF; 6207 u32 IF;
6212 6208
@@ -6218,14 +6214,39 @@ static int drxk_set_parameters(struct dvb_frontend *fe,
6218 return -EINVAL; 6214 return -EINVAL;
6219 } 6215 }
6220 6216
6221
6222 if (fe->ops.i2c_gate_ctrl) 6217 if (fe->ops.i2c_gate_ctrl)
6223 fe->ops.i2c_gate_ctrl(fe, 1); 6218 fe->ops.i2c_gate_ctrl(fe, 1);
6224 if (fe->ops.tuner_ops.set_params) 6219 if (fe->ops.tuner_ops.set_params)
6225 fe->ops.tuner_ops.set_params(fe, p); 6220 fe->ops.tuner_ops.set_params(fe);
6226 if (fe->ops.i2c_gate_ctrl) 6221 if (fe->ops.i2c_gate_ctrl)
6227 fe->ops.i2c_gate_ctrl(fe, 0); 6222 fe->ops.i2c_gate_ctrl(fe, 0);
6228 state->param = *p; 6223
6224 old_delsys = state->props.delivery_system;
6225 state->props = *p;
6226
6227 if (old_delsys != delsys) {
6228 ShutDown(state);
6229 switch (delsys) {
6230 case SYS_DVBC_ANNEX_A:
6231 case SYS_DVBC_ANNEX_C:
6232 if (!state->m_hasDVBC)
6233 return -EINVAL;
6234 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false;
6235 if (state->m_itut_annex_c)
6236 SetOperationMode(state, OM_QAM_ITU_C);
6237 else
6238 SetOperationMode(state, OM_QAM_ITU_A);
6239 break;
6240 case SYS_DVBT:
6241 if (!state->m_hasDVBT)
6242 return -EINVAL;
6243 SetOperationMode(state, OM_DVBT);
6244 break;
6245 default:
6246 return -EINVAL;
6247 }
6248 }
6249
6229 fe->ops.tuner_ops.get_if_frequency(fe, &IF); 6250 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6230 Start(state, 0, IF); 6251 Start(state, 0, IF);
6231 6252
@@ -6234,13 +6255,6 @@ static int drxk_set_parameters(struct dvb_frontend *fe,
6234 return 0; 6255 return 0;
6235} 6256}
6236 6257
6237static int drxk_c_get_frontend(struct dvb_frontend *fe,
6238 struct dvb_frontend_parameters *p)
6239{
6240 dprintk(1, "\n");
6241 return 0;
6242}
6243
6244static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status) 6258static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6245{ 6259{
6246 struct drxk_state *state = fe->demodulator_priv; 6260 struct drxk_state *state = fe->demodulator_priv;
@@ -6300,102 +6314,54 @@ static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6300 return 0; 6314 return 0;
6301} 6315}
6302 6316
6303static int drxk_c_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings 6317static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
6304 *sets) 6318 *sets)
6305{ 6319{
6306 dprintk(1, "\n"); 6320 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6307 sets->min_delay_ms = 3000;
6308 sets->max_drift = 0;
6309 sets->step_size = 0;
6310 return 0;
6311}
6312
6313static void drxk_t_release(struct dvb_frontend *fe)
6314{
6315 /*
6316 * There's nothing to release here, as the state struct
6317 * is already freed by drxk_c_release.
6318 */
6319}
6320
6321static int drxk_t_init(struct dvb_frontend *fe)
6322{
6323 struct drxk_state *state = fe->demodulator_priv;
6324 6321
6325 dprintk(1, "\n"); 6322 dprintk(1, "\n");
6326 if (mutex_trylock(&state->ctlock) == 0) 6323 switch (p->delivery_system) {
6327 return -EBUSY; 6324 case SYS_DVBC_ANNEX_A:
6328 SetOperationMode(state, OM_DVBT); 6325 case SYS_DVBC_ANNEX_C:
6329 return 0; 6326 sets->min_delay_ms = 3000;
6330} 6327 sets->max_drift = 0;
6331 6328 sets->step_size = 0;
6332static int drxk_t_sleep(struct dvb_frontend *fe) 6329 return 0;
6333{ 6330 default:
6334 struct drxk_state *state = fe->demodulator_priv; 6331 /*
6335 6332 * For DVB-T, let it use the default DVB core way, that is:
6336 dprintk(1, "\n"); 6333 * fepriv->step_size = fe->ops.info.frequency_stepsize * 2
6337 mutex_unlock(&state->ctlock); 6334 */
6338 return 0; 6335 return -EINVAL;
6339} 6336 }
6340
6341static int drxk_t_get_frontend(struct dvb_frontend *fe,
6342 struct dvb_frontend_parameters *p)
6343{
6344 dprintk(1, "\n");
6345
6346 return 0;
6347} 6337}
6348 6338
6349static struct dvb_frontend_ops drxk_c_ops = { 6339static struct dvb_frontend_ops drxk_ops = {
6340 /* .delsys will be filled dynamically */
6350 .info = { 6341 .info = {
6351 .name = "DRXK DVB-C", 6342 .name = "DRXK",
6352 .type = FE_QAM, 6343 .frequency_min = 47000000,
6353 .frequency_stepsize = 62500, 6344 .frequency_max = 865000000,
6354 .frequency_min = 47000000, 6345 /* For DVB-C */
6355 .frequency_max = 862000000, 6346 .symbol_rate_min = 870000,
6356 .symbol_rate_min = 870000, 6347 .symbol_rate_max = 11700000,
6357 .symbol_rate_max = 11700000, 6348 /* For DVB-T */
6358 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | 6349 .frequency_stepsize = 166667,
6359 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO}, 6350
6360 .release = drxk_c_release, 6351 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6361 .init = drxk_c_init, 6352 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6362 .sleep = drxk_c_sleep, 6353 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6354 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6355 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6356 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6357 },
6358
6359 .release = drxk_release,
6360 .sleep = drxk_sleep,
6363 .i2c_gate_ctrl = drxk_gate_ctrl, 6361 .i2c_gate_ctrl = drxk_gate_ctrl,
6364 6362
6365 .set_frontend = drxk_set_parameters, 6363 .set_frontend = drxk_set_parameters,
6366 .get_frontend = drxk_c_get_frontend, 6364 .get_tune_settings = drxk_get_tune_settings,
6367 .get_tune_settings = drxk_c_get_tune_settings,
6368
6369 .read_status = drxk_read_status,
6370 .read_ber = drxk_read_ber,
6371 .read_signal_strength = drxk_read_signal_strength,
6372 .read_snr = drxk_read_snr,
6373 .read_ucblocks = drxk_read_ucblocks,
6374};
6375
6376static struct dvb_frontend_ops drxk_t_ops = {
6377 .info = {
6378 .name = "DRXK DVB-T",
6379 .type = FE_OFDM,
6380 .frequency_min = 47125000,
6381 .frequency_max = 865000000,
6382 .frequency_stepsize = 166667,
6383 .frequency_tolerance = 0,
6384 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
6385 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
6386 FE_CAN_FEC_AUTO |
6387 FE_CAN_QAM_16 | FE_CAN_QAM_64 |
6388 FE_CAN_QAM_AUTO |
6389 FE_CAN_TRANSMISSION_MODE_AUTO |
6390 FE_CAN_GUARD_INTERVAL_AUTO |
6391 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
6392 .release = drxk_t_release,
6393 .init = drxk_t_init,
6394 .sleep = drxk_t_sleep,
6395 .i2c_gate_ctrl = drxk_gate_ctrl,
6396
6397 .set_frontend = drxk_set_parameters,
6398 .get_frontend = drxk_t_get_frontend,
6399 6365
6400 .read_status = drxk_read_status, 6366 .read_status = drxk_read_status,
6401 .read_ber = drxk_read_ber, 6367 .read_ber = drxk_read_ber,
@@ -6405,9 +6371,10 @@ static struct dvb_frontend_ops drxk_t_ops = {
6405}; 6371};
6406 6372
6407struct dvb_frontend *drxk_attach(const struct drxk_config *config, 6373struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6408 struct i2c_adapter *i2c, 6374 struct i2c_adapter *i2c)
6409 struct dvb_frontend **fe_t)
6410{ 6375{
6376 int n;
6377
6411 struct drxk_state *state = NULL; 6378 struct drxk_state *state = NULL;
6412 u8 adr = config->adr; 6379 u8 adr = config->adr;
6413 6380
@@ -6423,6 +6390,12 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6423 state->no_i2c_bridge = config->no_i2c_bridge; 6390 state->no_i2c_bridge = config->no_i2c_bridge;
6424 state->antenna_gpio = config->antenna_gpio; 6391 state->antenna_gpio = config->antenna_gpio;
6425 state->antenna_dvbt = config->antenna_dvbt; 6392 state->antenna_dvbt = config->antenna_dvbt;
6393 state->m_ChunkSize = config->chunk_size;
6394
6395 if (config->parallel_ts)
6396 state->m_enableParallel = true;
6397 else
6398 state->m_enableParallel = false;
6426 6399
6427 /* NOTE: as more UIO bits will be used, add them to the mask */ 6400 /* NOTE: as more UIO bits will be used, add them to the mask */
6428 state->UIO_mask = config->antenna_gpio; 6401 state->UIO_mask = config->antenna_gpio;
@@ -6434,21 +6407,30 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6434 state->m_GPIO &= ~state->antenna_gpio; 6407 state->m_GPIO &= ~state->antenna_gpio;
6435 6408
6436 mutex_init(&state->mutex); 6409 mutex_init(&state->mutex);
6437 mutex_init(&state->ctlock);
6438 6410
6439 memcpy(&state->c_frontend.ops, &drxk_c_ops, 6411 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6440 sizeof(struct dvb_frontend_ops)); 6412 state->frontend.demodulator_priv = state;
6441 memcpy(&state->t_frontend.ops, &drxk_t_ops,
6442 sizeof(struct dvb_frontend_ops));
6443 state->c_frontend.demodulator_priv = state;
6444 state->t_frontend.demodulator_priv = state;
6445 6413
6446 init_state(state); 6414 init_state(state);
6447 if (init_drxk(state) < 0) 6415 if (init_drxk(state) < 0)
6448 goto error; 6416 goto error;
6449 *fe_t = &state->t_frontend;
6450 6417
6451 return &state->c_frontend; 6418 /* Initialize the supported delivery systems */
6419 n = 0;
6420 if (state->m_hasDVBC) {
6421 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6422 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6423 strlcat(state->frontend.ops.info.name, " DVB-C",
6424 sizeof(state->frontend.ops.info.name));
6425 }
6426 if (state->m_hasDVBT) {
6427 state->frontend.ops.delsys[n++] = SYS_DVBT;
6428 strlcat(state->frontend.ops.info.name, " DVB-T",
6429 sizeof(state->frontend.ops.info.name));
6430 }
6431
6432 printk(KERN_INFO "drxk: frontend initialized.\n");
6433 return &state->frontend;
6452 6434
6453error: 6435error:
6454 printk(KERN_ERR "drxk: not found\n"); 6436 printk(KERN_ERR "drxk: not found\n");
diff --git a/drivers/media/dvb/frontends/drxk_hard.h b/drivers/media/dvb/frontends/drxk_hard.h
index a05c32eecdcc..3a58b73eb9b9 100644
--- a/drivers/media/dvb/frontends/drxk_hard.h
+++ b/drivers/media/dvb/frontends/drxk_hard.h
@@ -195,9 +195,8 @@ struct DRXKOfdmScCmd_t {
195}; 195};
196 196
197struct drxk_state { 197struct drxk_state {
198 struct dvb_frontend c_frontend; 198 struct dvb_frontend frontend;
199 struct dvb_frontend t_frontend; 199 struct dtv_frontend_properties props;
200 struct dvb_frontend_parameters param;
201 struct device *dev; 200 struct device *dev;
202 201
203 struct i2c_adapter *i2c; 202 struct i2c_adapter *i2c;
@@ -205,7 +204,6 @@ struct drxk_state {
205 void *priv; 204 void *priv;
206 205
207 struct mutex mutex; 206 struct mutex mutex;
208 struct mutex ctlock;
209 207
210 u32 m_Instance; /**< Channel 1,2,3 or 4 */ 208 u32 m_Instance; /**< Channel 1,2,3 or 4 */
211 209
@@ -263,6 +261,8 @@ struct drxk_state {
263 u8 m_TSDataStrength; 261 u8 m_TSDataStrength;
264 u8 m_TSClockkStrength; 262 u8 m_TSClockkStrength;
265 263
264 bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */
265
266 enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width */ 266 enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width */
267 u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case 267 u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case
268 static clockrate is selected */ 268 static clockrate is selected */
diff --git a/drivers/media/dvb/frontends/ds3000.c b/drivers/media/dvb/frontends/ds3000.c
index 90bf573308b0..938777065de6 100644
--- a/drivers/media/dvb/frontends/ds3000.c
+++ b/drivers/media/dvb/frontends/ds3000.c
@@ -934,20 +934,6 @@ error2:
934} 934}
935EXPORT_SYMBOL(ds3000_attach); 935EXPORT_SYMBOL(ds3000_attach);
936 936
937static int ds3000_set_property(struct dvb_frontend *fe,
938 struct dtv_property *tvp)
939{
940 dprintk("%s(..)\n", __func__);
941 return 0;
942}
943
944static int ds3000_get_property(struct dvb_frontend *fe,
945 struct dtv_property *tvp)
946{
947 dprintk("%s(..)\n", __func__);
948 return 0;
949}
950
951static int ds3000_set_carrier_offset(struct dvb_frontend *fe, 937static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
952 s32 carrier_offset_khz) 938 s32 carrier_offset_khz)
953{ 939{
@@ -967,8 +953,7 @@ static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
967 return 0; 953 return 0;
968} 954}
969 955
970static int ds3000_set_frontend(struct dvb_frontend *fe, 956static int ds3000_set_frontend(struct dvb_frontend *fe)
971 struct dvb_frontend_parameters *p)
972{ 957{
973 struct ds3000_state *state = fe->demodulator_priv; 958 struct ds3000_state *state = fe->demodulator_priv;
974 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 959 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
@@ -994,15 +979,15 @@ static int ds3000_set_frontend(struct dvb_frontend *fe,
994 div4 = 0; 979 div4 = 0;
995 980
996 /* calculate and set freq divider */ 981 /* calculate and set freq divider */
997 if (p->frequency < 1146000) { 982 if (c->frequency < 1146000) {
998 ds3000_tuner_writereg(state, 0x10, 0x11); 983 ds3000_tuner_writereg(state, 0x10, 0x11);
999 div4 = 1; 984 div4 = 1;
1000 ndiv = ((p->frequency * (6 + 8) * 4) + 985 ndiv = ((c->frequency * (6 + 8) * 4) +
1001 (DS3000_XTAL_FREQ / 2)) / 986 (DS3000_XTAL_FREQ / 2)) /
1002 DS3000_XTAL_FREQ - 1024; 987 DS3000_XTAL_FREQ - 1024;
1003 } else { 988 } else {
1004 ds3000_tuner_writereg(state, 0x10, 0x01); 989 ds3000_tuner_writereg(state, 0x10, 0x01);
1005 ndiv = ((p->frequency * (6 + 8) * 2) + 990 ndiv = ((c->frequency * (6 + 8) * 2) +
1006 (DS3000_XTAL_FREQ / 2)) / 991 (DS3000_XTAL_FREQ / 2)) /
1007 DS3000_XTAL_FREQ - 1024; 992 DS3000_XTAL_FREQ - 1024;
1008 } 993 }
@@ -1101,7 +1086,7 @@ static int ds3000_set_frontend(struct dvb_frontend *fe,
1101 msleep(60); 1086 msleep(60);
1102 1087
1103 offset_khz = (ndiv - ndiv % 2 + 1024) * DS3000_XTAL_FREQ 1088 offset_khz = (ndiv - ndiv % 2 + 1024) * DS3000_XTAL_FREQ
1104 / (6 + 8) / (div4 + 1) / 2 - p->frequency; 1089 / (6 + 8) / (div4 + 1) / 2 - c->frequency;
1105 1090
1106 /* ds3000 global reset */ 1091 /* ds3000 global reset */
1107 ds3000_writereg(state, 0x07, 0x80); 1092 ds3000_writereg(state, 0x07, 0x80);
@@ -1220,13 +1205,13 @@ static int ds3000_set_frontend(struct dvb_frontend *fe,
1220} 1205}
1221 1206
1222static int ds3000_tune(struct dvb_frontend *fe, 1207static int ds3000_tune(struct dvb_frontend *fe,
1223 struct dvb_frontend_parameters *p, 1208 bool re_tune,
1224 unsigned int mode_flags, 1209 unsigned int mode_flags,
1225 unsigned int *delay, 1210 unsigned int *delay,
1226 fe_status_t *status) 1211 fe_status_t *status)
1227{ 1212{
1228 if (p) { 1213 if (re_tune) {
1229 int ret = ds3000_set_frontend(fe, p); 1214 int ret = ds3000_set_frontend(fe);
1230 if (ret) 1215 if (ret)
1231 return ret; 1216 return ret;
1232 } 1217 }
@@ -1279,10 +1264,9 @@ static int ds3000_sleep(struct dvb_frontend *fe)
1279} 1264}
1280 1265
1281static struct dvb_frontend_ops ds3000_ops = { 1266static struct dvb_frontend_ops ds3000_ops = {
1282 1267 .delsys = { SYS_DVBS, SYS_DVBS2},
1283 .info = { 1268 .info = {
1284 .name = "Montage Technology DS3000/TS2020", 1269 .name = "Montage Technology DS3000/TS2020",
1285 .type = FE_QPSK,
1286 .frequency_min = 950000, 1270 .frequency_min = 950000,
1287 .frequency_max = 2150000, 1271 .frequency_max = 2150000,
1288 .frequency_stepsize = 1011, /* kHz for QPSK frontends */ 1272 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
@@ -1312,8 +1296,6 @@ static struct dvb_frontend_ops ds3000_ops = {
1312 .diseqc_send_burst = ds3000_diseqc_send_burst, 1296 .diseqc_send_burst = ds3000_diseqc_send_burst,
1313 .get_frontend_algo = ds3000_get_algo, 1297 .get_frontend_algo = ds3000_get_algo,
1314 1298
1315 .set_property = ds3000_set_property,
1316 .get_property = ds3000_get_property,
1317 .set_frontend = ds3000_set_frontend, 1299 .set_frontend = ds3000_set_frontend,
1318 .tune = ds3000_tune, 1300 .tune = ds3000_tune,
1319}; 1301};
diff --git a/drivers/media/dvb/frontends/dvb-pll.c b/drivers/media/dvb/frontends/dvb-pll.c
index 62a65efdf8d6..1ab34838221c 100644
--- a/drivers/media/dvb/frontends/dvb-pll.c
+++ b/drivers/media/dvb/frontends/dvb-pll.c
@@ -61,8 +61,7 @@ struct dvb_pll_desc {
61 u32 min; 61 u32 min;
62 u32 max; 62 u32 max;
63 u32 iffreq; 63 u32 iffreq;
64 void (*set)(struct dvb_frontend *fe, u8 *buf, 64 void (*set)(struct dvb_frontend *fe, u8 *buf);
65 const struct dvb_frontend_parameters *params);
66 u8 *initdata; 65 u8 *initdata;
67 u8 *initdata2; 66 u8 *initdata2;
68 u8 *sleepdata; 67 u8 *sleepdata;
@@ -93,10 +92,10 @@ static struct dvb_pll_desc dvb_pll_thomson_dtt7579 = {
93 }, 92 },
94}; 93};
95 94
96static void thomson_dtt759x_bw(struct dvb_frontend *fe, u8 *buf, 95static void thomson_dtt759x_bw(struct dvb_frontend *fe, u8 *buf)
97 const struct dvb_frontend_parameters *params)
98{ 96{
99 if (BANDWIDTH_7_MHZ == params->u.ofdm.bandwidth) 97 u32 bw = fe->dtv_property_cache.bandwidth_hz;
98 if (bw == 7000000)
100 buf[3] |= 0x10; 99 buf[3] |= 0x10;
101} 100}
102 101
@@ -186,10 +185,10 @@ static struct dvb_pll_desc dvb_pll_env57h1xd5 = {
186/* Philips TDA6650/TDA6651 185/* Philips TDA6650/TDA6651
187 * used in Panasonic ENV77H11D5 186 * used in Panasonic ENV77H11D5
188 */ 187 */
189static void tda665x_bw(struct dvb_frontend *fe, u8 *buf, 188static void tda665x_bw(struct dvb_frontend *fe, u8 *buf)
190 const struct dvb_frontend_parameters *params)
191{ 189{
192 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) 190 u32 bw = fe->dtv_property_cache.bandwidth_hz;
191 if (bw == 8000000)
193 buf[3] |= 0x08; 192 buf[3] |= 0x08;
194} 193}
195 194
@@ -220,10 +219,10 @@ static struct dvb_pll_desc dvb_pll_tda665x = {
220/* Infineon TUA6034 219/* Infineon TUA6034
221 * used in LG TDTP E102P 220 * used in LG TDTP E102P
222 */ 221 */
223static void tua6034_bw(struct dvb_frontend *fe, u8 *buf, 222static void tua6034_bw(struct dvb_frontend *fe, u8 *buf)
224 const struct dvb_frontend_parameters *params)
225{ 223{
226 if (BANDWIDTH_7_MHZ != params->u.ofdm.bandwidth) 224 u32 bw = fe->dtv_property_cache.bandwidth_hz;
225 if (bw == 7000000)
227 buf[3] |= 0x08; 226 buf[3] |= 0x08;
228} 227}
229 228
@@ -244,10 +243,10 @@ static struct dvb_pll_desc dvb_pll_tua6034 = {
244/* ALPS TDED4 243/* ALPS TDED4
245 * used in Nebula-Cards and USB boxes 244 * used in Nebula-Cards and USB boxes
246 */ 245 */
247static void tded4_bw(struct dvb_frontend *fe, u8 *buf, 246static void tded4_bw(struct dvb_frontend *fe, u8 *buf)
248 const struct dvb_frontend_parameters *params)
249{ 247{
250 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) 248 u32 bw = fe->dtv_property_cache.bandwidth_hz;
249 if (bw == 8000000)
251 buf[3] |= 0x04; 250 buf[3] |= 0x04;
252} 251}
253 252
@@ -319,11 +318,11 @@ static struct dvb_pll_desc dvb_pll_philips_sd1878_tda8261 = {
319 }, 318 },
320}; 319};
321 320
322static void opera1_bw(struct dvb_frontend *fe, u8 *buf, 321static void opera1_bw(struct dvb_frontend *fe, u8 *buf)
323 const struct dvb_frontend_parameters *params)
324{ 322{
323 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
325 struct dvb_pll_priv *priv = fe->tuner_priv; 324 struct dvb_pll_priv *priv = fe->tuner_priv;
326 u32 b_w = (params->u.qpsk.symbol_rate * 27) / 32000; 325 u32 b_w = (c->symbol_rate * 27) / 32000;
327 struct i2c_msg msg = { 326 struct i2c_msg msg = {
328 .addr = priv->pll_i2c_address, 327 .addr = priv->pll_i2c_address,
329 .flags = 0, 328 .flags = 0,
@@ -392,8 +391,7 @@ static struct dvb_pll_desc dvb_pll_opera1 = {
392 } 391 }
393}; 392};
394 393
395static void samsung_dtos403ih102a_set(struct dvb_frontend *fe, u8 *buf, 394static void samsung_dtos403ih102a_set(struct dvb_frontend *fe, u8 *buf)
396 const struct dvb_frontend_parameters *params)
397{ 395{
398 struct dvb_pll_priv *priv = fe->tuner_priv; 396 struct dvb_pll_priv *priv = fe->tuner_priv;
399 struct i2c_msg msg = { 397 struct i2c_msg msg = {
@@ -537,30 +535,29 @@ static struct dvb_pll_desc *pll_list[] = {
537/* code */ 535/* code */
538 536
539static int dvb_pll_configure(struct dvb_frontend *fe, u8 *buf, 537static int dvb_pll_configure(struct dvb_frontend *fe, u8 *buf,
540 const struct dvb_frontend_parameters *params) 538 const u32 frequency)
541{ 539{
542 struct dvb_pll_priv *priv = fe->tuner_priv; 540 struct dvb_pll_priv *priv = fe->tuner_priv;
543 struct dvb_pll_desc *desc = priv->pll_desc; 541 struct dvb_pll_desc *desc = priv->pll_desc;
544 u32 div; 542 u32 div;
545 int i; 543 int i;
546 544
547 if (params->frequency != 0 && (params->frequency < desc->min || 545 if (frequency && (frequency < desc->min || frequency > desc->max))
548 params->frequency > desc->max))
549 return -EINVAL; 546 return -EINVAL;
550 547
551 for (i = 0; i < desc->count; i++) { 548 for (i = 0; i < desc->count; i++) {
552 if (params->frequency > desc->entries[i].limit) 549 if (frequency > desc->entries[i].limit)
553 continue; 550 continue;
554 break; 551 break;
555 } 552 }
556 553
557 if (debug) 554 if (debug)
558 printk("pll: %s: freq=%d | i=%d/%d\n", desc->name, 555 printk("pll: %s: freq=%d | i=%d/%d\n", desc->name,
559 params->frequency, i, desc->count); 556 frequency, i, desc->count);
560 if (i == desc->count) 557 if (i == desc->count)
561 return -EINVAL; 558 return -EINVAL;
562 559
563 div = (params->frequency + desc->iffreq + 560 div = (frequency + desc->iffreq +
564 desc->entries[i].stepsize/2) / desc->entries[i].stepsize; 561 desc->entries[i].stepsize/2) / desc->entries[i].stepsize;
565 buf[0] = div >> 8; 562 buf[0] = div >> 8;
566 buf[1] = div & 0xff; 563 buf[1] = div & 0xff;
@@ -568,7 +565,7 @@ static int dvb_pll_configure(struct dvb_frontend *fe, u8 *buf,
568 buf[3] = desc->entries[i].cb; 565 buf[3] = desc->entries[i].cb;
569 566
570 if (desc->set) 567 if (desc->set)
571 desc->set(fe, buf, params); 568 desc->set(fe, buf);
572 569
573 if (debug) 570 if (debug)
574 printk("pll: %s: div=%d | buf=0x%02x,0x%02x,0x%02x,0x%02x\n", 571 printk("pll: %s: div=%d | buf=0x%02x,0x%02x,0x%02x,0x%02x\n",
@@ -611,9 +608,9 @@ static int dvb_pll_sleep(struct dvb_frontend *fe)
611 return -EINVAL; 608 return -EINVAL;
612} 609}
613 610
614static int dvb_pll_set_params(struct dvb_frontend *fe, 611static int dvb_pll_set_params(struct dvb_frontend *fe)
615 struct dvb_frontend_parameters *params)
616{ 612{
613 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
617 struct dvb_pll_priv *priv = fe->tuner_priv; 614 struct dvb_pll_priv *priv = fe->tuner_priv;
618 u8 buf[4]; 615 u8 buf[4];
619 struct i2c_msg msg = 616 struct i2c_msg msg =
@@ -625,7 +622,8 @@ static int dvb_pll_set_params(struct dvb_frontend *fe,
625 if (priv->i2c == NULL) 622 if (priv->i2c == NULL)
626 return -EINVAL; 623 return -EINVAL;
627 624
628 if ((result = dvb_pll_configure(fe, buf, params)) < 0) 625 result = dvb_pll_configure(fe, buf, c->frequency);
626 if (result < 0)
629 return result; 627 return result;
630 else 628 else
631 frequency = result; 629 frequency = result;
@@ -637,15 +635,15 @@ static int dvb_pll_set_params(struct dvb_frontend *fe,
637 } 635 }
638 636
639 priv->frequency = frequency; 637 priv->frequency = frequency;
640 priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0; 638 priv->bandwidth = c->bandwidth_hz;
641 639
642 return 0; 640 return 0;
643} 641}
644 642
645static int dvb_pll_calc_regs(struct dvb_frontend *fe, 643static int dvb_pll_calc_regs(struct dvb_frontend *fe,
646 struct dvb_frontend_parameters *params,
647 u8 *buf, int buf_len) 644 u8 *buf, int buf_len)
648{ 645{
646 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
649 struct dvb_pll_priv *priv = fe->tuner_priv; 647 struct dvb_pll_priv *priv = fe->tuner_priv;
650 int result; 648 int result;
651 u32 frequency = 0; 649 u32 frequency = 0;
@@ -653,7 +651,8 @@ static int dvb_pll_calc_regs(struct dvb_frontend *fe,
653 if (buf_len < 5) 651 if (buf_len < 5)
654 return -EINVAL; 652 return -EINVAL;
655 653
656 if ((result = dvb_pll_configure(fe, buf+1, params)) < 0) 654 result = dvb_pll_configure(fe, buf + 1, c->frequency);
655 if (result < 0)
657 return result; 656 return result;
658 else 657 else
659 frequency = result; 658 frequency = result;
@@ -661,7 +660,7 @@ static int dvb_pll_calc_regs(struct dvb_frontend *fe,
661 buf[0] = priv->pll_i2c_address; 660 buf[0] = priv->pll_i2c_address;
662 661
663 priv->frequency = frequency; 662 priv->frequency = frequency;
664 priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0; 663 priv->bandwidth = c->bandwidth_hz;
665 664
666 return 5; 665 return 5;
667} 666}
diff --git a/drivers/media/dvb/frontends/dvb_dummy_fe.c b/drivers/media/dvb/frontends/dvb_dummy_fe.c
index a7fc7e53a551..dcfc902c8678 100644
--- a/drivers/media/dvb/frontends/dvb_dummy_fe.c
+++ b/drivers/media/dvb/frontends/dvb_dummy_fe.c
@@ -68,15 +68,18 @@ static int dvb_dummy_fe_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
68 return 0; 68 return 0;
69} 69}
70 70
71static int dvb_dummy_fe_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 71/*
72 * Only needed if it actually reads something from the hardware
73 */
74static int dvb_dummy_fe_get_frontend(struct dvb_frontend *fe)
72{ 75{
73 return 0; 76 return 0;
74} 77}
75 78
76static int dvb_dummy_fe_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 79static int dvb_dummy_fe_set_frontend(struct dvb_frontend *fe)
77{ 80{
78 if (fe->ops.tuner_ops.set_params) { 81 if (fe->ops.tuner_ops.set_params) {
79 fe->ops.tuner_ops.set_params(fe, p); 82 fe->ops.tuner_ops.set_params(fe);
80 if (fe->ops.i2c_gate_ctrl) 83 if (fe->ops.i2c_gate_ctrl)
81 fe->ops.i2c_gate_ctrl(fe, 0); 84 fe->ops.i2c_gate_ctrl(fe, 0);
82 } 85 }
@@ -171,10 +174,9 @@ error:
171} 174}
172 175
173static struct dvb_frontend_ops dvb_dummy_fe_ofdm_ops = { 176static struct dvb_frontend_ops dvb_dummy_fe_ofdm_ops = {
174 177 .delsys = { SYS_DVBT },
175 .info = { 178 .info = {
176 .name = "Dummy DVB-T", 179 .name = "Dummy DVB-T",
177 .type = FE_OFDM,
178 .frequency_min = 0, 180 .frequency_min = 0,
179 .frequency_max = 863250000, 181 .frequency_max = 863250000,
180 .frequency_stepsize = 62500, 182 .frequency_stepsize = 62500,
@@ -203,10 +205,9 @@ static struct dvb_frontend_ops dvb_dummy_fe_ofdm_ops = {
203}; 205};
204 206
205static struct dvb_frontend_ops dvb_dummy_fe_qam_ops = { 207static struct dvb_frontend_ops dvb_dummy_fe_qam_ops = {
206 208 .delsys = { SYS_DVBC_ANNEX_A },
207 .info = { 209 .info = {
208 .name = "Dummy DVB-C", 210 .name = "Dummy DVB-C",
209 .type = FE_QAM,
210 .frequency_stepsize = 62500, 211 .frequency_stepsize = 62500,
211 .frequency_min = 51000000, 212 .frequency_min = 51000000,
212 .frequency_max = 858000000, 213 .frequency_max = 858000000,
@@ -233,10 +234,9 @@ static struct dvb_frontend_ops dvb_dummy_fe_qam_ops = {
233}; 234};
234 235
235static struct dvb_frontend_ops dvb_dummy_fe_qpsk_ops = { 236static struct dvb_frontend_ops dvb_dummy_fe_qpsk_ops = {
236 237 .delsys = { SYS_DVBS },
237 .info = { 238 .info = {
238 .name = "Dummy DVB-S", 239 .name = "Dummy DVB-S",
239 .type = FE_QPSK,
240 .frequency_min = 950000, 240 .frequency_min = 950000,
241 .frequency_max = 2150000, 241 .frequency_max = 2150000,
242 .frequency_stepsize = 250, /* kHz for QPSK frontends */ 242 .frequency_stepsize = 250, /* kHz for QPSK frontends */
diff --git a/drivers/media/dvb/frontends/ec100.c b/drivers/media/dvb/frontends/ec100.c
index 2414dc6ee5d9..c56fddbf53b7 100644
--- a/drivers/media/dvb/frontends/ec100.c
+++ b/drivers/media/dvb/frontends/ec100.c
@@ -76,19 +76,19 @@ static int ec100_read_reg(struct ec100_state *state, u8 reg, u8 *val)
76 return 0; 76 return 0;
77} 77}
78 78
79static int ec100_set_frontend(struct dvb_frontend *fe, 79static int ec100_set_frontend(struct dvb_frontend *fe)
80 struct dvb_frontend_parameters *params)
81{ 80{
81 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
82 struct ec100_state *state = fe->demodulator_priv; 82 struct ec100_state *state = fe->demodulator_priv;
83 int ret; 83 int ret;
84 u8 tmp, tmp2; 84 u8 tmp, tmp2;
85 85
86 deb_info("%s: freq:%d bw:%d\n", __func__, params->frequency, 86 deb_info("%s: freq:%d bw:%d\n", __func__, c->frequency,
87 params->u.ofdm.bandwidth); 87 c->bandwidth_hz);
88 88
89 /* program tuner */ 89 /* program tuner */
90 if (fe->ops.tuner_ops.set_params) 90 if (fe->ops.tuner_ops.set_params)
91 fe->ops.tuner_ops.set_params(fe, params); 91 fe->ops.tuner_ops.set_params(fe);
92 92
93 ret = ec100_write_reg(state, 0x04, 0x06); 93 ret = ec100_write_reg(state, 0x04, 0x06);
94 if (ret) 94 if (ret)
@@ -108,16 +108,16 @@ static int ec100_set_frontend(struct dvb_frontend *fe,
108 B 0x1b | 0xb7 | 0x00 | 0x49 108 B 0x1b | 0xb7 | 0x00 | 0x49
109 B 0x1c | 0x55 | 0x64 | 0x72 */ 109 B 0x1c | 0x55 | 0x64 | 0x72 */
110 110
111 switch (params->u.ofdm.bandwidth) { 111 switch (c->bandwidth_hz) {
112 case BANDWIDTH_6_MHZ: 112 case 6000000:
113 tmp = 0xb7; 113 tmp = 0xb7;
114 tmp2 = 0x55; 114 tmp2 = 0x55;
115 break; 115 break;
116 case BANDWIDTH_7_MHZ: 116 case 7000000:
117 tmp = 0x00; 117 tmp = 0x00;
118 tmp2 = 0x64; 118 tmp2 = 0x64;
119 break; 119 break;
120 case BANDWIDTH_8_MHZ: 120 case 8000000:
121 default: 121 default:
122 tmp = 0x49; 122 tmp = 0x49;
123 tmp2 = 0x72; 123 tmp2 = 0x72;
@@ -306,9 +306,9 @@ error:
306EXPORT_SYMBOL(ec100_attach); 306EXPORT_SYMBOL(ec100_attach);
307 307
308static struct dvb_frontend_ops ec100_ops = { 308static struct dvb_frontend_ops ec100_ops = {
309 .delsys = { SYS_DVBT },
309 .info = { 310 .info = {
310 .name = "E3C EC100 DVB-T", 311 .name = "E3C EC100 DVB-T",
311 .type = FE_OFDM,
312 .caps = 312 .caps =
313 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 313 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
314 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 314 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
diff --git a/drivers/media/dvb/frontends/hd29l2.c b/drivers/media/dvb/frontends/hd29l2.c
new file mode 100644
index 000000000000..a00318190837
--- /dev/null
+++ b/drivers/media/dvb/frontends/hd29l2.c
@@ -0,0 +1,861 @@
1/*
2 * HDIC HD29L2 DMB-TH demodulator driver
3 *
4 * Copyright (C) 2011 Metropolia University of Applied Sciences, Electria R&D
5 *
6 * Author: Antti Palosaari <crope@iki.fi>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include "hd29l2_priv.h"
24
25int hd29l2_debug;
26module_param_named(debug, hd29l2_debug, int, 0644);
27MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
28
29/* write multiple registers */
30static int hd29l2_wr_regs(struct hd29l2_priv *priv, u8 reg, u8 *val, int len)
31{
32 int ret;
33 u8 buf[2 + len];
34 struct i2c_msg msg[1] = {
35 {
36 .addr = priv->cfg.i2c_addr,
37 .flags = 0,
38 .len = sizeof(buf),
39 .buf = buf,
40 }
41 };
42
43 buf[0] = 0x00;
44 buf[1] = reg;
45 memcpy(&buf[2], val, len);
46
47 ret = i2c_transfer(priv->i2c, msg, 1);
48 if (ret == 1) {
49 ret = 0;
50 } else {
51 warn("i2c wr failed=%d reg=%02x len=%d", ret, reg, len);
52 ret = -EREMOTEIO;
53 }
54
55 return ret;
56}
57
58/* read multiple registers */
59static int hd29l2_rd_regs(struct hd29l2_priv *priv, u8 reg, u8 *val, int len)
60{
61 int ret;
62 u8 buf[2] = { 0x00, reg };
63 struct i2c_msg msg[2] = {
64 {
65 .addr = priv->cfg.i2c_addr,
66 .flags = 0,
67 .len = 2,
68 .buf = buf,
69 }, {
70 .addr = priv->cfg.i2c_addr,
71 .flags = I2C_M_RD,
72 .len = len,
73 .buf = val,
74 }
75 };
76
77 ret = i2c_transfer(priv->i2c, msg, 2);
78 if (ret == 2) {
79 ret = 0;
80 } else {
81 warn("i2c rd failed=%d reg=%02x len=%d", ret, reg, len);
82 ret = -EREMOTEIO;
83 }
84
85 return ret;
86}
87
88/* write single register */
89static int hd29l2_wr_reg(struct hd29l2_priv *priv, u8 reg, u8 val)
90{
91 return hd29l2_wr_regs(priv, reg, &val, 1);
92}
93
94/* read single register */
95static int hd29l2_rd_reg(struct hd29l2_priv *priv, u8 reg, u8 *val)
96{
97 return hd29l2_rd_regs(priv, reg, val, 1);
98}
99
100/* write single register with mask */
101static int hd29l2_wr_reg_mask(struct hd29l2_priv *priv, u8 reg, u8 val, u8 mask)
102{
103 int ret;
104 u8 tmp;
105
106 /* no need for read if whole reg is written */
107 if (mask != 0xff) {
108 ret = hd29l2_rd_regs(priv, reg, &tmp, 1);
109 if (ret)
110 return ret;
111
112 val &= mask;
113 tmp &= ~mask;
114 val |= tmp;
115 }
116
117 return hd29l2_wr_regs(priv, reg, &val, 1);
118}
119
120/* read single register with mask */
121int hd29l2_rd_reg_mask(struct hd29l2_priv *priv, u8 reg, u8 *val, u8 mask)
122{
123 int ret, i;
124 u8 tmp;
125
126 ret = hd29l2_rd_regs(priv, reg, &tmp, 1);
127 if (ret)
128 return ret;
129
130 tmp &= mask;
131
132 /* find position of the first bit */
133 for (i = 0; i < 8; i++) {
134 if ((mask >> i) & 0x01)
135 break;
136 }
137 *val = tmp >> i;
138
139 return 0;
140}
141
142static int hd29l2_soft_reset(struct hd29l2_priv *priv)
143{
144 int ret;
145 u8 tmp;
146
147 ret = hd29l2_rd_reg(priv, 0x26, &tmp);
148 if (ret)
149 goto err;
150
151 ret = hd29l2_wr_reg(priv, 0x26, 0x0d);
152 if (ret)
153 goto err;
154
155 usleep_range(10000, 20000);
156
157 ret = hd29l2_wr_reg(priv, 0x26, tmp);
158 if (ret)
159 goto err;
160
161 return 0;
162err:
163 dbg("%s: failed=%d", __func__, ret);
164 return ret;
165}
166
167static int hd29l2_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
168{
169 int ret, i;
170 struct hd29l2_priv *priv = fe->demodulator_priv;
171 u8 tmp;
172
173 dbg("%s: enable=%d", __func__, enable);
174
175 /* set tuner address for demod */
176 if (!priv->tuner_i2c_addr_programmed && enable) {
177 /* no need to set tuner address every time, once is enough */
178 ret = hd29l2_wr_reg(priv, 0x9d, priv->cfg.tuner_i2c_addr << 1);
179 if (ret)
180 goto err;
181
182 priv->tuner_i2c_addr_programmed = true;
183 }
184
185 /* open / close gate */
186 ret = hd29l2_wr_reg(priv, 0x9f, enable);
187 if (ret)
188 goto err;
189
190 /* wait demod ready */
191 for (i = 10; i; i--) {
192 ret = hd29l2_rd_reg(priv, 0x9e, &tmp);
193 if (ret)
194 goto err;
195
196 if (tmp == enable)
197 break;
198
199 usleep_range(5000, 10000);
200 }
201
202 dbg("%s: loop=%d", __func__, i);
203
204 return ret;
205err:
206 dbg("%s: failed=%d", __func__, ret);
207 return ret;
208}
209
210static int hd29l2_read_status(struct dvb_frontend *fe, fe_status_t *status)
211{
212 int ret;
213 struct hd29l2_priv *priv = fe->demodulator_priv;
214 u8 buf[2];
215
216 *status = 0;
217
218 ret = hd29l2_rd_reg(priv, 0x05, &buf[0]);
219 if (ret)
220 goto err;
221
222 if (buf[0] & 0x01) {
223 /* full lock */
224 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI |
225 FE_HAS_SYNC | FE_HAS_LOCK;
226 } else {
227 ret = hd29l2_rd_reg(priv, 0x0d, &buf[1]);
228 if (ret)
229 goto err;
230
231 if ((buf[1] & 0xfe) == 0x78)
232 /* partial lock */
233 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
234 FE_HAS_VITERBI | FE_HAS_SYNC;
235 }
236
237 priv->fe_status = *status;
238
239 return 0;
240err:
241 dbg("%s: failed=%d", __func__, ret);
242 return ret;
243}
244
245static int hd29l2_read_snr(struct dvb_frontend *fe, u16 *snr)
246{
247 int ret;
248 struct hd29l2_priv *priv = fe->demodulator_priv;
249 u8 buf[2];
250 u16 tmp;
251
252 if (!(priv->fe_status & FE_HAS_LOCK)) {
253 *snr = 0;
254 ret = 0;
255 goto err;
256 }
257
258 ret = hd29l2_rd_regs(priv, 0x0b, buf, 2);
259 if (ret)
260 goto err;
261
262 tmp = (buf[0] << 8) | buf[1];
263
264 /* report SNR in dB * 10 */
265 #define LOG10_20736_24 72422627 /* log10(20736) << 24 */
266 if (tmp)
267 *snr = (LOG10_20736_24 - intlog10(tmp)) / ((1 << 24) / 100);
268 else
269 *snr = 0;
270
271 return 0;
272err:
273 dbg("%s: failed=%d", __func__, ret);
274 return ret;
275}
276
277static int hd29l2_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
278{
279 int ret;
280 struct hd29l2_priv *priv = fe->demodulator_priv;
281 u8 buf[2];
282 u16 tmp;
283
284 *strength = 0;
285
286 ret = hd29l2_rd_regs(priv, 0xd5, buf, 2);
287 if (ret)
288 goto err;
289
290 tmp = buf[0] << 8 | buf[1];
291 tmp = ~tmp & 0x0fff;
292
293 /* scale value to 0x0000-0xffff from 0x0000-0x0fff */
294 *strength = tmp * 0xffff / 0x0fff;
295
296 return 0;
297err:
298 dbg("%s: failed=%d", __func__, ret);
299 return ret;
300}
301
302static int hd29l2_read_ber(struct dvb_frontend *fe, u32 *ber)
303{
304 int ret;
305 struct hd29l2_priv *priv = fe->demodulator_priv;
306 u8 buf[2];
307
308 if (!(priv->fe_status & FE_HAS_SYNC)) {
309 *ber = 0;
310 ret = 0;
311 goto err;
312 }
313
314 ret = hd29l2_rd_regs(priv, 0xd9, buf, 2);
315 if (ret) {
316 *ber = 0;
317 goto err;
318 }
319
320 /* LDPC BER */
321 *ber = ((buf[0] & 0x0f) << 8) | buf[1];
322
323 return 0;
324err:
325 dbg("%s: failed=%d", __func__, ret);
326 return ret;
327}
328
329static int hd29l2_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
330{
331 /* no way to read? */
332 *ucblocks = 0;
333 return 0;
334}
335
336static enum dvbfe_search hd29l2_search(struct dvb_frontend *fe)
337{
338 int ret, i;
339 struct hd29l2_priv *priv = fe->demodulator_priv;
340 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
341 u8 tmp, buf[3];
342 u8 modulation, carrier, guard_interval, interleave, code_rate;
343 u64 num64;
344 u32 if_freq, if_ctl;
345 bool auto_mode;
346
347 dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d " \
348 "modulation=%d inversion=%d fec_inner=%d guard_interval=%d",
349 __func__,
350 c->delivery_system, c->frequency, c->bandwidth_hz,
351 c->modulation, c->inversion, c->fec_inner, c->guard_interval);
352
353 /* as for now we detect always params automatically */
354 auto_mode = true;
355
356 /* program tuner */
357 if (fe->ops.tuner_ops.set_params)
358 fe->ops.tuner_ops.set_params(fe);
359
360 /* get and program IF */
361 if (fe->ops.tuner_ops.get_if_frequency)
362 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
363 else
364 if_freq = 0;
365
366 if (if_freq) {
367 /* normal IF */
368
369 /* calc IF control value */
370 num64 = if_freq;
371 num64 *= 0x800000;
372 num64 = div_u64(num64, HD29L2_XTAL);
373 num64 -= 0x800000;
374 if_ctl = num64;
375
376 tmp = 0xfc; /* tuner type normal */
377 } else {
378 /* zero IF */
379 if_ctl = 0;
380 tmp = 0xfe; /* tuner type Zero-IF */
381 }
382
383 buf[0] = ((if_ctl >> 0) & 0xff);
384 buf[1] = ((if_ctl >> 8) & 0xff);
385 buf[2] = ((if_ctl >> 16) & 0xff);
386
387 /* program IF control */
388 ret = hd29l2_wr_regs(priv, 0x14, buf, 3);
389 if (ret)
390 goto err;
391
392 /* program tuner type */
393 ret = hd29l2_wr_reg(priv, 0xab, tmp);
394 if (ret)
395 goto err;
396
397 dbg("%s: if_freq=%d if_ctl=%x", __func__, if_freq, if_ctl);
398
399 if (auto_mode) {
400 /*
401 * use auto mode
402 */
403
404 /* disable quick mode */
405 ret = hd29l2_wr_reg_mask(priv, 0xac, 0 << 7, 0x80);
406 if (ret)
407 goto err;
408
409 ret = hd29l2_wr_reg_mask(priv, 0x82, 1 << 1, 0x02);
410 if (ret)
411 goto err;
412
413 /* enable auto mode */
414 ret = hd29l2_wr_reg_mask(priv, 0x7d, 1 << 6, 0x40);
415 if (ret)
416 goto err;
417
418 ret = hd29l2_wr_reg_mask(priv, 0x81, 1 << 3, 0x08);
419 if (ret)
420 goto err;
421
422 /* soft reset */
423 ret = hd29l2_soft_reset(priv);
424 if (ret)
425 goto err;
426
427 /* detect modulation */
428 for (i = 30; i; i--) {
429 msleep(100);
430
431 ret = hd29l2_rd_reg(priv, 0x0d, &tmp);
432 if (ret)
433 goto err;
434
435 if ((((tmp & 0xf0) >= 0x10) &&
436 ((tmp & 0x0f) == 0x08)) || (tmp >= 0x2c))
437 break;
438 }
439
440 dbg("%s: loop=%d", __func__, i);
441
442 if (i == 0)
443 /* detection failed */
444 return DVBFE_ALGO_SEARCH_FAILED;
445
446 /* read modulation */
447 ret = hd29l2_rd_reg_mask(priv, 0x7d, &modulation, 0x07);
448 if (ret)
449 goto err;
450 } else {
451 /*
452 * use manual mode
453 */
454
455 modulation = HD29L2_QAM64;
456 carrier = HD29L2_CARRIER_MULTI;
457 guard_interval = HD29L2_PN945;
458 interleave = HD29L2_INTERLEAVER_420;
459 code_rate = HD29L2_CODE_RATE_08;
460
461 tmp = (code_rate << 3) | modulation;
462 ret = hd29l2_wr_reg_mask(priv, 0x7d, tmp, 0x5f);
463 if (ret)
464 goto err;
465
466 tmp = (carrier << 2) | guard_interval;
467 ret = hd29l2_wr_reg_mask(priv, 0x81, tmp, 0x0f);
468 if (ret)
469 goto err;
470
471 tmp = interleave;
472 ret = hd29l2_wr_reg_mask(priv, 0x82, tmp, 0x03);
473 if (ret)
474 goto err;
475 }
476
477 /* ensure modulation validy */
478 /* 0=QAM4_NR, 1=QAM4, 2=QAM16, 3=QAM32, 4=QAM64 */
479 if (modulation > (ARRAY_SIZE(reg_mod_vals_tab[0].val) - 1)) {
480 dbg("%s: modulation=%d not valid", __func__, modulation);
481 goto err;
482 }
483
484 /* program registers according to modulation */
485 for (i = 0; i < ARRAY_SIZE(reg_mod_vals_tab); i++) {
486 ret = hd29l2_wr_reg(priv, reg_mod_vals_tab[i].reg,
487 reg_mod_vals_tab[i].val[modulation]);
488 if (ret)
489 goto err;
490 }
491
492 /* read guard interval */
493 ret = hd29l2_rd_reg_mask(priv, 0x81, &guard_interval, 0x03);
494 if (ret)
495 goto err;
496
497 /* read carrier mode */
498 ret = hd29l2_rd_reg_mask(priv, 0x81, &carrier, 0x04);
499 if (ret)
500 goto err;
501
502 dbg("%s: modulation=%d guard_interval=%d carrier=%d",
503 __func__, modulation, guard_interval, carrier);
504
505 if ((carrier == HD29L2_CARRIER_MULTI) && (modulation == HD29L2_QAM64) &&
506 (guard_interval == HD29L2_PN945)) {
507 dbg("%s: C=3780 && QAM64 && PN945", __func__);
508
509 ret = hd29l2_wr_reg(priv, 0x42, 0x33);
510 if (ret)
511 goto err;
512
513 ret = hd29l2_wr_reg(priv, 0xdd, 0x01);
514 if (ret)
515 goto err;
516 }
517
518 usleep_range(10000, 20000);
519
520 /* soft reset */
521 ret = hd29l2_soft_reset(priv);
522 if (ret)
523 goto err;
524
525 /* wait demod lock */
526 for (i = 30; i; i--) {
527 msleep(100);
528
529 /* read lock bit */
530 ret = hd29l2_rd_reg_mask(priv, 0x05, &tmp, 0x01);
531 if (ret)
532 goto err;
533
534 if (tmp)
535 break;
536 }
537
538 dbg("%s: loop=%d", __func__, i);
539
540 if (i == 0)
541 return DVBFE_ALGO_SEARCH_AGAIN;
542
543 return DVBFE_ALGO_SEARCH_SUCCESS;
544err:
545 dbg("%s: failed=%d", __func__, ret);
546 return DVBFE_ALGO_SEARCH_ERROR;
547}
548
549static int hd29l2_get_frontend_algo(struct dvb_frontend *fe)
550{
551 return DVBFE_ALGO_CUSTOM;
552}
553
554static int hd29l2_get_frontend(struct dvb_frontend *fe)
555{
556 int ret;
557 struct hd29l2_priv *priv = fe->demodulator_priv;
558 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
559 u8 buf[3];
560 u32 if_ctl;
561 char *str_constellation, *str_code_rate, *str_constellation_code_rate,
562 *str_guard_interval, *str_carrier, *str_guard_interval_carrier,
563 *str_interleave, *str_interleave_;
564
565 ret = hd29l2_rd_reg(priv, 0x7d, &buf[0]);
566 if (ret)
567 goto err;
568
569 ret = hd29l2_rd_regs(priv, 0x81, &buf[1], 2);
570 if (ret)
571 goto err;
572
573 /* constellation, 0x7d[2:0] */
574 switch ((buf[0] >> 0) & 0x07) {
575 case 0: /* QAM4NR */
576 str_constellation = "QAM4NR";
577 c->modulation = QAM_AUTO; /* FIXME */
578 break;
579 case 1: /* QAM4 */
580 str_constellation = "QAM4";
581 c->modulation = QPSK; /* FIXME */
582 break;
583 case 2:
584 str_constellation = "QAM16";
585 c->modulation = QAM_16;
586 break;
587 case 3:
588 str_constellation = "QAM32";
589 c->modulation = QAM_32;
590 break;
591 case 4:
592 str_constellation = "QAM64";
593 c->modulation = QAM_64;
594 break;
595 default:
596 str_constellation = "?";
597 }
598
599 /* LDPC code rate, 0x7d[4:3] */
600 switch ((buf[0] >> 3) & 0x03) {
601 case 0: /* 0.4 */
602 str_code_rate = "0.4";
603 c->fec_inner = FEC_AUTO; /* FIXME */
604 break;
605 case 1: /* 0.6 */
606 str_code_rate = "0.6";
607 c->fec_inner = FEC_3_5;
608 break;
609 case 2: /* 0.8 */
610 str_code_rate = "0.8";
611 c->fec_inner = FEC_4_5;
612 break;
613 default:
614 str_code_rate = "?";
615 }
616
617 /* constellation & code rate set, 0x7d[6] */
618 switch ((buf[0] >> 6) & 0x01) {
619 case 0:
620 str_constellation_code_rate = "manual";
621 break;
622 case 1:
623 str_constellation_code_rate = "auto";
624 break;
625 default:
626 str_constellation_code_rate = "?";
627 }
628
629 /* frame header, 0x81[1:0] */
630 switch ((buf[1] >> 0) & 0x03) {
631 case 0: /* PN945 */
632 str_guard_interval = "PN945";
633 c->guard_interval = GUARD_INTERVAL_AUTO; /* FIXME */
634 break;
635 case 1: /* PN595 */
636 str_guard_interval = "PN595";
637 c->guard_interval = GUARD_INTERVAL_AUTO; /* FIXME */
638 break;
639 case 2: /* PN420 */
640 str_guard_interval = "PN420";
641 c->guard_interval = GUARD_INTERVAL_AUTO; /* FIXME */
642 break;
643 default:
644 str_guard_interval = "?";
645 }
646
647 /* carrier, 0x81[2] */
648 switch ((buf[1] >> 2) & 0x01) {
649 case 0:
650 str_carrier = "C=1";
651 break;
652 case 1:
653 str_carrier = "C=3780";
654 break;
655 default:
656 str_carrier = "?";
657 }
658
659 /* frame header & carrier set, 0x81[3] */
660 switch ((buf[1] >> 3) & 0x01) {
661 case 0:
662 str_guard_interval_carrier = "manual";
663 break;
664 case 1:
665 str_guard_interval_carrier = "auto";
666 break;
667 default:
668 str_guard_interval_carrier = "?";
669 }
670
671 /* interleave, 0x82[0] */
672 switch ((buf[2] >> 0) & 0x01) {
673 case 0:
674 str_interleave = "M=720";
675 break;
676 case 1:
677 str_interleave = "M=240";
678 break;
679 default:
680 str_interleave = "?";
681 }
682
683 /* interleave set, 0x82[1] */
684 switch ((buf[2] >> 1) & 0x01) {
685 case 0:
686 str_interleave_ = "manual";
687 break;
688 case 1:
689 str_interleave_ = "auto";
690 break;
691 default:
692 str_interleave_ = "?";
693 }
694
695 /*
696 * We can read out current detected NCO and use that value next
697 * time instead of calculating new value from targed IF.
698 * I think it will not effect receiver sensitivity but gaining lock
699 * after tune could be easier...
700 */
701 ret = hd29l2_rd_regs(priv, 0xb1, &buf[0], 3);
702 if (ret)
703 goto err;
704
705 if_ctl = (buf[0] << 16) | ((buf[1] - 7) << 8) | buf[2];
706
707 dbg("%s: %s %s %s | %s %s %s | %s %s | NCO=%06x", __func__,
708 str_constellation, str_code_rate, str_constellation_code_rate,
709 str_guard_interval, str_carrier, str_guard_interval_carrier,
710 str_interleave, str_interleave_, if_ctl);
711
712 return 0;
713err:
714 dbg("%s: failed=%d", __func__, ret);
715 return ret;
716}
717
718static int hd29l2_init(struct dvb_frontend *fe)
719{
720 int ret, i;
721 struct hd29l2_priv *priv = fe->demodulator_priv;
722 u8 tmp;
723 static const struct reg_val tab[] = {
724 { 0x3a, 0x06 },
725 { 0x3b, 0x03 },
726 { 0x3c, 0x04 },
727 { 0xaf, 0x06 },
728 { 0xb0, 0x1b },
729 { 0x80, 0x64 },
730 { 0x10, 0x38 },
731 };
732
733 dbg("%s:", __func__);
734
735 /* reset demod */
736 /* it is recommended to HW reset chip using RST_N pin */
737 if (fe->callback) {
738 ret = fe->callback(fe, DVB_FRONTEND_COMPONENT_DEMOD, 0, 0);
739 if (ret)
740 goto err;
741
742 /* reprogramming needed because HW reset clears registers */
743 priv->tuner_i2c_addr_programmed = false;
744 }
745
746 /* init */
747 for (i = 0; i < ARRAY_SIZE(tab); i++) {
748 ret = hd29l2_wr_reg(priv, tab[i].reg, tab[i].val);
749 if (ret)
750 goto err;
751 }
752
753 /* TS params */
754 ret = hd29l2_rd_reg(priv, 0x36, &tmp);
755 if (ret)
756 goto err;
757
758 tmp &= 0x1b;
759 tmp |= priv->cfg.ts_mode;
760 ret = hd29l2_wr_reg(priv, 0x36, tmp);
761 if (ret)
762 goto err;
763
764 ret = hd29l2_rd_reg(priv, 0x31, &tmp);
765 tmp &= 0xef;
766
767 if (!(priv->cfg.ts_mode >> 7))
768 /* set b4 for serial TS */
769 tmp |= 0x10;
770
771 ret = hd29l2_wr_reg(priv, 0x31, tmp);
772 if (ret)
773 goto err;
774
775 return ret;
776err:
777 dbg("%s: failed=%d", __func__, ret);
778 return ret;
779}
780
781static void hd29l2_release(struct dvb_frontend *fe)
782{
783 struct hd29l2_priv *priv = fe->demodulator_priv;
784 kfree(priv);
785}
786
787static struct dvb_frontend_ops hd29l2_ops;
788
789struct dvb_frontend *hd29l2_attach(const struct hd29l2_config *config,
790 struct i2c_adapter *i2c)
791{
792 int ret;
793 struct hd29l2_priv *priv = NULL;
794 u8 tmp;
795
796 /* allocate memory for the internal state */
797 priv = kzalloc(sizeof(struct hd29l2_priv), GFP_KERNEL);
798 if (priv == NULL)
799 goto err;
800
801 /* setup the state */
802 priv->i2c = i2c;
803 memcpy(&priv->cfg, config, sizeof(struct hd29l2_config));
804
805
806 /* check if the demod is there */
807 ret = hd29l2_rd_reg(priv, 0x00, &tmp);
808 if (ret)
809 goto err;
810
811 /* create dvb_frontend */
812 memcpy(&priv->fe.ops, &hd29l2_ops, sizeof(struct dvb_frontend_ops));
813 priv->fe.demodulator_priv = priv;
814
815 return &priv->fe;
816err:
817 kfree(priv);
818 return NULL;
819}
820EXPORT_SYMBOL(hd29l2_attach);
821
822static struct dvb_frontend_ops hd29l2_ops = {
823 .delsys = { SYS_DVBT },
824 .info = {
825 .name = "HDIC HD29L2 DMB-TH",
826 .frequency_min = 474000000,
827 .frequency_max = 858000000,
828 .frequency_stepsize = 10000,
829 .caps = FE_CAN_FEC_AUTO |
830 FE_CAN_QPSK |
831 FE_CAN_QAM_16 |
832 FE_CAN_QAM_32 |
833 FE_CAN_QAM_64 |
834 FE_CAN_QAM_AUTO |
835 FE_CAN_TRANSMISSION_MODE_AUTO |
836 FE_CAN_BANDWIDTH_AUTO |
837 FE_CAN_GUARD_INTERVAL_AUTO |
838 FE_CAN_HIERARCHY_AUTO |
839 FE_CAN_RECOVER
840 },
841
842 .release = hd29l2_release,
843
844 .init = hd29l2_init,
845
846 .get_frontend_algo = hd29l2_get_frontend_algo,
847 .search = hd29l2_search,
848 .get_frontend = hd29l2_get_frontend,
849
850 .read_status = hd29l2_read_status,
851 .read_snr = hd29l2_read_snr,
852 .read_signal_strength = hd29l2_read_signal_strength,
853 .read_ber = hd29l2_read_ber,
854 .read_ucblocks = hd29l2_read_ucblocks,
855
856 .i2c_gate_ctrl = hd29l2_i2c_gate_ctrl,
857};
858
859MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
860MODULE_DESCRIPTION("HDIC HD29L2 DMB-TH demodulator driver");
861MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/hd29l2.h b/drivers/media/dvb/frontends/hd29l2.h
new file mode 100644
index 000000000000..a7a64431364d
--- /dev/null
+++ b/drivers/media/dvb/frontends/hd29l2.h
@@ -0,0 +1,66 @@
1/*
2 * HDIC HD29L2 DMB-TH demodulator driver
3 *
4 * Copyright (C) 2011 Metropolia University of Applied Sciences, Electria R&D
5 *
6 * Author: Antti Palosaari <crope@iki.fi>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef HD29L2_H
24#define HD29L2_H
25
26#include <linux/dvb/frontend.h>
27
28struct hd29l2_config {
29 /*
30 * demodulator I2C address
31 */
32 u8 i2c_addr;
33
34 /*
35 * tuner I2C address
36 * only needed when tuner is behind demod I2C-gate
37 */
38 u8 tuner_i2c_addr;
39
40 /*
41 * TS settings
42 */
43#define HD29L2_TS_SERIAL 0x00
44#define HD29L2_TS_PARALLEL 0x80
45#define HD29L2_TS_CLK_NORMAL 0x40
46#define HD29L2_TS_CLK_INVERTED 0x00
47#define HD29L2_TS_CLK_GATED 0x20
48#define HD29L2_TS_CLK_FREE 0x00
49 u8 ts_mode;
50};
51
52
53#if defined(CONFIG_DVB_HD29L2) || \
54 (defined(CONFIG_DVB_HD29L2_MODULE) && defined(MODULE))
55extern struct dvb_frontend *hd29l2_attach(const struct hd29l2_config *config,
56 struct i2c_adapter *i2c);
57#else
58static inline struct dvb_frontend *hd29l2_attach(
59const struct hd29l2_config *config, struct i2c_adapter *i2c)
60{
61 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
62 return NULL;
63}
64#endif
65
66#endif /* HD29L2_H */
diff --git a/drivers/media/dvb/frontends/hd29l2_priv.h b/drivers/media/dvb/frontends/hd29l2_priv.h
new file mode 100644
index 000000000000..ba16dc3ec2bd
--- /dev/null
+++ b/drivers/media/dvb/frontends/hd29l2_priv.h
@@ -0,0 +1,314 @@
1/*
2 * HDIC HD29L2 DMB-TH demodulator driver
3 *
4 * Copyright (C) 2011 Metropolia University of Applied Sciences, Electria R&D
5 *
6 * Author: Antti Palosaari <crope@iki.fi>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef HD29L2_PRIV
24#define HD29L2_PRIV
25
26#include <linux/dvb/version.h>
27#include "dvb_frontend.h"
28#include "dvb_math.h"
29#include "hd29l2.h"
30
31#define LOG_PREFIX "hd29l2"
32
33#undef dbg
34#define dbg(f, arg...) \
35 if (hd29l2_debug) \
36 printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
37#undef err
38#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg)
39#undef info
40#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
41#undef warn
42#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
43
44#define HD29L2_XTAL 30400000 /* Hz */
45
46
47#define HD29L2_QAM4NR 0x00
48#define HD29L2_QAM4 0x01
49#define HD29L2_QAM16 0x02
50#define HD29L2_QAM32 0x03
51#define HD29L2_QAM64 0x04
52
53#define HD29L2_CODE_RATE_04 0x00
54#define HD29L2_CODE_RATE_06 0x08
55#define HD29L2_CODE_RATE_08 0x10
56
57#define HD29L2_PN945 0x00
58#define HD29L2_PN595 0x01
59#define HD29L2_PN420 0x02
60
61#define HD29L2_CARRIER_SINGLE 0x00
62#define HD29L2_CARRIER_MULTI 0x01
63
64#define HD29L2_INTERLEAVER_720 0x00
65#define HD29L2_INTERLEAVER_420 0x01
66
67struct reg_val {
68 u8 reg;
69 u8 val;
70};
71
72struct reg_mod_vals {
73 u8 reg;
74 u8 val[5];
75};
76
77struct hd29l2_priv {
78 struct i2c_adapter *i2c;
79 struct dvb_frontend fe;
80 struct hd29l2_config cfg;
81 u8 tuner_i2c_addr_programmed:1;
82
83 fe_status_t fe_status;
84};
85
86static const struct reg_mod_vals reg_mod_vals_tab[] = {
87 /* REG, QAM4NR, QAM4,QAM16,QAM32,QAM64 */
88 { 0x01, { 0x10, 0x10, 0x10, 0x10, 0x10 } },
89 { 0x02, { 0x07, 0x07, 0x07, 0x07, 0x07 } },
90 { 0x03, { 0x10, 0x10, 0x10, 0x10, 0x10 } },
91 { 0x04, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
92 { 0x05, { 0x61, 0x60, 0x60, 0x61, 0x60 } },
93 { 0x06, { 0xff, 0xff, 0xff, 0xff, 0xff } },
94 { 0x07, { 0xff, 0xff, 0xff, 0xff, 0xff } },
95 { 0x08, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
96 { 0x09, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
97 { 0x0a, { 0x15, 0x15, 0x03, 0x03, 0x03 } },
98 { 0x0d, { 0x78, 0x78, 0x88, 0x78, 0x78 } },
99 { 0x0e, { 0xa0, 0x90, 0xa0, 0xa0, 0xa0 } },
100 { 0x0f, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
101 { 0x10, { 0xa0, 0xa0, 0x58, 0x38, 0x38 } },
102 { 0x11, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
103 { 0x12, { 0x5a, 0x5a, 0x5a, 0x5a, 0x5a } },
104 { 0x13, { 0xa2, 0xa2, 0xa2, 0xa2, 0xa2 } },
105 { 0x17, { 0x40, 0x40, 0x40, 0x40, 0x40 } },
106 { 0x18, { 0x21, 0x21, 0x42, 0x52, 0x42 } },
107 { 0x19, { 0x21, 0x21, 0x62, 0x72, 0x62 } },
108 { 0x1a, { 0x32, 0x43, 0xa9, 0xb9, 0xa9 } },
109 { 0x1b, { 0x32, 0x43, 0xb9, 0xd8, 0xb9 } },
110 { 0x1c, { 0x02, 0x02, 0x03, 0x02, 0x03 } },
111 { 0x1d, { 0x0c, 0x0c, 0x01, 0x02, 0x02 } },
112 { 0x1e, { 0x02, 0x02, 0x02, 0x01, 0x02 } },
113 { 0x1f, { 0x02, 0x02, 0x01, 0x02, 0x04 } },
114 { 0x20, { 0x01, 0x02, 0x01, 0x01, 0x01 } },
115 { 0x21, { 0x08, 0x08, 0x0a, 0x0a, 0x0a } },
116 { 0x22, { 0x06, 0x06, 0x04, 0x05, 0x05 } },
117 { 0x23, { 0x06, 0x06, 0x05, 0x03, 0x05 } },
118 { 0x24, { 0x08, 0x08, 0x05, 0x07, 0x07 } },
119 { 0x25, { 0x16, 0x10, 0x10, 0x0a, 0x10 } },
120 { 0x26, { 0x14, 0x14, 0x04, 0x04, 0x04 } },
121 { 0x27, { 0x58, 0x58, 0x58, 0x5c, 0x58 } },
122 { 0x28, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
123 { 0x29, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
124 { 0x2a, { 0x08, 0x0a, 0x08, 0x08, 0x08 } },
125 { 0x2b, { 0x08, 0x08, 0x08, 0x08, 0x08 } },
126 { 0x2c, { 0x06, 0x06, 0x06, 0x06, 0x06 } },
127 { 0x2d, { 0x05, 0x06, 0x06, 0x06, 0x06 } },
128 { 0x2e, { 0x21, 0x21, 0x21, 0x21, 0x21 } },
129 { 0x2f, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
130 { 0x30, { 0x14, 0x14, 0x14, 0x14, 0x14 } },
131 { 0x33, { 0xb7, 0xb7, 0xb7, 0xb7, 0xb7 } },
132 { 0x34, { 0x81, 0x81, 0x81, 0x81, 0x81 } },
133 { 0x35, { 0x80, 0x80, 0x80, 0x80, 0x80 } },
134 { 0x37, { 0x70, 0x70, 0x70, 0x70, 0x70 } },
135 { 0x38, { 0x04, 0x04, 0x02, 0x02, 0x02 } },
136 { 0x39, { 0x07, 0x07, 0x05, 0x05, 0x05 } },
137 { 0x3a, { 0x06, 0x06, 0x06, 0x06, 0x06 } },
138 { 0x3b, { 0x03, 0x03, 0x03, 0x03, 0x03 } },
139 { 0x3c, { 0x07, 0x06, 0x04, 0x04, 0x04 } },
140 { 0x3d, { 0xf0, 0xf0, 0xf0, 0xf0, 0x80 } },
141 { 0x3e, { 0x60, 0x60, 0x60, 0x60, 0xff } },
142 { 0x3f, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
143 { 0x40, { 0x5b, 0x5b, 0x5b, 0x57, 0x50 } },
144 { 0x41, { 0x30, 0x30, 0x30, 0x30, 0x18 } },
145 { 0x42, { 0x20, 0x20, 0x20, 0x00, 0x30 } },
146 { 0x43, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
147 { 0x44, { 0x3f, 0x3f, 0x3f, 0x3f, 0x3f } },
148 { 0x45, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
149 { 0x46, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
150 { 0x47, { 0x00, 0x00, 0x95, 0x00, 0x95 } },
151 { 0x48, { 0xc0, 0xc0, 0xc0, 0xc0, 0xc0 } },
152 { 0x49, { 0xc0, 0xc0, 0xc0, 0xc0, 0xc0 } },
153 { 0x4a, { 0x40, 0x40, 0x33, 0x11, 0x11 } },
154 { 0x4b, { 0x40, 0x40, 0x00, 0x00, 0x00 } },
155 { 0x4c, { 0x40, 0x40, 0x99, 0x11, 0x11 } },
156 { 0x4d, { 0x40, 0x40, 0x00, 0x00, 0x00 } },
157 { 0x4e, { 0x40, 0x40, 0x66, 0x77, 0x77 } },
158 { 0x4f, { 0x40, 0x40, 0x00, 0x00, 0x00 } },
159 { 0x50, { 0x40, 0x40, 0x88, 0x33, 0x11 } },
160 { 0x51, { 0x40, 0x40, 0x00, 0x00, 0x00 } },
161 { 0x52, { 0x40, 0x40, 0x88, 0x02, 0x02 } },
162 { 0x53, { 0x40, 0x40, 0x00, 0x02, 0x02 } },
163 { 0x54, { 0x00, 0x00, 0x88, 0x33, 0x33 } },
164 { 0x55, { 0x40, 0x40, 0x00, 0x00, 0x00 } },
165 { 0x56, { 0x00, 0x00, 0x00, 0x0b, 0x00 } },
166 { 0x57, { 0x40, 0x40, 0x0a, 0x0b, 0x0a } },
167 { 0x58, { 0xaa, 0x00, 0x00, 0x00, 0x00 } },
168 { 0x59, { 0x7a, 0x40, 0x02, 0x02, 0x02 } },
169 { 0x5a, { 0x18, 0x18, 0x01, 0x01, 0x01 } },
170 { 0x5b, { 0x18, 0x18, 0x01, 0x01, 0x01 } },
171 { 0x5c, { 0x18, 0x18, 0x01, 0x01, 0x01 } },
172 { 0x5d, { 0x18, 0x18, 0x01, 0x01, 0x01 } },
173 { 0x5e, { 0xc0, 0xc0, 0xc0, 0xff, 0xc0 } },
174 { 0x5f, { 0xc0, 0xc0, 0xc0, 0xff, 0xc0 } },
175 { 0x60, { 0x40, 0x40, 0x00, 0x30, 0x30 } },
176 { 0x61, { 0x40, 0x40, 0x10, 0x30, 0x30 } },
177 { 0x62, { 0x40, 0x40, 0x00, 0x30, 0x30 } },
178 { 0x63, { 0x40, 0x40, 0x05, 0x30, 0x30 } },
179 { 0x64, { 0x40, 0x40, 0x06, 0x00, 0x30 } },
180 { 0x65, { 0x40, 0x40, 0x06, 0x08, 0x30 } },
181 { 0x66, { 0x40, 0x40, 0x00, 0x00, 0x20 } },
182 { 0x67, { 0x40, 0x40, 0x01, 0x04, 0x20 } },
183 { 0x68, { 0x00, 0x00, 0x30, 0x00, 0x20 } },
184 { 0x69, { 0xa0, 0xa0, 0x00, 0x08, 0x20 } },
185 { 0x6a, { 0x00, 0x00, 0x30, 0x00, 0x25 } },
186 { 0x6b, { 0xa0, 0xa0, 0x00, 0x06, 0x25 } },
187 { 0x6c, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
188 { 0x6d, { 0xa0, 0x60, 0x0c, 0x03, 0x0c } },
189 { 0x6e, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
190 { 0x6f, { 0xa0, 0x60, 0x04, 0x01, 0x04 } },
191 { 0x70, { 0x58, 0x58, 0xaa, 0xaa, 0xaa } },
192 { 0x71, { 0x58, 0x58, 0xaa, 0xaa, 0xaa } },
193 { 0x72, { 0x58, 0x58, 0xff, 0xff, 0xff } },
194 { 0x73, { 0x58, 0x58, 0xff, 0xff, 0xff } },
195 { 0x74, { 0x06, 0x06, 0x09, 0x05, 0x05 } },
196 { 0x75, { 0x06, 0x06, 0x0a, 0x10, 0x10 } },
197 { 0x76, { 0x10, 0x10, 0x06, 0x0a, 0x0a } },
198 { 0x77, { 0x12, 0x18, 0x28, 0x10, 0x28 } },
199 { 0x78, { 0xf8, 0xf8, 0xf8, 0xf8, 0xf8 } },
200 { 0x79, { 0x15, 0x15, 0x03, 0x03, 0x03 } },
201 { 0x7a, { 0x02, 0x02, 0x01, 0x04, 0x03 } },
202 { 0x7b, { 0x01, 0x02, 0x03, 0x03, 0x03 } },
203 { 0x7c, { 0x28, 0x28, 0x28, 0x28, 0x28 } },
204 { 0x7f, { 0x25, 0x92, 0x5f, 0x17, 0x2d } },
205 { 0x80, { 0x64, 0x64, 0x64, 0x74, 0x64 } },
206 { 0x83, { 0x06, 0x03, 0x04, 0x04, 0x04 } },
207 { 0x84, { 0xff, 0xff, 0xff, 0xff, 0xff } },
208 { 0x85, { 0x05, 0x05, 0x05, 0x05, 0x05 } },
209 { 0x86, { 0x00, 0x00, 0x11, 0x11, 0x11 } },
210 { 0x87, { 0x03, 0x03, 0x03, 0x03, 0x03 } },
211 { 0x88, { 0x09, 0x09, 0x09, 0x09, 0x09 } },
212 { 0x89, { 0x20, 0x20, 0x30, 0x20, 0x20 } },
213 { 0x8a, { 0x03, 0x03, 0x02, 0x03, 0x02 } },
214 { 0x8b, { 0x00, 0x07, 0x09, 0x00, 0x09 } },
215 { 0x8c, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
216 { 0x8d, { 0x4f, 0x4f, 0x4f, 0x3f, 0x4f } },
217 { 0x8e, { 0xf0, 0xf0, 0x60, 0xf0, 0xa0 } },
218 { 0x8f, { 0xe8, 0xe8, 0xe8, 0xe8, 0xe8 } },
219 { 0x90, { 0x10, 0x10, 0x10, 0x10, 0x10 } },
220 { 0x91, { 0x40, 0x40, 0x70, 0x70, 0x10 } },
221 { 0x92, { 0x00, 0x00, 0x00, 0x00, 0x04 } },
222 { 0x93, { 0x60, 0x60, 0x60, 0x60, 0x60 } },
223 { 0x94, { 0x00, 0x00, 0x00, 0x00, 0x03 } },
224 { 0x95, { 0x09, 0x09, 0x47, 0x47, 0x47 } },
225 { 0x96, { 0x80, 0xa0, 0xa0, 0x40, 0xa0 } },
226 { 0x97, { 0x60, 0x60, 0x60, 0x60, 0x60 } },
227 { 0x98, { 0x50, 0x50, 0x50, 0x30, 0x50 } },
228 { 0x99, { 0x10, 0x10, 0x10, 0x10, 0x10 } },
229 { 0x9a, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
230 { 0x9b, { 0x40, 0x40, 0x40, 0x30, 0x40 } },
231 { 0x9c, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
232 { 0xa0, { 0xf0, 0xf0, 0xf0, 0xf0, 0xf0 } },
233 { 0xa1, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
234 { 0xa2, { 0x30, 0x30, 0x00, 0x30, 0x00 } },
235 { 0xa3, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
236 { 0xa4, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
237 { 0xa5, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
238 { 0xa6, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
239 { 0xa7, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
240 { 0xa8, { 0x77, 0x77, 0x77, 0x77, 0x77 } },
241 { 0xa9, { 0x02, 0x02, 0x02, 0x02, 0x02 } },
242 { 0xaa, { 0x40, 0x40, 0x40, 0x40, 0x40 } },
243 { 0xac, { 0x1f, 0x1f, 0x1f, 0x1f, 0x1f } },
244 { 0xad, { 0x14, 0x14, 0x14, 0x14, 0x14 } },
245 { 0xae, { 0x78, 0x78, 0x78, 0x78, 0x78 } },
246 { 0xaf, { 0x06, 0x06, 0x06, 0x06, 0x07 } },
247 { 0xb0, { 0x1b, 0x1b, 0x1b, 0x19, 0x1b } },
248 { 0xb1, { 0x18, 0x17, 0x17, 0x18, 0x17 } },
249 { 0xb2, { 0x35, 0x82, 0x82, 0x38, 0x82 } },
250 { 0xb3, { 0xb6, 0xce, 0xc7, 0x5c, 0xb0 } },
251 { 0xb4, { 0x3f, 0x3e, 0x3e, 0x3f, 0x3e } },
252 { 0xb5, { 0x70, 0x58, 0x50, 0x68, 0x50 } },
253 { 0xb6, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
254 { 0xb7, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
255 { 0xb8, { 0x03, 0x03, 0x01, 0x01, 0x01 } },
256 { 0xb9, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
257 { 0xba, { 0x06, 0x06, 0x0a, 0x05, 0x0a } },
258 { 0xbb, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
259 { 0xbc, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
260 { 0xbd, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
261 { 0xbe, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
262 { 0xbf, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
263 { 0xc0, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
264 { 0xc1, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
265 { 0xc2, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
266 { 0xc3, { 0x00, 0x00, 0x88, 0x66, 0x88 } },
267 { 0xc4, { 0x10, 0x10, 0x00, 0x00, 0x00 } },
268 { 0xc5, { 0x00, 0x00, 0x44, 0x60, 0x44 } },
269 { 0xc6, { 0x10, 0x0a, 0x00, 0x00, 0x00 } },
270 { 0xc7, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
271 { 0xc8, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
272 { 0xc9, { 0x90, 0x04, 0x00, 0x00, 0x00 } },
273 { 0xca, { 0x90, 0x08, 0x01, 0x01, 0x01 } },
274 { 0xcb, { 0xa0, 0x04, 0x00, 0x44, 0x00 } },
275 { 0xcc, { 0xa0, 0x10, 0x03, 0x00, 0x03 } },
276 { 0xcd, { 0x06, 0x06, 0x06, 0x05, 0x06 } },
277 { 0xce, { 0x05, 0x05, 0x01, 0x01, 0x01 } },
278 { 0xcf, { 0x40, 0x20, 0x18, 0x18, 0x18 } },
279 { 0xd0, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
280 { 0xd1, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
281 { 0xd2, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
282 { 0xd3, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
283 { 0xd4, { 0x05, 0x05, 0x05, 0x05, 0x05 } },
284 { 0xd5, { 0x05, 0x05, 0x05, 0x03, 0x05 } },
285 { 0xd6, { 0xac, 0x22, 0xca, 0x8f, 0xca } },
286 { 0xd7, { 0x20, 0x20, 0x20, 0x20, 0x20 } },
287 { 0xd8, { 0x01, 0x01, 0x01, 0x01, 0x01 } },
288 { 0xd9, { 0x00, 0x00, 0x0f, 0x00, 0x0f } },
289 { 0xda, { 0x00, 0xff, 0xff, 0x0e, 0xff } },
290 { 0xdb, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
291 { 0xdc, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
292 { 0xdd, { 0x05, 0x05, 0x05, 0x05, 0x05 } },
293 { 0xde, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
294 { 0xdf, { 0x42, 0x42, 0x44, 0x44, 0x04 } },
295 { 0xe0, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
296 { 0xe1, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
297 { 0xe2, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
298 { 0xe3, { 0x00, 0x00, 0x26, 0x06, 0x26 } },
299 { 0xe4, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
300 { 0xe5, { 0x01, 0x0a, 0x01, 0x01, 0x01 } },
301 { 0xe6, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
302 { 0xe7, { 0x08, 0x08, 0x08, 0x08, 0x08 } },
303 { 0xe8, { 0x63, 0x63, 0x63, 0x63, 0x63 } },
304 { 0xe9, { 0x59, 0x59, 0x59, 0x59, 0x59 } },
305 { 0xea, { 0x80, 0x80, 0x20, 0x80, 0x80 } },
306 { 0xeb, { 0x37, 0x37, 0x78, 0x37, 0x77 } },
307 { 0xec, { 0x1f, 0x1f, 0x25, 0x25, 0x25 } },
308 { 0xed, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
309 { 0xee, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
310 { 0xef, { 0x70, 0x70, 0x58, 0x38, 0x58 } },
311 { 0xf0, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
312};
313
314#endif /* HD29L2_PRIV */
diff --git a/drivers/media/dvb/frontends/it913x-fe-priv.h b/drivers/media/dvb/frontends/it913x-fe-priv.h
index 1c6fb4b66255..93b086ea7e1c 100644
--- a/drivers/media/dvb/frontends/it913x-fe-priv.h
+++ b/drivers/media/dvb/frontends/it913x-fe-priv.h
@@ -22,126 +22,126 @@ struct adctable { u32 adcFrequency;
22/* clock and coeff tables only table 3 is used with IT9137*/ 22/* clock and coeff tables only table 3 is used with IT9137*/
23/* TODO other tables relate AF9035 may be removed */ 23/* TODO other tables relate AF9035 may be removed */
24static struct adctable tab1[] = { 24static struct adctable tab1[] = {
25 { 20156250, BANDWIDTH_6_MHZ, 25 { 20156250, 6000000,
26 0x02b8ba6e, 0x015c5d37, 0x00ae340d, 0x00ae2e9b, 0x00ae292a, 26 0x02b8ba6e, 0x015c5d37, 0x00ae340d, 0x00ae2e9b, 0x00ae292a,
27 0x015c5d37, 0x00ae2e9b, 0x0057174e, 0x02f1, 0x015c }, 27 0x015c5d37, 0x00ae2e9b, 0x0057174e, 0x02f1, 0x015c },
28 { 20156250, BANDWIDTH_7_MHZ, 28 { 20156250, 7000000,
29 0x032cd980, 0x01966cc0, 0x00cb3cba, 0x00cb3660, 0x00cb3007, 29 0x032cd980, 0x01966cc0, 0x00cb3cba, 0x00cb3660, 0x00cb3007,
30 0x01966cc0, 0x00cb3660, 0x00659b30, 0x0285, 0x0196 }, 30 0x01966cc0, 0x00cb3660, 0x00659b30, 0x0285, 0x0196 },
31 { 20156250, BANDWIDTH_8_MHZ, 31 { 20156250, 8000000,
32 0x03a0f893, 0x01d07c49, 0x00e84567, 0x00e83e25, 0x00e836e3, 32 0x03a0f893, 0x01d07c49, 0x00e84567, 0x00e83e25, 0x00e836e3,
33 0x01d07c49, 0x00e83e25, 0x00741f12, 0x0234, 0x01d0 }, 33 0x01d07c49, 0x00e83e25, 0x00741f12, 0x0234, 0x01d0 },
34 { 20156250, BANDWIDTH_5_MHZ, 34 { 20156250, 5000000,
35 0x02449b5c, 0x01224dae, 0x00912b60, 0x009126d7, 0x0091224e, 35 0x02449b5c, 0x01224dae, 0x00912b60, 0x009126d7, 0x0091224e,
36 0x01224dae, 0x009126d7, 0x0048936b, 0x0387, 0x0122 } 36 0x01224dae, 0x009126d7, 0x0048936b, 0x0387, 0x0122 }
37}; 37};
38 38
39static struct adctable tab2[] = { 39static struct adctable tab2[] = {
40 { 20187500, BANDWIDTH_6_MHZ, 40 { 20187500, 6000000,
41 0x02b7a654, 0x015bd32a, 0x00adef04, 0x00ade995, 0x00ade426, 41 0x02b7a654, 0x015bd32a, 0x00adef04, 0x00ade995, 0x00ade426,
42 0x015bd32a, 0x00ade995, 0x0056f4ca, 0x02f2, 0x015c }, 42 0x015bd32a, 0x00ade995, 0x0056f4ca, 0x02f2, 0x015c },
43 { 20187500, BANDWIDTH_7_MHZ, 43 { 20187500, 7000000,
44 0x032b9761, 0x0195cbb1, 0x00caec30, 0x00cae5d8, 0x00cadf81, 44 0x032b9761, 0x0195cbb1, 0x00caec30, 0x00cae5d8, 0x00cadf81,
45 0x0195cbb1, 0x00cae5d8, 0x006572ec, 0x0286, 0x0196 }, 45 0x0195cbb1, 0x00cae5d8, 0x006572ec, 0x0286, 0x0196 },
46 { 20187500, BANDWIDTH_8_MHZ, 46 { 20187500, 8000000,
47 0x039f886f, 0x01cfc438, 0x00e7e95b, 0x00e7e21c, 0x00e7dadd, 47 0x039f886f, 0x01cfc438, 0x00e7e95b, 0x00e7e21c, 0x00e7dadd,
48 0x01cfc438, 0x00e7e21c, 0x0073f10e, 0x0235, 0x01d0 }, 48 0x01cfc438, 0x00e7e21c, 0x0073f10e, 0x0235, 0x01d0 },
49 { 20187500, BANDWIDTH_5_MHZ, 49 { 20187500, 5000000,
50 0x0243b546, 0x0121daa3, 0x0090f1d9, 0x0090ed51, 0x0090e8ca, 50 0x0243b546, 0x0121daa3, 0x0090f1d9, 0x0090ed51, 0x0090e8ca,
51 0x0121daa3, 0x0090ed51, 0x004876a9, 0x0388, 0x0122 } 51 0x0121daa3, 0x0090ed51, 0x004876a9, 0x0388, 0x0122 }
52 52
53}; 53};
54 54
55static struct adctable tab3[] = { 55static struct adctable tab3[] = {
56 { 20250000, BANDWIDTH_6_MHZ, 56 { 20250000, 6000000,
57 0x02b580ad, 0x015ac057, 0x00ad6597, 0x00ad602b, 0x00ad5ac1, 57 0x02b580ad, 0x015ac057, 0x00ad6597, 0x00ad602b, 0x00ad5ac1,
58 0x015ac057, 0x00ad602b, 0x0056b016, 0x02f4, 0x015b }, 58 0x015ac057, 0x00ad602b, 0x0056b016, 0x02f4, 0x015b },
59 { 20250000, BANDWIDTH_7_MHZ, 59 { 20250000, 7000000,
60 0x03291620, 0x01948b10, 0x00ca4bda, 0x00ca4588, 0x00ca3f36, 60 0x03291620, 0x01948b10, 0x00ca4bda, 0x00ca4588, 0x00ca3f36,
61 0x01948b10, 0x00ca4588, 0x006522c4, 0x0288, 0x0195 }, 61 0x01948b10, 0x00ca4588, 0x006522c4, 0x0288, 0x0195 },
62 { 20250000, BANDWIDTH_8_MHZ, 62 { 20250000, 8000000,
63 0x039cab92, 0x01ce55c9, 0x00e7321e, 0x00e72ae4, 0x00e723ab, 63 0x039cab92, 0x01ce55c9, 0x00e7321e, 0x00e72ae4, 0x00e723ab,
64 0x01ce55c9, 0x00e72ae4, 0x00739572, 0x0237, 0x01ce }, 64 0x01ce55c9, 0x00e72ae4, 0x00739572, 0x0237, 0x01ce },
65 { 20250000, BANDWIDTH_5_MHZ, 65 { 20250000, 5000000,
66 0x0241eb3b, 0x0120f59e, 0x00907f53, 0x00907acf, 0x0090764b, 66 0x0241eb3b, 0x0120f59e, 0x00907f53, 0x00907acf, 0x0090764b,
67 0x0120f59e, 0x00907acf, 0x00483d67, 0x038b, 0x0121 } 67 0x0120f59e, 0x00907acf, 0x00483d67, 0x038b, 0x0121 }
68 68
69}; 69};
70 70
71static struct adctable tab4[] = { 71static struct adctable tab4[] = {
72 { 20583333, BANDWIDTH_6_MHZ, 72 { 20583333, 6000000,
73 0x02aa4598, 0x015522cc, 0x00aa96bb, 0x00aa9166, 0x00aa8c12, 73 0x02aa4598, 0x015522cc, 0x00aa96bb, 0x00aa9166, 0x00aa8c12,
74 0x015522cc, 0x00aa9166, 0x005548b3, 0x0300, 0x0155 }, 74 0x015522cc, 0x00aa9166, 0x005548b3, 0x0300, 0x0155 },
75 { 20583333, BANDWIDTH_7_MHZ, 75 { 20583333, 7000000,
76 0x031bfbdc, 0x018dfdee, 0x00c7052f, 0x00c6fef7, 0x00c6f8bf, 76 0x031bfbdc, 0x018dfdee, 0x00c7052f, 0x00c6fef7, 0x00c6f8bf,
77 0x018dfdee, 0x00c6fef7, 0x00637f7b, 0x0293, 0x018e }, 77 0x018dfdee, 0x00c6fef7, 0x00637f7b, 0x0293, 0x018e },
78 { 20583333, BANDWIDTH_8_MHZ, 78 { 20583333, 8000000,
79 0x038db21f, 0x01c6d910, 0x00e373a3, 0x00e36c88, 0x00e3656d, 79 0x038db21f, 0x01c6d910, 0x00e373a3, 0x00e36c88, 0x00e3656d,
80 0x01c6d910, 0x00e36c88, 0x0071b644, 0x0240, 0x01c7 }, 80 0x01c6d910, 0x00e36c88, 0x0071b644, 0x0240, 0x01c7 },
81 { 20583333, BANDWIDTH_5_MHZ, 81 { 20583333, 5000000,
82 0x02388f54, 0x011c47aa, 0x008e2846, 0x008e23d5, 0x008e1f64, 82 0x02388f54, 0x011c47aa, 0x008e2846, 0x008e23d5, 0x008e1f64,
83 0x011c47aa, 0x008e23d5, 0x004711ea, 0x039a, 0x011c } 83 0x011c47aa, 0x008e23d5, 0x004711ea, 0x039a, 0x011c }
84 84
85}; 85};
86 86
87static struct adctable tab5[] = { 87static struct adctable tab5[] = {
88 { 20416667, BANDWIDTH_6_MHZ, 88 { 20416667, 6000000,
89 0x02afd765, 0x0157ebb3, 0x00abfb39, 0x00abf5d9, 0x00abf07a, 89 0x02afd765, 0x0157ebb3, 0x00abfb39, 0x00abf5d9, 0x00abf07a,
90 0x0157ebb3, 0x00abf5d9, 0x0055faed, 0x02fa, 0x0158 }, 90 0x0157ebb3, 0x00abf5d9, 0x0055faed, 0x02fa, 0x0158 },
91 { 20416667, BANDWIDTH_7_MHZ, 91 { 20416667, 7000000,
92 0x03227b4b, 0x01913da6, 0x00c8a518, 0x00c89ed3, 0x00c8988e, 92 0x03227b4b, 0x01913da6, 0x00c8a518, 0x00c89ed3, 0x00c8988e,
93 0x01913da6, 0x00c89ed3, 0x00644f69, 0x028d, 0x0191 }, 93 0x01913da6, 0x00c89ed3, 0x00644f69, 0x028d, 0x0191 },
94 { 20416667, BANDWIDTH_8_MHZ, 94 { 20416667, 8000000,
95 0x03951f32, 0x01ca8f99, 0x00e54ef7, 0x00e547cc, 0x00e540a2, 95 0x03951f32, 0x01ca8f99, 0x00e54ef7, 0x00e547cc, 0x00e540a2,
96 0x01ca8f99, 0x00e547cc, 0x0072a3e6, 0x023c, 0x01cb }, 96 0x01ca8f99, 0x00e547cc, 0x0072a3e6, 0x023c, 0x01cb },
97 { 20416667, BANDWIDTH_5_MHZ, 97 { 20416667, 5000000,
98 0x023d337f, 0x011e99c0, 0x008f515a, 0x008f4ce0, 0x008f4865, 98 0x023d337f, 0x011e99c0, 0x008f515a, 0x008f4ce0, 0x008f4865,
99 0x011e99c0, 0x008f4ce0, 0x0047a670, 0x0393, 0x011f } 99 0x011e99c0, 0x008f4ce0, 0x0047a670, 0x0393, 0x011f }
100 100
101}; 101};
102 102
103static struct adctable tab6[] = { 103static struct adctable tab6[] = {
104 { 20480000, BANDWIDTH_6_MHZ, 104 { 20480000, 6000000,
105 0x02adb6db, 0x0156db6e, 0x00ab7312, 0x00ab6db7, 0x00ab685c, 105 0x02adb6db, 0x0156db6e, 0x00ab7312, 0x00ab6db7, 0x00ab685c,
106 0x0156db6e, 0x00ab6db7, 0x0055b6db, 0x02fd, 0x0157 }, 106 0x0156db6e, 0x00ab6db7, 0x0055b6db, 0x02fd, 0x0157 },
107 { 20480000, BANDWIDTH_7_MHZ, 107 { 20480000, 7000000,
108 0x03200000, 0x01900000, 0x00c80640, 0x00c80000, 0x00c7f9c0, 108 0x03200000, 0x01900000, 0x00c80640, 0x00c80000, 0x00c7f9c0,
109 0x01900000, 0x00c80000, 0x00640000, 0x028f, 0x0190 }, 109 0x01900000, 0x00c80000, 0x00640000, 0x028f, 0x0190 },
110 { 20480000, BANDWIDTH_8_MHZ, 110 { 20480000, 8000000,
111 0x03924925, 0x01c92492, 0x00e4996e, 0x00e49249, 0x00e48b25, 111 0x03924925, 0x01c92492, 0x00e4996e, 0x00e49249, 0x00e48b25,
112 0x01c92492, 0x00e49249, 0x00724925, 0x023d, 0x01c9 }, 112 0x01c92492, 0x00e49249, 0x00724925, 0x023d, 0x01c9 },
113 { 20480000, BANDWIDTH_5_MHZ, 113 { 20480000, 5000000,
114 0x023b6db7, 0x011db6db, 0x008edfe5, 0x008edb6e, 0x008ed6f7, 114 0x023b6db7, 0x011db6db, 0x008edfe5, 0x008edb6e, 0x008ed6f7,
115 0x011db6db, 0x008edb6e, 0x00476db7, 0x0396, 0x011e } 115 0x011db6db, 0x008edb6e, 0x00476db7, 0x0396, 0x011e }
116}; 116};
117 117
118static struct adctable tab7[] = { 118static struct adctable tab7[] = {
119 { 20500000, BANDWIDTH_6_MHZ, 119 { 20500000, 6000000,
120 0x02ad0b99, 0x015685cc, 0x00ab4840, 0x00ab42e6, 0x00ab3d8c, 120 0x02ad0b99, 0x015685cc, 0x00ab4840, 0x00ab42e6, 0x00ab3d8c,
121 0x015685cc, 0x00ab42e6, 0x0055a173, 0x02fd, 0x0157 }, 121 0x015685cc, 0x00ab42e6, 0x0055a173, 0x02fd, 0x0157 },
122 { 20500000, BANDWIDTH_7_MHZ, 122 { 20500000, 7000000,
123 0x031f3832, 0x018f9c19, 0x00c7d44b, 0x00c7ce0c, 0x00c7c7ce, 123 0x031f3832, 0x018f9c19, 0x00c7d44b, 0x00c7ce0c, 0x00c7c7ce,
124 0x018f9c19, 0x00c7ce0c, 0x0063e706, 0x0290, 0x0190 }, 124 0x018f9c19, 0x00c7ce0c, 0x0063e706, 0x0290, 0x0190 },
125 { 20500000, BANDWIDTH_8_MHZ, 125 { 20500000, 8000000,
126 0x039164cb, 0x01c8b266, 0x00e46056, 0x00e45933, 0x00e45210, 126 0x039164cb, 0x01c8b266, 0x00e46056, 0x00e45933, 0x00e45210,
127 0x01c8b266, 0x00e45933, 0x00722c99, 0x023e, 0x01c9 }, 127 0x01c8b266, 0x00e45933, 0x00722c99, 0x023e, 0x01c9 },
128 { 20500000, BANDWIDTH_5_MHZ, 128 { 20500000, 5000000,
129 0x023adeff, 0x011d6f80, 0x008ebc36, 0x008eb7c0, 0x008eb34a, 129 0x023adeff, 0x011d6f80, 0x008ebc36, 0x008eb7c0, 0x008eb34a,
130 0x011d6f80, 0x008eb7c0, 0x00475be0, 0x0396, 0x011d } 130 0x011d6f80, 0x008eb7c0, 0x00475be0, 0x0396, 0x011d }
131 131
132}; 132};
133 133
134static struct adctable tab8[] = { 134static struct adctable tab8[] = {
135 { 20625000, BANDWIDTH_6_MHZ, 135 { 20625000, 6000000,
136 0x02a8e4bd, 0x0154725e, 0x00aa3e81, 0x00aa392f, 0x00aa33de, 136 0x02a8e4bd, 0x0154725e, 0x00aa3e81, 0x00aa392f, 0x00aa33de,
137 0x0154725e, 0x00aa392f, 0x00551c98, 0x0302, 0x0154 }, 137 0x0154725e, 0x00aa392f, 0x00551c98, 0x0302, 0x0154 },
138 { 20625000, BANDWIDTH_7_MHZ, 138 { 20625000, 7000000,
139 0x031a6032, 0x018d3019, 0x00c69e41, 0x00c6980c, 0x00c691d8, 139 0x031a6032, 0x018d3019, 0x00c69e41, 0x00c6980c, 0x00c691d8,
140 0x018d3019, 0x00c6980c, 0x00634c06, 0x0294, 0x018d }, 140 0x018d3019, 0x00c6980c, 0x00634c06, 0x0294, 0x018d },
141 { 20625000, BANDWIDTH_8_MHZ, 141 { 20625000, 8000000,
142 0x038bdba6, 0x01c5edd3, 0x00e2fe02, 0x00e2f6ea, 0x00e2efd2, 142 0x038bdba6, 0x01c5edd3, 0x00e2fe02, 0x00e2f6ea, 0x00e2efd2,
143 0x01c5edd3, 0x00e2f6ea, 0x00717b75, 0x0242, 0x01c6 }, 143 0x01c5edd3, 0x00e2f6ea, 0x00717b75, 0x0242, 0x01c6 },
144 { 20625000, BANDWIDTH_5_MHZ, 144 { 20625000, 5000000,
145 0x02376948, 0x011bb4a4, 0x008ddec1, 0x008dda52, 0x008dd5e3, 145 0x02376948, 0x011bb4a4, 0x008ddec1, 0x008dda52, 0x008dd5e3,
146 0x011bb4a4, 0x008dda52, 0x0046ed29, 0x039c, 0x011c } 146 0x011bb4a4, 0x008dda52, 0x0046ed29, 0x039c, 0x011c }
147 147
@@ -153,8 +153,7 @@ struct table {
153}; 153};
154 154
155static struct table fe_clockTable[] = { 155static struct table fe_clockTable[] = {
156 {12000000, tab3}, /* FPGA */ 156 {12000000, tab3}, /* 12.00MHz */
157 {16384000, tab6}, /* 16.38MHz */
158 {20480000, tab6}, /* 20.48MHz */ 157 {20480000, tab6}, /* 20.48MHz */
159 {36000000, tab3}, /* 36.00MHz */ 158 {36000000, tab3}, /* 36.00MHz */
160 {30000000, tab1}, /* 30.00MHz */ 159 {30000000, tab1}, /* 30.00MHz */
@@ -164,7 +163,6 @@ static struct table fe_clockTable[] = {
164 {34000000, tab2}, /* 34.00MHz */ 163 {34000000, tab2}, /* 34.00MHz */
165 {24000000, tab1}, /* 24.00MHz */ 164 {24000000, tab1}, /* 24.00MHz */
166 {22000000, tab8}, /* 22.00MHz */ 165 {22000000, tab8}, /* 22.00MHz */
167 {12000000, tab3} /* 12.00MHz */
168}; 166};
169 167
170/* fe get */ 168/* fe get */
@@ -205,6 +203,10 @@ fe_modulation_t fe_con[] = {
205 203
206/* Standard demodulator functions */ 204/* Standard demodulator functions */
207static struct it913xset set_solo_fe[] = { 205static struct it913xset set_solo_fe[] = {
206 {PRO_LINK, GPIOH5_EN, {0x01}, 0x01},
207 {PRO_LINK, GPIOH5_ON, {0x01}, 0x01},
208 {PRO_LINK, GPIOH5_O, {0x00}, 0x01},
209 {PRO_LINK, GPIOH5_O, {0x01}, 0x01},
208 {PRO_LINK, DVBT_INTEN, {0x04}, 0x01}, 210 {PRO_LINK, DVBT_INTEN, {0x04}, 0x01},
209 {PRO_LINK, DVBT_ENABLE, {0x05}, 0x01}, 211 {PRO_LINK, DVBT_ENABLE, {0x05}, 0x01},
210 {PRO_DMOD, MP2IF_MPEG_PAR_MODE, {0x00}, 0x01}, 212 {PRO_DMOD, MP2IF_MPEG_PAR_MODE, {0x00}, 0x01},
@@ -228,13 +230,127 @@ static struct it913xset init_1[] = {
228 {PRO_LINK, LOCK3_OUT, {0x01}, 0x01}, 230 {PRO_LINK, LOCK3_OUT, {0x01}, 0x01},
229 {PRO_LINK, PADMISCDRSR, {0x01}, 0x01}, 231 {PRO_LINK, PADMISCDRSR, {0x01}, 0x01},
230 {PRO_LINK, PADMISCDR2, {0x00}, 0x01}, 232 {PRO_LINK, PADMISCDR2, {0x00}, 0x01},
233 {PRO_DMOD, 0xec57, {0x00, 0x00}, 0x02},
231 {PRO_LINK, PADMISCDR4, {0x00}, 0x01}, /* Power up */ 234 {PRO_LINK, PADMISCDR4, {0x00}, 0x01}, /* Power up */
232 {PRO_LINK, PADMISCDR8, {0x00}, 0x01}, 235 {PRO_LINK, PADMISCDR8, {0x00}, 0x01},
233 {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ 236 {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */
234}; 237};
235 238
236/* ---------IT9137 0x38 tuner init---------- */ 239
237static struct it913xset it9137_set[] = { 240/* Version 1 types */
241static struct it913xset it9135_v1[] = {
242 {PRO_DMOD, 0x0051, {0x01}, 0x01},
243 {PRO_DMOD, 0x0070, {0x0a}, 0x01},
244 {PRO_DMOD, 0x007e, {0x04}, 0x01},
245 {PRO_DMOD, 0x0081, {0x0a}, 0x01},
246 {PRO_DMOD, 0x008a, {0x01}, 0x01},
247 {PRO_DMOD, 0x008e, {0x01}, 0x01},
248 {PRO_DMOD, 0x0092, {0x06}, 0x01},
249 {PRO_DMOD, 0x0099, {0x01}, 0x01},
250 {PRO_DMOD, 0x009f, {0xe1}, 0x01},
251 {PRO_DMOD, 0x00a0, {0xcf}, 0x01},
252 {PRO_DMOD, 0x00a3, {0x01}, 0x01},
253 {PRO_DMOD, 0x00a5, {0x01}, 0x01},
254 {PRO_DMOD, 0x00a6, {0x01}, 0x01},
255 {PRO_DMOD, 0x00a9, {0x00}, 0x01},
256 {PRO_DMOD, 0x00aa, {0x01}, 0x01},
257 {PRO_DMOD, 0x00b0, {0x01}, 0x01},
258 {PRO_DMOD, 0x00c2, {0x05}, 0x01},
259 {PRO_DMOD, 0x00c6, {0x19}, 0x01},
260 {PRO_DMOD, 0xf000, {0x0f}, 0x01},
261 {PRO_DMOD, 0xf016, {0x10}, 0x01},
262 {PRO_DMOD, 0xf017, {0x04}, 0x01},
263 {PRO_DMOD, 0xf018, {0x05}, 0x01},
264 {PRO_DMOD, 0xf019, {0x04}, 0x01},
265 {PRO_DMOD, 0xf01a, {0x05}, 0x01},
266 {PRO_DMOD, 0xf021, {0x03}, 0x01},
267 {PRO_DMOD, 0xf022, {0x0a}, 0x01},
268 {PRO_DMOD, 0xf023, {0x0a}, 0x01},
269 {PRO_DMOD, 0xf02b, {0x00}, 0x01},
270 {PRO_DMOD, 0xf02c, {0x01}, 0x01},
271 {PRO_DMOD, 0xf064, {0x03}, 0x01},
272 {PRO_DMOD, 0xf065, {0xf9}, 0x01},
273 {PRO_DMOD, 0xf066, {0x03}, 0x01},
274 {PRO_DMOD, 0xf067, {0x01}, 0x01},
275 {PRO_DMOD, 0xf06f, {0xe0}, 0x01},
276 {PRO_DMOD, 0xf070, {0x03}, 0x01},
277 {PRO_DMOD, 0xf072, {0x0f}, 0x01},
278 {PRO_DMOD, 0xf073, {0x03}, 0x01},
279 {PRO_DMOD, 0xf078, {0x00}, 0x01},
280 {PRO_DMOD, 0xf087, {0x00}, 0x01},
281 {PRO_DMOD, 0xf09b, {0x3f}, 0x01},
282 {PRO_DMOD, 0xf09c, {0x00}, 0x01},
283 {PRO_DMOD, 0xf09d, {0x20}, 0x01},
284 {PRO_DMOD, 0xf09e, {0x00}, 0x01},
285 {PRO_DMOD, 0xf09f, {0x0c}, 0x01},
286 {PRO_DMOD, 0xf0a0, {0x00}, 0x01},
287 {PRO_DMOD, 0xf130, {0x04}, 0x01},
288 {PRO_DMOD, 0xf132, {0x04}, 0x01},
289 {PRO_DMOD, 0xf144, {0x1a}, 0x01},
290 {PRO_DMOD, 0xf146, {0x00}, 0x01},
291 {PRO_DMOD, 0xf14a, {0x01}, 0x01},
292 {PRO_DMOD, 0xf14c, {0x00}, 0x01},
293 {PRO_DMOD, 0xf14d, {0x00}, 0x01},
294 {PRO_DMOD, 0xf14f, {0x04}, 0x01},
295 {PRO_DMOD, 0xf158, {0x7f}, 0x01},
296 {PRO_DMOD, 0xf15a, {0x00}, 0x01},
297 {PRO_DMOD, 0xf15b, {0x08}, 0x01},
298 {PRO_DMOD, 0xf15d, {0x03}, 0x01},
299 {PRO_DMOD, 0xf15e, {0x05}, 0x01},
300 {PRO_DMOD, 0xf163, {0x05}, 0x01},
301 {PRO_DMOD, 0xf166, {0x01}, 0x01},
302 {PRO_DMOD, 0xf167, {0x40}, 0x01},
303 {PRO_DMOD, 0xf168, {0x0f}, 0x01},
304 {PRO_DMOD, 0xf17a, {0x00}, 0x01},
305 {PRO_DMOD, 0xf17b, {0x00}, 0x01},
306 {PRO_DMOD, 0xf183, {0x01}, 0x01},
307 {PRO_DMOD, 0xf19d, {0x40}, 0x01},
308 {PRO_DMOD, 0xf1bc, {0x36}, 0x01},
309 {PRO_DMOD, 0xf1bd, {0x00}, 0x01},
310 {PRO_DMOD, 0xf1cb, {0xa0}, 0x01},
311 {PRO_DMOD, 0xf1cc, {0x01}, 0x01},
312 {PRO_DMOD, 0xf204, {0x10}, 0x01},
313 {PRO_DMOD, 0xf214, {0x00}, 0x01},
314 {PRO_DMOD, 0xf40e, {0x0a}, 0x01},
315 {PRO_DMOD, 0xf40f, {0x40}, 0x01},
316 {PRO_DMOD, 0xf410, {0x08}, 0x01},
317 {PRO_DMOD, 0xf55f, {0x0a}, 0x01},
318 {PRO_DMOD, 0xf561, {0x15}, 0x01},
319 {PRO_DMOD, 0xf562, {0x20}, 0x01},
320 {PRO_DMOD, 0xf5df, {0xfb}, 0x01},
321 {PRO_DMOD, 0xf5e0, {0x00}, 0x01},
322 {PRO_DMOD, 0xf5e3, {0x09}, 0x01},
323 {PRO_DMOD, 0xf5e4, {0x01}, 0x01},
324 {PRO_DMOD, 0xf5e5, {0x01}, 0x01},
325 {PRO_DMOD, 0xf5f8, {0x01}, 0x01},
326 {PRO_DMOD, 0xf5fd, {0x01}, 0x01},
327 {PRO_DMOD, 0xf600, {0x05}, 0x01},
328 {PRO_DMOD, 0xf601, {0x08}, 0x01},
329 {PRO_DMOD, 0xf602, {0x0b}, 0x01},
330 {PRO_DMOD, 0xf603, {0x0e}, 0x01},
331 {PRO_DMOD, 0xf604, {0x11}, 0x01},
332 {PRO_DMOD, 0xf605, {0x14}, 0x01},
333 {PRO_DMOD, 0xf606, {0x17}, 0x01},
334 {PRO_DMOD, 0xf607, {0x1f}, 0x01},
335 {PRO_DMOD, 0xf60e, {0x00}, 0x01},
336 {PRO_DMOD, 0xf60f, {0x04}, 0x01},
337 {PRO_DMOD, 0xf610, {0x32}, 0x01},
338 {PRO_DMOD, 0xf611, {0x10}, 0x01},
339 {PRO_DMOD, 0xf707, {0xfc}, 0x01},
340 {PRO_DMOD, 0xf708, {0x00}, 0x01},
341 {PRO_DMOD, 0xf709, {0x37}, 0x01},
342 {PRO_DMOD, 0xf70a, {0x00}, 0x01},
343 {PRO_DMOD, 0xf78b, {0x01}, 0x01},
344 {PRO_DMOD, 0xf80f, {0x40}, 0x01},
345 {PRO_DMOD, 0xf810, {0x54}, 0x01},
346 {PRO_DMOD, 0xf811, {0x5a}, 0x01},
347 {PRO_DMOD, 0xf905, {0x01}, 0x01},
348 {PRO_DMOD, 0xfb06, {0x03}, 0x01},
349 {PRO_DMOD, 0xfd8b, {0x00}, 0x01},
350 {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */
351};
352
353static struct it913xset it9135_38[] = {
238 {PRO_DMOD, 0x0043, {0x00}, 0x01}, 354 {PRO_DMOD, 0x0043, {0x00}, 0x01},
239 {PRO_DMOD, 0x0046, {0x38}, 0x01}, 355 {PRO_DMOD, 0x0046, {0x38}, 0x01},
240 {PRO_DMOD, 0x0051, {0x01}, 0x01}, 356 {PRO_DMOD, 0x0051, {0x01}, 0x01},
@@ -244,7 +360,7 @@ static struct it913xset it9137_set[] = {
244 {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0xc8, 0x01}, 0x05}, 360 {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0xc8, 0x01}, 0x05},
245 {PRO_DMOD, 0x007e, {0x04, 0x00}, 0x02}, 361 {PRO_DMOD, 0x007e, {0x04, 0x00}, 0x02},
246 {PRO_DMOD, 0x0081, { 0x0a, 0x12, 0x02, 0x0a, 0x03, 0xc8, 0xb8, 362 {PRO_DMOD, 0x0081, { 0x0a, 0x12, 0x02, 0x0a, 0x03, 0xc8, 0xb8,
247 0xd0, 0xc3, 0x01 }, 0x0a}, 363 0xd0, 0xc3, 0x01}, 0x0a},
248 {PRO_DMOD, 0x008e, {0x01}, 0x01}, 364 {PRO_DMOD, 0x008e, {0x01}, 0x01},
249 {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05}, 365 {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05},
250 {PRO_DMOD, 0x0099, {0x01}, 0x01}, 366 {PRO_DMOD, 0x0099, {0x01}, 0x01},
@@ -262,15 +378,25 @@ static struct it913xset it9137_set[] = {
262 {PRO_DMOD, 0x00f3, {0x05, 0x8c, 0x8c}, 0x03}, 378 {PRO_DMOD, 0x00f3, {0x05, 0x8c, 0x8c}, 0x03},
263 {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03}, 379 {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03},
264 {PRO_DMOD, 0x00fc, { 0x02, 0x02, 0x02, 0x09, 0x50, 0x7b, 0x77, 380 {PRO_DMOD, 0x00fc, { 0x02, 0x02, 0x02, 0x09, 0x50, 0x7b, 0x77,
265 0x00, 0x02, 0xc8, 0x05, 0x7b }, 0x0c}, 381 0x00, 0x02, 0xc8, 0x05, 0x7b}, 0x0c},
266 {PRO_DMOD, 0x0109, {0x02}, 0x01}, 382 {PRO_DMOD, 0x0109, {0x02}, 0x01},
267 {PRO_DMOD, 0x0115, {0x0a, 0x03}, 0x02}, 383 {PRO_DMOD, 0x0115, {0x0a, 0x03, 0x02, 0x80}, 0x04},
268 {PRO_DMOD, 0x011a, {0xc8, 0x7b, 0xbc, 0xa0}, 0x04}, 384 {PRO_DMOD, 0x011a, {0xc8, 0x7b, 0x8a, 0xa0}, 0x04},
269 {PRO_DMOD, 0x0122, {0x02, 0x18, 0xc3}, 0x03}, 385 {PRO_DMOD, 0x0122, {0x02, 0x18, 0xc3}, 0x03},
270 {PRO_DMOD, 0x0127, {0x00, 0x07}, 0x02}, 386 {PRO_DMOD, 0x0127, {0x00, 0x07}, 0x02},
271 {PRO_DMOD, 0x012a, {0x53, 0x51, 0x4e, 0x43}, 0x04}, 387 {PRO_DMOD, 0x012a, {0x53, 0x51, 0x4e, 0x43}, 0x04},
272 {PRO_DMOD, 0x0137, {0x01, 0x00, 0x07, 0x00, 0x06}, 0x05}, 388 {PRO_DMOD, 0x0137, {0x01, 0x00, 0x07, 0x00, 0x06}, 0x05},
273 {PRO_DMOD, 0x013d, {0x00, 0x01, 0x5b, 0xc8}, 0x04}, 389 {PRO_DMOD, 0x013d, {0x00, 0x01, 0x5b, 0xc8, 0x59}, 0x05},
390 {PRO_DMOD, 0xf000, {0x0f}, 0x01},
391 {PRO_DMOD, 0xf016, {0x10, 0x04, 0x05, 0x04, 0x05}, 0x05},
392 {PRO_DMOD, 0xf01f, {0x8c, 0x00, 0x03, 0x0a, 0x0a}, 0x05},
393 {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00, 0x01}, 0x04},
394 {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04},
395 {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02},
396 {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02},
397 {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02},
398 {PRO_DMOD, 0xf085, {0x00, 0x02, 0x00}, 0x03},
399 {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06},
274 {PRO_DMOD, 0xf130, {0x04}, 0x01}, 400 {PRO_DMOD, 0xf130, {0x04}, 0x01},
275 {PRO_DMOD, 0xf132, {0x04}, 0x01}, 401 {PRO_DMOD, 0xf132, {0x04}, 0x01},
276 {PRO_DMOD, 0xf144, {0x1a}, 0x01}, 402 {PRO_DMOD, 0xf144, {0x1a}, 0x01},
@@ -301,7 +427,7 @@ static struct it913xset it9137_set[] = {
301 {PRO_DMOD, 0xf5f8, {0x01}, 0x01}, 427 {PRO_DMOD, 0xf5f8, {0x01}, 0x01},
302 {PRO_DMOD, 0xf5fd, {0x01}, 0x01}, 428 {PRO_DMOD, 0xf5fd, {0x01}, 0x01},
303 {PRO_DMOD, 0xf600, { 0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17, 429 {PRO_DMOD, 0xf600, { 0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17,
304 0x1f }, 0x08}, 430 0x1f}, 0x08},
305 {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04}, 431 {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04},
306 {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04}, 432 {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04},
307 {PRO_DMOD, 0xf78b, {0x01}, 0x01}, 433 {PRO_DMOD, 0xf78b, {0x01}, 0x01},
@@ -309,21 +435,605 @@ static struct it913xset it9137_set[] = {
309 {PRO_DMOD, 0xf905, {0x01}, 0x01}, 435 {PRO_DMOD, 0xf905, {0x01}, 0x01},
310 {PRO_DMOD, 0xfb06, {0x03}, 0x01}, 436 {PRO_DMOD, 0xfb06, {0x03}, 0x01},
311 {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, 437 {PRO_DMOD, 0xfd8b, {0x00}, 0x01},
312 {PRO_LINK, GPIOH5_EN, {0x01}, 0x01}, 438 {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */
313 {PRO_LINK, GPIOH5_ON, {0x01}, 0x01}, 439};
314 {PRO_LINK, GPIOH5_O, {0x00}, 0x01}, 440
315 {PRO_LINK, GPIOH5_O, {0x01}, 0x01}, 441static struct it913xset it9135_51[] = {
316 {0xff, 0x0000, {0x00}, 0x00}, /* Terminating Entry */ 442 {PRO_DMOD, 0x0043, {0x00}, 0x01},
443 {PRO_DMOD, 0x0046, {0x51}, 0x01},
444 {PRO_DMOD, 0x0051, {0x01}, 0x01},
445 {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02},
446 {PRO_DMOD, 0x0068, {0x0a}, 0x01},
447 {PRO_DMOD, 0x0070, {0x0a, 0x06, 0x02}, 0x03},
448 {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0xc8, 0x01}, 0x05},
449 {PRO_DMOD, 0x007e, {0x04, 0x00}, 0x02},
450 {PRO_DMOD, 0x0081, { 0x0a, 0x12, 0x02, 0x0a, 0x03, 0xc0, 0x96,
451 0xcf, 0xc3, 0x01}, 0x0a},
452 {PRO_DMOD, 0x008e, {0x01}, 0x01},
453 {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05},
454 {PRO_DMOD, 0x0099, {0x01}, 0x01},
455 {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02},
456 {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02},
457 {PRO_DMOD, 0x00a3, {0x01, 0x5a, 0x01, 0x01}, 0x04},
458 {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02},
459 {PRO_DMOD, 0x00b0, {0x01}, 0x01},
460 {PRO_DMOD, 0x00b3, {0x02, 0x3c}, 0x02},
461 {PRO_DMOD, 0x00b6, {0x14}, 0x01},
462 {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05}, 0x03},
463 {PRO_DMOD, 0x00c4, {0x00}, 0x01},
464 {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02},
465 {PRO_DMOD, 0x00cc, {0x2e, 0x51, 0x33}, 0x03},
466 {PRO_DMOD, 0x00f3, {0x05, 0x8c, 0x8c}, 0x03},
467 {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03},
468 {PRO_DMOD, 0x00fc, { 0x03, 0x02, 0x02, 0x09, 0x50, 0x7a, 0x77,
469 0x01, 0x02, 0xb0, 0x02, 0x7a}, 0x0c},
470 {PRO_DMOD, 0x0109, {0x02}, 0x01},
471 {PRO_DMOD, 0x0115, {0x0a, 0x03, 0x02, 0x80}, 0x04},
472 {PRO_DMOD, 0x011a, {0xc0, 0x7a, 0xac, 0x8c}, 0x04},
473 {PRO_DMOD, 0x0122, {0x02, 0x70, 0xa4}, 0x03},
474 {PRO_DMOD, 0x0127, {0x00, 0x07}, 0x02},
475 {PRO_DMOD, 0x012a, {0x53, 0x51, 0x4e, 0x43}, 0x04},
476 {PRO_DMOD, 0x0137, {0x01, 0x00, 0x07, 0x00, 0x06}, 0x05},
477 {PRO_DMOD, 0x013d, {0x00, 0x01, 0x5b, 0xc0, 0x59}, 0x05},
478 {PRO_DMOD, 0xf000, {0x0f}, 0x01},
479 {PRO_DMOD, 0xf016, {0x10, 0x04, 0x05, 0x04, 0x05}, 0x05},
480 {PRO_DMOD, 0xf01f, {0x8c, 0x00, 0x03, 0x0a, 0x0a}, 0x05},
481 {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00, 0x01}, 0x04},
482 {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04},
483 {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02},
484 {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02},
485 {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02},
486 {PRO_DMOD, 0xf085, {0xc0, 0x01, 0x00}, 0x03},
487 {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06},
488 {PRO_DMOD, 0xf130, {0x04}, 0x01},
489 {PRO_DMOD, 0xf132, {0x04}, 0x01},
490 {PRO_DMOD, 0xf144, {0x1a}, 0x01},
491 {PRO_DMOD, 0xf146, {0x00}, 0x01},
492 {PRO_DMOD, 0xf14a, {0x01}, 0x01},
493 {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02},
494 {PRO_DMOD, 0xf14f, {0x04}, 0x01},
495 {PRO_DMOD, 0xf158, {0x7f}, 0x01},
496 {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02},
497 {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02},
498 {PRO_DMOD, 0xf163, {0x05}, 0x01},
499 {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03},
500 {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02},
501 {PRO_DMOD, 0xf183, {0x01}, 0x01},
502 {PRO_DMOD, 0xf19d, {0x40}, 0x01},
503 {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02},
504 {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02},
505 {PRO_DMOD, 0xf204, {0x10}, 0x01},
506 {PRO_DMOD, 0xf214, {0x00}, 0x01},
507 {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04},
508 {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05},
509 {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04},
510 {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03},
511 {PRO_DMOD, 0xf55f, {0x0a}, 0x01},
512 {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02},
513 {PRO_DMOD, 0xf5df, {0xfb, 0x00}, 0x02},
514 {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03},
515 {PRO_DMOD, 0xf5f8, {0x01}, 0x01},
516 {PRO_DMOD, 0xf5fd, {0x01}, 0x01},
517 {PRO_DMOD, 0xf600, { 0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17,
518 0x1f}, 0x08},
519 {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04},
520 {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04},
521 {PRO_DMOD, 0xf78b, {0x01}, 0x01},
522 {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03},
523 {PRO_DMOD, 0xf905, {0x01}, 0x01},
524 {PRO_DMOD, 0xfb06, {0x03}, 0x01},
525 {PRO_DMOD, 0xfd8b, {0x00}, 0x01},
526 {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */
527};
528
529static struct it913xset it9135_52[] = {
530 {PRO_DMOD, 0x0043, {0x00}, 0x01},
531 {PRO_DMOD, 0x0046, {0x52}, 0x01},
532 {PRO_DMOD, 0x0051, {0x01}, 0x01},
533 {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02},
534 {PRO_DMOD, 0x0068, {0x10}, 0x01},
535 {PRO_DMOD, 0x0070, {0x0a, 0x05, 0x02}, 0x03},
536 {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0xa0, 0x01}, 0x05},
537 {PRO_DMOD, 0x007e, {0x04, 0x00}, 0x02},
538 {PRO_DMOD, 0x0081, { 0x0a, 0x12, 0x03, 0x0a, 0x03, 0xb3, 0x97,
539 0xc0, 0x9e, 0x01}, 0x0a},
540 {PRO_DMOD, 0x008e, {0x01}, 0x01},
541 {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05},
542 {PRO_DMOD, 0x0099, {0x01}, 0x01},
543 {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02},
544 {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02},
545 {PRO_DMOD, 0x00a3, {0x01, 0x5c, 0x01, 0x01}, 0x04},
546 {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02},
547 {PRO_DMOD, 0x00b0, {0x01}, 0x01},
548 {PRO_DMOD, 0x00b3, {0x02, 0x3c}, 0x02},
549 {PRO_DMOD, 0x00b6, {0x14}, 0x01},
550 {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05}, 0x03},
551 {PRO_DMOD, 0x00c4, {0x00}, 0x01},
552 {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02},
553 {PRO_DMOD, 0x00cc, {0x2e, 0x51, 0x33}, 0x03},
554 {PRO_DMOD, 0x00f3, {0x05, 0x91, 0x8c}, 0x03},
555 {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03},
556 {PRO_DMOD, 0x00fc, { 0x03, 0x02, 0x02, 0x09, 0x50, 0x74, 0x77,
557 0x02, 0x02, 0xae, 0x02, 0x6e}, 0x0c},
558 {PRO_DMOD, 0x0109, {0x02}, 0x01},
559 {PRO_DMOD, 0x0115, {0x0a, 0x03, 0x02, 0x80}, 0x04},
560 {PRO_DMOD, 0x011a, {0xcd, 0x62, 0xa4, 0x8c}, 0x04},
561 {PRO_DMOD, 0x0122, {0x03, 0x18, 0x9e}, 0x03},
562 {PRO_DMOD, 0x0127, {0x00, 0x07}, 0x02},
563 {PRO_DMOD, 0x012a, {0x53, 0x51, 0x4e, 0x43}, 0x04},
564 {PRO_DMOD, 0x0137, {0x00, 0x00, 0x07, 0x00, 0x06}, 0x05},
565 {PRO_DMOD, 0x013d, {0x00, 0x01, 0x5b, 0xb6, 0x59}, 0x05},
566 {PRO_DMOD, 0xf000, {0x0f}, 0x01},
567 {PRO_DMOD, 0xf016, {0x10, 0x04, 0x05, 0x04, 0x05}, 0x05},
568 {PRO_DMOD, 0xf01f, {0x8c, 0x00, 0x03, 0x0a, 0x0a}, 0x05},
569 {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00, 0x01}, 0x04},
570 {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04},
571 {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02},
572 {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02},
573 {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02},
574 {PRO_DMOD, 0xf085, {0xc0, 0x01, 0x00}, 0x03},
575 {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06},
576 {PRO_DMOD, 0xf130, {0x04}, 0x01},
577 {PRO_DMOD, 0xf132, {0x04}, 0x01},
578 {PRO_DMOD, 0xf144, {0x1a}, 0x01},
579 {PRO_DMOD, 0xf146, {0x00}, 0x01},
580 {PRO_DMOD, 0xf14a, {0x01}, 0x01},
581 {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02},
582 {PRO_DMOD, 0xf14f, {0x04}, 0x01},
583 {PRO_DMOD, 0xf158, {0x7f}, 0x01},
584 {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02},
585 {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02},
586 {PRO_DMOD, 0xf163, {0x05}, 0x01},
587 {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03},
588 {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02},
589 {PRO_DMOD, 0xf183, {0x01}, 0x01},
590 {PRO_DMOD, 0xf19d, {0x40}, 0x01},
591 {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02},
592 {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02},
593 {PRO_DMOD, 0xf204, {0x10}, 0x01},
594 {PRO_DMOD, 0xf214, {0x00}, 0x01},
595 {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04},
596 {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05},
597 {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04},
598 {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03},
599 {PRO_DMOD, 0xf55f, {0x0a}, 0x01},
600 {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02},
601 {PRO_DMOD, 0xf5df, {0xfb, 0x00}, 0x02},
602 {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03},
603 {PRO_DMOD, 0xf5f8, {0x01}, 0x01},
604 {PRO_DMOD, 0xf5fd, {0x01}, 0x01},
605 {PRO_DMOD, 0xf600, {0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17,
606 0x1f}, 0x08},
607 {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04},
608 {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04},
609 {PRO_DMOD, 0xf78b, {0x01}, 0x01},
610 {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03},
611 {PRO_DMOD, 0xf905, {0x01}, 0x01},
612 {PRO_DMOD, 0xfb06, {0x03}, 0x01},
613 {PRO_DMOD, 0xfd8b, {0x00}, 0x01},
614 {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */
317}; 615};
318 616
617/* Version 2 types */
618static struct it913xset it9135_v2[] = {
619 {PRO_DMOD, 0x0051, {0x01}, 0x01},
620 {PRO_DMOD, 0x0070, {0x0a}, 0x01},
621 {PRO_DMOD, 0x007e, {0x04}, 0x01},
622 {PRO_DMOD, 0x0081, {0x0a}, 0x01},
623 {PRO_DMOD, 0x008a, {0x01}, 0x01},
624 {PRO_DMOD, 0x008e, {0x01}, 0x01},
625 {PRO_DMOD, 0x0092, {0x06}, 0x01},
626 {PRO_DMOD, 0x0099, {0x01}, 0x01},
627 {PRO_DMOD, 0x009f, {0xe1}, 0x01},
628 {PRO_DMOD, 0x00a0, {0xcf}, 0x01},
629 {PRO_DMOD, 0x00a3, {0x01}, 0x01},
630 {PRO_DMOD, 0x00a5, {0x01}, 0x01},
631 {PRO_DMOD, 0x00a6, {0x01}, 0x01},
632 {PRO_DMOD, 0x00a9, {0x00}, 0x01},
633 {PRO_DMOD, 0x00aa, {0x01}, 0x01},
634 {PRO_DMOD, 0x00b0, {0x01}, 0x01},
635 {PRO_DMOD, 0x00c2, {0x05}, 0x01},
636 {PRO_DMOD, 0x00c6, {0x19}, 0x01},
637 {PRO_DMOD, 0xf000, {0x0f}, 0x01},
638 {PRO_DMOD, 0xf02b, {0x00}, 0x01},
639 {PRO_DMOD, 0xf064, {0x03}, 0x01},
640 {PRO_DMOD, 0xf065, {0xf9}, 0x01},
641 {PRO_DMOD, 0xf066, {0x03}, 0x01},
642 {PRO_DMOD, 0xf067, {0x01}, 0x01},
643 {PRO_DMOD, 0xf06f, {0xe0}, 0x01},
644 {PRO_DMOD, 0xf070, {0x03}, 0x01},
645 {PRO_DMOD, 0xf072, {0x0f}, 0x01},
646 {PRO_DMOD, 0xf073, {0x03}, 0x01},
647 {PRO_DMOD, 0xf078, {0x00}, 0x01},
648 {PRO_DMOD, 0xf087, {0x00}, 0x01},
649 {PRO_DMOD, 0xf09b, {0x3f}, 0x01},
650 {PRO_DMOD, 0xf09c, {0x00}, 0x01},
651 {PRO_DMOD, 0xf09d, {0x20}, 0x01},
652 {PRO_DMOD, 0xf09e, {0x00}, 0x01},
653 {PRO_DMOD, 0xf09f, {0x0c}, 0x01},
654 {PRO_DMOD, 0xf0a0, {0x00}, 0x01},
655 {PRO_DMOD, 0xf130, {0x04}, 0x01},
656 {PRO_DMOD, 0xf132, {0x04}, 0x01},
657 {PRO_DMOD, 0xf144, {0x1a}, 0x01},
658 {PRO_DMOD, 0xf146, {0x00}, 0x01},
659 {PRO_DMOD, 0xf14a, {0x01}, 0x01},
660 {PRO_DMOD, 0xf14c, {0x00}, 0x01},
661 {PRO_DMOD, 0xf14d, {0x00}, 0x01},
662 {PRO_DMOD, 0xf14f, {0x04}, 0x01},
663 {PRO_DMOD, 0xf158, {0x7f}, 0x01},
664 {PRO_DMOD, 0xf15a, {0x00}, 0x01},
665 {PRO_DMOD, 0xf15b, {0x08}, 0x01},
666 {PRO_DMOD, 0xf15d, {0x03}, 0x01},
667 {PRO_DMOD, 0xf15e, {0x05}, 0x01},
668 {PRO_DMOD, 0xf163, {0x05}, 0x01},
669 {PRO_DMOD, 0xf166, {0x01}, 0x01},
670 {PRO_DMOD, 0xf167, {0x40}, 0x01},
671 {PRO_DMOD, 0xf168, {0x0f}, 0x01},
672 {PRO_DMOD, 0xf17a, {0x00}, 0x01},
673 {PRO_DMOD, 0xf17b, {0x00}, 0x01},
674 {PRO_DMOD, 0xf183, {0x01}, 0x01},
675 {PRO_DMOD, 0xf19d, {0x40}, 0x01},
676 {PRO_DMOD, 0xf1bc, {0x36}, 0x01},
677 {PRO_DMOD, 0xf1bd, {0x00}, 0x01},
678 {PRO_DMOD, 0xf1cb, {0xa0}, 0x01},
679 {PRO_DMOD, 0xf1cc, {0x01}, 0x01},
680 {PRO_DMOD, 0xf204, {0x10}, 0x01},
681 {PRO_DMOD, 0xf214, {0x00}, 0x01},
682 {PRO_DMOD, 0xf40e, {0x0a}, 0x01},
683 {PRO_DMOD, 0xf40f, {0x40}, 0x01},
684 {PRO_DMOD, 0xf410, {0x08}, 0x01},
685 {PRO_DMOD, 0xf55f, {0x0a}, 0x01},
686 {PRO_DMOD, 0xf561, {0x15}, 0x01},
687 {PRO_DMOD, 0xf562, {0x20}, 0x01},
688 {PRO_DMOD, 0xf5e3, {0x09}, 0x01},
689 {PRO_DMOD, 0xf5e4, {0x01}, 0x01},
690 {PRO_DMOD, 0xf5e5, {0x01}, 0x01},
691 {PRO_DMOD, 0xf600, {0x05}, 0x01},
692 {PRO_DMOD, 0xf601, {0x08}, 0x01},
693 {PRO_DMOD, 0xf602, {0x0b}, 0x01},
694 {PRO_DMOD, 0xf603, {0x0e}, 0x01},
695 {PRO_DMOD, 0xf604, {0x11}, 0x01},
696 {PRO_DMOD, 0xf605, {0x14}, 0x01},
697 {PRO_DMOD, 0xf606, {0x17}, 0x01},
698 {PRO_DMOD, 0xf607, {0x1f}, 0x01},
699 {PRO_DMOD, 0xf60e, {0x00}, 0x01},
700 {PRO_DMOD, 0xf60f, {0x04}, 0x01},
701 {PRO_DMOD, 0xf610, {0x32}, 0x01},
702 {PRO_DMOD, 0xf611, {0x10}, 0x01},
703 {PRO_DMOD, 0xf707, {0xfc}, 0x01},
704 {PRO_DMOD, 0xf708, {0x00}, 0x01},
705 {PRO_DMOD, 0xf709, {0x37}, 0x01},
706 {PRO_DMOD, 0xf70a, {0x00}, 0x01},
707 {PRO_DMOD, 0xf78b, {0x01}, 0x01},
708 {PRO_DMOD, 0xf80f, {0x40}, 0x01},
709 {PRO_DMOD, 0xf810, {0x54}, 0x01},
710 {PRO_DMOD, 0xf811, {0x5a}, 0x01},
711 {PRO_DMOD, 0xf905, {0x01}, 0x01},
712 {PRO_DMOD, 0xfb06, {0x03}, 0x01},
713 {PRO_DMOD, 0xfd8b, {0x00}, 0x01},
714 {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */
715};
716
717static struct it913xset it9135_60[] = {
718 {PRO_DMOD, 0x0043, {0x00}, 0x01},
719 {PRO_DMOD, 0x0046, {0x60}, 0x01},
720 {PRO_DMOD, 0x0051, {0x01}, 0x01},
721 {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02},
722 {PRO_DMOD, 0x0068, {0x0a}, 0x01},
723 {PRO_DMOD, 0x006a, {0x03}, 0x01},
724 {PRO_DMOD, 0x0070, {0x0a, 0x05, 0x02}, 0x03},
725 {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0x8c, 0x01}, 0x05},
726 {PRO_DMOD, 0x007e, {0x04}, 0x01},
727 {PRO_DMOD, 0x0081, {0x0a, 0x12}, 0x02},
728 {PRO_DMOD, 0x0084, {0x0a, 0x33, 0xbe, 0xa0, 0xc6, 0xb6, 0x01}, 0x07},
729 {PRO_DMOD, 0x008e, {0x01}, 0x01},
730 {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05},
731 {PRO_DMOD, 0x0099, {0x01}, 0x01},
732 {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02},
733 {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02},
734 {PRO_DMOD, 0x00a3, {0x01, 0x5a, 0x01, 0x01}, 0x04},
735 {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02},
736 {PRO_DMOD, 0x00b0, {0x01}, 0x01},
737 {PRO_DMOD, 0x00b3, {0x02, 0x3a}, 0x02},
738 {PRO_DMOD, 0x00b6, {0x14}, 0x01},
739 {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05, 0x01, 0x00}, 0x05},
740 {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02},
741 {PRO_DMOD, 0x00cb, {0x32, 0x2c, 0x4f, 0x30}, 0x04},
742 {PRO_DMOD, 0x00f3, {0x05, 0xa0, 0x8c}, 0x03},
743 {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03},
744 {PRO_DMOD, 0x00fc, { 0x03, 0x03, 0x02, 0x0a, 0x50, 0x7b, 0x8c,
745 0x00, 0x02, 0xbe, 0x00}, 0x0b},
746 {PRO_DMOD, 0x0109, {0x02}, 0x01},
747 {PRO_DMOD, 0x0115, {0x0a, 0x03}, 0x02},
748 {PRO_DMOD, 0x011a, {0xbe}, 0x01},
749 {PRO_DMOD, 0x0124, {0xae}, 0x01},
750 {PRO_DMOD, 0x0127, {0x00}, 0x01},
751 {PRO_DMOD, 0x012a, {0x56, 0x50, 0x47, 0x42}, 0x04},
752 {PRO_DMOD, 0x0137, {0x00}, 0x01},
753 {PRO_DMOD, 0x013b, {0x08}, 0x01},
754 {PRO_DMOD, 0x013f, {0x5b}, 0x01},
755 {PRO_DMOD, 0x0141, { 0x59, 0xf9, 0x19, 0x19, 0x8c, 0x8c, 0x8c,
756 0x6e, 0x8c, 0x50, 0x8c, 0x8c, 0xac, 0xc6,
757 0x33}, 0x0f},
758 {PRO_DMOD, 0x0151, {0x28}, 0x01},
759 {PRO_DMOD, 0x0153, {0xbc}, 0x01},
760 {PRO_DMOD, 0x0178, {0x09}, 0x01},
761 {PRO_DMOD, 0x0181, {0x94, 0x6e}, 0x02},
762 {PRO_DMOD, 0x0185, {0x24}, 0x01},
763 {PRO_DMOD, 0x0187, {0x00, 0x00, 0xbe, 0x02, 0x80}, 0x05},
764 {PRO_DMOD, 0xed02, {0xff}, 0x01},
765 {PRO_DMOD, 0xee42, {0xff}, 0x01},
766 {PRO_DMOD, 0xee82, {0xff}, 0x01},
767 {PRO_DMOD, 0xf000, {0x0f}, 0x01},
768 {PRO_DMOD, 0xf01f, {0x8c, 0x00}, 0x02},
769 {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00}, 0x03},
770 {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04},
771 {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02},
772 {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02},
773 {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02},
774 {PRO_DMOD, 0xf087, {0x00}, 0x01},
775 {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06},
776 {PRO_DMOD, 0xf130, {0x04}, 0x01},
777 {PRO_DMOD, 0xf132, {0x04}, 0x01},
778 {PRO_DMOD, 0xf144, {0x1a}, 0x01},
779 {PRO_DMOD, 0xf146, {0x00}, 0x01},
780 {PRO_DMOD, 0xf14a, {0x01}, 0x01},
781 {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02},
782 {PRO_DMOD, 0xf14f, {0x04}, 0x01},
783 {PRO_DMOD, 0xf158, {0x7f}, 0x01},
784 {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02},
785 {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02},
786 {PRO_DMOD, 0xf163, {0x05}, 0x01},
787 {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03},
788 {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02},
789 {PRO_DMOD, 0xf183, {0x01}, 0x01},
790 {PRO_DMOD, 0xf19d, {0x40}, 0x01},
791 {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02},
792 {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02},
793 {PRO_DMOD, 0xf204, {0x10}, 0x01},
794 {PRO_DMOD, 0xf214, {0x00}, 0x01},
795 {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04},
796 {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05},
797 {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04},
798 {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03},
799 {PRO_DMOD, 0xf55f, {0x0a}, 0x01},
800 {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02},
801 {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03},
802 {PRO_DMOD, 0xf600, {0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17
803 , 0x1f}, 0x08},
804 {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04},
805 {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04},
806 {PRO_DMOD, 0xf78b, {0x01}, 0x01},
807 {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03},
808 {PRO_DMOD, 0xf905, {0x01}, 0x01},
809 {PRO_DMOD, 0xfb06, {0x03}, 0x01},
810 {PRO_DMOD, 0xfd8b, {0x00}, 0x01},
811 {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */
812};
813
814static struct it913xset it9135_61[] = {
815 {PRO_DMOD, 0x0043, {0x00}, 0x01},
816 {PRO_DMOD, 0x0046, {0x61}, 0x01},
817 {PRO_DMOD, 0x0051, {0x01}, 0x01},
818 {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02},
819 {PRO_DMOD, 0x0068, {0x06}, 0x01},
820 {PRO_DMOD, 0x006a, {0x03}, 0x01},
821 {PRO_DMOD, 0x0070, {0x0a, 0x05, 0x02}, 0x03},
822 {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0x90, 0x01}, 0x05},
823 {PRO_DMOD, 0x007e, {0x04}, 0x01},
824 {PRO_DMOD, 0x0081, {0x0a, 0x12}, 0x02},
825 {PRO_DMOD, 0x0084, {0x0a, 0x33, 0xbc, 0x9c, 0xcc, 0xa8, 0x01}, 0x07},
826 {PRO_DMOD, 0x008e, {0x01}, 0x01},
827 {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05},
828 {PRO_DMOD, 0x0099, {0x01}, 0x01},
829 {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02},
830 {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02},
831 {PRO_DMOD, 0x00a3, {0x01, 0x5c, 0x01, 0x01}, 0x04},
832 {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02},
833 {PRO_DMOD, 0x00b0, {0x01}, 0x01},
834 {PRO_DMOD, 0x00b3, {0x02, 0x3a}, 0x02},
835 {PRO_DMOD, 0x00b6, {0x14}, 0x01},
836 {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05, 0x01, 0x00}, 0x05},
837 {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02},
838 {PRO_DMOD, 0x00cb, {0x32, 0x2c, 0x4f, 0x30}, 0x04},
839 {PRO_DMOD, 0x00f3, {0x05, 0xa0, 0x8c}, 0x03},
840 {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03},
841 {PRO_DMOD, 0x00fc, { 0x03, 0x03, 0x02, 0x08, 0x50, 0x7b, 0x8c,
842 0x01, 0x02, 0xc8, 0x00}, 0x0b},
843 {PRO_DMOD, 0x0109, {0x02}, 0x01},
844 {PRO_DMOD, 0x0115, {0x0a, 0x03}, 0x02},
845 {PRO_DMOD, 0x011a, {0xc6}, 0x01},
846 {PRO_DMOD, 0x0124, {0xa8}, 0x01},
847 {PRO_DMOD, 0x0127, {0x00}, 0x01},
848 {PRO_DMOD, 0x012a, {0x59, 0x50, 0x47, 0x42}, 0x04},
849 {PRO_DMOD, 0x0137, {0x00}, 0x01},
850 {PRO_DMOD, 0x013b, {0x05}, 0x01},
851 {PRO_DMOD, 0x013f, {0x5b}, 0x01},
852 {PRO_DMOD, 0x0141, { 0x59, 0xf9, 0x59, 0x59, 0x8c, 0x8c, 0x8c,
853 0x7b, 0x8c, 0x50, 0x8c, 0x8c, 0xa8, 0xc6,
854 0x33}, 0x0f},
855 {PRO_DMOD, 0x0151, {0x28}, 0x01},
856 {PRO_DMOD, 0x0153, {0xcc}, 0x01},
857 {PRO_DMOD, 0x0178, {0x09}, 0x01},
858 {PRO_DMOD, 0x0181, {0x9c, 0x76}, 0x02},
859 {PRO_DMOD, 0x0185, {0x28}, 0x01},
860 {PRO_DMOD, 0x0187, {0x01, 0x00, 0xaa, 0x02, 0x80}, 0x05},
861 {PRO_DMOD, 0xed02, {0xff}, 0x01},
862 {PRO_DMOD, 0xee42, {0xff}, 0x01},
863 {PRO_DMOD, 0xee82, {0xff}, 0x01},
864 {PRO_DMOD, 0xf000, {0x0f}, 0x01},
865 {PRO_DMOD, 0xf01f, {0x8c, 0x00}, 0x02},
866 {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00}, 0x03},
867 {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04},
868 {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02},
869 {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02},
870 {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02},
871 {PRO_DMOD, 0xf087, {0x00}, 0x01},
872 {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06},
873 {PRO_DMOD, 0xf130, {0x04}, 0x01},
874 {PRO_DMOD, 0xf132, {0x04}, 0x01},
875 {PRO_DMOD, 0xf144, {0x1a}, 0x01},
876 {PRO_DMOD, 0xf146, {0x00}, 0x01},
877 {PRO_DMOD, 0xf14a, {0x01}, 0x01},
878 {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02},
879 {PRO_DMOD, 0xf14f, {0x04}, 0x01},
880 {PRO_DMOD, 0xf158, {0x7f}, 0x01},
881 {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02},
882 {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02},
883 {PRO_DMOD, 0xf163, {0x05}, 0x01},
884 {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03},
885 {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02},
886 {PRO_DMOD, 0xf183, {0x01}, 0x01},
887 {PRO_DMOD, 0xf19d, {0x40}, 0x01},
888 {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02},
889 {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02},
890 {PRO_DMOD, 0xf204, {0x10}, 0x01},
891 {PRO_DMOD, 0xf214, {0x00}, 0x01},
892 {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04},
893 {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05},
894 {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04},
895 {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03},
896 {PRO_DMOD, 0xf55f, {0x0a}, 0x01},
897 {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02},
898 {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03},
899 {PRO_DMOD, 0xf600, { 0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17,
900 0x1f}, 0x08},
901 {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04},
902 {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04},
903 {PRO_DMOD, 0xf78b, {0x01}, 0x01},
904 {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03},
905 {PRO_DMOD, 0xf905, {0x01}, 0x01},
906 {PRO_DMOD, 0xfb06, {0x03}, 0x01},
907 {PRO_DMOD, 0xfd8b, {0x00}, 0x01},
908 {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */
909};
910
911static struct it913xset it9135_62[] = {
912 {PRO_DMOD, 0x0043, {0x00}, 0x01},
913 {PRO_DMOD, 0x0046, {0x62}, 0x01},
914 {PRO_DMOD, 0x0051, {0x01}, 0x01},
915 {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02},
916 {PRO_DMOD, 0x0068, {0x0a}, 0x01},
917 {PRO_DMOD, 0x006a, {0x03}, 0x01},
918 {PRO_DMOD, 0x0070, {0x0a, 0x05, 0x02}, 0x03},
919 {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0x8c, 0x01}, 0x05},
920 {PRO_DMOD, 0x007e, {0x04}, 0x01},
921 {PRO_DMOD, 0x0081, {0x0a, 0x12}, 0x02},
922 {PRO_DMOD, 0x0084, { 0x0a, 0x33, 0xb8, 0x9c, 0xb2, 0xa6, 0x01},
923 0x07},
924 {PRO_DMOD, 0x008e, {0x01}, 0x01},
925 {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05},
926 {PRO_DMOD, 0x0099, {0x01}, 0x01},
927 {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02},
928 {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02},
929 {PRO_DMOD, 0x00a3, {0x01, 0x5a, 0x01, 0x01}, 0x04},
930 {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02},
931 {PRO_DMOD, 0x00b0, {0x01}, 0x01},
932 {PRO_DMOD, 0x00b3, {0x02, 0x3a}, 0x02},
933 {PRO_DMOD, 0x00b6, {0x14}, 0x01},
934 {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05, 0x01, 0x00}, 0x05},
935 {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02},
936 {PRO_DMOD, 0x00cb, {0x32, 0x2c, 0x4f, 0x30}, 0x04},
937 {PRO_DMOD, 0x00f3, {0x05, 0x8c, 0x8c}, 0x03},
938 {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03},
939 {PRO_DMOD, 0x00fc, { 0x02, 0x03, 0x02, 0x09, 0x50, 0x6e, 0x8c,
940 0x02, 0x02, 0xc2, 0x00}, 0x0b},
941 {PRO_DMOD, 0x0109, {0x02}, 0x01},
942 {PRO_DMOD, 0x0115, {0x0a, 0x03}, 0x02},
943 {PRO_DMOD, 0x011a, {0xb8}, 0x01},
944 {PRO_DMOD, 0x0124, {0xa8}, 0x01},
945 {PRO_DMOD, 0x0127, {0x00}, 0x01},
946 {PRO_DMOD, 0x012a, {0x53, 0x51, 0x4e, 0x43}, 0x04},
947 {PRO_DMOD, 0x0137, {0x00}, 0x01},
948 {PRO_DMOD, 0x013b, {0x05}, 0x01},
949 {PRO_DMOD, 0x013f, {0x5b}, 0x01},
950 {PRO_DMOD, 0x0141, { 0x59, 0xf9, 0x59, 0x19, 0x8c, 0x8c, 0x8c,
951 0x7b, 0x8c, 0x50, 0x70, 0x8c, 0x96, 0xd0,
952 0x33}, 0x0f},
953 {PRO_DMOD, 0x0151, {0x28}, 0x01},
954 {PRO_DMOD, 0x0153, {0xb2}, 0x01},
955 {PRO_DMOD, 0x0178, {0x09}, 0x01},
956 {PRO_DMOD, 0x0181, {0x9c, 0x6e}, 0x02},
957 {PRO_DMOD, 0x0185, {0x24}, 0x01},
958 {PRO_DMOD, 0x0187, {0x00, 0x00, 0xb8, 0x02, 0x80}, 0x05},
959 {PRO_DMOD, 0xed02, {0xff}, 0x01},
960 {PRO_DMOD, 0xee42, {0xff}, 0x01},
961 {PRO_DMOD, 0xee82, {0xff}, 0x01},
962 {PRO_DMOD, 0xf000, {0x0f}, 0x01},
963 {PRO_DMOD, 0xf01f, {0x8c, 0x00}, 0x02},
964 {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00}, 0x03},
965 {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04},
966 {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02},
967 {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02},
968 {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02},
969 {PRO_DMOD, 0xf087, {0x00}, 0x01},
970 {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06},
971 {PRO_DMOD, 0xf130, {0x04}, 0x01},
972 {PRO_DMOD, 0xf132, {0x04}, 0x01},
973 {PRO_DMOD, 0xf144, {0x1a}, 0x01},
974 {PRO_DMOD, 0xf146, {0x00}, 0x01},
975 {PRO_DMOD, 0xf14a, {0x01}, 0x01},
976 {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02},
977 {PRO_DMOD, 0xf14f, {0x04}, 0x01},
978 {PRO_DMOD, 0xf158, {0x7f}, 0x01},
979 {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02},
980 {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02},
981 {PRO_DMOD, 0xf163, {0x05}, 0x01},
982 {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03},
983 {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02},
984 {PRO_DMOD, 0xf183, {0x01}, 0x01},
985 {PRO_DMOD, 0xf19d, {0x40}, 0x01},
986 {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02},
987 {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02},
988 {PRO_DMOD, 0xf204, {0x10}, 0x01},
989 {PRO_DMOD, 0xf214, {0x00}, 0x01},
990 {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04},
991 {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05},
992 {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04},
993 {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03},
994 {PRO_DMOD, 0xf55f, {0x0a}, 0x01},
995 {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02},
996 {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03},
997 {PRO_DMOD, 0xf600, { 0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17,
998 0x1f}, 0x08},
999 {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04},
1000 {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04},
1001 {PRO_DMOD, 0xf78b, {0x01}, 0x01},
1002 {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03},
1003 {PRO_DMOD, 0xf905, {0x01}, 0x01},
1004 {PRO_DMOD, 0xfb06, {0x03}, 0x01},
1005 {PRO_DMOD, 0xfd8b, {0x00}, 0x01},
1006 {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */
1007};
1008
1009/* Tuner setting scripts (still keeping it9137) */
319static struct it913xset it9137_tuner_off[] = { 1010static struct it913xset it9137_tuner_off[] = {
320 {PRO_DMOD, 0xfba8, {0x01}, 0x01}, /* Tuner Clock Off */ 1011 {PRO_DMOD, 0xfba8, {0x01}, 0x01}, /* Tuner Clock Off */
321 {PRO_DMOD, 0xec40, {0x00}, 0x01}, /* Power Down Tuner */ 1012 {PRO_DMOD, 0xec40, {0x00}, 0x01}, /* Power Down Tuner */
322 {PRO_DMOD, 0xec02, {0x3f, 0x1f, 0x3f, 0x3f}, 0x04}, 1013 {PRO_DMOD, 0xec02, {0x3f, 0x1f, 0x3f, 0x3f}, 0x04},
1014 {PRO_DMOD, 0xec06, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1015 0x00, 0x00, 0x00, 0x00}, 0x0c},
1016 {PRO_DMOD, 0xec12, {0x00, 0x00, 0x00, 0x00}, 0x04},
1017 {PRO_DMOD, 0xec17, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1018 0x00}, 0x09},
1019 {PRO_DMOD, 0xec22, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1020 0x00, 0x00}, 0x0a},
1021 {PRO_DMOD, 0xec20, {0x00}, 0x01},
323 {PRO_DMOD, 0xec3f, {0x01}, 0x01}, 1022 {PRO_DMOD, 0xec3f, {0x01}, 0x01},
324 {0xff, 0x0000, {0x00}, 0x00}, /* Terminating Entry */ 1023 {0xff, 0x0000, {0x00}, 0x00}, /* Terminating Entry */
325}; 1024};
326 1025
1026static struct it913xset set_it9135_template[] = {
1027 {PRO_DMOD, 0xee06, {0x00}, 0x01},
1028 {PRO_DMOD, 0xec56, {0x00}, 0x01},
1029 {PRO_DMOD, 0xec4c, {0x00}, 0x01},
1030 {PRO_DMOD, 0xec4d, {0x00}, 0x01},
1031 {PRO_DMOD, 0xec4e, {0x00}, 0x01},
1032 {PRO_DMOD, 0x011e, {0x00}, 0x01}, /* Older Devices */
1033 {PRO_DMOD, 0x011f, {0x00}, 0x01},
1034 {0xff, 0x0000, {0x00}, 0x00}, /* Terminating Entry */
1035};
1036
327static struct it913xset set_it9137_template[] = { 1037static struct it913xset set_it9137_template[] = {
328 {PRO_DMOD, 0xee06, {0x00}, 0x01}, 1038 {PRO_DMOD, 0xee06, {0x00}, 0x01},
329 {PRO_DMOD, 0xec56, {0x00}, 0x01}, 1039 {PRO_DMOD, 0xec56, {0x00}, 0x01},
diff --git a/drivers/media/dvb/frontends/it913x-fe.c b/drivers/media/dvb/frontends/it913x-fe.c
index d4bd24eb4700..ccc36bf2deb4 100644
--- a/drivers/media/dvb/frontends/it913x-fe.c
+++ b/drivers/media/dvb/frontends/it913x-fe.c
@@ -46,13 +46,17 @@ MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
46 dprintk(level, name" (%02x%02x%02x%02x%02x%02x%02x%02x)", \ 46 dprintk(level, name" (%02x%02x%02x%02x%02x%02x%02x%02x)", \
47 *p, *(p+1), *(p+2), *(p+3), *(p+4), \ 47 *p, *(p+1), *(p+2), *(p+3), *(p+4), \
48 *(p+5), *(p+6), *(p+7)); 48 *(p+5), *(p+6), *(p+7));
49#define info(format, arg...) \
50 printk(KERN_INFO "it913x-fe: " format "\n" , ## arg)
49 51
50struct it913x_fe_state { 52struct it913x_fe_state {
51 struct dvb_frontend frontend; 53 struct dvb_frontend frontend;
52 struct i2c_adapter *i2c_adap; 54 struct i2c_adapter *i2c_adap;
55 struct ite_config *config;
53 u8 i2c_addr; 56 u8 i2c_addr;
54 u32 frequency; 57 u32 frequency;
55 u8 adf; 58 fe_modulation_t constellation;
59 fe_transmit_mode_t transmission_mode;
56 u32 crystalFrequency; 60 u32 crystalFrequency;
57 u32 adcFrequency; 61 u32 adcFrequency;
58 u8 tuner_type; 62 u8 tuner_type;
@@ -62,6 +66,7 @@ struct it913x_fe_state {
62 u8 tun_fdiv; 66 u8 tun_fdiv;
63 u8 tun_clk_mode; 67 u8 tun_clk_mode;
64 u32 tun_fn_min; 68 u32 tun_fn_min;
69 u32 ucblocks;
65}; 70};
66 71
67static int it913x_read_reg(struct it913x_fe_state *state, 72static int it913x_read_reg(struct it913x_fe_state *state,
@@ -211,20 +216,24 @@ static int it913x_init_tuner(struct it913x_fe_state *state)
211 state->tun_fn_min /= (state->tun_fdiv * nv_val); 216 state->tun_fn_min /= (state->tun_fdiv * nv_val);
212 deb_info("Tuner fn_min %d", state->tun_fn_min); 217 deb_info("Tuner fn_min %d", state->tun_fn_min);
213 218
214 for (i = 0; i < 50; i++) { 219 if (state->config->chip_ver > 1)
215 reg = it913x_read_reg_u8(state, 0xec82); 220 msleep(50);
216 if (reg > 0) 221 else {
217 break; 222 for (i = 0; i < 50; i++) {
218 if (reg < 0) 223 reg = it913x_read_reg_u8(state, 0xec82);
219 return -ENODEV; 224 if (reg > 0)
220 udelay(2000); 225 break;
226 if (reg < 0)
227 return -ENODEV;
228 udelay(2000);
229 }
221 } 230 }
222 231
223 return it913x_write_reg(state, PRO_DMOD, 0xed81, val); 232 return it913x_write_reg(state, PRO_DMOD, 0xed81, val);
224} 233}
225 234
226static int it9137_set_tuner(struct it913x_fe_state *state, 235static int it9137_set_tuner(struct it913x_fe_state *state,
227 enum fe_bandwidth bandwidth, u32 frequency_m) 236 u32 bandwidth, u32 frequency_m)
228{ 237{
229 struct it913xset *set_tuner = set_it9137_template; 238 struct it913xset *set_tuner = set_it9137_template;
230 int ret, reg; 239 int ret, reg;
@@ -237,6 +246,11 @@ static int it9137_set_tuner(struct it913x_fe_state *state,
237 u8 lna_band; 246 u8 lna_band;
238 u8 bw; 247 u8 bw;
239 248
249 if (state->config->firmware_ver == 1)
250 set_tuner = set_it9135_template;
251 else
252 set_tuner = set_it9137_template;
253
240 deb_info("Tuner Frequency %d Bandwidth %d", frequency, bandwidth); 254 deb_info("Tuner Frequency %d Bandwidth %d", frequency, bandwidth);
241 255
242 if (frequency >= 51000 && frequency <= 440000) { 256 if (frequency >= 51000 && frequency <= 440000) {
@@ -273,16 +287,21 @@ static int it9137_set_tuner(struct it913x_fe_state *state,
273 return -EINVAL; 287 return -EINVAL;
274 set_tuner[0].reg[0] = lna_band; 288 set_tuner[0].reg[0] = lna_band;
275 289
276 if (bandwidth == BANDWIDTH_5_MHZ) 290 switch (bandwidth) {
291 case 5000000:
277 bw = 0; 292 bw = 0;
278 else if (bandwidth == BANDWIDTH_6_MHZ) 293 break;
294 case 6000000:
279 bw = 2; 295 bw = 2;
280 else if (bandwidth == BANDWIDTH_7_MHZ) 296 break;
297 case 7000000:
281 bw = 4; 298 bw = 4;
282 else if (bandwidth == BANDWIDTH_8_MHZ) 299 break;
283 bw = 6; 300 default:
284 else 301 case 8000000:
285 bw = 6; 302 bw = 6;
303 break;
304 }
286 305
287 set_tuner[1].reg[0] = bw; 306 set_tuner[1].reg[0] = bw;
288 set_tuner[2].reg[0] = 0xa0 | (l_band << 3); 307 set_tuner[2].reg[0] = 0xa0 | (l_band << 3);
@@ -361,7 +380,7 @@ static int it9137_set_tuner(struct it913x_fe_state *state,
361} 380}
362 381
363static int it913x_fe_select_bw(struct it913x_fe_state *state, 382static int it913x_fe_select_bw(struct it913x_fe_state *state,
364 enum fe_bandwidth bandwidth, u32 adcFrequency) 383 u32 bandwidth, u32 adcFrequency)
365{ 384{
366 int ret, i; 385 int ret, i;
367 u8 buffer[256]; 386 u8 buffer[256];
@@ -374,17 +393,21 @@ static int it913x_fe_select_bw(struct it913x_fe_state *state,
374 393
375 deb_info("Bandwidth %d Adc %d", bandwidth, adcFrequency); 394 deb_info("Bandwidth %d Adc %d", bandwidth, adcFrequency);
376 395
377 if (bandwidth == BANDWIDTH_5_MHZ) 396 switch (bandwidth) {
397 case 5000000:
378 bw = 3; 398 bw = 3;
379 else if (bandwidth == BANDWIDTH_6_MHZ) 399 break;
400 case 6000000:
380 bw = 0; 401 bw = 0;
381 else if (bandwidth == BANDWIDTH_7_MHZ) 402 break;
403 case 7000000:
382 bw = 1; 404 bw = 1;
383 else if (bandwidth == BANDWIDTH_8_MHZ) 405 break;
384 bw = 2; 406 default:
385 else 407 case 8000000:
386 bw = 2; 408 bw = 2;
387 409 break;
410 }
388 ret = it913x_write_reg(state, PRO_DMOD, REG_BW, bw); 411 ret = it913x_write_reg(state, PRO_DMOD, REG_BW, bw);
389 412
390 if (state->table == NULL) 413 if (state->table == NULL)
@@ -492,31 +515,79 @@ static int it913x_fe_read_signal_strength(struct dvb_frontend *fe,
492 return 0; 515 return 0;
493} 516}
494 517
495static int it913x_fe_read_snr(struct dvb_frontend *fe, u16* snr) 518static int it913x_fe_read_snr(struct dvb_frontend *fe, u16 *snr)
496{ 519{
497 struct it913x_fe_state *state = fe->demodulator_priv; 520 struct it913x_fe_state *state = fe->demodulator_priv;
498 int ret = it913x_read_reg_u8(state, SIGNAL_QUALITY); 521 int ret;
499 ret = (ret * 0xff) / 0x64; 522 u8 reg[3];
500 ret |= (ret << 0x8); 523 u32 snr_val, snr_min, snr_max;
501 *snr = ~ret; 524 u32 temp;
502 return 0; 525
526 ret = it913x_read_reg(state, 0x2c, reg, sizeof(reg));
527
528 snr_val = (u32)(reg[2] << 16) | (reg[1] << 8) | reg[0];
529
530 ret |= it913x_read_reg(state, 0xf78b, reg, 1);
531 if (reg[0])
532 snr_val /= reg[0];
533
534 if (state->transmission_mode == TRANSMISSION_MODE_2K)
535 snr_val *= 4;
536 else if (state->transmission_mode == TRANSMISSION_MODE_4K)
537 snr_val *= 2;
538
539 if (state->constellation == QPSK) {
540 snr_min = 0xb4711;
541 snr_max = 0x191451;
542 } else if (state->constellation == QAM_16) {
543 snr_min = 0x4f0d5;
544 snr_max = 0xc7925;
545 } else if (state->constellation == QAM_64) {
546 snr_min = 0x256d0;
547 snr_max = 0x626be;
548 } else
549 return -EINVAL;
550
551 if (snr_val < snr_min)
552 *snr = 0;
553 else if (snr_val < snr_max) {
554 temp = (snr_val - snr_min) >> 5;
555 temp *= 0xffff;
556 temp /= (snr_max - snr_min) >> 5;
557 *snr = (u16)temp;
558 } else
559 *snr = 0xffff;
560
561 return (ret < 0) ? -ENODEV : 0;
503} 562}
504 563
505static int it913x_fe_read_ber(struct dvb_frontend *fe, u32 *ber) 564static int it913x_fe_read_ber(struct dvb_frontend *fe, u32 *ber)
506{ 565{
507 *ber = 0; 566 struct it913x_fe_state *state = fe->demodulator_priv;
567 int ret;
568 u8 reg[5];
569 /* Read Aborted Packets and Pre-Viterbi error rate 5 bytes */
570 ret = it913x_read_reg(state, RSD_ABORT_PKT_LSB, reg, sizeof(reg));
571 state->ucblocks += (u32)(reg[1] << 8) | reg[0];
572 *ber = (u32)(reg[4] << 16) | (reg[3] << 8) | reg[2];
508 return 0; 573 return 0;
509} 574}
510 575
511static int it913x_fe_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 576static int it913x_fe_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
512{ 577{
513 *ucblocks = 0; 578 struct it913x_fe_state *state = fe->demodulator_priv;
514 return 0; 579 int ret;
580 u8 reg[2];
581 /* Aborted Packets */
582 ret = it913x_read_reg(state, RSD_ABORT_PKT_LSB, reg, sizeof(reg));
583 state->ucblocks += (u32)(reg[1] << 8) | reg[0];
584 *ucblocks = state->ucblocks;
585 return ret;
515} 586}
516 587
517static int it913x_fe_get_frontend(struct dvb_frontend *fe, 588static int it913x_fe_get_frontend(struct dvb_frontend *fe)
518 struct dvb_frontend_parameters *p)
519{ 589{
590 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
520 struct it913x_fe_state *state = fe->demodulator_priv; 591 struct it913x_fe_state *state = fe->demodulator_priv;
521 int ret; 592 int ret;
522 u8 reg[8]; 593 u8 reg[8];
@@ -524,26 +595,30 @@ static int it913x_fe_get_frontend(struct dvb_frontend *fe,
524 ret = it913x_read_reg(state, REG_TPSD_TX_MODE, reg, sizeof(reg)); 595 ret = it913x_read_reg(state, REG_TPSD_TX_MODE, reg, sizeof(reg));
525 596
526 if (reg[3] < 3) 597 if (reg[3] < 3)
527 p->u.ofdm.constellation = fe_con[reg[3]]; 598 p->modulation = fe_con[reg[3]];
528 599
529 if (reg[0] < 3) 600 if (reg[0] < 3)
530 p->u.ofdm.transmission_mode = fe_mode[reg[0]]; 601 p->transmission_mode = fe_mode[reg[0]];
531 602
532 if (reg[1] < 4) 603 if (reg[1] < 4)
533 p->u.ofdm.guard_interval = fe_gi[reg[1]]; 604 p->guard_interval = fe_gi[reg[1]];
534 605
535 if (reg[2] < 4) 606 if (reg[2] < 4)
536 p->u.ofdm.hierarchy_information = fe_hi[reg[2]]; 607 p->hierarchy = fe_hi[reg[2]];
608
609 p->code_rate_HP = (reg[6] < 6) ? fe_code[reg[6]] : FEC_NONE;
610 p->code_rate_LP = (reg[7] < 6) ? fe_code[reg[7]] : FEC_NONE;
537 611
538 p->u.ofdm.code_rate_HP = (reg[6] < 6) ? fe_code[reg[6]] : FEC_NONE; 612 /* Update internal state to reflect the autodetected props */
539 p->u.ofdm.code_rate_LP = (reg[7] < 6) ? fe_code[reg[7]] : FEC_NONE; 613 state->constellation = p->modulation;
614 state->transmission_mode = p->transmission_mode;
540 615
541 return 0; 616 return 0;
542} 617}
543 618
544static int it913x_fe_set_frontend(struct dvb_frontend *fe, 619static int it913x_fe_set_frontend(struct dvb_frontend *fe)
545 struct dvb_frontend_parameters *p)
546{ 620{
621 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
547 struct it913x_fe_state *state = fe->demodulator_priv; 622 struct it913x_fe_state *state = fe->demodulator_priv;
548 int ret, i; 623 int ret, i;
549 u8 empty_ch, last_ch; 624 u8 empty_ch, last_ch;
@@ -551,7 +626,7 @@ static int it913x_fe_set_frontend(struct dvb_frontend *fe,
551 state->it913x_status = 0; 626 state->it913x_status = 0;
552 627
553 /* Set bw*/ 628 /* Set bw*/
554 ret = it913x_fe_select_bw(state, p->u.ofdm.bandwidth, 629 ret = it913x_fe_select_bw(state, p->bandwidth_hz,
555 state->adcFrequency); 630 state->adcFrequency);
556 631
557 /* Training Mode Off */ 632 /* Training Mode Off */
@@ -571,20 +646,25 @@ static int it913x_fe_set_frontend(struct dvb_frontend *fe,
571 i = 1; 646 i = 1;
572 else if ((p->frequency >= 1450000000) && (p->frequency <= 1680000000)) 647 else if ((p->frequency >= 1450000000) && (p->frequency <= 1680000000))
573 i = 2; 648 i = 2;
574 else 649 else
575 return -EOPNOTSUPP; 650 return -EOPNOTSUPP;
576 651
577 ret = it913x_write_reg(state, PRO_DMOD, FREE_BAND, i); 652 ret = it913x_write_reg(state, PRO_DMOD, FREE_BAND, i);
578 653
579 deb_info("Frontend Set Tuner Type %02x", state->tuner_type); 654 deb_info("Frontend Set Tuner Type %02x", state->tuner_type);
580 switch (state->tuner_type) { 655 switch (state->tuner_type) {
581 case IT9137: /* Tuner type 0x38 */ 656 case IT9135_38:
657 case IT9135_51:
658 case IT9135_52:
659 case IT9135_60:
660 case IT9135_61:
661 case IT9135_62:
582 ret = it9137_set_tuner(state, 662 ret = it9137_set_tuner(state,
583 p->u.ofdm.bandwidth, p->frequency); 663 p->bandwidth_hz, p->frequency);
584 break; 664 break;
585 default: 665 default:
586 if (fe->ops.tuner_ops.set_params) { 666 if (fe->ops.tuner_ops.set_params) {
587 fe->ops.tuner_ops.set_params(fe, p); 667 fe->ops.tuner_ops.set_params(fe);
588 if (fe->ops.i2c_gate_ctrl) 668 if (fe->ops.i2c_gate_ctrl)
589 fe->ops.i2c_gate_ctrl(fe, 0); 669 fe->ops.i2c_gate_ctrl(fe, 0);
590 } 670 }
@@ -678,16 +758,19 @@ static u32 compute_div(u32 a, u32 b, u32 x)
678 758
679static int it913x_fe_start(struct it913x_fe_state *state) 759static int it913x_fe_start(struct it913x_fe_state *state)
680{ 760{
681 struct it913xset *set_fe; 761 struct it913xset *set_lna;
682 struct it913xset *set_mode; 762 struct it913xset *set_mode;
683 int ret; 763 int ret;
684 u8 adf = (state->adf & 0xf); 764 u8 adf = (state->config->adf & 0xf);
685 u32 adc, xtal; 765 u32 adc, xtal;
686 u8 b[4]; 766 u8 b[4];
687 767
688 ret = it913x_init_tuner(state); 768 if (state->config->chip_ver == 1)
769 ret = it913x_init_tuner(state);
770
771 info("ADF table value :%02x", adf);
689 772
690 if (adf < 12) { 773 if (adf < 10) {
691 state->crystalFrequency = fe_clockTable[adf].xtal ; 774 state->crystalFrequency = fe_clockTable[adf].xtal ;
692 state->table = fe_clockTable[adf].table; 775 state->table = fe_clockTable[adf].table;
693 state->adcFrequency = state->table->adcFrequency; 776 state->adcFrequency = state->table->adcFrequency;
@@ -698,9 +781,6 @@ static int it913x_fe_start(struct it913x_fe_state *state)
698 } else 781 } else
699 return -EINVAL; 782 return -EINVAL;
700 783
701 deb_info("Xtal Freq :%d Adc Freq :%d Adc %08x Xtal %08x",
702 state->crystalFrequency, state->adcFrequency, adc, xtal);
703
704 /* Set LED indicator on GPIOH3 */ 784 /* Set LED indicator on GPIOH3 */
705 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_EN, 0x1); 785 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_EN, 0x1);
706 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_ON, 0x1); 786 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_ON, 0x1);
@@ -721,22 +801,71 @@ static int it913x_fe_start(struct it913x_fe_state *state)
721 b[2] = (adc >> 16) & 0xff; 801 b[2] = (adc >> 16) & 0xff;
722 ret |= it913x_write(state, PRO_DMOD, ADC_FREQ, b, 3); 802 ret |= it913x_write(state, PRO_DMOD, ADC_FREQ, b, 3);
723 803
804 if (state->config->adc_x2)
805 ret |= it913x_write_reg(state, PRO_DMOD, ADC_X_2, 0x01);
806 b[0] = 0;
807 b[1] = 0;
808 b[2] = 0;
809 ret |= it913x_write(state, PRO_DMOD, 0x0029, b, 3);
810
811 info("Crystal Frequency :%d Adc Frequency :%d ADC X2: %02x",
812 state->crystalFrequency, state->adcFrequency,
813 state->config->adc_x2);
814 deb_info("Xtal value :%04x Adc value :%04x", xtal, adc);
815
816 if (ret < 0)
817 return -ENODEV;
818
819 /* v1 or v2 tuner script */
820 if (state->config->chip_ver > 1)
821 ret = it913x_fe_script_loader(state, it9135_v2);
822 else
823 ret = it913x_fe_script_loader(state, it9135_v1);
824 if (ret < 0)
825 return ret;
826
827 /* LNA Scripts */
724 switch (state->tuner_type) { 828 switch (state->tuner_type) {
725 case IT9137: /* Tuner type 0x38 */ 829 case IT9135_51:
726 set_fe = it9137_set; 830 set_lna = it9135_51;
831 break;
832 case IT9135_52:
833 set_lna = it9135_52;
834 break;
835 case IT9135_60:
836 set_lna = it9135_60;
837 break;
838 case IT9135_61:
839 set_lna = it9135_61;
727 break; 840 break;
841 case IT9135_62:
842 set_lna = it9135_62;
843 break;
844 case IT9135_38:
728 default: 845 default:
729 return -EINVAL; 846 set_lna = it9135_38;
730 } 847 }
848 info("Tuner LNA type :%02x", state->tuner_type);
849
850 ret = it913x_fe_script_loader(state, set_lna);
851 if (ret < 0)
852 return ret;
853
854 if (state->config->chip_ver == 2) {
855 ret = it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x1);
856 ret |= it913x_write_reg(state, PRO_LINK, PADODPU, 0x0);
857 ret |= it913x_write_reg(state, PRO_LINK, AGC_O_D, 0x0);
858 ret |= it913x_init_tuner(state);
859 }
860 if (ret < 0)
861 return -ENODEV;
731 862
732 /* set the demod */
733 ret = it913x_fe_script_loader(state, set_fe);
734 /* Always solo frontend */ 863 /* Always solo frontend */
735 set_mode = set_solo_fe; 864 set_mode = set_solo_fe;
736 ret |= it913x_fe_script_loader(state, set_mode); 865 ret |= it913x_fe_script_loader(state, set_mode);
737 866
738 ret |= it913x_fe_suspend(state); 867 ret |= it913x_fe_suspend(state);
739 return 0; 868 return (ret < 0) ? -ENODEV : 0;
740} 869}
741 870
742static int it913x_fe_init(struct dvb_frontend *fe) 871static int it913x_fe_init(struct dvb_frontend *fe)
@@ -746,17 +875,11 @@ static int it913x_fe_init(struct dvb_frontend *fe)
746 /* Power Up Tuner - common all versions */ 875 /* Power Up Tuner - common all versions */
747 ret = it913x_write_reg(state, PRO_DMOD, 0xec40, 0x1); 876 ret = it913x_write_reg(state, PRO_DMOD, 0xec40, 0x1);
748 877
749 ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x0);
750
751 ret |= it913x_fe_script_loader(state, init_1); 878 ret |= it913x_fe_script_loader(state, init_1);
752 879
753 switch (state->tuner_type) { 880 ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x0);
754 case IT9137: 881
755 ret |= it913x_write_reg(state, PRO_DMOD, 0xfba8, 0x0); 882 ret |= it913x_write_reg(state, PRO_DMOD, 0xfba8, 0x0);
756 break;
757 default:
758 return -EINVAL;
759 }
760 883
761 return (ret < 0) ? -ENODEV : 0; 884 return (ret < 0) ? -ENODEV : 0;
762} 885}
@@ -770,19 +893,34 @@ static void it913x_fe_release(struct dvb_frontend *fe)
770static struct dvb_frontend_ops it913x_fe_ofdm_ops; 893static struct dvb_frontend_ops it913x_fe_ofdm_ops;
771 894
772struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap, 895struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap,
773 u8 i2c_addr, u8 adf, u8 type) 896 u8 i2c_addr, struct ite_config *config)
774{ 897{
775 struct it913x_fe_state *state = NULL; 898 struct it913x_fe_state *state = NULL;
776 int ret; 899 int ret;
900
777 /* allocate memory for the internal state */ 901 /* allocate memory for the internal state */
778 state = kzalloc(sizeof(struct it913x_fe_state), GFP_KERNEL); 902 state = kzalloc(sizeof(struct it913x_fe_state), GFP_KERNEL);
779 if (state == NULL) 903 if (state == NULL)
904 return NULL;
905 if (config == NULL)
780 goto error; 906 goto error;
781 907
782 state->i2c_adap = i2c_adap; 908 state->i2c_adap = i2c_adap;
783 state->i2c_addr = i2c_addr; 909 state->i2c_addr = i2c_addr;
784 state->adf = adf; 910 state->config = config;
785 state->tuner_type = type; 911
912 switch (state->config->tuner_id_0) {
913 case IT9135_51:
914 case IT9135_52:
915 case IT9135_60:
916 case IT9135_61:
917 case IT9135_62:
918 state->tuner_type = state->config->tuner_id_0;
919 break;
920 default:
921 case IT9135_38:
922 state->tuner_type = IT9135_38;
923 }
786 924
787 ret = it913x_fe_start(state); 925 ret = it913x_fe_start(state);
788 if (ret < 0) 926 if (ret < 0)
@@ -802,10 +940,9 @@ error:
802EXPORT_SYMBOL(it913x_fe_attach); 940EXPORT_SYMBOL(it913x_fe_attach);
803 941
804static struct dvb_frontend_ops it913x_fe_ofdm_ops = { 942static struct dvb_frontend_ops it913x_fe_ofdm_ops = {
805 943 .delsys = { SYS_DVBT },
806 .info = { 944 .info = {
807 .name = "it913x-fe DVB-T", 945 .name = "it913x-fe DVB-T",
808 .type = FE_OFDM,
809 .frequency_min = 51000000, 946 .frequency_min = 51000000,
810 .frequency_max = 1680000000, 947 .frequency_max = 1680000000,
811 .frequency_stepsize = 62500, 948 .frequency_stepsize = 62500,
@@ -835,5 +972,5 @@ static struct dvb_frontend_ops it913x_fe_ofdm_ops = {
835 972
836MODULE_DESCRIPTION("it913x Frontend and it9137 tuner"); 973MODULE_DESCRIPTION("it913x Frontend and it9137 tuner");
837MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com"); 974MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
838MODULE_VERSION("1.07"); 975MODULE_VERSION("1.13");
839MODULE_LICENSE("GPL"); 976MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/it913x-fe.h b/drivers/media/dvb/frontends/it913x-fe.h
index 9d97f32e690b..c4a908e354e0 100644
--- a/drivers/media/dvb/frontends/it913x-fe.h
+++ b/drivers/media/dvb/frontends/it913x-fe.h
@@ -23,13 +23,27 @@
23 23
24#include <linux/dvb/frontend.h> 24#include <linux/dvb/frontend.h>
25#include "dvb_frontend.h" 25#include "dvb_frontend.h"
26
27struct ite_config {
28 u8 chip_ver;
29 u16 chip_type;
30 u32 firmware;
31 u8 firmware_ver;
32 u8 adc_x2;
33 u8 tuner_id_0;
34 u8 tuner_id_1;
35 u8 dual_mode;
36 u8 adf;
37};
38
26#if defined(CONFIG_DVB_IT913X_FE) || (defined(CONFIG_DVB_IT913X_FE_MODULE) && \ 39#if defined(CONFIG_DVB_IT913X_FE) || (defined(CONFIG_DVB_IT913X_FE_MODULE) && \
27defined(MODULE)) 40defined(MODULE))
28extern struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap, 41extern struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap,
29 u8 i2c_addr, u8 adf, u8 type); 42 u8 i2c_addr, struct ite_config *config);
30#else 43#else
31static inline struct dvb_frontend *it913x_fe_attach( 44static inline struct dvb_frontend *it913x_fe_attach(
32 struct i2c_adapter *i2c_adap, u8 i2c_addr, u8 adf, u8 type) 45 struct i2c_adapter *i2c_adap,
46 u8 i2c_addr, struct ite_config *config)
33{ 47{
34 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 48 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
35 return NULL; 49 return NULL;
@@ -134,6 +148,16 @@ static inline struct dvb_frontend *it913x_fe_attach(
134#define COEFF_1_2048 0x0001 148#define COEFF_1_2048 0x0001
135#define XTAL_CLK 0x0025 149#define XTAL_CLK 0x0025
136#define BFS_FCW 0x0029 150#define BFS_FCW 0x0029
151
152/* Error Regs */
153#define RSD_ABORT_PKT_LSB 0x0032
154#define RSD_ABORT_PKT_MSB 0x0033
155#define RSD_BIT_ERR_0_7 0x0034
156#define RSD_BIT_ERR_8_15 0x0035
157#define RSD_BIT_ERR_23_16 0x0036
158#define RSD_BIT_COUNT_LSB 0x0037
159#define RSD_BIT_COUNT_MSB 0x0038
160
137#define TPSD_LOCK 0x003c 161#define TPSD_LOCK 0x003c
138#define TRAINING_MODE 0x0040 162#define TRAINING_MODE 0x0040
139#define ADC_X_2 0x0045 163#define ADC_X_2 0x0045
@@ -144,8 +168,14 @@ static inline struct dvb_frontend *it913x_fe_attach(
144#define EST_SIGNAL_LEVEL 0x004a 168#define EST_SIGNAL_LEVEL 0x004a
145#define FREE_BAND 0x004b 169#define FREE_BAND 0x004b
146#define SUSPEND_FLAG 0x004c 170#define SUSPEND_FLAG 0x004c
147/* Build in tuners */ 171/* Build in tuner types */
148#define IT9137 0x38 172#define IT9137 0x38
173#define IT9135_38 0x38
174#define IT9135_51 0x51
175#define IT9135_52 0x52
176#define IT9135_60 0x60
177#define IT9135_61 0x61
178#define IT9135_62 0x62
149 179
150enum { 180enum {
151 CMD_DEMOD_READ = 0, 181 CMD_DEMOD_READ = 0,
@@ -193,4 +223,11 @@ enum {
193 WRITE_CMD, 223 WRITE_CMD,
194}; 224};
195 225
226enum {
227 IT9135_AUTO = 0,
228 IT9137_FW,
229 IT9135_V1_FW,
230 IT9135_V2_FW,
231};
232
196#endif /* IT913X_FE_H */ 233#endif /* IT913X_FE_H */
diff --git a/drivers/media/dvb/frontends/itd1000.c b/drivers/media/dvb/frontends/itd1000.c
index aa9ccb821fa5..316457584fe7 100644
--- a/drivers/media/dvb/frontends/itd1000.c
+++ b/drivers/media/dvb/frontends/itd1000.c
@@ -250,13 +250,14 @@ static void itd1000_set_lo(struct itd1000_state *state, u32 freq_khz)
250 itd1000_set_vco(state, freq_khz); 250 itd1000_set_vco(state, freq_khz);
251} 251}
252 252
253static int itd1000_set_parameters(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) 253static int itd1000_set_parameters(struct dvb_frontend *fe)
254{ 254{
255 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
255 struct itd1000_state *state = fe->tuner_priv; 256 struct itd1000_state *state = fe->tuner_priv;
256 u8 pllcon1; 257 u8 pllcon1;
257 258
258 itd1000_set_lo(state, p->frequency); 259 itd1000_set_lo(state, c->frequency);
259 itd1000_set_lpf_bw(state, p->u.qpsk.symbol_rate); 260 itd1000_set_lpf_bw(state, c->symbol_rate);
260 261
261 pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f; 262 pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f;
262 itd1000_write_reg(state, PLLCON1, pllcon1 | (1 << 7)); 263 itd1000_write_reg(state, PLLCON1, pllcon1 | (1 << 7));
diff --git a/drivers/media/dvb/frontends/ix2505v.c b/drivers/media/dvb/frontends/ix2505v.c
index 9a517a4bf96d..bc5a82082aaa 100644
--- a/drivers/media/dvb/frontends/ix2505v.c
+++ b/drivers/media/dvb/frontends/ix2505v.c
@@ -129,12 +129,12 @@ static int ix2505v_release(struct dvb_frontend *fe)
129 * 1 -> 8 -> 6 129 * 1 -> 8 -> 6
130 */ 130 */
131 131
132static int ix2505v_set_params(struct dvb_frontend *fe, 132static int ix2505v_set_params(struct dvb_frontend *fe)
133 struct dvb_frontend_parameters *params)
134{ 133{
134 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
135 struct ix2505v_state *state = fe->tuner_priv; 135 struct ix2505v_state *state = fe->tuner_priv;
136 u32 frequency = params->frequency; 136 u32 frequency = c->frequency;
137 u32 b_w = (params->u.qpsk.symbol_rate * 27) / 32000; 137 u32 b_w = (c->symbol_rate * 27) / 32000;
138 u32 div_factor, N , A, x; 138 u32 div_factor, N , A, x;
139 int ret = 0, len; 139 int ret = 0, len;
140 u8 gain, cc, ref, psc, local_osc, lpf; 140 u8 gain, cc, ref, psc, local_osc, lpf;
diff --git a/drivers/media/dvb/frontends/l64781.c b/drivers/media/dvb/frontends/l64781.c
index 445fa1068064..36fcf559e361 100644
--- a/drivers/media/dvb/frontends/l64781.c
+++ b/drivers/media/dvb/frontends/l64781.c
@@ -117,18 +117,17 @@ static int reset_and_configure (struct l64781_state* state)
117 return (i2c_transfer(state->i2c, &msg, 1) == 1) ? 0 : -ENODEV; 117 return (i2c_transfer(state->i2c, &msg, 1) == 1) ? 0 : -ENODEV;
118} 118}
119 119
120static int apply_frontend_param (struct dvb_frontend* fe, struct dvb_frontend_parameters *param) 120static int apply_frontend_param(struct dvb_frontend *fe)
121{ 121{
122 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
122 struct l64781_state* state = fe->demodulator_priv; 123 struct l64781_state* state = fe->demodulator_priv;
123 /* The coderates for FEC_NONE, FEC_4_5 and FEC_FEC_6_7 are arbitrary */ 124 /* The coderates for FEC_NONE, FEC_4_5 and FEC_FEC_6_7 are arbitrary */
124 static const u8 fec_tab[] = { 7, 0, 1, 2, 9, 3, 10, 4 }; 125 static const u8 fec_tab[] = { 7, 0, 1, 2, 9, 3, 10, 4 };
125 /* QPSK, QAM_16, QAM_64 */ 126 /* QPSK, QAM_16, QAM_64 */
126 static const u8 qam_tab [] = { 2, 4, 0, 6 }; 127 static const u8 qam_tab [] = { 2, 4, 0, 6 };
127 static const u8 bw_tab [] = { 8, 7, 6 }; /* 8Mhz, 7MHz, 6MHz */
128 static const u8 guard_tab [] = { 1, 2, 4, 8 }; 128 static const u8 guard_tab [] = { 1, 2, 4, 8 };
129 /* The Grundig 29504-401.04 Tuner comes with 18.432MHz crystal. */ 129 /* The Grundig 29504-401.04 Tuner comes with 18.432MHz crystal. */
130 static const u32 ppm = 8000; 130 static const u32 ppm = 8000;
131 struct dvb_ofdm_parameters *p = &param->u.ofdm;
132 u32 ddfs_offset_fixed; 131 u32 ddfs_offset_fixed;
133/* u32 ddfs_offset_variable = 0x6000-((1000000UL+ppm)/ */ 132/* u32 ddfs_offset_variable = 0x6000-((1000000UL+ppm)/ */
134/* bw_tab[p->bandWidth]<<10)/15625; */ 133/* bw_tab[p->bandWidth]<<10)/15625; */
@@ -137,18 +136,29 @@ static int apply_frontend_param (struct dvb_frontend* fe, struct dvb_frontend_pa
137 u8 val0x04; 136 u8 val0x04;
138 u8 val0x05; 137 u8 val0x05;
139 u8 val0x06; 138 u8 val0x06;
140 int bw = p->bandwidth - BANDWIDTH_8_MHZ; 139 int bw;
140
141 switch (p->bandwidth_hz) {
142 case 8000000:
143 bw = 8;
144 break;
145 case 7000000:
146 bw = 7;
147 break;
148 case 6000000:
149 bw = 6;
150 break;
151 default:
152 return -EINVAL;
153 }
141 154
142 if (fe->ops.tuner_ops.set_params) { 155 if (fe->ops.tuner_ops.set_params) {
143 fe->ops.tuner_ops.set_params(fe, param); 156 fe->ops.tuner_ops.set_params(fe);
144 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 157 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
145 } 158 }
146 159
147 if (param->inversion != INVERSION_ON && 160 if (p->inversion != INVERSION_ON &&
148 param->inversion != INVERSION_OFF) 161 p->inversion != INVERSION_OFF)
149 return -EINVAL;
150
151 if (bw < 0 || bw > 2)
152 return -EINVAL; 162 return -EINVAL;
153 163
154 if (p->code_rate_HP != FEC_1_2 && p->code_rate_HP != FEC_2_3 && 164 if (p->code_rate_HP != FEC_1_2 && p->code_rate_HP != FEC_2_3 &&
@@ -156,14 +166,14 @@ static int apply_frontend_param (struct dvb_frontend* fe, struct dvb_frontend_pa
156 p->code_rate_HP != FEC_7_8) 166 p->code_rate_HP != FEC_7_8)
157 return -EINVAL; 167 return -EINVAL;
158 168
159 if (p->hierarchy_information != HIERARCHY_NONE && 169 if (p->hierarchy != HIERARCHY_NONE &&
160 (p->code_rate_LP != FEC_1_2 && p->code_rate_LP != FEC_2_3 && 170 (p->code_rate_LP != FEC_1_2 && p->code_rate_LP != FEC_2_3 &&
161 p->code_rate_LP != FEC_3_4 && p->code_rate_LP != FEC_5_6 && 171 p->code_rate_LP != FEC_3_4 && p->code_rate_LP != FEC_5_6 &&
162 p->code_rate_LP != FEC_7_8)) 172 p->code_rate_LP != FEC_7_8))
163 return -EINVAL; 173 return -EINVAL;
164 174
165 if (p->constellation != QPSK && p->constellation != QAM_16 && 175 if (p->modulation != QPSK && p->modulation != QAM_16 &&
166 p->constellation != QAM_64) 176 p->modulation != QAM_64)
167 return -EINVAL; 177 return -EINVAL;
168 178
169 if (p->transmission_mode != TRANSMISSION_MODE_2K && 179 if (p->transmission_mode != TRANSMISSION_MODE_2K &&
@@ -174,22 +184,22 @@ static int apply_frontend_param (struct dvb_frontend* fe, struct dvb_frontend_pa
174 p->guard_interval > GUARD_INTERVAL_1_4) 184 p->guard_interval > GUARD_INTERVAL_1_4)
175 return -EINVAL; 185 return -EINVAL;
176 186
177 if (p->hierarchy_information < HIERARCHY_NONE || 187 if (p->hierarchy < HIERARCHY_NONE ||
178 p->hierarchy_information > HIERARCHY_4) 188 p->hierarchy > HIERARCHY_4)
179 return -EINVAL; 189 return -EINVAL;
180 190
181 ddfs_offset_fixed = 0x4000-(ppm<<16)/bw_tab[p->bandwidth]/1000000; 191 ddfs_offset_fixed = 0x4000-(ppm<<16)/bw/1000000;
182 192
183 /* This works up to 20000 ppm, it overflows if too large ppm! */ 193 /* This works up to 20000 ppm, it overflows if too large ppm! */
184 init_freq = (((8UL<<25) + (8UL<<19) / 25*ppm / (15625/25)) / 194 init_freq = (((8UL<<25) + (8UL<<19) / 25*ppm / (15625/25)) /
185 bw_tab[p->bandwidth] & 0xFFFFFF); 195 bw & 0xFFFFFF);
186 196
187 /* SPI bias calculation is slightly modified to fit in 32bit */ 197 /* SPI bias calculation is slightly modified to fit in 32bit */
188 /* will work for high ppm only... */ 198 /* will work for high ppm only... */
189 spi_bias = 378 * (1 << 10); 199 spi_bias = 378 * (1 << 10);
190 spi_bias *= 16; 200 spi_bias *= 16;
191 spi_bias *= bw_tab[p->bandwidth]; 201 spi_bias *= bw;
192 spi_bias *= qam_tab[p->constellation]; 202 spi_bias *= qam_tab[p->modulation];
193 spi_bias /= p->code_rate_HP + 1; 203 spi_bias /= p->code_rate_HP + 1;
194 spi_bias /= (guard_tab[p->guard_interval] + 32); 204 spi_bias /= (guard_tab[p->guard_interval] + 32);
195 spi_bias *= 1000; 205 spi_bias *= 1000;
@@ -199,10 +209,10 @@ static int apply_frontend_param (struct dvb_frontend* fe, struct dvb_frontend_pa
199 val0x04 = (p->transmission_mode << 2) | p->guard_interval; 209 val0x04 = (p->transmission_mode << 2) | p->guard_interval;
200 val0x05 = fec_tab[p->code_rate_HP]; 210 val0x05 = fec_tab[p->code_rate_HP];
201 211
202 if (p->hierarchy_information != HIERARCHY_NONE) 212 if (p->hierarchy != HIERARCHY_NONE)
203 val0x05 |= (p->code_rate_LP - FEC_1_2) << 3; 213 val0x05 |= (p->code_rate_LP - FEC_1_2) << 3;
204 214
205 val0x06 = (p->hierarchy_information << 2) | p->constellation; 215 val0x06 = (p->hierarchy << 2) | p->modulation;
206 216
207 l64781_writereg (state, 0x04, val0x04); 217 l64781_writereg (state, 0x04, val0x04);
208 l64781_writereg (state, 0x05, val0x05); 218 l64781_writereg (state, 0x05, val0x05);
@@ -220,7 +230,7 @@ static int apply_frontend_param (struct dvb_frontend* fe, struct dvb_frontend_pa
220 l64781_writereg (state, 0x1b, spi_bias & 0xff); 230 l64781_writereg (state, 0x1b, spi_bias & 0xff);
221 l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff); 231 l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff);
222 l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) | 232 l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) |
223 (param->inversion == INVERSION_ON ? 0x80 : 0x00)); 233 (p->inversion == INVERSION_ON ? 0x80 : 0x00));
224 234
225 l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff); 235 l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff);
226 l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f); 236 l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f);
@@ -233,8 +243,9 @@ static int apply_frontend_param (struct dvb_frontend* fe, struct dvb_frontend_pa
233 return 0; 243 return 0;
234} 244}
235 245
236static int get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters* param) 246static int get_frontend(struct dvb_frontend *fe)
237{ 247{
248 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
238 struct l64781_state* state = fe->demodulator_priv; 249 struct l64781_state* state = fe->demodulator_priv;
239 int tmp; 250 int tmp;
240 251
@@ -242,98 +253,95 @@ static int get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters*
242 tmp = l64781_readreg(state, 0x04); 253 tmp = l64781_readreg(state, 0x04);
243 switch(tmp & 3) { 254 switch(tmp & 3) {
244 case 0: 255 case 0:
245 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; 256 p->guard_interval = GUARD_INTERVAL_1_32;
246 break; 257 break;
247 case 1: 258 case 1:
248 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; 259 p->guard_interval = GUARD_INTERVAL_1_16;
249 break; 260 break;
250 case 2: 261 case 2:
251 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; 262 p->guard_interval = GUARD_INTERVAL_1_8;
252 break; 263 break;
253 case 3: 264 case 3:
254 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; 265 p->guard_interval = GUARD_INTERVAL_1_4;
255 break; 266 break;
256 } 267 }
257 switch((tmp >> 2) & 3) { 268 switch((tmp >> 2) & 3) {
258 case 0: 269 case 0:
259 param->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; 270 p->transmission_mode = TRANSMISSION_MODE_2K;
260 break; 271 break;
261 case 1: 272 case 1:
262 param->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; 273 p->transmission_mode = TRANSMISSION_MODE_8K;
263 break; 274 break;
264 default: 275 default:
265 printk("Unexpected value for transmission_mode\n"); 276 printk(KERN_WARNING "Unexpected value for transmission_mode\n");
266 } 277 }
267 278
268
269
270 tmp = l64781_readreg(state, 0x05); 279 tmp = l64781_readreg(state, 0x05);
271 switch(tmp & 7) { 280 switch(tmp & 7) {
272 case 0: 281 case 0:
273 param->u.ofdm.code_rate_HP = FEC_1_2; 282 p->code_rate_HP = FEC_1_2;
274 break; 283 break;
275 case 1: 284 case 1:
276 param->u.ofdm.code_rate_HP = FEC_2_3; 285 p->code_rate_HP = FEC_2_3;
277 break; 286 break;
278 case 2: 287 case 2:
279 param->u.ofdm.code_rate_HP = FEC_3_4; 288 p->code_rate_HP = FEC_3_4;
280 break; 289 break;
281 case 3: 290 case 3:
282 param->u.ofdm.code_rate_HP = FEC_5_6; 291 p->code_rate_HP = FEC_5_6;
283 break; 292 break;
284 case 4: 293 case 4:
285 param->u.ofdm.code_rate_HP = FEC_7_8; 294 p->code_rate_HP = FEC_7_8;
286 break; 295 break;
287 default: 296 default:
288 printk("Unexpected value for code_rate_HP\n"); 297 printk("Unexpected value for code_rate_HP\n");
289 } 298 }
290 switch((tmp >> 3) & 7) { 299 switch((tmp >> 3) & 7) {
291 case 0: 300 case 0:
292 param->u.ofdm.code_rate_LP = FEC_1_2; 301 p->code_rate_LP = FEC_1_2;
293 break; 302 break;
294 case 1: 303 case 1:
295 param->u.ofdm.code_rate_LP = FEC_2_3; 304 p->code_rate_LP = FEC_2_3;
296 break; 305 break;
297 case 2: 306 case 2:
298 param->u.ofdm.code_rate_LP = FEC_3_4; 307 p->code_rate_LP = FEC_3_4;
299 break; 308 break;
300 case 3: 309 case 3:
301 param->u.ofdm.code_rate_LP = FEC_5_6; 310 p->code_rate_LP = FEC_5_6;
302 break; 311 break;
303 case 4: 312 case 4:
304 param->u.ofdm.code_rate_LP = FEC_7_8; 313 p->code_rate_LP = FEC_7_8;
305 break; 314 break;
306 default: 315 default:
307 printk("Unexpected value for code_rate_LP\n"); 316 printk("Unexpected value for code_rate_LP\n");
308 } 317 }
309 318
310
311 tmp = l64781_readreg(state, 0x06); 319 tmp = l64781_readreg(state, 0x06);
312 switch(tmp & 3) { 320 switch(tmp & 3) {
313 case 0: 321 case 0:
314 param->u.ofdm.constellation = QPSK; 322 p->modulation = QPSK;
315 break; 323 break;
316 case 1: 324 case 1:
317 param->u.ofdm.constellation = QAM_16; 325 p->modulation = QAM_16;
318 break; 326 break;
319 case 2: 327 case 2:
320 param->u.ofdm.constellation = QAM_64; 328 p->modulation = QAM_64;
321 break; 329 break;
322 default: 330 default:
323 printk("Unexpected value for constellation\n"); 331 printk(KERN_WARNING "Unexpected value for modulation\n");
324 } 332 }
325 switch((tmp >> 2) & 7) { 333 switch((tmp >> 2) & 7) {
326 case 0: 334 case 0:
327 param->u.ofdm.hierarchy_information = HIERARCHY_NONE; 335 p->hierarchy = HIERARCHY_NONE;
328 break; 336 break;
329 case 1: 337 case 1:
330 param->u.ofdm.hierarchy_information = HIERARCHY_1; 338 p->hierarchy = HIERARCHY_1;
331 break; 339 break;
332 case 2: 340 case 2:
333 param->u.ofdm.hierarchy_information = HIERARCHY_2; 341 p->hierarchy = HIERARCHY_2;
334 break; 342 break;
335 case 3: 343 case 3:
336 param->u.ofdm.hierarchy_information = HIERARCHY_4; 344 p->hierarchy = HIERARCHY_4;
337 break; 345 break;
338 default: 346 default:
339 printk("Unexpected value for hierarchy\n"); 347 printk("Unexpected value for hierarchy\n");
@@ -341,12 +349,12 @@ static int get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters*
341 349
342 350
343 tmp = l64781_readreg (state, 0x1d); 351 tmp = l64781_readreg (state, 0x1d);
344 param->inversion = (tmp & 0x80) ? INVERSION_ON : INVERSION_OFF; 352 p->inversion = (tmp & 0x80) ? INVERSION_ON : INVERSION_OFF;
345 353
346 tmp = (int) (l64781_readreg (state, 0x08) | 354 tmp = (int) (l64781_readreg (state, 0x08) |
347 (l64781_readreg (state, 0x09) << 8) | 355 (l64781_readreg (state, 0x09) << 8) |
348 (l64781_readreg (state, 0x0a) << 16)); 356 (l64781_readreg (state, 0x0a) << 16));
349 param->frequency += tmp; 357 p->frequency += tmp;
350 358
351 return 0; 359 return 0;
352} 360}
@@ -564,10 +572,9 @@ error:
564} 572}
565 573
566static struct dvb_frontend_ops l64781_ops = { 574static struct dvb_frontend_ops l64781_ops = {
567 575 .delsys = { SYS_DVBT },
568 .info = { 576 .info = {
569 .name = "LSI L64781 DVB-T", 577 .name = "LSI L64781 DVB-T",
570 .type = FE_OFDM,
571 /* .frequency_min = ???,*/ 578 /* .frequency_min = ???,*/
572 /* .frequency_max = ???,*/ 579 /* .frequency_max = ???,*/
573 .frequency_stepsize = 166666, 580 .frequency_stepsize = 166666,
diff --git a/drivers/media/dvb/frontends/lgdt3305.c b/drivers/media/dvb/frontends/lgdt3305.c
index 3272881cb112..1d2c47378cf8 100644
--- a/drivers/media/dvb/frontends/lgdt3305.c
+++ b/drivers/media/dvb/frontends/lgdt3305.c
@@ -266,7 +266,7 @@ fail:
266} 266}
267 267
268static int lgdt3305_set_modulation(struct lgdt3305_state *state, 268static int lgdt3305_set_modulation(struct lgdt3305_state *state,
269 struct dvb_frontend_parameters *param) 269 struct dtv_frontend_properties *p)
270{ 270{
271 u8 opermode; 271 u8 opermode;
272 int ret; 272 int ret;
@@ -279,7 +279,7 @@ static int lgdt3305_set_modulation(struct lgdt3305_state *state,
279 279
280 opermode &= ~0x03; 280 opermode &= ~0x03;
281 281
282 switch (param->u.vsb.modulation) { 282 switch (p->modulation) {
283 case VSB_8: 283 case VSB_8:
284 opermode |= 0x03; 284 opermode |= 0x03;
285 break; 285 break;
@@ -298,11 +298,11 @@ fail:
298} 298}
299 299
300static int lgdt3305_set_filter_extension(struct lgdt3305_state *state, 300static int lgdt3305_set_filter_extension(struct lgdt3305_state *state,
301 struct dvb_frontend_parameters *param) 301 struct dtv_frontend_properties *p)
302{ 302{
303 int val; 303 int val;
304 304
305 switch (param->u.vsb.modulation) { 305 switch (p->modulation) {
306 case VSB_8: 306 case VSB_8:
307 val = 0; 307 val = 0;
308 break; 308 break;
@@ -321,11 +321,11 @@ static int lgdt3305_set_filter_extension(struct lgdt3305_state *state,
321/* ------------------------------------------------------------------------ */ 321/* ------------------------------------------------------------------------ */
322 322
323static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state, 323static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state,
324 struct dvb_frontend_parameters *param) 324 struct dtv_frontend_properties *p)
325{ 325{
326 u16 agc_ref; 326 u16 agc_ref;
327 327
328 switch (param->u.vsb.modulation) { 328 switch (p->modulation) {
329 case VSB_8: 329 case VSB_8:
330 agc_ref = 0x32c4; 330 agc_ref = 0x32c4;
331 break; 331 break;
@@ -348,11 +348,11 @@ static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state,
348} 348}
349 349
350static int lgdt3305_rfagc_loop(struct lgdt3305_state *state, 350static int lgdt3305_rfagc_loop(struct lgdt3305_state *state,
351 struct dvb_frontend_parameters *param) 351 struct dtv_frontend_properties *p)
352{ 352{
353 u16 ifbw, rfbw, agcdelay; 353 u16 ifbw, rfbw, agcdelay;
354 354
355 switch (param->u.vsb.modulation) { 355 switch (p->modulation) {
356 case VSB_8: 356 case VSB_8:
357 agcdelay = 0x04c0; 357 agcdelay = 0x04c0;
358 rfbw = 0x8000; 358 rfbw = 0x8000;
@@ -398,11 +398,11 @@ static int lgdt3305_rfagc_loop(struct lgdt3305_state *state,
398} 398}
399 399
400static int lgdt3305_agc_setup(struct lgdt3305_state *state, 400static int lgdt3305_agc_setup(struct lgdt3305_state *state,
401 struct dvb_frontend_parameters *param) 401 struct dtv_frontend_properties *p)
402{ 402{
403 int lockdten, acqen; 403 int lockdten, acqen;
404 404
405 switch (param->u.vsb.modulation) { 405 switch (p->modulation) {
406 case VSB_8: 406 case VSB_8:
407 lockdten = 0; 407 lockdten = 0;
408 acqen = 0; 408 acqen = 0;
@@ -432,15 +432,15 @@ static int lgdt3305_agc_setup(struct lgdt3305_state *state,
432 return -EINVAL; 432 return -EINVAL;
433 } 433 }
434 434
435 return lgdt3305_rfagc_loop(state, param); 435 return lgdt3305_rfagc_loop(state, p);
436} 436}
437 437
438static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state, 438static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state,
439 struct dvb_frontend_parameters *param) 439 struct dtv_frontend_properties *p)
440{ 440{
441 u16 usref = 0; 441 u16 usref = 0;
442 442
443 switch (param->u.vsb.modulation) { 443 switch (p->modulation) {
444 case VSB_8: 444 case VSB_8:
445 if (state->cfg->usref_8vsb) 445 if (state->cfg->usref_8vsb)
446 usref = state->cfg->usref_8vsb; 446 usref = state->cfg->usref_8vsb;
@@ -473,14 +473,14 @@ static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state,
473/* ------------------------------------------------------------------------ */ 473/* ------------------------------------------------------------------------ */
474 474
475static int lgdt3305_spectral_inversion(struct lgdt3305_state *state, 475static int lgdt3305_spectral_inversion(struct lgdt3305_state *state,
476 struct dvb_frontend_parameters *param, 476 struct dtv_frontend_properties *p,
477 int inversion) 477 int inversion)
478{ 478{
479 int ret; 479 int ret;
480 480
481 lg_dbg("(%d)\n", inversion); 481 lg_dbg("(%d)\n", inversion);
482 482
483 switch (param->u.vsb.modulation) { 483 switch (p->modulation) {
484 case VSB_8: 484 case VSB_8:
485 ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7, 485 ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7,
486 inversion ? 0xf9 : 0x79); 486 inversion ? 0xf9 : 0x79);
@@ -497,13 +497,13 @@ static int lgdt3305_spectral_inversion(struct lgdt3305_state *state,
497} 497}
498 498
499static int lgdt3305_set_if(struct lgdt3305_state *state, 499static int lgdt3305_set_if(struct lgdt3305_state *state,
500 struct dvb_frontend_parameters *param) 500 struct dtv_frontend_properties *p)
501{ 501{
502 u16 if_freq_khz; 502 u16 if_freq_khz;
503 u8 nco1, nco2, nco3, nco4; 503 u8 nco1, nco2, nco3, nco4;
504 u64 nco; 504 u64 nco;
505 505
506 switch (param->u.vsb.modulation) { 506 switch (p->modulation) {
507 case VSB_8: 507 case VSB_8:
508 if_freq_khz = state->cfg->vsb_if_khz; 508 if_freq_khz = state->cfg->vsb_if_khz;
509 break; 509 break;
@@ -517,7 +517,7 @@ static int lgdt3305_set_if(struct lgdt3305_state *state,
517 517
518 nco = if_freq_khz / 10; 518 nco = if_freq_khz / 10;
519 519
520 switch (param->u.vsb.modulation) { 520 switch (p->modulation) {
521 case VSB_8: 521 case VSB_8:
522 nco <<= 24; 522 nco <<= 24;
523 do_div(nco, 625); 523 do_div(nco, 625);
@@ -677,37 +677,37 @@ fail:
677 return ret; 677 return ret;
678} 678}
679 679
680static int lgdt3304_set_parameters(struct dvb_frontend *fe, 680static int lgdt3304_set_parameters(struct dvb_frontend *fe)
681 struct dvb_frontend_parameters *param)
682{ 681{
682 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
683 struct lgdt3305_state *state = fe->demodulator_priv; 683 struct lgdt3305_state *state = fe->demodulator_priv;
684 int ret; 684 int ret;
685 685
686 lg_dbg("(%d, %d)\n", param->frequency, param->u.vsb.modulation); 686 lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
687 687
688 if (fe->ops.tuner_ops.set_params) { 688 if (fe->ops.tuner_ops.set_params) {
689 ret = fe->ops.tuner_ops.set_params(fe, param); 689 ret = fe->ops.tuner_ops.set_params(fe);
690 if (fe->ops.i2c_gate_ctrl) 690 if (fe->ops.i2c_gate_ctrl)
691 fe->ops.i2c_gate_ctrl(fe, 0); 691 fe->ops.i2c_gate_ctrl(fe, 0);
692 if (lg_fail(ret)) 692 if (lg_fail(ret))
693 goto fail; 693 goto fail;
694 state->current_frequency = param->frequency; 694 state->current_frequency = p->frequency;
695 } 695 }
696 696
697 ret = lgdt3305_set_modulation(state, param); 697 ret = lgdt3305_set_modulation(state, p);
698 if (lg_fail(ret)) 698 if (lg_fail(ret))
699 goto fail; 699 goto fail;
700 700
701 ret = lgdt3305_passband_digital_agc(state, param); 701 ret = lgdt3305_passband_digital_agc(state, p);
702 if (lg_fail(ret)) 702 if (lg_fail(ret))
703 goto fail; 703 goto fail;
704 704
705 ret = lgdt3305_agc_setup(state, param); 705 ret = lgdt3305_agc_setup(state, p);
706 if (lg_fail(ret)) 706 if (lg_fail(ret))
707 goto fail; 707 goto fail;
708 708
709 /* reg 0x030d is 3304-only... seen in vsb and qam usbsnoops... */ 709 /* reg 0x030d is 3304-only... seen in vsb and qam usbsnoops... */
710 switch (param->u.vsb.modulation) { 710 switch (p->modulation) {
711 case VSB_8: 711 case VSB_8:
712 lgdt3305_write_reg(state, 0x030d, 0x00); 712 lgdt3305_write_reg(state, 0x030d, 0x00);
713 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f); 713 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f);
@@ -718,7 +718,7 @@ static int lgdt3304_set_parameters(struct dvb_frontend *fe,
718 case QAM_64: 718 case QAM_64:
719 case QAM_256: 719 case QAM_256:
720 lgdt3305_write_reg(state, 0x030d, 0x14); 720 lgdt3305_write_reg(state, 0x030d, 0x14);
721 ret = lgdt3305_set_if(state, param); 721 ret = lgdt3305_set_if(state, p);
722 if (lg_fail(ret)) 722 if (lg_fail(ret))
723 goto fail; 723 goto fail;
724 break; 724 break;
@@ -727,13 +727,13 @@ static int lgdt3304_set_parameters(struct dvb_frontend *fe,
727 } 727 }
728 728
729 729
730 ret = lgdt3305_spectral_inversion(state, param, 730 ret = lgdt3305_spectral_inversion(state, p,
731 state->cfg->spectral_inversion 731 state->cfg->spectral_inversion
732 ? 1 : 0); 732 ? 1 : 0);
733 if (lg_fail(ret)) 733 if (lg_fail(ret))
734 goto fail; 734 goto fail;
735 735
736 state->current_modulation = param->u.vsb.modulation; 736 state->current_modulation = p->modulation;
737 737
738 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode); 738 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
739 if (lg_fail(ret)) 739 if (lg_fail(ret))
@@ -747,34 +747,34 @@ fail:
747 return ret; 747 return ret;
748} 748}
749 749
750static int lgdt3305_set_parameters(struct dvb_frontend *fe, 750static int lgdt3305_set_parameters(struct dvb_frontend *fe)
751 struct dvb_frontend_parameters *param)
752{ 751{
752 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
753 struct lgdt3305_state *state = fe->demodulator_priv; 753 struct lgdt3305_state *state = fe->demodulator_priv;
754 int ret; 754 int ret;
755 755
756 lg_dbg("(%d, %d)\n", param->frequency, param->u.vsb.modulation); 756 lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
757 757
758 if (fe->ops.tuner_ops.set_params) { 758 if (fe->ops.tuner_ops.set_params) {
759 ret = fe->ops.tuner_ops.set_params(fe, param); 759 ret = fe->ops.tuner_ops.set_params(fe);
760 if (fe->ops.i2c_gate_ctrl) 760 if (fe->ops.i2c_gate_ctrl)
761 fe->ops.i2c_gate_ctrl(fe, 0); 761 fe->ops.i2c_gate_ctrl(fe, 0);
762 if (lg_fail(ret)) 762 if (lg_fail(ret))
763 goto fail; 763 goto fail;
764 state->current_frequency = param->frequency; 764 state->current_frequency = p->frequency;
765 } 765 }
766 766
767 ret = lgdt3305_set_modulation(state, param); 767 ret = lgdt3305_set_modulation(state, p);
768 if (lg_fail(ret)) 768 if (lg_fail(ret))
769 goto fail; 769 goto fail;
770 770
771 ret = lgdt3305_passband_digital_agc(state, param); 771 ret = lgdt3305_passband_digital_agc(state, p);
772 if (lg_fail(ret)) 772 if (lg_fail(ret))
773 goto fail; 773 goto fail;
774 ret = lgdt3305_set_agc_power_ref(state, param); 774 ret = lgdt3305_set_agc_power_ref(state, p);
775 if (lg_fail(ret)) 775 if (lg_fail(ret))
776 goto fail; 776 goto fail;
777 ret = lgdt3305_agc_setup(state, param); 777 ret = lgdt3305_agc_setup(state, p);
778 if (lg_fail(ret)) 778 if (lg_fail(ret))
779 goto fail; 779 goto fail;
780 780
@@ -786,20 +786,20 @@ static int lgdt3305_set_parameters(struct dvb_frontend *fe,
786 if (lg_fail(ret)) 786 if (lg_fail(ret))
787 goto fail; 787 goto fail;
788 788
789 ret = lgdt3305_set_if(state, param); 789 ret = lgdt3305_set_if(state, p);
790 if (lg_fail(ret)) 790 if (lg_fail(ret))
791 goto fail; 791 goto fail;
792 ret = lgdt3305_spectral_inversion(state, param, 792 ret = lgdt3305_spectral_inversion(state, p,
793 state->cfg->spectral_inversion 793 state->cfg->spectral_inversion
794 ? 1 : 0); 794 ? 1 : 0);
795 if (lg_fail(ret)) 795 if (lg_fail(ret))
796 goto fail; 796 goto fail;
797 797
798 ret = lgdt3305_set_filter_extension(state, param); 798 ret = lgdt3305_set_filter_extension(state, p);
799 if (lg_fail(ret)) 799 if (lg_fail(ret))
800 goto fail; 800 goto fail;
801 801
802 state->current_modulation = param->u.vsb.modulation; 802 state->current_modulation = p->modulation;
803 803
804 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode); 804 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
805 if (lg_fail(ret)) 805 if (lg_fail(ret))
@@ -813,15 +813,15 @@ fail:
813 return ret; 813 return ret;
814} 814}
815 815
816static int lgdt3305_get_frontend(struct dvb_frontend *fe, 816static int lgdt3305_get_frontend(struct dvb_frontend *fe)
817 struct dvb_frontend_parameters *param)
818{ 817{
818 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
819 struct lgdt3305_state *state = fe->demodulator_priv; 819 struct lgdt3305_state *state = fe->demodulator_priv;
820 820
821 lg_dbg("\n"); 821 lg_dbg("\n");
822 822
823 param->u.vsb.modulation = state->current_modulation; 823 p->modulation = state->current_modulation;
824 param->frequency = state->current_frequency; 824 p->frequency = state->current_frequency;
825 return 0; 825 return 0;
826} 826}
827 827
@@ -1166,9 +1166,9 @@ fail:
1166EXPORT_SYMBOL(lgdt3305_attach); 1166EXPORT_SYMBOL(lgdt3305_attach);
1167 1167
1168static struct dvb_frontend_ops lgdt3304_ops = { 1168static struct dvb_frontend_ops lgdt3304_ops = {
1169 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1169 .info = { 1170 .info = {
1170 .name = "LG Electronics LGDT3304 VSB/QAM Frontend", 1171 .name = "LG Electronics LGDT3304 VSB/QAM Frontend",
1171 .type = FE_ATSC,
1172 .frequency_min = 54000000, 1172 .frequency_min = 54000000,
1173 .frequency_max = 858000000, 1173 .frequency_max = 858000000,
1174 .frequency_stepsize = 62500, 1174 .frequency_stepsize = 62500,
@@ -1188,9 +1188,9 @@ static struct dvb_frontend_ops lgdt3304_ops = {
1188}; 1188};
1189 1189
1190static struct dvb_frontend_ops lgdt3305_ops = { 1190static struct dvb_frontend_ops lgdt3305_ops = {
1191 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1191 .info = { 1192 .info = {
1192 .name = "LG Electronics LGDT3305 VSB/QAM Frontend", 1193 .name = "LG Electronics LGDT3305 VSB/QAM Frontend",
1193 .type = FE_ATSC,
1194 .frequency_min = 54000000, 1194 .frequency_min = 54000000,
1195 .frequency_max = 858000000, 1195 .frequency_max = 858000000,
1196 .frequency_stepsize = 62500, 1196 .frequency_stepsize = 62500,
diff --git a/drivers/media/dvb/frontends/lgdt330x.c b/drivers/media/dvb/frontends/lgdt330x.c
index 43971e63baa7..c990d35a13dc 100644
--- a/drivers/media/dvb/frontends/lgdt330x.c
+++ b/drivers/media/dvb/frontends/lgdt330x.c
@@ -288,6 +288,8 @@ static int lgdt330x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
288 int err; 288 int err;
289 u8 buf[2]; 289 u8 buf[2];
290 290
291 *ucblocks = 0;
292
291 switch (state->config->demod_chip) { 293 switch (state->config->demod_chip) {
292 case LGDT3302: 294 case LGDT3302:
293 err = i2c_read_demod_bytes(state, LGDT3302_PACKET_ERR_COUNTER1, 295 err = i2c_read_demod_bytes(state, LGDT3302_PACKET_ERR_COUNTER1,
@@ -302,14 +304,16 @@ static int lgdt330x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
302 "Only LGDT3302 and LGDT3303 are supported chips.\n"); 304 "Only LGDT3302 and LGDT3303 are supported chips.\n");
303 err = -ENODEV; 305 err = -ENODEV;
304 } 306 }
307 if (err < 0)
308 return err;
305 309
306 *ucblocks = (buf[0] << 8) | buf[1]; 310 *ucblocks = (buf[0] << 8) | buf[1];
307 return 0; 311 return 0;
308} 312}
309 313
310static int lgdt330x_set_parameters(struct dvb_frontend* fe, 314static int lgdt330x_set_parameters(struct dvb_frontend *fe)
311 struct dvb_frontend_parameters *param)
312{ 315{
316 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
313 /* 317 /*
314 * Array of byte pairs <address, value> 318 * Array of byte pairs <address, value>
315 * to initialize 8VSB for lgdt3303 chip 50 MHz IF 319 * to initialize 8VSB for lgdt3303 chip 50 MHz IF
@@ -343,10 +347,10 @@ static int lgdt330x_set_parameters(struct dvb_frontend* fe,
343 347
344 static u8 top_ctrl_cfg[] = { TOP_CONTROL, 0x03 }; 348 static u8 top_ctrl_cfg[] = { TOP_CONTROL, 0x03 };
345 349
346 int err; 350 int err = 0;
347 /* Change only if we are actually changing the modulation */ 351 /* Change only if we are actually changing the modulation */
348 if (state->current_modulation != param->u.vsb.modulation) { 352 if (state->current_modulation != p->modulation) {
349 switch(param->u.vsb.modulation) { 353 switch (p->modulation) {
350 case VSB_8: 354 case VSB_8:
351 dprintk("%s: VSB_8 MODE\n", __func__); 355 dprintk("%s: VSB_8 MODE\n", __func__);
352 356
@@ -395,9 +399,14 @@ static int lgdt330x_set_parameters(struct dvb_frontend* fe,
395 } 399 }
396 break; 400 break;
397 default: 401 default:
398 printk(KERN_WARNING "lgdt330x: %s: Modulation type(%d) UNSUPPORTED\n", __func__, param->u.vsb.modulation); 402 printk(KERN_WARNING "lgdt330x: %s: Modulation type(%d) UNSUPPORTED\n", __func__, p->modulation);
399 return -1; 403 return -1;
400 } 404 }
405 if (err < 0)
406 printk(KERN_WARNING "lgdt330x: %s: error blasting "
407 "bytes to lgdt3303 for modulation type(%d)\n",
408 __func__, p->modulation);
409
401 /* 410 /*
402 * select serial or parallel MPEG harware interface 411 * select serial or parallel MPEG harware interface
403 * Serial: 0x04 for LGDT3302 or 0x40 for LGDT3303 412 * Serial: 0x04 for LGDT3302 or 0x40 for LGDT3303
@@ -410,29 +419,29 @@ static int lgdt330x_set_parameters(struct dvb_frontend* fe,
410 sizeof(top_ctrl_cfg)); 419 sizeof(top_ctrl_cfg));
411 if (state->config->set_ts_params) 420 if (state->config->set_ts_params)
412 state->config->set_ts_params(fe, 0); 421 state->config->set_ts_params(fe, 0);
413 state->current_modulation = param->u.vsb.modulation; 422 state->current_modulation = p->modulation;
414 } 423 }
415 424
416 /* Tune to the specified frequency */ 425 /* Tune to the specified frequency */
417 if (fe->ops.tuner_ops.set_params) { 426 if (fe->ops.tuner_ops.set_params) {
418 fe->ops.tuner_ops.set_params(fe, param); 427 fe->ops.tuner_ops.set_params(fe);
419 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 428 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
420 } 429 }
421 430
422 /* Keep track of the new frequency */ 431 /* Keep track of the new frequency */
423 /* FIXME this is the wrong way to do this... */ 432 /* FIXME this is the wrong way to do this... */
424 /* The tuner is shared with the video4linux analog API */ 433 /* The tuner is shared with the video4linux analog API */
425 state->current_frequency = param->frequency; 434 state->current_frequency = p->frequency;
426 435
427 lgdt330x_SwReset(state); 436 lgdt330x_SwReset(state);
428 return 0; 437 return 0;
429} 438}
430 439
431static int lgdt330x_get_frontend(struct dvb_frontend* fe, 440static int lgdt330x_get_frontend(struct dvb_frontend *fe)
432 struct dvb_frontend_parameters* param)
433{ 441{
442 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
434 struct lgdt330x_state *state = fe->demodulator_priv; 443 struct lgdt330x_state *state = fe->demodulator_priv;
435 param->frequency = state->current_frequency; 444 p->frequency = state->current_frequency;
436 return 0; 445 return 0;
437} 446}
438 447
@@ -762,9 +771,9 @@ error:
762} 771}
763 772
764static struct dvb_frontend_ops lgdt3302_ops = { 773static struct dvb_frontend_ops lgdt3302_ops = {
774 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
765 .info = { 775 .info = {
766 .name= "LG Electronics LGDT3302 VSB/QAM Frontend", 776 .name= "LG Electronics LGDT3302 VSB/QAM Frontend",
767 .type = FE_ATSC,
768 .frequency_min= 54000000, 777 .frequency_min= 54000000,
769 .frequency_max= 858000000, 778 .frequency_max= 858000000,
770 .frequency_stepsize= 62500, 779 .frequency_stepsize= 62500,
@@ -785,9 +794,9 @@ static struct dvb_frontend_ops lgdt3302_ops = {
785}; 794};
786 795
787static struct dvb_frontend_ops lgdt3303_ops = { 796static struct dvb_frontend_ops lgdt3303_ops = {
797 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
788 .info = { 798 .info = {
789 .name= "LG Electronics LGDT3303 VSB/QAM Frontend", 799 .name= "LG Electronics LGDT3303 VSB/QAM Frontend",
790 .type = FE_ATSC,
791 .frequency_min= 54000000, 800 .frequency_min= 54000000,
792 .frequency_max= 858000000, 801 .frequency_max= 858000000,
793 .frequency_stepsize= 62500, 802 .frequency_stepsize= 62500,
diff --git a/drivers/media/dvb/frontends/lgs8gl5.c b/drivers/media/dvb/frontends/lgs8gl5.c
index bb37ed289a05..2cec8041a106 100644
--- a/drivers/media/dvb/frontends/lgs8gl5.c
+++ b/drivers/media/dvb/frontends/lgs8gl5.c
@@ -311,18 +311,18 @@ lgs8gl5_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
311 311
312 312
313static int 313static int
314lgs8gl5_set_frontend(struct dvb_frontend *fe, 314lgs8gl5_set_frontend(struct dvb_frontend *fe)
315 struct dvb_frontend_parameters *p)
316{ 315{
316 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
317 struct lgs8gl5_state *state = fe->demodulator_priv; 317 struct lgs8gl5_state *state = fe->demodulator_priv;
318 318
319 dprintk("%s\n", __func__); 319 dprintk("%s\n", __func__);
320 320
321 if (p->u.ofdm.bandwidth != BANDWIDTH_8_MHZ) 321 if (p->bandwidth_hz != 8000000)
322 return -EINVAL; 322 return -EINVAL;
323 323
324 if (fe->ops.tuner_ops.set_params) { 324 if (fe->ops.tuner_ops.set_params) {
325 fe->ops.tuner_ops.set_params(fe, p); 325 fe->ops.tuner_ops.set_params(fe);
326 if (fe->ops.i2c_gate_ctrl) 326 if (fe->ops.i2c_gate_ctrl)
327 fe->ops.i2c_gate_ctrl(fe, 0); 327 fe->ops.i2c_gate_ctrl(fe, 0);
328 } 328 }
@@ -336,22 +336,21 @@ lgs8gl5_set_frontend(struct dvb_frontend *fe,
336 336
337 337
338static int 338static int
339lgs8gl5_get_frontend(struct dvb_frontend *fe, 339lgs8gl5_get_frontend(struct dvb_frontend *fe)
340 struct dvb_frontend_parameters *p)
341{ 340{
341 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
342 struct lgs8gl5_state *state = fe->demodulator_priv; 342 struct lgs8gl5_state *state = fe->demodulator_priv;
343 u8 inv = lgs8gl5_read_reg(state, REG_INVERSION); 343 u8 inv = lgs8gl5_read_reg(state, REG_INVERSION);
344 struct dvb_ofdm_parameters *o = &p->u.ofdm;
345 344
346 p->inversion = (inv & REG_INVERSION_ON) ? INVERSION_ON : INVERSION_OFF; 345 p->inversion = (inv & REG_INVERSION_ON) ? INVERSION_ON : INVERSION_OFF;
347 346
348 o->code_rate_HP = FEC_1_2; 347 p->code_rate_HP = FEC_1_2;
349 o->code_rate_LP = FEC_7_8; 348 p->code_rate_LP = FEC_7_8;
350 o->guard_interval = GUARD_INTERVAL_1_32; 349 p->guard_interval = GUARD_INTERVAL_1_32;
351 o->transmission_mode = TRANSMISSION_MODE_2K; 350 p->transmission_mode = TRANSMISSION_MODE_2K;
352 o->constellation = QAM_64; 351 p->modulation = QAM_64;
353 o->hierarchy_information = HIERARCHY_NONE; 352 p->hierarchy = HIERARCHY_NONE;
354 o->bandwidth = BANDWIDTH_8_MHZ; 353 p->bandwidth_hz = 8000000;
355 354
356 return 0; 355 return 0;
357} 356}
@@ -413,9 +412,9 @@ EXPORT_SYMBOL(lgs8gl5_attach);
413 412
414 413
415static struct dvb_frontend_ops lgs8gl5_ops = { 414static struct dvb_frontend_ops lgs8gl5_ops = {
415 .delsys = { SYS_DMBTH },
416 .info = { 416 .info = {
417 .name = "Legend Silicon LGS-8GL5 DMB-TH", 417 .name = "Legend Silicon LGS-8GL5 DMB-TH",
418 .type = FE_OFDM,
419 .frequency_min = 474000000, 418 .frequency_min = 474000000,
420 .frequency_max = 858000000, 419 .frequency_max = 858000000,
421 .frequency_stepsize = 10000, 420 .frequency_stepsize = 10000,
diff --git a/drivers/media/dvb/frontends/lgs8gxx.c b/drivers/media/dvb/frontends/lgs8gxx.c
index 1172b54689f8..4de1d3520cd2 100644
--- a/drivers/media/dvb/frontends/lgs8gxx.c
+++ b/drivers/media/dvb/frontends/lgs8gxx.c
@@ -669,16 +669,16 @@ static int lgs8gxx_write(struct dvb_frontend *fe, const u8 buf[], int len)
669 return lgs8gxx_write_reg(priv, buf[0], buf[1]); 669 return lgs8gxx_write_reg(priv, buf[0], buf[1]);
670} 670}
671 671
672static int lgs8gxx_set_fe(struct dvb_frontend *fe, 672static int lgs8gxx_set_fe(struct dvb_frontend *fe)
673 struct dvb_frontend_parameters *fe_params)
674{ 673{
674
675 struct lgs8gxx_state *priv = fe->demodulator_priv; 675 struct lgs8gxx_state *priv = fe->demodulator_priv;
676 676
677 dprintk("%s\n", __func__); 677 dprintk("%s\n", __func__);
678 678
679 /* set frequency */ 679 /* set frequency */
680 if (fe->ops.tuner_ops.set_params) { 680 if (fe->ops.tuner_ops.set_params) {
681 fe->ops.tuner_ops.set_params(fe, fe_params); 681 fe->ops.tuner_ops.set_params(fe);
682 if (fe->ops.i2c_gate_ctrl) 682 if (fe->ops.i2c_gate_ctrl)
683 fe->ops.i2c_gate_ctrl(fe, 0); 683 fe->ops.i2c_gate_ctrl(fe, 0);
684 } 684 }
@@ -691,9 +691,9 @@ static int lgs8gxx_set_fe(struct dvb_frontend *fe,
691 return 0; 691 return 0;
692} 692}
693 693
694static int lgs8gxx_get_fe(struct dvb_frontend *fe, 694static int lgs8gxx_get_fe(struct dvb_frontend *fe)
695 struct dvb_frontend_parameters *fe_params)
696{ 695{
696 struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
697 dprintk("%s\n", __func__); 697 dprintk("%s\n", __func__);
698 698
699 /* TODO: get real readings from device */ 699 /* TODO: get real readings from device */
@@ -701,21 +701,21 @@ static int lgs8gxx_get_fe(struct dvb_frontend *fe,
701 fe_params->inversion = INVERSION_OFF; 701 fe_params->inversion = INVERSION_OFF;
702 702
703 /* bandwidth */ 703 /* bandwidth */
704 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; 704 fe_params->bandwidth_hz = 8000000;
705 705
706 fe_params->u.ofdm.code_rate_HP = FEC_AUTO; 706 fe_params->code_rate_HP = FEC_AUTO;
707 fe_params->u.ofdm.code_rate_LP = FEC_AUTO; 707 fe_params->code_rate_LP = FEC_AUTO;
708 708
709 fe_params->u.ofdm.constellation = QAM_AUTO; 709 fe_params->modulation = QAM_AUTO;
710 710
711 /* transmission mode */ 711 /* transmission mode */
712 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO; 712 fe_params->transmission_mode = TRANSMISSION_MODE_AUTO;
713 713
714 /* guard interval */ 714 /* guard interval */
715 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO; 715 fe_params->guard_interval = GUARD_INTERVAL_AUTO;
716 716
717 /* hierarchy */ 717 /* hierarchy */
718 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE; 718 fe_params->hierarchy = HIERARCHY_NONE;
719 719
720 return 0; 720 return 0;
721} 721}
@@ -994,9 +994,9 @@ static int lgs8gxx_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
994} 994}
995 995
996static struct dvb_frontend_ops lgs8gxx_ops = { 996static struct dvb_frontend_ops lgs8gxx_ops = {
997 .delsys = { SYS_DMBTH },
997 .info = { 998 .info = {
998 .name = "Legend Silicon LGS8913/LGS8GXX DMB-TH", 999 .name = "Legend Silicon LGS8913/LGS8GXX DMB-TH",
999 .type = FE_OFDM,
1000 .frequency_min = 474000000, 1000 .frequency_min = 474000000,
1001 .frequency_max = 858000000, 1001 .frequency_max = 858000000,
1002 .frequency_stepsize = 10000, 1002 .frequency_stepsize = 10000,
diff --git a/drivers/media/dvb/frontends/mb86a16.c b/drivers/media/dvb/frontends/mb86a16.c
index c283112051b1..9ae40abfd71a 100644
--- a/drivers/media/dvb/frontends/mb86a16.c
+++ b/drivers/media/dvb/frontends/mb86a16.c
@@ -1621,13 +1621,13 @@ err:
1621 return -EREMOTEIO; 1621 return -EREMOTEIO;
1622} 1622}
1623 1623
1624static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe, 1624static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe)
1625 struct dvb_frontend_parameters *p)
1626{ 1625{
1626 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1627 struct mb86a16_state *state = fe->demodulator_priv; 1627 struct mb86a16_state *state = fe->demodulator_priv;
1628 1628
1629 state->frequency = p->frequency / 1000; 1629 state->frequency = p->frequency / 1000;
1630 state->srate = p->u.qpsk.symbol_rate / 1000; 1630 state->srate = p->symbol_rate / 1000;
1631 1631
1632 if (!mb86a16_set_fe(state)) { 1632 if (!mb86a16_set_fe(state)) {
1633 dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK"); 1633 dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK");
@@ -1814,9 +1814,9 @@ static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe)
1814} 1814}
1815 1815
1816static struct dvb_frontend_ops mb86a16_ops = { 1816static struct dvb_frontend_ops mb86a16_ops = {
1817 .delsys = { SYS_DVBS },
1817 .info = { 1818 .info = {
1818 .name = "Fujitsu MB86A16 DVB-S", 1819 .name = "Fujitsu MB86A16 DVB-S",
1819 .type = FE_QPSK,
1820 .frequency_min = 950000, 1820 .frequency_min = 950000,
1821 .frequency_max = 2150000, 1821 .frequency_max = 2150000,
1822 .frequency_stepsize = 3000, 1822 .frequency_stepsize = 3000,
diff --git a/drivers/media/dvb/frontends/mb86a20s.c b/drivers/media/dvb/frontends/mb86a20s.c
index 0f867a5055fb..7fa3e472cdca 100644
--- a/drivers/media/dvb/frontends/mb86a20s.c
+++ b/drivers/media/dvb/frontends/mb86a20s.c
@@ -61,244 +61,111 @@ static struct regdata mb86a20s_init[] = {
61 { 0x70, 0xff }, 61 { 0x70, 0xff },
62 { 0x08, 0x01 }, 62 { 0x08, 0x01 },
63 { 0x09, 0x3e }, 63 { 0x09, 0x3e },
64 { 0x50, 0xd1 }, 64 { 0x50, 0xd1 }, { 0x51, 0x22 },
65 { 0x51, 0x22 },
66 { 0x39, 0x01 }, 65 { 0x39, 0x01 },
67 { 0x71, 0x00 }, 66 { 0x71, 0x00 },
68 { 0x28, 0x2a }, 67 { 0x28, 0x2a }, { 0x29, 0x00 }, { 0x2a, 0xff }, { 0x2b, 0x80 },
69 { 0x29, 0x00 }, 68 { 0x28, 0x20 }, { 0x29, 0x33 }, { 0x2a, 0xdf }, { 0x2b, 0xa9 },
70 { 0x2a, 0xff }, 69 { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 },
71 { 0x2b, 0x80 },
72 { 0x28, 0x20 },
73 { 0x29, 0x33 },
74 { 0x2a, 0xdf },
75 { 0x2b, 0xa9 },
76 { 0x3b, 0x21 }, 70 { 0x3b, 0x21 },
77 { 0x3c, 0x3a }, 71 { 0x3c, 0x3a },
78 { 0x01, 0x0d }, 72 { 0x01, 0x0d },
79 { 0x04, 0x08 }, 73 { 0x04, 0x08 }, { 0x05, 0x05 },
80 { 0x05, 0x05 }, 74 { 0x04, 0x0e }, { 0x05, 0x00 },
81 { 0x04, 0x0e }, 75 { 0x04, 0x0f }, { 0x05, 0x14 },
82 { 0x05, 0x00 }, 76 { 0x04, 0x0b }, { 0x05, 0x8c },
83 { 0x04, 0x0f }, 77 { 0x04, 0x00 }, { 0x05, 0x00 },
84 { 0x05, 0x14 }, 78 { 0x04, 0x01 }, { 0x05, 0x07 },
85 { 0x04, 0x0b }, 79 { 0x04, 0x02 }, { 0x05, 0x0f },
86 { 0x05, 0x8c }, 80 { 0x04, 0x03 }, { 0x05, 0xa0 },
87 { 0x04, 0x00 }, 81 { 0x04, 0x09 }, { 0x05, 0x00 },
88 { 0x05, 0x00 }, 82 { 0x04, 0x0a }, { 0x05, 0xff },
89 { 0x04, 0x01 }, 83 { 0x04, 0x27 }, { 0x05, 0x64 },
90 { 0x05, 0x07 }, 84 { 0x04, 0x28 }, { 0x05, 0x00 },
91 { 0x04, 0x02 }, 85 { 0x04, 0x1e }, { 0x05, 0xff },
92 { 0x05, 0x0f }, 86 { 0x04, 0x29 }, { 0x05, 0x0a },
93 { 0x04, 0x03 }, 87 { 0x04, 0x32 }, { 0x05, 0x0a },
94 { 0x05, 0xa0 }, 88 { 0x04, 0x14 }, { 0x05, 0x02 },
95 { 0x04, 0x09 }, 89 { 0x04, 0x04 }, { 0x05, 0x00 },
96 { 0x05, 0x00 }, 90 { 0x04, 0x05 }, { 0x05, 0x22 },
97 { 0x04, 0x0a }, 91 { 0x04, 0x06 }, { 0x05, 0x0e },
98 { 0x05, 0xff }, 92 { 0x04, 0x07 }, { 0x05, 0xd8 },
99 { 0x04, 0x27 }, 93 { 0x04, 0x12 }, { 0x05, 0x00 },
100 { 0x05, 0x64 }, 94 { 0x04, 0x13 }, { 0x05, 0xff },
101 { 0x04, 0x28 }, 95 { 0x04, 0x15 }, { 0x05, 0x4e },
102 { 0x05, 0x00 }, 96 { 0x04, 0x16 }, { 0x05, 0x20 },
103 { 0x04, 0x1e },
104 { 0x05, 0xff },
105 { 0x04, 0x29 },
106 { 0x05, 0x0a },
107 { 0x04, 0x32 },
108 { 0x05, 0x0a },
109 { 0x04, 0x14 },
110 { 0x05, 0x02 },
111 { 0x04, 0x04 },
112 { 0x05, 0x00 },
113 { 0x04, 0x05 },
114 { 0x05, 0x22 },
115 { 0x04, 0x06 },
116 { 0x05, 0x0e },
117 { 0x04, 0x07 },
118 { 0x05, 0xd8 },
119 { 0x04, 0x12 },
120 { 0x05, 0x00 },
121 { 0x04, 0x13 },
122 { 0x05, 0xff },
123 { 0x52, 0x01 }, 97 { 0x52, 0x01 },
124 { 0x50, 0xa7 }, 98 { 0x50, 0xa7 }, { 0x51, 0xff },
125 { 0x51, 0x00 }, 99 { 0x50, 0xa8 }, { 0x51, 0xff },
126 { 0x50, 0xa8 }, 100 { 0x50, 0xa9 }, { 0x51, 0xff },
127 { 0x51, 0xff }, 101 { 0x50, 0xaa }, { 0x51, 0xff },
128 { 0x50, 0xa9 }, 102 { 0x50, 0xab }, { 0x51, 0xff },
129 { 0x51, 0xff }, 103 { 0x50, 0xac }, { 0x51, 0xff },
130 { 0x50, 0xaa }, 104 { 0x50, 0xad }, { 0x51, 0xff },
131 { 0x51, 0x00 }, 105 { 0x50, 0xae }, { 0x51, 0xff },
132 { 0x50, 0xab }, 106 { 0x50, 0xaf }, { 0x51, 0xff },
133 { 0x51, 0xff },
134 { 0x50, 0xac },
135 { 0x51, 0xff },
136 { 0x50, 0xad },
137 { 0x51, 0x00 },
138 { 0x50, 0xae },
139 { 0x51, 0xff },
140 { 0x50, 0xaf },
141 { 0x51, 0xff },
142 { 0x5e, 0x07 }, 107 { 0x5e, 0x07 },
143 { 0x50, 0xdc }, 108 { 0x50, 0xdc }, { 0x51, 0x01 },
144 { 0x51, 0x01 }, 109 { 0x50, 0xdd }, { 0x51, 0xf4 },
145 { 0x50, 0xdd }, 110 { 0x50, 0xde }, { 0x51, 0x01 },
146 { 0x51, 0xf4 }, 111 { 0x50, 0xdf }, { 0x51, 0xf4 },
147 { 0x50, 0xde }, 112 { 0x50, 0xe0 }, { 0x51, 0x01 },
148 { 0x51, 0x01 }, 113 { 0x50, 0xe1 }, { 0x51, 0xf4 },
149 { 0x50, 0xdf }, 114 { 0x50, 0xb0 }, { 0x51, 0x07 },
150 { 0x51, 0xf4 }, 115 { 0x50, 0xb2 }, { 0x51, 0xff },
151 { 0x50, 0xe0 }, 116 { 0x50, 0xb3 }, { 0x51, 0xff },
152 { 0x51, 0x01 }, 117 { 0x50, 0xb4 }, { 0x51, 0xff },
153 { 0x50, 0xe1 }, 118 { 0x50, 0xb5 }, { 0x51, 0xff },
154 { 0x51, 0xf4 }, 119 { 0x50, 0xb6 }, { 0x51, 0xff },
155 { 0x50, 0xb0 }, 120 { 0x50, 0xb7 }, { 0x51, 0xff },
156 { 0x51, 0x07 }, 121 { 0x50, 0x50 }, { 0x51, 0x02 },
157 { 0x50, 0xb2 }, 122 { 0x50, 0x51 }, { 0x51, 0x04 },
158 { 0x51, 0xff },
159 { 0x50, 0xb3 },
160 { 0x51, 0xff },
161 { 0x50, 0xb4 },
162 { 0x51, 0xff },
163 { 0x50, 0xb5 },
164 { 0x51, 0xff },
165 { 0x50, 0xb6 },
166 { 0x51, 0xff },
167 { 0x50, 0xb7 },
168 { 0x51, 0xff },
169 { 0x50, 0x50 },
170 { 0x51, 0x02 },
171 { 0x50, 0x51 },
172 { 0x51, 0x04 },
173 { 0x45, 0x04 }, 123 { 0x45, 0x04 },
174 { 0x48, 0x04 }, 124 { 0x48, 0x04 },
175 { 0x50, 0xd5 }, 125 { 0x50, 0xd5 }, { 0x51, 0x01 }, /* Serial */
176 { 0x51, 0x01 }, /* Serial */ 126 { 0x50, 0xd6 }, { 0x51, 0x1f },
177 { 0x50, 0xd6 }, 127 { 0x50, 0xd2 }, { 0x51, 0x03 },
178 { 0x51, 0x1f }, 128 { 0x50, 0xd7 }, { 0x51, 0x3f },
179 { 0x50, 0xd2 }, 129 { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x28, 0x74 }, { 0x29, 0x40 },
180 { 0x51, 0x03 }, 130 { 0x28, 0x46 }, { 0x29, 0x2c }, { 0x28, 0x46 }, { 0x29, 0x0c },
181 { 0x50, 0xd7 }, 131 { 0x04, 0x40 }, { 0x05, 0x01 },
182 { 0x51, 0x3f }, 132 { 0x28, 0x00 }, { 0x29, 0x10 },
133 { 0x28, 0x05 }, { 0x29, 0x02 },
183 { 0x1c, 0x01 }, 134 { 0x1c, 0x01 },
184 { 0x28, 0x06 }, 135 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 },
185 { 0x29, 0x00 }, 136 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d },
186 { 0x2a, 0x00 }, 137 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
187 { 0x2b, 0x03 }, 138 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 },
188 { 0x28, 0x07 }, 139 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 },
189 { 0x29, 0x00 }, 140 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 },
190 { 0x2a, 0x00 }, 141 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
191 { 0x2b, 0x0d }, 142 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 },
192 { 0x28, 0x08 }, 143 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e },
193 { 0x29, 0x00 }, 144 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e },
194 { 0x2a, 0x00 }, 145 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 },
195 { 0x2b, 0x02 }, 146 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
196 { 0x28, 0x09 }, 147 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 },
197 { 0x29, 0x00 }, 148 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 },
198 { 0x2a, 0x00 }, 149 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe },
199 { 0x2b, 0x01 }, 150 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 },
200 { 0x28, 0x0a }, 151 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee },
201 { 0x29, 0x00 }, 152 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 },
202 { 0x2a, 0x00 }, 153 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f },
203 { 0x2b, 0x21 }, 154 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 },
204 { 0x28, 0x0b }, 155 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 },
205 { 0x29, 0x00 }, 156 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a },
206 { 0x2a, 0x00 }, 157 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc },
207 { 0x2b, 0x29 }, 158 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba },
208 { 0x28, 0x0c }, 159 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 },
209 { 0x29, 0x00 }, 160 { 0x50, 0x1e }, { 0x51, 0x5d },
210 { 0x2a, 0x00 }, 161 { 0x50, 0x22 }, { 0x51, 0x00 },
211 { 0x2b, 0x16 }, 162 { 0x50, 0x23 }, { 0x51, 0xc8 },
212 { 0x28, 0x0d }, 163 { 0x50, 0x24 }, { 0x51, 0x00 },
213 { 0x29, 0x00 }, 164 { 0x50, 0x25 }, { 0x51, 0xf0 },
214 { 0x2a, 0x00 }, 165 { 0x50, 0x26 }, { 0x51, 0x00 },
215 { 0x2b, 0x31 }, 166 { 0x50, 0x27 }, { 0x51, 0xc3 },
216 { 0x28, 0x0e }, 167 { 0x50, 0x39 }, { 0x51, 0x02 },
217 { 0x29, 0x00 }, 168 { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
218 { 0x2a, 0x00 },
219 { 0x2b, 0x0e },
220 { 0x28, 0x0f },
221 { 0x29, 0x00 },
222 { 0x2a, 0x00 },
223 { 0x2b, 0x4e },
224 { 0x28, 0x10 },
225 { 0x29, 0x00 },
226 { 0x2a, 0x00 },
227 { 0x2b, 0x46 },
228 { 0x28, 0x11 },
229 { 0x29, 0x00 },
230 { 0x2a, 0x00 },
231 { 0x2b, 0x0f },
232 { 0x28, 0x12 },
233 { 0x29, 0x00 },
234 { 0x2a, 0x00 },
235 { 0x2b, 0x56 },
236 { 0x28, 0x13 },
237 { 0x29, 0x00 },
238 { 0x2a, 0x00 },
239 { 0x2b, 0x35 },
240 { 0x28, 0x14 },
241 { 0x29, 0x00 },
242 { 0x2a, 0x01 },
243 { 0x2b, 0xbe },
244 { 0x28, 0x15 },
245 { 0x29, 0x00 },
246 { 0x2a, 0x01 },
247 { 0x2b, 0x84 },
248 { 0x28, 0x16 },
249 { 0x29, 0x00 },
250 { 0x2a, 0x03 },
251 { 0x2b, 0xee },
252 { 0x28, 0x17 },
253 { 0x29, 0x00 },
254 { 0x2a, 0x00 },
255 { 0x2b, 0x98 },
256 { 0x28, 0x18 },
257 { 0x29, 0x00 },
258 { 0x2a, 0x00 },
259 { 0x2b, 0x9f },
260 { 0x28, 0x19 },
261 { 0x29, 0x00 },
262 { 0x2a, 0x07 },
263 { 0x2b, 0xb2 },
264 { 0x28, 0x1a },
265 { 0x29, 0x00 },
266 { 0x2a, 0x06 },
267 { 0x2b, 0xc2 },
268 { 0x28, 0x1b },
269 { 0x29, 0x00 },
270 { 0x2a, 0x07 },
271 { 0x2b, 0x4a },
272 { 0x28, 0x1c },
273 { 0x29, 0x00 },
274 { 0x2a, 0x01 },
275 { 0x2b, 0xbc },
276 { 0x28, 0x1d },
277 { 0x29, 0x00 },
278 { 0x2a, 0x04 },
279 { 0x2b, 0xba },
280 { 0x28, 0x1e },
281 { 0x29, 0x00 },
282 { 0x2a, 0x06 },
283 { 0x2b, 0x14 },
284 { 0x50, 0x1e },
285 { 0x51, 0x5d },
286 { 0x50, 0x22 },
287 { 0x51, 0x00 },
288 { 0x50, 0x23 },
289 { 0x51, 0xc8 },
290 { 0x50, 0x24 },
291 { 0x51, 0x00 },
292 { 0x50, 0x25 },
293 { 0x51, 0xf0 },
294 { 0x50, 0x26 },
295 { 0x51, 0x00 },
296 { 0x50, 0x27 },
297 { 0x51, 0xc3 },
298 { 0x50, 0x39 },
299 { 0x51, 0x02 },
300 { 0x50, 0xd5 },
301 { 0x51, 0x01 },
302 { 0xd0, 0x00 }, 169 { 0xd0, 0x00 },
303}; 170};
304 171
@@ -485,18 +352,23 @@ static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status)
485 return 0; 352 return 0;
486} 353}
487 354
488static int mb86a20s_set_frontend(struct dvb_frontend *fe, 355static int mb86a20s_set_frontend(struct dvb_frontend *fe)
489 struct dvb_frontend_parameters *p)
490{ 356{
491 struct mb86a20s_state *state = fe->demodulator_priv; 357 struct mb86a20s_state *state = fe->demodulator_priv;
492 int rc; 358 int rc;
359#if 0
360 /*
361 * FIXME: Properly implement the set frontend properties
362 */
363 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
364#endif
493 365
494 dprintk("\n"); 366 dprintk("\n");
495 367
496 if (fe->ops.i2c_gate_ctrl) 368 if (fe->ops.i2c_gate_ctrl)
497 fe->ops.i2c_gate_ctrl(fe, 1); 369 fe->ops.i2c_gate_ctrl(fe, 1);
498 dprintk("Calling tuner set parameters\n"); 370 dprintk("Calling tuner set parameters\n");
499 fe->ops.tuner_ops.set_params(fe, p); 371 fe->ops.tuner_ops.set_params(fe);
500 372
501 /* 373 /*
502 * Make it more reliable: if, for some reason, the initial 374 * Make it more reliable: if, for some reason, the initial
@@ -520,22 +392,212 @@ static int mb86a20s_set_frontend(struct dvb_frontend *fe,
520 return rc; 392 return rc;
521} 393}
522 394
523static int mb86a20s_get_frontend(struct dvb_frontend *fe, 395static int mb86a20s_get_modulation(struct mb86a20s_state *state,
524 struct dvb_frontend_parameters *p) 396 unsigned layer)
397{
398 int rc;
399 static unsigned char reg[] = {
400 [0] = 0x86, /* Layer A */
401 [1] = 0x8a, /* Layer B */
402 [2] = 0x8e, /* Layer C */
403 };
404
405 if (layer > ARRAY_SIZE(reg))
406 return -EINVAL;
407 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
408 if (rc < 0)
409 return rc;
410 rc = mb86a20s_readreg(state, 0x6e);
411 if (rc < 0)
412 return rc;
413 switch ((rc & 0x70) >> 4) {
414 case 0:
415 return DQPSK;
416 case 1:
417 return QPSK;
418 case 2:
419 return QAM_16;
420 case 3:
421 return QAM_64;
422 default:
423 return QAM_AUTO;
424 }
425}
426
427static int mb86a20s_get_fec(struct mb86a20s_state *state,
428 unsigned layer)
525{ 429{
430 int rc;
526 431
527 /* FIXME: For now, it does nothing */ 432 static unsigned char reg[] = {
433 [0] = 0x87, /* Layer A */
434 [1] = 0x8b, /* Layer B */
435 [2] = 0x8f, /* Layer C */
436 };
528 437
529 fe->dtv_property_cache.bandwidth_hz = 6000000; 438 if (layer > ARRAY_SIZE(reg))
530 fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO; 439 return -EINVAL;
531 fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO; 440 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
532 fe->dtv_property_cache.isdbt_partial_reception = 0; 441 if (rc < 0)
442 return rc;
443 rc = mb86a20s_readreg(state, 0x6e);
444 if (rc < 0)
445 return rc;
446 switch (rc) {
447 case 0:
448 return FEC_1_2;
449 case 1:
450 return FEC_2_3;
451 case 2:
452 return FEC_3_4;
453 case 3:
454 return FEC_5_6;
455 case 4:
456 return FEC_7_8;
457 default:
458 return FEC_AUTO;
459 }
460}
461
462static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
463 unsigned layer)
464{
465 int rc;
466
467 static unsigned char reg[] = {
468 [0] = 0x88, /* Layer A */
469 [1] = 0x8c, /* Layer B */
470 [2] = 0x90, /* Layer C */
471 };
472
473 if (layer > ARRAY_SIZE(reg))
474 return -EINVAL;
475 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
476 if (rc < 0)
477 return rc;
478 rc = mb86a20s_readreg(state, 0x6e);
479 if (rc < 0)
480 return rc;
481 if (rc > 3)
482 return -EINVAL; /* Not used */
483 return rc;
484}
485
486static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
487 unsigned layer)
488{
489 int rc, count;
490
491 static unsigned char reg[] = {
492 [0] = 0x89, /* Layer A */
493 [1] = 0x8d, /* Layer B */
494 [2] = 0x91, /* Layer C */
495 };
496
497 if (layer > ARRAY_SIZE(reg))
498 return -EINVAL;
499 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
500 if (rc < 0)
501 return rc;
502 rc = mb86a20s_readreg(state, 0x6e);
503 if (rc < 0)
504 return rc;
505 count = (rc >> 4) & 0x0f;
506
507 return count;
508}
509
510static int mb86a20s_get_frontend(struct dvb_frontend *fe)
511{
512 struct mb86a20s_state *state = fe->demodulator_priv;
513 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
514 int i, rc;
515
516 /* Fixed parameters */
517 p->delivery_system = SYS_ISDBT;
518 p->bandwidth_hz = 6000000;
519
520 if (fe->ops.i2c_gate_ctrl)
521 fe->ops.i2c_gate_ctrl(fe, 0);
522
523 /* Check for partial reception */
524 rc = mb86a20s_writereg(state, 0x6d, 0x85);
525 if (rc >= 0)
526 rc = mb86a20s_readreg(state, 0x6e);
527 if (rc >= 0)
528 p->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
529
530 /* Get per-layer data */
531 p->isdbt_layer_enabled = 0;
532 for (i = 0; i < 3; i++) {
533 rc = mb86a20s_get_segment_count(state, i);
534 if (rc >= 0 && rc < 14)
535 p->layer[i].segment_count = rc;
536 if (rc == 0x0f)
537 continue;
538 p->isdbt_layer_enabled |= 1 << i;
539 rc = mb86a20s_get_modulation(state, i);
540 if (rc >= 0)
541 p->layer[i].modulation = rc;
542 rc = mb86a20s_get_fec(state, i);
543 if (rc >= 0)
544 p->layer[i].fec = rc;
545 rc = mb86a20s_get_interleaving(state, i);
546 if (rc >= 0)
547 p->layer[i].interleaving = rc;
548 }
549
550 p->isdbt_sb_mode = 0;
551 rc = mb86a20s_writereg(state, 0x6d, 0x84);
552 if ((rc >= 0) && ((rc & 0x60) == 0x20)) {
553 p->isdbt_sb_mode = 1;
554 /* At least, one segment should exist */
555 if (!p->isdbt_sb_segment_count)
556 p->isdbt_sb_segment_count = 1;
557 } else
558 p->isdbt_sb_segment_count = 0;
559
560 /* Get transmission mode and guard interval */
561 p->transmission_mode = TRANSMISSION_MODE_AUTO;
562 p->guard_interval = GUARD_INTERVAL_AUTO;
563 rc = mb86a20s_readreg(state, 0x07);
564 if (rc >= 0) {
565 if ((rc & 0x60) == 0x20) {
566 switch (rc & 0x0c >> 2) {
567 case 0:
568 p->transmission_mode = TRANSMISSION_MODE_2K;
569 break;
570 case 1:
571 p->transmission_mode = TRANSMISSION_MODE_4K;
572 break;
573 case 2:
574 p->transmission_mode = TRANSMISSION_MODE_8K;
575 break;
576 }
577 }
578 if (!(rc & 0x10)) {
579 switch (rc & 0x3) {
580 case 0:
581 p->guard_interval = GUARD_INTERVAL_1_4;
582 break;
583 case 1:
584 p->guard_interval = GUARD_INTERVAL_1_8;
585 break;
586 case 2:
587 p->guard_interval = GUARD_INTERVAL_1_16;
588 break;
589 }
590 }
591 }
592
593 if (fe->ops.i2c_gate_ctrl)
594 fe->ops.i2c_gate_ctrl(fe, 1);
533 595
534 return 0; 596 return 0;
535} 597}
536 598
537static int mb86a20s_tune(struct dvb_frontend *fe, 599static int mb86a20s_tune(struct dvb_frontend *fe,
538 struct dvb_frontend_parameters *params, 600 bool re_tune,
539 unsigned int mode_flags, 601 unsigned int mode_flags,
540 unsigned int *delay, 602 unsigned int *delay,
541 fe_status_t *status) 603 fe_status_t *status)
@@ -544,8 +606,8 @@ static int mb86a20s_tune(struct dvb_frontend *fe,
544 606
545 dprintk("\n"); 607 dprintk("\n");
546 608
547 if (params != NULL) 609 if (re_tune)
548 rc = mb86a20s_set_frontend(fe, params); 610 rc = mb86a20s_set_frontend(fe);
549 611
550 if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) 612 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
551 mb86a20s_read_status(fe, status); 613 mb86a20s_read_status(fe, status);
@@ -608,10 +670,10 @@ error:
608EXPORT_SYMBOL(mb86a20s_attach); 670EXPORT_SYMBOL(mb86a20s_attach);
609 671
610static struct dvb_frontend_ops mb86a20s_ops = { 672static struct dvb_frontend_ops mb86a20s_ops = {
673 .delsys = { SYS_ISDBT },
611 /* Use dib8000 values per default */ 674 /* Use dib8000 values per default */
612 .info = { 675 .info = {
613 .name = "Fujitsu mb86A20s", 676 .name = "Fujitsu mb86A20s",
614 .type = FE_OFDM,
615 .caps = FE_CAN_INVERSION_AUTO | FE_CAN_RECOVER | 677 .caps = FE_CAN_INVERSION_AUTO | FE_CAN_RECOVER |
616 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 678 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
617 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 679 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
diff --git a/drivers/media/dvb/frontends/mt312.c b/drivers/media/dvb/frontends/mt312.c
index 83e6f1a1b700..e20bf13aa860 100644
--- a/drivers/media/dvb/frontends/mt312.c
+++ b/drivers/media/dvb/frontends/mt312.c
@@ -531,9 +531,9 @@ static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc)
531 return 0; 531 return 0;
532} 532}
533 533
534static int mt312_set_frontend(struct dvb_frontend *fe, 534static int mt312_set_frontend(struct dvb_frontend *fe)
535 struct dvb_frontend_parameters *p)
536{ 535{
536 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
537 struct mt312_state *state = fe->demodulator_priv; 537 struct mt312_state *state = fe->demodulator_priv;
538 int ret; 538 int ret;
539 u8 buf[5], config_val; 539 u8 buf[5], config_val;
@@ -553,16 +553,16 @@ static int mt312_set_frontend(struct dvb_frontend *fe,
553 || (p->inversion > INVERSION_ON)) 553 || (p->inversion > INVERSION_ON))
554 return -EINVAL; 554 return -EINVAL;
555 555
556 if ((p->u.qpsk.symbol_rate < fe->ops.info.symbol_rate_min) 556 if ((p->symbol_rate < fe->ops.info.symbol_rate_min)
557 || (p->u.qpsk.symbol_rate > fe->ops.info.symbol_rate_max)) 557 || (p->symbol_rate > fe->ops.info.symbol_rate_max))
558 return -EINVAL; 558 return -EINVAL;
559 559
560 if ((p->u.qpsk.fec_inner < FEC_NONE) 560 if ((p->fec_inner < FEC_NONE)
561 || (p->u.qpsk.fec_inner > FEC_AUTO)) 561 || (p->fec_inner > FEC_AUTO))
562 return -EINVAL; 562 return -EINVAL;
563 563
564 if ((p->u.qpsk.fec_inner == FEC_4_5) 564 if ((p->fec_inner == FEC_4_5)
565 || (p->u.qpsk.fec_inner == FEC_8_9)) 565 || (p->fec_inner == FEC_8_9))
566 return -EINVAL; 566 return -EINVAL;
567 567
568 switch (state->id) { 568 switch (state->id) {
@@ -574,7 +574,7 @@ static int mt312_set_frontend(struct dvb_frontend *fe,
574 ret = mt312_readreg(state, CONFIG, &config_val); 574 ret = mt312_readreg(state, CONFIG, &config_val);
575 if (ret < 0) 575 if (ret < 0)
576 return ret; 576 return ret;
577 if (p->u.qpsk.symbol_rate >= 30000000) { 577 if (p->symbol_rate >= 30000000) {
578 /* Note that 30MS/s should use 90MHz */ 578 /* Note that 30MS/s should use 90MHz */
579 if (state->freq_mult == 6) { 579 if (state->freq_mult == 6) {
580 /* We are running 60MHz */ 580 /* We are running 60MHz */
@@ -603,25 +603,25 @@ static int mt312_set_frontend(struct dvb_frontend *fe,
603 } 603 }
604 604
605 if (fe->ops.tuner_ops.set_params) { 605 if (fe->ops.tuner_ops.set_params) {
606 fe->ops.tuner_ops.set_params(fe, p); 606 fe->ops.tuner_ops.set_params(fe);
607 if (fe->ops.i2c_gate_ctrl) 607 if (fe->ops.i2c_gate_ctrl)
608 fe->ops.i2c_gate_ctrl(fe, 0); 608 fe->ops.i2c_gate_ctrl(fe, 0);
609 } 609 }
610 610
611 /* sr = (u16)(sr * 256.0 / 1000000.0) */ 611 /* sr = (u16)(sr * 256.0 / 1000000.0) */
612 sr = mt312_div(p->u.qpsk.symbol_rate * 4, 15625); 612 sr = mt312_div(p->symbol_rate * 4, 15625);
613 613
614 /* SYM_RATE */ 614 /* SYM_RATE */
615 buf[0] = (sr >> 8) & 0x3f; 615 buf[0] = (sr >> 8) & 0x3f;
616 buf[1] = (sr >> 0) & 0xff; 616 buf[1] = (sr >> 0) & 0xff;
617 617
618 /* VIT_MODE */ 618 /* VIT_MODE */
619 buf[2] = inv_tab[p->inversion] | fec_tab[p->u.qpsk.fec_inner]; 619 buf[2] = inv_tab[p->inversion] | fec_tab[p->fec_inner];
620 620
621 /* QPSK_CTRL */ 621 /* QPSK_CTRL */
622 buf[3] = 0x40; /* swap I and Q before QPSK demodulation */ 622 buf[3] = 0x40; /* swap I and Q before QPSK demodulation */
623 623
624 if (p->u.qpsk.symbol_rate < 10000000) 624 if (p->symbol_rate < 10000000)
625 buf[3] |= 0x04; /* use afc mode */ 625 buf[3] |= 0x04; /* use afc mode */
626 626
627 /* GO */ 627 /* GO */
@@ -636,9 +636,9 @@ static int mt312_set_frontend(struct dvb_frontend *fe,
636 return 0; 636 return 0;
637} 637}
638 638
639static int mt312_get_frontend(struct dvb_frontend *fe, 639static int mt312_get_frontend(struct dvb_frontend *fe)
640 struct dvb_frontend_parameters *p)
641{ 640{
641 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
642 struct mt312_state *state = fe->demodulator_priv; 642 struct mt312_state *state = fe->demodulator_priv;
643 int ret; 643 int ret;
644 644
@@ -646,11 +646,11 @@ static int mt312_get_frontend(struct dvb_frontend *fe,
646 if (ret < 0) 646 if (ret < 0)
647 return ret; 647 return ret;
648 648
649 ret = mt312_get_symbol_rate(state, &p->u.qpsk.symbol_rate); 649 ret = mt312_get_symbol_rate(state, &p->symbol_rate);
650 if (ret < 0) 650 if (ret < 0)
651 return ret; 651 return ret;
652 652
653 ret = mt312_get_code_rate(state, &p->u.qpsk.fec_inner); 653 ret = mt312_get_code_rate(state, &p->fec_inner);
654 if (ret < 0) 654 if (ret < 0)
655 return ret; 655 return ret;
656 656
@@ -738,10 +738,9 @@ static void mt312_release(struct dvb_frontend *fe)
738 738
739#define MT312_SYS_CLK 90000000UL /* 90 MHz */ 739#define MT312_SYS_CLK 90000000UL /* 90 MHz */
740static struct dvb_frontend_ops mt312_ops = { 740static struct dvb_frontend_ops mt312_ops = {
741 741 .delsys = { SYS_DVBS },
742 .info = { 742 .info = {
743 .name = "Zarlink ???? DVB-S", 743 .name = "Zarlink ???? DVB-S",
744 .type = FE_QPSK,
745 .frequency_min = 950000, 744 .frequency_min = 950000,
746 .frequency_max = 2150000, 745 .frequency_max = 2150000,
747 /* FIXME: adjust freq to real used xtal */ 746 /* FIXME: adjust freq to real used xtal */
diff --git a/drivers/media/dvb/frontends/mt352.c b/drivers/media/dvb/frontends/mt352.c
index 319672f8e1a7..2c3b50e828d7 100644
--- a/drivers/media/dvb/frontends/mt352.c
+++ b/drivers/media/dvb/frontends/mt352.c
@@ -111,20 +111,20 @@ static int mt352_sleep(struct dvb_frontend* fe)
111} 111}
112 112
113static void mt352_calc_nominal_rate(struct mt352_state* state, 113static void mt352_calc_nominal_rate(struct mt352_state* state,
114 enum fe_bandwidth bandwidth, 114 u32 bandwidth,
115 unsigned char *buf) 115 unsigned char *buf)
116{ 116{
117 u32 adc_clock = 20480; /* 20.340 MHz */ 117 u32 adc_clock = 20480; /* 20.340 MHz */
118 u32 bw,value; 118 u32 bw,value;
119 119
120 switch (bandwidth) { 120 switch (bandwidth) {
121 case BANDWIDTH_6_MHZ: 121 case 6000000:
122 bw = 6; 122 bw = 6;
123 break; 123 break;
124 case BANDWIDTH_7_MHZ: 124 case 7000000:
125 bw = 7; 125 bw = 7;
126 break; 126 break;
127 case BANDWIDTH_8_MHZ: 127 case 8000000:
128 default: 128 default:
129 bw = 8; 129 bw = 8;
130 break; 130 break;
@@ -166,15 +166,14 @@ static void mt352_calc_input_freq(struct mt352_state* state,
166 buf[1] = lsb(value); 166 buf[1] = lsb(value);
167} 167}
168 168
169static int mt352_set_parameters(struct dvb_frontend* fe, 169static int mt352_set_parameters(struct dvb_frontend *fe)
170 struct dvb_frontend_parameters *param)
171{ 170{
171 struct dtv_frontend_properties *op = &fe->dtv_property_cache;
172 struct mt352_state* state = fe->demodulator_priv; 172 struct mt352_state* state = fe->demodulator_priv;
173 unsigned char buf[13]; 173 unsigned char buf[13];
174 static unsigned char tuner_go[] = { 0x5d, 0x01 }; 174 static unsigned char tuner_go[] = { 0x5d, 0x01 };
175 static unsigned char fsm_go[] = { 0x5e, 0x01 }; 175 static unsigned char fsm_go[] = { 0x5e, 0x01 };
176 unsigned int tps = 0; 176 unsigned int tps = 0;
177 struct dvb_ofdm_parameters *op = &param->u.ofdm;
178 177
179 switch (op->code_rate_HP) { 178 switch (op->code_rate_HP) {
180 case FEC_2_3: 179 case FEC_2_3:
@@ -213,14 +212,14 @@ static int mt352_set_parameters(struct dvb_frontend* fe,
213 case FEC_AUTO: 212 case FEC_AUTO:
214 break; 213 break;
215 case FEC_NONE: 214 case FEC_NONE:
216 if (op->hierarchy_information == HIERARCHY_AUTO || 215 if (op->hierarchy == HIERARCHY_AUTO ||
217 op->hierarchy_information == HIERARCHY_NONE) 216 op->hierarchy == HIERARCHY_NONE)
218 break; 217 break;
219 default: 218 default:
220 return -EINVAL; 219 return -EINVAL;
221 } 220 }
222 221
223 switch (op->constellation) { 222 switch (op->modulation) {
224 case QPSK: 223 case QPSK:
225 break; 224 break;
226 case QAM_AUTO: 225 case QAM_AUTO:
@@ -262,7 +261,7 @@ static int mt352_set_parameters(struct dvb_frontend* fe,
262 return -EINVAL; 261 return -EINVAL;
263 } 262 }
264 263
265 switch (op->hierarchy_information) { 264 switch (op->hierarchy) {
266 case HIERARCHY_AUTO: 265 case HIERARCHY_AUTO:
267 case HIERARCHY_NONE: 266 case HIERARCHY_NONE:
268 break; 267 break;
@@ -288,12 +287,12 @@ static int mt352_set_parameters(struct dvb_frontend* fe,
288 buf[3] = 0x50; // old 287 buf[3] = 0x50; // old
289// buf[3] = 0xf4; // pinnacle 288// buf[3] = 0xf4; // pinnacle
290 289
291 mt352_calc_nominal_rate(state, op->bandwidth, buf+4); 290 mt352_calc_nominal_rate(state, op->bandwidth_hz, buf+4);
292 mt352_calc_input_freq(state, buf+6); 291 mt352_calc_input_freq(state, buf+6);
293 292
294 if (state->config.no_tuner) { 293 if (state->config.no_tuner) {
295 if (fe->ops.tuner_ops.set_params) { 294 if (fe->ops.tuner_ops.set_params) {
296 fe->ops.tuner_ops.set_params(fe, param); 295 fe->ops.tuner_ops.set_params(fe);
297 if (fe->ops.i2c_gate_ctrl) 296 if (fe->ops.i2c_gate_ctrl)
298 fe->ops.i2c_gate_ctrl(fe, 0); 297 fe->ops.i2c_gate_ctrl(fe, 0);
299 } 298 }
@@ -302,7 +301,7 @@ static int mt352_set_parameters(struct dvb_frontend* fe,
302 _mt352_write(fe, fsm_go, 2); 301 _mt352_write(fe, fsm_go, 2);
303 } else { 302 } else {
304 if (fe->ops.tuner_ops.calc_regs) { 303 if (fe->ops.tuner_ops.calc_regs) {
305 fe->ops.tuner_ops.calc_regs(fe, param, buf+8, 5); 304 fe->ops.tuner_ops.calc_regs(fe, buf+8, 5);
306 buf[8] <<= 1; 305 buf[8] <<= 1;
307 _mt352_write(fe, buf, sizeof(buf)); 306 _mt352_write(fe, buf, sizeof(buf));
308 _mt352_write(fe, tuner_go, 2); 307 _mt352_write(fe, tuner_go, 2);
@@ -312,14 +311,13 @@ static int mt352_set_parameters(struct dvb_frontend* fe,
312 return 0; 311 return 0;
313} 312}
314 313
315static int mt352_get_parameters(struct dvb_frontend* fe, 314static int mt352_get_parameters(struct dvb_frontend* fe)
316 struct dvb_frontend_parameters *param)
317{ 315{
316 struct dtv_frontend_properties *op = &fe->dtv_property_cache;
318 struct mt352_state* state = fe->demodulator_priv; 317 struct mt352_state* state = fe->demodulator_priv;
319 u16 tps; 318 u16 tps;
320 u16 div; 319 u16 div;
321 u8 trl; 320 u8 trl;
322 struct dvb_ofdm_parameters *op = &param->u.ofdm;
323 static const u8 tps_fec_to_api[8] = 321 static const u8 tps_fec_to_api[8] =
324 { 322 {
325 FEC_1_2, 323 FEC_1_2,
@@ -348,16 +346,16 @@ static int mt352_get_parameters(struct dvb_frontend* fe,
348 switch ( (tps >> 13) & 3) 346 switch ( (tps >> 13) & 3)
349 { 347 {
350 case 0: 348 case 0:
351 op->constellation = QPSK; 349 op->modulation = QPSK;
352 break; 350 break;
353 case 1: 351 case 1:
354 op->constellation = QAM_16; 352 op->modulation = QAM_16;
355 break; 353 break;
356 case 2: 354 case 2:
357 op->constellation = QAM_64; 355 op->modulation = QAM_64;
358 break; 356 break;
359 default: 357 default:
360 op->constellation = QAM_AUTO; 358 op->modulation = QAM_AUTO;
361 break; 359 break;
362 } 360 }
363 361
@@ -385,36 +383,36 @@ static int mt352_get_parameters(struct dvb_frontend* fe,
385 switch ( (tps >> 10) & 7) 383 switch ( (tps >> 10) & 7)
386 { 384 {
387 case 0: 385 case 0:
388 op->hierarchy_information = HIERARCHY_NONE; 386 op->hierarchy = HIERARCHY_NONE;
389 break; 387 break;
390 case 1: 388 case 1:
391 op->hierarchy_information = HIERARCHY_1; 389 op->hierarchy = HIERARCHY_1;
392 break; 390 break;
393 case 2: 391 case 2:
394 op->hierarchy_information = HIERARCHY_2; 392 op->hierarchy = HIERARCHY_2;
395 break; 393 break;
396 case 3: 394 case 3:
397 op->hierarchy_information = HIERARCHY_4; 395 op->hierarchy = HIERARCHY_4;
398 break; 396 break;
399 default: 397 default:
400 op->hierarchy_information = HIERARCHY_AUTO; 398 op->hierarchy = HIERARCHY_AUTO;
401 break; 399 break;
402 } 400 }
403 401
404 param->frequency = ( 500 * (div - IF_FREQUENCYx6) ) / 3 * 1000; 402 op->frequency = (500 * (div - IF_FREQUENCYx6)) / 3 * 1000;
405 403
406 if (trl == 0x72) 404 if (trl == 0x72)
407 op->bandwidth = BANDWIDTH_8_MHZ; 405 op->bandwidth_hz = 8000000;
408 else if (trl == 0x64) 406 else if (trl == 0x64)
409 op->bandwidth = BANDWIDTH_7_MHZ; 407 op->bandwidth_hz = 7000000;
410 else 408 else
411 op->bandwidth = BANDWIDTH_6_MHZ; 409 op->bandwidth_hz = 6000000;
412 410
413 411
414 if (mt352_read_register(state, STATUS_2) & 0x02) 412 if (mt352_read_register(state, STATUS_2) & 0x02)
415 param->inversion = INVERSION_OFF; 413 op->inversion = INVERSION_OFF;
416 else 414 else
417 param->inversion = INVERSION_ON; 415 op->inversion = INVERSION_ON;
418 416
419 return 0; 417 return 0;
420} 418}
@@ -569,10 +567,9 @@ error:
569} 567}
570 568
571static struct dvb_frontend_ops mt352_ops = { 569static struct dvb_frontend_ops mt352_ops = {
572 570 .delsys = { SYS_DVBT },
573 .info = { 571 .info = {
574 .name = "Zarlink MT352 DVB-T", 572 .name = "Zarlink MT352 DVB-T",
575 .type = FE_OFDM,
576 .frequency_min = 174000000, 573 .frequency_min = 174000000,
577 .frequency_max = 862000000, 574 .frequency_max = 862000000,
578 .frequency_stepsize = 166667, 575 .frequency_stepsize = 166667,
diff --git a/drivers/media/dvb/frontends/nxt200x.c b/drivers/media/dvb/frontends/nxt200x.c
index eac20650499f..49ca78d883b1 100644
--- a/drivers/media/dvb/frontends/nxt200x.c
+++ b/drivers/media/dvb/frontends/nxt200x.c
@@ -528,9 +528,9 @@ static int nxt2004_load_firmware (struct dvb_frontend* fe, const struct firmware
528 return 0; 528 return 0;
529}; 529};
530 530
531static int nxt200x_setup_frontend_parameters (struct dvb_frontend* fe, 531static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe)
532 struct dvb_frontend_parameters *p)
533{ 532{
533 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
534 struct nxt200x_state* state = fe->demodulator_priv; 534 struct nxt200x_state* state = fe->demodulator_priv;
535 u8 buf[5]; 535 u8 buf[5];
536 536
@@ -546,7 +546,7 @@ static int nxt200x_setup_frontend_parameters (struct dvb_frontend* fe,
546 } 546 }
547 547
548 /* set additional params */ 548 /* set additional params */
549 switch (p->u.vsb.modulation) { 549 switch (p->modulation) {
550 case QAM_64: 550 case QAM_64:
551 case QAM_256: 551 case QAM_256:
552 /* Set punctured clock for QAM */ 552 /* Set punctured clock for QAM */
@@ -566,7 +566,7 @@ static int nxt200x_setup_frontend_parameters (struct dvb_frontend* fe,
566 566
567 if (fe->ops.tuner_ops.calc_regs) { 567 if (fe->ops.tuner_ops.calc_regs) {
568 /* get tuning information */ 568 /* get tuning information */
569 fe->ops.tuner_ops.calc_regs(fe, p, buf, 5); 569 fe->ops.tuner_ops.calc_regs(fe, buf, 5);
570 570
571 /* write frequency information */ 571 /* write frequency information */
572 nxt200x_writetuner(state, buf); 572 nxt200x_writetuner(state, buf);
@@ -576,7 +576,7 @@ static int nxt200x_setup_frontend_parameters (struct dvb_frontend* fe,
576 nxt200x_agc_reset(state); 576 nxt200x_agc_reset(state);
577 577
578 /* set target power level */ 578 /* set target power level */
579 switch (p->u.vsb.modulation) { 579 switch (p->modulation) {
580 case QAM_64: 580 case QAM_64:
581 case QAM_256: 581 case QAM_256:
582 buf[0] = 0x74; 582 buf[0] = 0x74;
@@ -620,7 +620,7 @@ static int nxt200x_setup_frontend_parameters (struct dvb_frontend* fe,
620 } 620 }
621 621
622 /* write sdmx input */ 622 /* write sdmx input */
623 switch (p->u.vsb.modulation) { 623 switch (p->modulation) {
624 case QAM_64: 624 case QAM_64:
625 buf[0] = 0x68; 625 buf[0] = 0x68;
626 break; 626 break;
@@ -714,7 +714,7 @@ static int nxt200x_setup_frontend_parameters (struct dvb_frontend* fe,
714 } 714 }
715 715
716 /* write agc ucgp0 */ 716 /* write agc ucgp0 */
717 switch (p->u.vsb.modulation) { 717 switch (p->modulation) {
718 case QAM_64: 718 case QAM_64:
719 buf[0] = 0x02; 719 buf[0] = 0x02;
720 break; 720 break;
@@ -1203,10 +1203,9 @@ error:
1203} 1203}
1204 1204
1205static struct dvb_frontend_ops nxt200x_ops = { 1205static struct dvb_frontend_ops nxt200x_ops = {
1206 1206 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1207 .info = { 1207 .info = {
1208 .name = "Nextwave NXT200X VSB/QAM frontend", 1208 .name = "Nextwave NXT200X VSB/QAM frontend",
1209 .type = FE_ATSC,
1210 .frequency_min = 54000000, 1209 .frequency_min = 54000000,
1211 .frequency_max = 860000000, 1210 .frequency_max = 860000000,
1212 .frequency_stepsize = 166666, /* stepsize is just a guess */ 1211 .frequency_stepsize = 166666, /* stepsize is just a guess */
diff --git a/drivers/media/dvb/frontends/nxt6000.c b/drivers/media/dvb/frontends/nxt6000.c
index 6599b8fea9e9..90ae6c72c0e3 100644
--- a/drivers/media/dvb/frontends/nxt6000.c
+++ b/drivers/media/dvb/frontends/nxt6000.c
@@ -81,22 +81,21 @@ static void nxt6000_reset(struct nxt6000_state* state)
81 nxt6000_writereg(state, OFDM_COR_CTL, val | COREACT); 81 nxt6000_writereg(state, OFDM_COR_CTL, val | COREACT);
82} 82}
83 83
84static int nxt6000_set_bandwidth(struct nxt6000_state* state, fe_bandwidth_t bandwidth) 84static int nxt6000_set_bandwidth(struct nxt6000_state *state, u32 bandwidth)
85{ 85{
86 u16 nominal_rate; 86 u16 nominal_rate;
87 int result; 87 int result;
88 88
89 switch (bandwidth) { 89 switch (bandwidth) {
90 90 case 6000000:
91 case BANDWIDTH_6_MHZ:
92 nominal_rate = 0x55B7; 91 nominal_rate = 0x55B7;
93 break; 92 break;
94 93
95 case BANDWIDTH_7_MHZ: 94 case 7000000:
96 nominal_rate = 0x6400; 95 nominal_rate = 0x6400;
97 break; 96 break;
98 97
99 case BANDWIDTH_8_MHZ: 98 case 8000000:
100 nominal_rate = 0x7249; 99 nominal_rate = 0x7249;
101 break; 100 break;
102 101
@@ -457,23 +456,31 @@ static int nxt6000_init(struct dvb_frontend* fe)
457 return 0; 456 return 0;
458} 457}
459 458
460static int nxt6000_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *param) 459static int nxt6000_set_frontend(struct dvb_frontend *fe)
461{ 460{
461 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
462 struct nxt6000_state* state = fe->demodulator_priv; 462 struct nxt6000_state* state = fe->demodulator_priv;
463 int result; 463 int result;
464 464
465 if (fe->ops.tuner_ops.set_params) { 465 if (fe->ops.tuner_ops.set_params) {
466 fe->ops.tuner_ops.set_params(fe, param); 466 fe->ops.tuner_ops.set_params(fe);
467 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 467 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
468 } 468 }
469 469
470 if ((result = nxt6000_set_bandwidth(state, param->u.ofdm.bandwidth)) < 0) 470 result = nxt6000_set_bandwidth(state, p->bandwidth_hz);
471 if (result < 0)
471 return result; 472 return result;
472 if ((result = nxt6000_set_guard_interval(state, param->u.ofdm.guard_interval)) < 0) 473
474 result = nxt6000_set_guard_interval(state, p->guard_interval);
475 if (result < 0)
473 return result; 476 return result;
474 if ((result = nxt6000_set_transmission_mode(state, param->u.ofdm.transmission_mode)) < 0) 477
478 result = nxt6000_set_transmission_mode(state, p->transmission_mode);
479 if (result < 0)
475 return result; 480 return result;
476 if ((result = nxt6000_set_inversion(state, param->inversion)) < 0) 481
482 result = nxt6000_set_inversion(state, p->inversion);
483 if (result < 0)
477 return result; 484 return result;
478 485
479 msleep(500); 486 msleep(500);
@@ -566,10 +573,9 @@ error:
566} 573}
567 574
568static struct dvb_frontend_ops nxt6000_ops = { 575static struct dvb_frontend_ops nxt6000_ops = {
569 576 .delsys = { SYS_DVBT },
570 .info = { 577 .info = {
571 .name = "NxtWave NXT6000 DVB-T", 578 .name = "NxtWave NXT6000 DVB-T",
572 .type = FE_OFDM,
573 .frequency_min = 0, 579 .frequency_min = 0,
574 .frequency_max = 863250000, 580 .frequency_max = 863250000,
575 .frequency_stepsize = 62500, 581 .frequency_stepsize = 62500,
diff --git a/drivers/media/dvb/frontends/or51132.c b/drivers/media/dvb/frontends/or51132.c
index 38e67accb8c3..5ef921823c15 100644
--- a/drivers/media/dvb/frontends/or51132.c
+++ b/drivers/media/dvb/frontends/or51132.c
@@ -306,9 +306,9 @@ static int modulation_fw_class(fe_modulation_t modulation)
306 } 306 }
307} 307}
308 308
309static int or51132_set_parameters(struct dvb_frontend* fe, 309static int or51132_set_parameters(struct dvb_frontend *fe)
310 struct dvb_frontend_parameters *param)
311{ 310{
311 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
312 int ret; 312 int ret;
313 struct or51132_state* state = fe->demodulator_priv; 313 struct or51132_state* state = fe->demodulator_priv;
314 const struct firmware *fw; 314 const struct firmware *fw;
@@ -317,8 +317,8 @@ static int or51132_set_parameters(struct dvb_frontend* fe,
317 317
318 /* Upload new firmware only if we need a different one */ 318 /* Upload new firmware only if we need a different one */
319 if (modulation_fw_class(state->current_modulation) != 319 if (modulation_fw_class(state->current_modulation) !=
320 modulation_fw_class(param->u.vsb.modulation)) { 320 modulation_fw_class(p->modulation)) {
321 switch(modulation_fw_class(param->u.vsb.modulation)) { 321 switch (modulation_fw_class(p->modulation)) {
322 case MOD_FWCLASS_VSB: 322 case MOD_FWCLASS_VSB:
323 dprintk("set_parameters VSB MODE\n"); 323 dprintk("set_parameters VSB MODE\n");
324 fwname = OR51132_VSB_FIRMWARE; 324 fwname = OR51132_VSB_FIRMWARE;
@@ -335,7 +335,7 @@ static int or51132_set_parameters(struct dvb_frontend* fe,
335 break; 335 break;
336 default: 336 default:
337 printk("or51132: Modulation type(%d) UNSUPPORTED\n", 337 printk("or51132: Modulation type(%d) UNSUPPORTED\n",
338 param->u.vsb.modulation); 338 p->modulation);
339 return -1; 339 return -1;
340 } 340 }
341 printk("or51132: Waiting for firmware upload(%s)...\n", 341 printk("or51132: Waiting for firmware upload(%s)...\n",
@@ -357,13 +357,13 @@ static int or51132_set_parameters(struct dvb_frontend* fe,
357 state->config->set_ts_params(fe, clock_mode); 357 state->config->set_ts_params(fe, clock_mode);
358 } 358 }
359 /* Change only if we are actually changing the modulation */ 359 /* Change only if we are actually changing the modulation */
360 if (state->current_modulation != param->u.vsb.modulation) { 360 if (state->current_modulation != p->modulation) {
361 state->current_modulation = param->u.vsb.modulation; 361 state->current_modulation = p->modulation;
362 or51132_setmode(fe); 362 or51132_setmode(fe);
363 } 363 }
364 364
365 if (fe->ops.tuner_ops.set_params) { 365 if (fe->ops.tuner_ops.set_params) {
366 fe->ops.tuner_ops.set_params(fe, param); 366 fe->ops.tuner_ops.set_params(fe);
367 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 367 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
368 } 368 }
369 369
@@ -371,13 +371,13 @@ static int or51132_set_parameters(struct dvb_frontend* fe,
371 or51132_setmode(fe); 371 or51132_setmode(fe);
372 372
373 /* Update current frequency */ 373 /* Update current frequency */
374 state->current_frequency = param->frequency; 374 state->current_frequency = p->frequency;
375 return 0; 375 return 0;
376} 376}
377 377
378static int or51132_get_parameters(struct dvb_frontend* fe, 378static int or51132_get_parameters(struct dvb_frontend* fe)
379 struct dvb_frontend_parameters *param)
380{ 379{
380 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
381 struct or51132_state* state = fe->demodulator_priv; 381 struct or51132_state* state = fe->demodulator_priv;
382 int status; 382 int status;
383 int retry = 1; 383 int retry = 1;
@@ -389,21 +389,28 @@ start:
389 return -EREMOTEIO; 389 return -EREMOTEIO;
390 } 390 }
391 switch(status&0xff) { 391 switch(status&0xff) {
392 case 0x06: param->u.vsb.modulation = VSB_8; break; 392 case 0x06:
393 case 0x43: param->u.vsb.modulation = QAM_64; break; 393 p->modulation = VSB_8;
394 case 0x45: param->u.vsb.modulation = QAM_256; break; 394 break;
395 default: 395 case 0x43:
396 if (retry--) goto start; 396 p->modulation = QAM_64;
397 printk(KERN_WARNING "or51132: unknown status 0x%02x\n", 397 break;
398 status&0xff); 398 case 0x45:
399 return -EREMOTEIO; 399 p->modulation = QAM_256;
400 break;
401 default:
402 if (retry--)
403 goto start;
404 printk(KERN_WARNING "or51132: unknown status 0x%02x\n",
405 status&0xff);
406 return -EREMOTEIO;
400 } 407 }
401 408
402 /* FIXME: Read frequency from frontend, take AFC into account */ 409 /* FIXME: Read frequency from frontend, take AFC into account */
403 param->frequency = state->current_frequency; 410 p->frequency = state->current_frequency;
404 411
405 /* FIXME: How to read inversion setting? Receiver 6 register? */ 412 /* FIXME: How to read inversion setting? Receiver 6 register? */
406 param->inversion = INVERSION_AUTO; 413 p->inversion = INVERSION_AUTO;
407 414
408 return 0; 415 return 0;
409} 416}
@@ -579,10 +586,9 @@ struct dvb_frontend* or51132_attach(const struct or51132_config* config,
579} 586}
580 587
581static struct dvb_frontend_ops or51132_ops = { 588static struct dvb_frontend_ops or51132_ops = {
582 589 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
583 .info = { 590 .info = {
584 .name = "Oren OR51132 VSB/QAM Frontend", 591 .name = "Oren OR51132 VSB/QAM Frontend",
585 .type = FE_ATSC,
586 .frequency_min = 44000000, 592 .frequency_min = 44000000,
587 .frequency_max = 958000000, 593 .frequency_max = 958000000,
588 .frequency_stepsize = 166666, 594 .frequency_stepsize = 166666,
diff --git a/drivers/media/dvb/frontends/or51211.c b/drivers/media/dvb/frontends/or51211.c
index c709ce6771c8..c625b57b4333 100644
--- a/drivers/media/dvb/frontends/or51211.c
+++ b/drivers/media/dvb/frontends/or51211.c
@@ -218,15 +218,15 @@ static int or51211_setmode(struct dvb_frontend* fe, int mode)
218 return 0; 218 return 0;
219} 219}
220 220
221static int or51211_set_parameters(struct dvb_frontend* fe, 221static int or51211_set_parameters(struct dvb_frontend *fe)
222 struct dvb_frontend_parameters *param)
223{ 222{
223 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
224 struct or51211_state* state = fe->demodulator_priv; 224 struct or51211_state* state = fe->demodulator_priv;
225 225
226 /* Change only if we are actually changing the channel */ 226 /* Change only if we are actually changing the channel */
227 if (state->current_frequency != param->frequency) { 227 if (state->current_frequency != p->frequency) {
228 if (fe->ops.tuner_ops.set_params) { 228 if (fe->ops.tuner_ops.set_params) {
229 fe->ops.tuner_ops.set_params(fe, param); 229 fe->ops.tuner_ops.set_params(fe);
230 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 230 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
231 } 231 }
232 232
@@ -234,7 +234,7 @@ static int or51211_set_parameters(struct dvb_frontend* fe,
234 or51211_setmode(fe,0); 234 or51211_setmode(fe,0);
235 235
236 /* Update current frequency */ 236 /* Update current frequency */
237 state->current_frequency = param->frequency; 237 state->current_frequency = p->frequency;
238 } 238 }
239 return 0; 239 return 0;
240} 240}
@@ -544,10 +544,9 @@ struct dvb_frontend* or51211_attach(const struct or51211_config* config,
544} 544}
545 545
546static struct dvb_frontend_ops or51211_ops = { 546static struct dvb_frontend_ops or51211_ops = {
547 547 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
548 .info = { 548 .info = {
549 .name = "Oren OR51211 VSB Frontend", 549 .name = "Oren OR51211 VSB Frontend",
550 .type = FE_ATSC,
551 .frequency_min = 44000000, 550 .frequency_min = 44000000,
552 .frequency_max = 958000000, 551 .frequency_max = 958000000,
553 .frequency_stepsize = 166666, 552 .frequency_stepsize = 166666,
diff --git a/drivers/media/dvb/frontends/s5h1409.c b/drivers/media/dvb/frontends/s5h1409.c
index 0e2f61a8978f..f71b06221e14 100644
--- a/drivers/media/dvb/frontends/s5h1409.c
+++ b/drivers/media/dvb/frontends/s5h1409.c
@@ -631,9 +631,9 @@ static void s5h1409_set_qam_interleave_mode_legacy(struct dvb_frontend *fe)
631} 631}
632 632
633/* Talk to the demod, set the FEC, GUARD, QAM settings etc */ 633/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
634static int s5h1409_set_frontend(struct dvb_frontend *fe, 634static int s5h1409_set_frontend(struct dvb_frontend *fe)
635 struct dvb_frontend_parameters *p)
636{ 635{
636 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
637 struct s5h1409_state *state = fe->demodulator_priv; 637 struct s5h1409_state *state = fe->demodulator_priv;
638 638
639 dprintk("%s(frequency=%d)\n", __func__, p->frequency); 639 dprintk("%s(frequency=%d)\n", __func__, p->frequency);
@@ -642,12 +642,12 @@ static int s5h1409_set_frontend(struct dvb_frontend *fe,
642 642
643 state->current_frequency = p->frequency; 643 state->current_frequency = p->frequency;
644 644
645 s5h1409_enable_modulation(fe, p->u.vsb.modulation); 645 s5h1409_enable_modulation(fe, p->modulation);
646 646
647 if (fe->ops.tuner_ops.set_params) { 647 if (fe->ops.tuner_ops.set_params) {
648 if (fe->ops.i2c_gate_ctrl) 648 if (fe->ops.i2c_gate_ctrl)
649 fe->ops.i2c_gate_ctrl(fe, 1); 649 fe->ops.i2c_gate_ctrl(fe, 1);
650 fe->ops.tuner_ops.set_params(fe, p); 650 fe->ops.tuner_ops.set_params(fe);
651 if (fe->ops.i2c_gate_ctrl) 651 if (fe->ops.i2c_gate_ctrl)
652 fe->ops.i2c_gate_ctrl(fe, 0); 652 fe->ops.i2c_gate_ctrl(fe, 0);
653 } 653 }
@@ -879,7 +879,36 @@ static int s5h1409_read_snr(struct dvb_frontend *fe, u16 *snr)
879static int s5h1409_read_signal_strength(struct dvb_frontend *fe, 879static int s5h1409_read_signal_strength(struct dvb_frontend *fe,
880 u16 *signal_strength) 880 u16 *signal_strength)
881{ 881{
882 return s5h1409_read_snr(fe, signal_strength); 882 /* borrowed from lgdt330x.c
883 *
884 * Calculate strength from SNR up to 35dB
885 * Even though the SNR can go higher than 35dB,
886 * there is some comfort factor in having a range of
887 * strong signals that can show at 100%
888 */
889 u16 snr;
890 u32 tmp;
891 int ret = s5h1409_read_snr(fe, &snr);
892
893 *signal_strength = 0;
894
895 if (0 == ret) {
896 /* The following calculation method was chosen
897 * purely for the sake of code re-use from the
898 * other demod drivers that use this method */
899
900 /* Convert from SNR in dB * 10 to 8.24 fixed-point */
901 tmp = (snr * ((1 << 24) / 10));
902
903 /* Convert from 8.24 fixed-point to
904 * scale the range 0 - 35*2^24 into 0 - 65535*/
905 if (tmp >= 8960 * 0x10000)
906 *signal_strength = 0xffff;
907 else
908 *signal_strength = tmp / 8960;
909 }
910
911 return ret;
883} 912}
884 913
885static int s5h1409_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 914static int s5h1409_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
@@ -896,13 +925,13 @@ static int s5h1409_read_ber(struct dvb_frontend *fe, u32 *ber)
896 return s5h1409_read_ucblocks(fe, ber); 925 return s5h1409_read_ucblocks(fe, ber);
897} 926}
898 927
899static int s5h1409_get_frontend(struct dvb_frontend *fe, 928static int s5h1409_get_frontend(struct dvb_frontend *fe)
900 struct dvb_frontend_parameters *p)
901{ 929{
930 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
902 struct s5h1409_state *state = fe->demodulator_priv; 931 struct s5h1409_state *state = fe->demodulator_priv;
903 932
904 p->frequency = state->current_frequency; 933 p->frequency = state->current_frequency;
905 p->u.vsb.modulation = state->current_modulation; 934 p->modulation = state->current_modulation;
906 935
907 return 0; 936 return 0;
908} 937}
@@ -967,10 +996,9 @@ error:
967EXPORT_SYMBOL(s5h1409_attach); 996EXPORT_SYMBOL(s5h1409_attach);
968 997
969static struct dvb_frontend_ops s5h1409_ops = { 998static struct dvb_frontend_ops s5h1409_ops = {
970 999 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
971 .info = { 1000 .info = {
972 .name = "Samsung S5H1409 QAM/8VSB Frontend", 1001 .name = "Samsung S5H1409 QAM/8VSB Frontend",
973 .type = FE_ATSC,
974 .frequency_min = 54000000, 1002 .frequency_min = 54000000,
975 .frequency_max = 858000000, 1003 .frequency_max = 858000000,
976 .frequency_stepsize = 62500, 1004 .frequency_stepsize = 62500,
diff --git a/drivers/media/dvb/frontends/s5h1411.c b/drivers/media/dvb/frontends/s5h1411.c
index d8adf1e32019..6cc4b7a9dd60 100644
--- a/drivers/media/dvb/frontends/s5h1411.c
+++ b/drivers/media/dvb/frontends/s5h1411.c
@@ -585,9 +585,9 @@ static int s5h1411_register_reset(struct dvb_frontend *fe)
585} 585}
586 586
587/* Talk to the demod, set the FEC, GUARD, QAM settings etc */ 587/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
588static int s5h1411_set_frontend(struct dvb_frontend *fe, 588static int s5h1411_set_frontend(struct dvb_frontend *fe)
589 struct dvb_frontend_parameters *p)
590{ 589{
590 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
591 struct s5h1411_state *state = fe->demodulator_priv; 591 struct s5h1411_state *state = fe->demodulator_priv;
592 592
593 dprintk("%s(frequency=%d)\n", __func__, p->frequency); 593 dprintk("%s(frequency=%d)\n", __func__, p->frequency);
@@ -596,13 +596,13 @@ static int s5h1411_set_frontend(struct dvb_frontend *fe,
596 596
597 state->current_frequency = p->frequency; 597 state->current_frequency = p->frequency;
598 598
599 s5h1411_enable_modulation(fe, p->u.vsb.modulation); 599 s5h1411_enable_modulation(fe, p->modulation);
600 600
601 if (fe->ops.tuner_ops.set_params) { 601 if (fe->ops.tuner_ops.set_params) {
602 if (fe->ops.i2c_gate_ctrl) 602 if (fe->ops.i2c_gate_ctrl)
603 fe->ops.i2c_gate_ctrl(fe, 1); 603 fe->ops.i2c_gate_ctrl(fe, 1);
604 604
605 fe->ops.tuner_ops.set_params(fe, p); 605 fe->ops.tuner_ops.set_params(fe);
606 606
607 if (fe->ops.i2c_gate_ctrl) 607 if (fe->ops.i2c_gate_ctrl)
608 fe->ops.i2c_gate_ctrl(fe, 0); 608 fe->ops.i2c_gate_ctrl(fe, 0);
@@ -794,7 +794,36 @@ static int s5h1411_read_snr(struct dvb_frontend *fe, u16 *snr)
794static int s5h1411_read_signal_strength(struct dvb_frontend *fe, 794static int s5h1411_read_signal_strength(struct dvb_frontend *fe,
795 u16 *signal_strength) 795 u16 *signal_strength)
796{ 796{
797 return s5h1411_read_snr(fe, signal_strength); 797 /* borrowed from lgdt330x.c
798 *
799 * Calculate strength from SNR up to 35dB
800 * Even though the SNR can go higher than 35dB,
801 * there is some comfort factor in having a range of
802 * strong signals that can show at 100%
803 */
804 u16 snr;
805 u32 tmp;
806 int ret = s5h1411_read_snr(fe, &snr);
807
808 *signal_strength = 0;
809
810 if (0 == ret) {
811 /* The following calculation method was chosen
812 * purely for the sake of code re-use from the
813 * other demod drivers that use this method */
814
815 /* Convert from SNR in dB * 10 to 8.24 fixed-point */
816 tmp = (snr * ((1 << 24) / 10));
817
818 /* Convert from 8.24 fixed-point to
819 * scale the range 0 - 35*2^24 into 0 - 65535*/
820 if (tmp >= 8960 * 0x10000)
821 *signal_strength = 0xffff;
822 else
823 *signal_strength = tmp / 8960;
824 }
825
826 return ret;
798} 827}
799 828
800static int s5h1411_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 829static int s5h1411_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
@@ -811,13 +840,13 @@ static int s5h1411_read_ber(struct dvb_frontend *fe, u32 *ber)
811 return s5h1411_read_ucblocks(fe, ber); 840 return s5h1411_read_ucblocks(fe, ber);
812} 841}
813 842
814static int s5h1411_get_frontend(struct dvb_frontend *fe, 843static int s5h1411_get_frontend(struct dvb_frontend *fe)
815 struct dvb_frontend_parameters *p)
816{ 844{
845 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
817 struct s5h1411_state *state = fe->demodulator_priv; 846 struct s5h1411_state *state = fe->demodulator_priv;
818 847
819 p->frequency = state->current_frequency; 848 p->frequency = state->current_frequency;
820 p->u.vsb.modulation = state->current_modulation; 849 p->modulation = state->current_modulation;
821 850
822 return 0; 851 return 0;
823} 852}
@@ -886,10 +915,9 @@ error:
886EXPORT_SYMBOL(s5h1411_attach); 915EXPORT_SYMBOL(s5h1411_attach);
887 916
888static struct dvb_frontend_ops s5h1411_ops = { 917static struct dvb_frontend_ops s5h1411_ops = {
889 918 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
890 .info = { 919 .info = {
891 .name = "Samsung S5H1411 QAM/8VSB Frontend", 920 .name = "Samsung S5H1411 QAM/8VSB Frontend",
892 .type = FE_ATSC,
893 .frequency_min = 54000000, 921 .frequency_min = 54000000,
894 .frequency_max = 858000000, 922 .frequency_max = 858000000,
895 .frequency_stepsize = 62500, 923 .frequency_stepsize = 62500,
diff --git a/drivers/media/dvb/frontends/s5h1420.c b/drivers/media/dvb/frontends/s5h1420.c
index 3879d2e378aa..2322257c69ae 100644
--- a/drivers/media/dvb/frontends/s5h1420.c
+++ b/drivers/media/dvb/frontends/s5h1420.c
@@ -472,15 +472,15 @@ static void s5h1420_reset(struct s5h1420_state* state)
472} 472}
473 473
474static void s5h1420_setsymbolrate(struct s5h1420_state* state, 474static void s5h1420_setsymbolrate(struct s5h1420_state* state,
475 struct dvb_frontend_parameters *p) 475 struct dtv_frontend_properties *p)
476{ 476{
477 u8 v; 477 u8 v;
478 u64 val; 478 u64 val;
479 479
480 dprintk("enter %s\n", __func__); 480 dprintk("enter %s\n", __func__);
481 481
482 val = ((u64) p->u.qpsk.symbol_rate / 1000ULL) * (1ULL<<24); 482 val = ((u64) p->symbol_rate / 1000ULL) * (1ULL<<24);
483 if (p->u.qpsk.symbol_rate < 29000000) 483 if (p->symbol_rate < 29000000)
484 val *= 2; 484 val *= 2;
485 do_div(val, (state->fclk / 1000)); 485 do_div(val, (state->fclk / 1000));
486 486
@@ -543,7 +543,7 @@ static int s5h1420_getfreqoffset(struct s5h1420_state* state)
543} 543}
544 544
545static void s5h1420_setfec_inversion(struct s5h1420_state* state, 545static void s5h1420_setfec_inversion(struct s5h1420_state* state,
546 struct dvb_frontend_parameters *p) 546 struct dtv_frontend_properties *p)
547{ 547{
548 u8 inversion = 0; 548 u8 inversion = 0;
549 u8 vit08, vit09; 549 u8 vit08, vit09;
@@ -555,11 +555,11 @@ static void s5h1420_setfec_inversion(struct s5h1420_state* state,
555 else if (p->inversion == INVERSION_ON) 555 else if (p->inversion == INVERSION_ON)
556 inversion = state->config->invert ? 0 : 0x08; 556 inversion = state->config->invert ? 0 : 0x08;
557 557
558 if ((p->u.qpsk.fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) { 558 if ((p->fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
559 vit08 = 0x3f; 559 vit08 = 0x3f;
560 vit09 = 0; 560 vit09 = 0;
561 } else { 561 } else {
562 switch(p->u.qpsk.fec_inner) { 562 switch (p->fec_inner) {
563 case FEC_1_2: 563 case FEC_1_2:
564 vit08 = 0x01; vit09 = 0x10; 564 vit08 = 0x01; vit09 = 0x10;
565 break; 565 break;
@@ -628,9 +628,9 @@ static fe_spectral_inversion_t s5h1420_getinversion(struct s5h1420_state* state)
628 return INVERSION_OFF; 628 return INVERSION_OFF;
629} 629}
630 630
631static int s5h1420_set_frontend(struct dvb_frontend* fe, 631static int s5h1420_set_frontend(struct dvb_frontend *fe)
632 struct dvb_frontend_parameters *p)
633{ 632{
633 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
634 struct s5h1420_state* state = fe->demodulator_priv; 634 struct s5h1420_state* state = fe->demodulator_priv;
635 int frequency_delta; 635 int frequency_delta;
636 struct dvb_frontend_tune_settings fesettings; 636 struct dvb_frontend_tune_settings fesettings;
@@ -639,17 +639,16 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
639 dprintk("enter %s\n", __func__); 639 dprintk("enter %s\n", __func__);
640 640
641 /* check if we should do a fast-tune */ 641 /* check if we should do a fast-tune */
642 memcpy(&fesettings.parameters, p, sizeof(struct dvb_frontend_parameters));
643 s5h1420_get_tune_settings(fe, &fesettings); 642 s5h1420_get_tune_settings(fe, &fesettings);
644 frequency_delta = p->frequency - state->tunedfreq; 643 frequency_delta = p->frequency - state->tunedfreq;
645 if ((frequency_delta > -fesettings.max_drift) && 644 if ((frequency_delta > -fesettings.max_drift) &&
646 (frequency_delta < fesettings.max_drift) && 645 (frequency_delta < fesettings.max_drift) &&
647 (frequency_delta != 0) && 646 (frequency_delta != 0) &&
648 (state->fec_inner == p->u.qpsk.fec_inner) && 647 (state->fec_inner == p->fec_inner) &&
649 (state->symbol_rate == p->u.qpsk.symbol_rate)) { 648 (state->symbol_rate == p->symbol_rate)) {
650 649
651 if (fe->ops.tuner_ops.set_params) { 650 if (fe->ops.tuner_ops.set_params) {
652 fe->ops.tuner_ops.set_params(fe, p); 651 fe->ops.tuner_ops.set_params(fe);
653 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 652 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
654 } 653 }
655 if (fe->ops.tuner_ops.get_frequency) { 654 if (fe->ops.tuner_ops.get_frequency) {
@@ -669,13 +668,13 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
669 s5h1420_reset(state); 668 s5h1420_reset(state);
670 669
671 /* set s5h1420 fclk PLL according to desired symbol rate */ 670 /* set s5h1420 fclk PLL according to desired symbol rate */
672 if (p->u.qpsk.symbol_rate > 33000000) 671 if (p->symbol_rate > 33000000)
673 state->fclk = 80000000; 672 state->fclk = 80000000;
674 else if (p->u.qpsk.symbol_rate > 28500000) 673 else if (p->symbol_rate > 28500000)
675 state->fclk = 59000000; 674 state->fclk = 59000000;
676 else if (p->u.qpsk.symbol_rate > 25000000) 675 else if (p->symbol_rate > 25000000)
677 state->fclk = 86000000; 676 state->fclk = 86000000;
678 else if (p->u.qpsk.symbol_rate > 1900000) 677 else if (p->symbol_rate > 1900000)
679 state->fclk = 88000000; 678 state->fclk = 88000000;
680 else 679 else
681 state->fclk = 44000000; 680 state->fclk = 44000000;
@@ -705,7 +704,7 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
705 s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32)); 704 s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
706 705
707 /* TODO DC offset removal, config parameter ? */ 706 /* TODO DC offset removal, config parameter ? */
708 if (p->u.qpsk.symbol_rate > 29000000) 707 if (p->symbol_rate > 29000000)
709 s5h1420_writereg(state, QPSK01, 0xae | 0x10); 708 s5h1420_writereg(state, QPSK01, 0xae | 0x10);
710 else 709 else
711 s5h1420_writereg(state, QPSK01, 0xac | 0x10); 710 s5h1420_writereg(state, QPSK01, 0xac | 0x10);
@@ -718,15 +717,15 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
718 s5h1420_writereg(state, Loop01, 0xF0); 717 s5h1420_writereg(state, Loop01, 0xF0);
719 s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */ 718 s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
720 s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */ 719 s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
721 if (p->u.qpsk.symbol_rate > 20000000) 720 if (p->symbol_rate > 20000000)
722 s5h1420_writereg(state, Loop04, 0x79); 721 s5h1420_writereg(state, Loop04, 0x79);
723 else 722 else
724 s5h1420_writereg(state, Loop04, 0x58); 723 s5h1420_writereg(state, Loop04, 0x58);
725 s5h1420_writereg(state, Loop05, 0x6b); 724 s5h1420_writereg(state, Loop05, 0x6b);
726 725
727 if (p->u.qpsk.symbol_rate >= 8000000) 726 if (p->symbol_rate >= 8000000)
728 s5h1420_writereg(state, Post01, (0 << 6) | 0x10); 727 s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
729 else if (p->u.qpsk.symbol_rate >= 4000000) 728 else if (p->symbol_rate >= 4000000)
730 s5h1420_writereg(state, Post01, (1 << 6) | 0x10); 729 s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
731 else 730 else
732 s5h1420_writereg(state, Post01, (3 << 6) | 0x10); 731 s5h1420_writereg(state, Post01, (3 << 6) | 0x10);
@@ -744,7 +743,7 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
744 743
745 /* set tuner PLL */ 744 /* set tuner PLL */
746 if (fe->ops.tuner_ops.set_params) { 745 if (fe->ops.tuner_ops.set_params) {
747 fe->ops.tuner_ops.set_params(fe, p); 746 fe->ops.tuner_ops.set_params(fe);
748 if (fe->ops.i2c_gate_ctrl) 747 if (fe->ops.i2c_gate_ctrl)
749 fe->ops.i2c_gate_ctrl(fe, 0); 748 fe->ops.i2c_gate_ctrl(fe, 0);
750 s5h1420_setfreqoffset(state, 0); 749 s5h1420_setfreqoffset(state, 0);
@@ -757,8 +756,8 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
757 /* start QPSK */ 756 /* start QPSK */
758 s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1); 757 s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);
759 758
760 state->fec_inner = p->u.qpsk.fec_inner; 759 state->fec_inner = p->fec_inner;
761 state->symbol_rate = p->u.qpsk.symbol_rate; 760 state->symbol_rate = p->symbol_rate;
762 state->postlocked = 0; 761 state->postlocked = 0;
763 state->tunedfreq = p->frequency; 762 state->tunedfreq = p->frequency;
764 763
@@ -766,15 +765,15 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
766 return 0; 765 return 0;
767} 766}
768 767
769static int s5h1420_get_frontend(struct dvb_frontend* fe, 768static int s5h1420_get_frontend(struct dvb_frontend* fe)
770 struct dvb_frontend_parameters *p)
771{ 769{
770 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
772 struct s5h1420_state* state = fe->demodulator_priv; 771 struct s5h1420_state* state = fe->demodulator_priv;
773 772
774 p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state); 773 p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state);
775 p->inversion = s5h1420_getinversion(state); 774 p->inversion = s5h1420_getinversion(state);
776 p->u.qpsk.symbol_rate = s5h1420_getsymbolrate(state); 775 p->symbol_rate = s5h1420_getsymbolrate(state);
777 p->u.qpsk.fec_inner = s5h1420_getfec(state); 776 p->fec_inner = s5h1420_getfec(state);
778 777
779 return 0; 778 return 0;
780} 779}
@@ -782,29 +781,30 @@ static int s5h1420_get_frontend(struct dvb_frontend* fe,
782static int s5h1420_get_tune_settings(struct dvb_frontend* fe, 781static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
783 struct dvb_frontend_tune_settings* fesettings) 782 struct dvb_frontend_tune_settings* fesettings)
784{ 783{
785 if (fesettings->parameters.u.qpsk.symbol_rate > 20000000) { 784 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
785 if (p->symbol_rate > 20000000) {
786 fesettings->min_delay_ms = 50; 786 fesettings->min_delay_ms = 50;
787 fesettings->step_size = 2000; 787 fesettings->step_size = 2000;
788 fesettings->max_drift = 8000; 788 fesettings->max_drift = 8000;
789 } else if (fesettings->parameters.u.qpsk.symbol_rate > 12000000) { 789 } else if (p->symbol_rate > 12000000) {
790 fesettings->min_delay_ms = 100; 790 fesettings->min_delay_ms = 100;
791 fesettings->step_size = 1500; 791 fesettings->step_size = 1500;
792 fesettings->max_drift = 9000; 792 fesettings->max_drift = 9000;
793 } else if (fesettings->parameters.u.qpsk.symbol_rate > 8000000) { 793 } else if (p->symbol_rate > 8000000) {
794 fesettings->min_delay_ms = 100; 794 fesettings->min_delay_ms = 100;
795 fesettings->step_size = 1000; 795 fesettings->step_size = 1000;
796 fesettings->max_drift = 8000; 796 fesettings->max_drift = 8000;
797 } else if (fesettings->parameters.u.qpsk.symbol_rate > 4000000) { 797 } else if (p->symbol_rate > 4000000) {
798 fesettings->min_delay_ms = 100; 798 fesettings->min_delay_ms = 100;
799 fesettings->step_size = 500; 799 fesettings->step_size = 500;
800 fesettings->max_drift = 7000; 800 fesettings->max_drift = 7000;
801 } else if (fesettings->parameters.u.qpsk.symbol_rate > 2000000) { 801 } else if (p->symbol_rate > 2000000) {
802 fesettings->min_delay_ms = 200; 802 fesettings->min_delay_ms = 200;
803 fesettings->step_size = (fesettings->parameters.u.qpsk.symbol_rate / 8000); 803 fesettings->step_size = (p->symbol_rate / 8000);
804 fesettings->max_drift = 14 * fesettings->step_size; 804 fesettings->max_drift = 14 * fesettings->step_size;
805 } else { 805 } else {
806 fesettings->min_delay_ms = 200; 806 fesettings->min_delay_ms = 200;
807 fesettings->step_size = (fesettings->parameters.u.qpsk.symbol_rate / 8000); 807 fesettings->step_size = (p->symbol_rate / 8000);
808 fesettings->max_drift = 18 * fesettings->step_size; 808 fesettings->max_drift = 18 * fesettings->step_size;
809 } 809 }
810 810
@@ -937,10 +937,9 @@ error:
937EXPORT_SYMBOL(s5h1420_attach); 937EXPORT_SYMBOL(s5h1420_attach);
938 938
939static struct dvb_frontend_ops s5h1420_ops = { 939static struct dvb_frontend_ops s5h1420_ops = {
940 940 .delsys = { SYS_DVBS },
941 .info = { 941 .info = {
942 .name = "Samsung S5H1420/PnpNetwork PN1010 DVB-S", 942 .name = "Samsung S5H1420/PnpNetwork PN1010 DVB-S",
943 .type = FE_QPSK,
944 .frequency_min = 950000, 943 .frequency_min = 950000,
945 .frequency_max = 2150000, 944 .frequency_max = 2150000,
946 .frequency_stepsize = 125, /* kHz for QPSK frontends */ 945 .frequency_stepsize = 125, /* kHz for QPSK frontends */
diff --git a/drivers/media/dvb/frontends/s5h1432.c b/drivers/media/dvb/frontends/s5h1432.c
index 0c6dcb90d168..8352ce1c9556 100644
--- a/drivers/media/dvb/frontends/s5h1432.c
+++ b/drivers/media/dvb/frontends/s5h1432.c
@@ -178,9 +178,9 @@ static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz)
178} 178}
179 179
180/* Talk to the demod, set the FEC, GUARD, QAM settings etc */ 180/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
181static int s5h1432_set_frontend(struct dvb_frontend *fe, 181static int s5h1432_set_frontend(struct dvb_frontend *fe)
182 struct dvb_frontend_parameters *p)
183{ 182{
183 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
184 u32 dvb_bandwidth = 8; 184 u32 dvb_bandwidth = 8;
185 struct s5h1432_state *state = fe->demodulator_priv; 185 struct s5h1432_state *state = fe->demodulator_priv;
186 186
@@ -188,26 +188,26 @@ static int s5h1432_set_frontend(struct dvb_frontend *fe,
188 /*current_frequency = p->frequency; */ 188 /*current_frequency = p->frequency; */
189 /*state->current_frequency = p->frequency; */ 189 /*state->current_frequency = p->frequency; */
190 } else { 190 } else {
191 fe->ops.tuner_ops.set_params(fe, p); 191 fe->ops.tuner_ops.set_params(fe);
192 msleep(300); 192 msleep(300);
193 s5h1432_set_channel_bandwidth(fe, dvb_bandwidth); 193 s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
194 switch (p->u.ofdm.bandwidth) { 194 switch (p->bandwidth_hz) {
195 case BANDWIDTH_6_MHZ: 195 case 6000000:
196 dvb_bandwidth = 6; 196 dvb_bandwidth = 6;
197 s5h1432_set_IF(fe, IF_FREQ_4_MHZ); 197 s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
198 break; 198 break;
199 case BANDWIDTH_7_MHZ: 199 case 7000000:
200 dvb_bandwidth = 7; 200 dvb_bandwidth = 7;
201 s5h1432_set_IF(fe, IF_FREQ_4_MHZ); 201 s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
202 break; 202 break;
203 case BANDWIDTH_8_MHZ: 203 case 8000000:
204 dvb_bandwidth = 8; 204 dvb_bandwidth = 8;
205 s5h1432_set_IF(fe, IF_FREQ_4_MHZ); 205 s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
206 break; 206 break;
207 default: 207 default:
208 return 0; 208 return 0;
209 } 209 }
210 /*fe->ops.tuner_ops.set_params(fe, p); */ 210 /*fe->ops.tuner_ops.set_params(fe); */
211/*Soft Reset chip*/ 211/*Soft Reset chip*/
212 msleep(30); 212 msleep(30);
213 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a); 213 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
@@ -215,23 +215,23 @@ static int s5h1432_set_frontend(struct dvb_frontend *fe,
215 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b); 215 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
216 216
217 s5h1432_set_channel_bandwidth(fe, dvb_bandwidth); 217 s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
218 switch (p->u.ofdm.bandwidth) { 218 switch (p->bandwidth_hz) {
219 case BANDWIDTH_6_MHZ: 219 case 6000000:
220 dvb_bandwidth = 6; 220 dvb_bandwidth = 6;
221 s5h1432_set_IF(fe, IF_FREQ_4_MHZ); 221 s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
222 break; 222 break;
223 case BANDWIDTH_7_MHZ: 223 case 7000000:
224 dvb_bandwidth = 7; 224 dvb_bandwidth = 7;
225 s5h1432_set_IF(fe, IF_FREQ_4_MHZ); 225 s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
226 break; 226 break;
227 case BANDWIDTH_8_MHZ: 227 case 8000000:
228 dvb_bandwidth = 8; 228 dvb_bandwidth = 8;
229 s5h1432_set_IF(fe, IF_FREQ_4_MHZ); 229 s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
230 break; 230 break;
231 default: 231 default:
232 return 0; 232 return 0;
233 } 233 }
234 /*fe->ops.tuner_ops.set_params(fe,p); */ 234 /*fe->ops.tuner_ops.set_params(fe); */
235 /*Soft Reset chip*/ 235 /*Soft Reset chip*/
236 msleep(30); 236 msleep(30);
237 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a); 237 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
@@ -329,12 +329,6 @@ static int s5h1432_read_ber(struct dvb_frontend *fe, u32 *ber)
329 return 0; 329 return 0;
330} 330}
331 331
332static int s5h1432_get_frontend(struct dvb_frontend *fe,
333 struct dvb_frontend_parameters *p)
334{
335 return 0;
336}
337
338static int s5h1432_get_tune_settings(struct dvb_frontend *fe, 332static int s5h1432_get_tune_settings(struct dvb_frontend *fe,
339 struct dvb_frontend_tune_settings *tune) 333 struct dvb_frontend_tune_settings *tune)
340{ 334{
@@ -381,10 +375,9 @@ error:
381EXPORT_SYMBOL(s5h1432_attach); 375EXPORT_SYMBOL(s5h1432_attach);
382 376
383static struct dvb_frontend_ops s5h1432_ops = { 377static struct dvb_frontend_ops s5h1432_ops = {
384 378 .delsys = { SYS_DVBT },
385 .info = { 379 .info = {
386 .name = "Samsung s5h1432 DVB-T Frontend", 380 .name = "Samsung s5h1432 DVB-T Frontend",
387 .type = FE_OFDM,
388 .frequency_min = 177000000, 381 .frequency_min = 177000000,
389 .frequency_max = 858000000, 382 .frequency_max = 858000000,
390 .frequency_stepsize = 166666, 383 .frequency_stepsize = 166666,
@@ -397,7 +390,6 @@ static struct dvb_frontend_ops s5h1432_ops = {
397 .init = s5h1432_init, 390 .init = s5h1432_init,
398 .sleep = s5h1432_sleep, 391 .sleep = s5h1432_sleep,
399 .set_frontend = s5h1432_set_frontend, 392 .set_frontend = s5h1432_set_frontend,
400 .get_frontend = s5h1432_get_frontend,
401 .get_tune_settings = s5h1432_get_tune_settings, 393 .get_tune_settings = s5h1432_get_tune_settings,
402 .read_status = s5h1432_read_status, 394 .read_status = s5h1432_read_status,
403 .read_ber = s5h1432_read_ber, 395 .read_ber = s5h1432_read_ber,
diff --git a/drivers/media/dvb/frontends/s921.c b/drivers/media/dvb/frontends/s921.c
index ca0103d5f148..cd2288c07147 100644
--- a/drivers/media/dvb/frontends/s921.c
+++ b/drivers/media/dvb/frontends/s921.c
@@ -262,9 +262,9 @@ static int s921_i2c_readreg(struct s921_state *state, u8 i2c_addr, u8 reg)
262 s921_i2c_writeregdata(state, state->config->demod_address, \ 262 s921_i2c_writeregdata(state, state->config->demod_address, \
263 regdata, ARRAY_SIZE(regdata)) 263 regdata, ARRAY_SIZE(regdata))
264 264
265static int s921_pll_tune(struct dvb_frontend *fe, 265static int s921_pll_tune(struct dvb_frontend *fe)
266 struct dvb_frontend_parameters *p)
267{ 266{
267 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
268 struct s921_state *state = fe->demodulator_priv; 268 struct s921_state *state = fe->demodulator_priv;
269 int band, rc, i; 269 int band, rc, i;
270 unsigned long f_offset; 270 unsigned long f_offset;
@@ -414,9 +414,9 @@ static int s921_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
414 return 0; 414 return 0;
415} 415}
416 416
417static int s921_set_frontend(struct dvb_frontend *fe, 417static int s921_set_frontend(struct dvb_frontend *fe)
418 struct dvb_frontend_parameters *p)
419{ 418{
419 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
420 struct s921_state *state = fe->demodulator_priv; 420 struct s921_state *state = fe->demodulator_priv;
421 int rc; 421 int rc;
422 422
@@ -424,7 +424,7 @@ static int s921_set_frontend(struct dvb_frontend *fe,
424 424
425 /* FIXME: We don't know how to use non-auto mode */ 425 /* FIXME: We don't know how to use non-auto mode */
426 426
427 rc = s921_pll_tune(fe, p); 427 rc = s921_pll_tune(fe);
428 if (rc < 0) 428 if (rc < 0)
429 return rc; 429 return rc;
430 430
@@ -433,19 +433,20 @@ static int s921_set_frontend(struct dvb_frontend *fe,
433 return 0; 433 return 0;
434} 434}
435 435
436static int s921_get_frontend(struct dvb_frontend *fe, 436static int s921_get_frontend(struct dvb_frontend *fe)
437 struct dvb_frontend_parameters *p)
438{ 437{
438 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
439 struct s921_state *state = fe->demodulator_priv; 439 struct s921_state *state = fe->demodulator_priv;
440 440
441 /* FIXME: Probably it is possible to get it from regs f1 and f2 */ 441 /* FIXME: Probably it is possible to get it from regs f1 and f2 */
442 p->frequency = state->currentfreq; 442 p->frequency = state->currentfreq;
443 p->delivery_system = SYS_ISDBT;
443 444
444 return 0; 445 return 0;
445} 446}
446 447
447static int s921_tune(struct dvb_frontend *fe, 448static int s921_tune(struct dvb_frontend *fe,
448 struct dvb_frontend_parameters *params, 449 bool re_tune,
449 unsigned int mode_flags, 450 unsigned int mode_flags,
450 unsigned int *delay, 451 unsigned int *delay,
451 fe_status_t *status) 452 fe_status_t *status)
@@ -454,8 +455,8 @@ static int s921_tune(struct dvb_frontend *fe,
454 455
455 dprintk("\n"); 456 dprintk("\n");
456 457
457 if (params != NULL) 458 if (re_tune)
458 rc = s921_set_frontend(fe, params); 459 rc = s921_set_frontend(fe);
459 460
460 if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) 461 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
461 s921_read_status(fe, status); 462 s921_read_status(fe, status);
@@ -510,10 +511,10 @@ rcor:
510EXPORT_SYMBOL(s921_attach); 511EXPORT_SYMBOL(s921_attach);
511 512
512static struct dvb_frontend_ops s921_ops = { 513static struct dvb_frontend_ops s921_ops = {
514 .delsys = { SYS_ISDBT },
513 /* Use dib8000 values per default */ 515 /* Use dib8000 values per default */
514 .info = { 516 .info = {
515 .name = "Sharp S921", 517 .name = "Sharp S921",
516 .type = FE_OFDM,
517 .frequency_min = 470000000, 518 .frequency_min = 470000000,
518 /* 519 /*
519 * Max should be 770MHz instead, according with Sharp docs, 520 * Max should be 770MHz instead, according with Sharp docs,
diff --git a/drivers/media/dvb/frontends/si21xx.c b/drivers/media/dvb/frontends/si21xx.c
index 4b0c99a08a85..a68a64800df7 100644
--- a/drivers/media/dvb/frontends/si21xx.c
+++ b/drivers/media/dvb/frontends/si21xx.c
@@ -690,20 +690,7 @@ static int si21xx_setacquire(struct dvb_frontend *fe, int symbrate,
690 return status; 690 return status;
691} 691}
692 692
693static int si21xx_set_property(struct dvb_frontend *fe, struct dtv_property *p) 693static int si21xx_set_frontend(struct dvb_frontend *fe)
694{
695 dprintk("%s(..)\n", __func__);
696 return 0;
697}
698
699static int si21xx_get_property(struct dvb_frontend *fe, struct dtv_property *p)
700{
701 dprintk("%s(..)\n", __func__);
702 return 0;
703}
704
705static int si21xx_set_frontend(struct dvb_frontend *fe,
706 struct dvb_frontend_parameters *dfp)
707{ 694{
708 struct si21xx_state *state = fe->demodulator_priv; 695 struct si21xx_state *state = fe->demodulator_priv;
709 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 696 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
@@ -877,10 +864,9 @@ static void si21xx_release(struct dvb_frontend *fe)
877} 864}
878 865
879static struct dvb_frontend_ops si21xx_ops = { 866static struct dvb_frontend_ops si21xx_ops = {
880 867 .delsys = { SYS_DVBS },
881 .info = { 868 .info = {
882 .name = "SL SI21XX DVB-S", 869 .name = "SL SI21XX DVB-S",
883 .type = FE_QPSK,
884 .frequency_min = 950000, 870 .frequency_min = 950000,
885 .frequency_max = 2150000, 871 .frequency_max = 2150000,
886 .frequency_stepsize = 125, /* kHz for QPSK frontends */ 872 .frequency_stepsize = 125, /* kHz for QPSK frontends */
@@ -908,8 +894,6 @@ static struct dvb_frontend_ops si21xx_ops = {
908 .set_tone = si21xx_set_tone, 894 .set_tone = si21xx_set_tone,
909 .set_voltage = si21xx_set_voltage, 895 .set_voltage = si21xx_set_voltage,
910 896
911 .set_property = si21xx_set_property,
912 .get_property = si21xx_get_property,
913 .set_frontend = si21xx_set_frontend, 897 .set_frontend = si21xx_set_frontend,
914}; 898};
915 899
diff --git a/drivers/media/dvb/frontends/sp8870.c b/drivers/media/dvb/frontends/sp8870.c
index b85eb60a893e..e37274c8f14e 100644
--- a/drivers/media/dvb/frontends/sp8870.c
+++ b/drivers/media/dvb/frontends/sp8870.c
@@ -168,13 +168,13 @@ static int sp8870_read_data_valid_signal(struct sp8870_state* state)
168 return (sp8870_readreg(state, 0x0D02) > 0); 168 return (sp8870_readreg(state, 0x0D02) > 0);
169} 169}
170 170
171static int configure_reg0xc05 (struct dvb_frontend_parameters *p, u16 *reg0xc05) 171static int configure_reg0xc05 (struct dtv_frontend_properties *p, u16 *reg0xc05)
172{ 172{
173 int known_parameters = 1; 173 int known_parameters = 1;
174 174
175 *reg0xc05 = 0x000; 175 *reg0xc05 = 0x000;
176 176
177 switch (p->u.ofdm.constellation) { 177 switch (p->modulation) {
178 case QPSK: 178 case QPSK:
179 break; 179 break;
180 case QAM_16: 180 case QAM_16:
@@ -190,7 +190,7 @@ static int configure_reg0xc05 (struct dvb_frontend_parameters *p, u16 *reg0xc05)
190 return -EINVAL; 190 return -EINVAL;
191 }; 191 };
192 192
193 switch (p->u.ofdm.hierarchy_information) { 193 switch (p->hierarchy) {
194 case HIERARCHY_NONE: 194 case HIERARCHY_NONE:
195 break; 195 break;
196 case HIERARCHY_1: 196 case HIERARCHY_1:
@@ -209,7 +209,7 @@ static int configure_reg0xc05 (struct dvb_frontend_parameters *p, u16 *reg0xc05)
209 return -EINVAL; 209 return -EINVAL;
210 }; 210 };
211 211
212 switch (p->u.ofdm.code_rate_HP) { 212 switch (p->code_rate_HP) {
213 case FEC_1_2: 213 case FEC_1_2:
214 break; 214 break;
215 case FEC_2_3: 215 case FEC_2_3:
@@ -245,9 +245,9 @@ static int sp8870_wake_up(struct sp8870_state* state)
245 return sp8870_writereg(state, 0xC18, 0x00D); 245 return sp8870_writereg(state, 0xC18, 0x00D);
246} 246}
247 247
248static int sp8870_set_frontend_parameters (struct dvb_frontend* fe, 248static int sp8870_set_frontend_parameters(struct dvb_frontend *fe)
249 struct dvb_frontend_parameters *p)
250{ 249{
250 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
251 struct sp8870_state* state = fe->demodulator_priv; 251 struct sp8870_state* state = fe->demodulator_priv;
252 int err; 252 int err;
253 u16 reg0xc05; 253 u16 reg0xc05;
@@ -260,7 +260,7 @@ static int sp8870_set_frontend_parameters (struct dvb_frontend* fe,
260 260
261 // set tuner parameters 261 // set tuner parameters
262 if (fe->ops.tuner_ops.set_params) { 262 if (fe->ops.tuner_ops.set_params) {
263 fe->ops.tuner_ops.set_params(fe, p); 263 fe->ops.tuner_ops.set_params(fe);
264 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 264 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
265 } 265 }
266 266
@@ -277,15 +277,15 @@ static int sp8870_set_frontend_parameters (struct dvb_frontend* fe,
277 sp8870_writereg(state, 0x030A, 0x0000); 277 sp8870_writereg(state, 0x030A, 0x0000);
278 278
279 // filter for 6/7/8 Mhz channel 279 // filter for 6/7/8 Mhz channel
280 if (p->u.ofdm.bandwidth == BANDWIDTH_6_MHZ) 280 if (p->bandwidth_hz == 6000000)
281 sp8870_writereg(state, 0x0311, 0x0002); 281 sp8870_writereg(state, 0x0311, 0x0002);
282 else if (p->u.ofdm.bandwidth == BANDWIDTH_7_MHZ) 282 else if (p->bandwidth_hz == 7000000)
283 sp8870_writereg(state, 0x0311, 0x0001); 283 sp8870_writereg(state, 0x0311, 0x0001);
284 else 284 else
285 sp8870_writereg(state, 0x0311, 0x0000); 285 sp8870_writereg(state, 0x0311, 0x0000);
286 286
287 // scan order: 2k first = 0x0000, 8k first = 0x0001 287 // scan order: 2k first = 0x0000, 8k first = 0x0001
288 if (p->u.ofdm.transmission_mode == TRANSMISSION_MODE_2K) 288 if (p->transmission_mode == TRANSMISSION_MODE_2K)
289 sp8870_writereg(state, 0x0338, 0x0000); 289 sp8870_writereg(state, 0x0338, 0x0000);
290 else 290 else
291 sp8870_writereg(state, 0x0338, 0x0001); 291 sp8870_writereg(state, 0x0338, 0x0001);
@@ -459,8 +459,9 @@ static int lockups;
459/* only for debugging: counter for channel switches */ 459/* only for debugging: counter for channel switches */
460static int switches; 460static int switches;
461 461
462static int sp8870_set_frontend (struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 462static int sp8870_set_frontend(struct dvb_frontend *fe)
463{ 463{
464 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
464 struct sp8870_state* state = fe->demodulator_priv; 465 struct sp8870_state* state = fe->demodulator_priv;
465 466
466 /* 467 /*
@@ -479,7 +480,8 @@ static int sp8870_set_frontend (struct dvb_frontend* fe, struct dvb_frontend_par
479 480
480 for (trials = 1; trials <= MAXTRIALS; trials++) { 481 for (trials = 1; trials <= MAXTRIALS; trials++) {
481 482
482 if ((err = sp8870_set_frontend_parameters(fe, p))) 483 err = sp8870_set_frontend_parameters(fe);
484 if (err)
483 return err; 485 return err;
484 486
485 for (check_count = 0; check_count < MAXCHECKS; check_count++) { 487 for (check_count = 0; check_count < MAXCHECKS; check_count++) {
@@ -579,10 +581,9 @@ error:
579} 581}
580 582
581static struct dvb_frontend_ops sp8870_ops = { 583static struct dvb_frontend_ops sp8870_ops = {
582 584 .delsys = { SYS_DVBT },
583 .info = { 585 .info = {
584 .name = "Spase SP8870 DVB-T", 586 .name = "Spase SP8870 DVB-T",
585 .type = FE_OFDM,
586 .frequency_min = 470000000, 587 .frequency_min = 470000000,
587 .frequency_max = 860000000, 588 .frequency_max = 860000000,
588 .frequency_stepsize = 166666, 589 .frequency_stepsize = 166666,
diff --git a/drivers/media/dvb/frontends/sp887x.c b/drivers/media/dvb/frontends/sp887x.c
index 4a7c3d842608..f4096ccb226e 100644
--- a/drivers/media/dvb/frontends/sp887x.c
+++ b/drivers/media/dvb/frontends/sp887x.c
@@ -209,13 +209,13 @@ static int sp887x_initial_setup (struct dvb_frontend* fe, const struct firmware
209 return 0; 209 return 0;
210}; 210};
211 211
212static int configure_reg0xc05 (struct dvb_frontend_parameters *p, u16 *reg0xc05) 212static int configure_reg0xc05(struct dtv_frontend_properties *p, u16 *reg0xc05)
213{ 213{
214 int known_parameters = 1; 214 int known_parameters = 1;
215 215
216 *reg0xc05 = 0x000; 216 *reg0xc05 = 0x000;
217 217
218 switch (p->u.ofdm.constellation) { 218 switch (p->modulation) {
219 case QPSK: 219 case QPSK:
220 break; 220 break;
221 case QAM_16: 221 case QAM_16:
@@ -231,7 +231,7 @@ static int configure_reg0xc05 (struct dvb_frontend_parameters *p, u16 *reg0xc05)
231 return -EINVAL; 231 return -EINVAL;
232 }; 232 };
233 233
234 switch (p->u.ofdm.hierarchy_information) { 234 switch (p->hierarchy) {
235 case HIERARCHY_NONE: 235 case HIERARCHY_NONE:
236 break; 236 break;
237 case HIERARCHY_1: 237 case HIERARCHY_1:
@@ -250,7 +250,7 @@ static int configure_reg0xc05 (struct dvb_frontend_parameters *p, u16 *reg0xc05)
250 return -EINVAL; 250 return -EINVAL;
251 }; 251 };
252 252
253 switch (p->u.ofdm.code_rate_HP) { 253 switch (p->code_rate_HP) {
254 case FEC_1_2: 254 case FEC_1_2:
255 break; 255 break;
256 case FEC_2_3: 256 case FEC_2_3:
@@ -303,17 +303,30 @@ static void divide (int n, int d, int *quotient_i, int *quotient_f)
303} 303}
304 304
305static void sp887x_correct_offsets (struct sp887x_state* state, 305static void sp887x_correct_offsets (struct sp887x_state* state,
306 struct dvb_frontend_parameters *p, 306 struct dtv_frontend_properties *p,
307 int actual_freq) 307 int actual_freq)
308{ 308{
309 static const u32 srate_correction [] = { 1879617, 4544878, 8098561 }; 309 static const u32 srate_correction [] = { 1879617, 4544878, 8098561 };
310 int bw_index = p->u.ofdm.bandwidth - BANDWIDTH_8_MHZ; 310 int bw_index;
311 int freq_offset = actual_freq - p->frequency; 311 int freq_offset = actual_freq - p->frequency;
312 int sysclock = 61003; //[kHz] 312 int sysclock = 61003; //[kHz]
313 int ifreq = 36000000; 313 int ifreq = 36000000;
314 int freq; 314 int freq;
315 int frequency_shift; 315 int frequency_shift;
316 316
317 switch (p->bandwidth_hz) {
318 default:
319 case 8000000:
320 bw_index = 0;
321 break;
322 case 7000000:
323 bw_index = 1;
324 break;
325 case 6000000:
326 bw_index = 2;
327 break;
328 }
329
317 if (p->inversion == INVERSION_ON) 330 if (p->inversion == INVERSION_ON)
318 freq = ifreq - freq_offset; 331 freq = ifreq - freq_offset;
319 else 332 else
@@ -333,17 +346,17 @@ static void sp887x_correct_offsets (struct sp887x_state* state,
333 sp887x_writereg(state, 0x30a, frequency_shift & 0xfff); 346 sp887x_writereg(state, 0x30a, frequency_shift & 0xfff);
334} 347}
335 348
336static int sp887x_setup_frontend_parameters (struct dvb_frontend* fe, 349static int sp887x_setup_frontend_parameters(struct dvb_frontend *fe)
337 struct dvb_frontend_parameters *p)
338{ 350{
351 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
339 struct sp887x_state* state = fe->demodulator_priv; 352 struct sp887x_state* state = fe->demodulator_priv;
340 unsigned actual_freq; 353 unsigned actual_freq;
341 int err; 354 int err;
342 u16 val, reg0xc05; 355 u16 val, reg0xc05;
343 356
344 if (p->u.ofdm.bandwidth != BANDWIDTH_8_MHZ && 357 if (p->bandwidth_hz != 8000000 &&
345 p->u.ofdm.bandwidth != BANDWIDTH_7_MHZ && 358 p->bandwidth_hz != 7000000 &&
346 p->u.ofdm.bandwidth != BANDWIDTH_6_MHZ) 359 p->bandwidth_hz != 6000000)
347 return -EINVAL; 360 return -EINVAL;
348 361
349 if ((err = configure_reg0xc05(p, &reg0xc05))) 362 if ((err = configure_reg0xc05(p, &reg0xc05)))
@@ -353,7 +366,7 @@ static int sp887x_setup_frontend_parameters (struct dvb_frontend* fe,
353 366
354 /* setup the PLL */ 367 /* setup the PLL */
355 if (fe->ops.tuner_ops.set_params) { 368 if (fe->ops.tuner_ops.set_params) {
356 fe->ops.tuner_ops.set_params(fe, p); 369 fe->ops.tuner_ops.set_params(fe);
357 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 370 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
358 } 371 }
359 if (fe->ops.tuner_ops.get_frequency) { 372 if (fe->ops.tuner_ops.get_frequency) {
@@ -369,9 +382,9 @@ static int sp887x_setup_frontend_parameters (struct dvb_frontend* fe,
369 sp887x_correct_offsets(state, p, actual_freq); 382 sp887x_correct_offsets(state, p, actual_freq);
370 383
371 /* filter for 6/7/8 Mhz channel */ 384 /* filter for 6/7/8 Mhz channel */
372 if (p->u.ofdm.bandwidth == BANDWIDTH_6_MHZ) 385 if (p->bandwidth_hz == 6000000)
373 val = 2; 386 val = 2;
374 else if (p->u.ofdm.bandwidth == BANDWIDTH_7_MHZ) 387 else if (p->bandwidth_hz == 7000000)
375 val = 1; 388 val = 1;
376 else 389 else
377 val = 0; 390 val = 0;
@@ -379,16 +392,16 @@ static int sp887x_setup_frontend_parameters (struct dvb_frontend* fe,
379 sp887x_writereg(state, 0x311, val); 392 sp887x_writereg(state, 0x311, val);
380 393
381 /* scan order: 2k first = 0, 8k first = 1 */ 394 /* scan order: 2k first = 0, 8k first = 1 */
382 if (p->u.ofdm.transmission_mode == TRANSMISSION_MODE_2K) 395 if (p->transmission_mode == TRANSMISSION_MODE_2K)
383 sp887x_writereg(state, 0x338, 0x000); 396 sp887x_writereg(state, 0x338, 0x000);
384 else 397 else
385 sp887x_writereg(state, 0x338, 0x001); 398 sp887x_writereg(state, 0x338, 0x001);
386 399
387 sp887x_writereg(state, 0xc05, reg0xc05); 400 sp887x_writereg(state, 0xc05, reg0xc05);
388 401
389 if (p->u.ofdm.bandwidth == BANDWIDTH_6_MHZ) 402 if (p->bandwidth_hz == 6000000)
390 val = 2 << 3; 403 val = 2 << 3;
391 else if (p->u.ofdm.bandwidth == BANDWIDTH_7_MHZ) 404 else if (p->bandwidth_hz == 7000000)
392 val = 3 << 3; 405 val = 3 << 3;
393 else 406 else
394 val = 0 << 3; 407 val = 0 << 3;
@@ -579,10 +592,9 @@ error:
579} 592}
580 593
581static struct dvb_frontend_ops sp887x_ops = { 594static struct dvb_frontend_ops sp887x_ops = {
582 595 .delsys = { SYS_DVBT },
583 .info = { 596 .info = {
584 .name = "Spase SP887x DVB-T", 597 .name = "Spase SP887x DVB-T",
585 .type = FE_OFDM,
586 .frequency_min = 50500000, 598 .frequency_min = 50500000,
587 .frequency_max = 858000000, 599 .frequency_max = 858000000,
588 .frequency_stepsize = 166666, 600 .frequency_stepsize = 166666,
diff --git a/drivers/media/dvb/frontends/stb0899_drv.c b/drivers/media/dvb/frontends/stb0899_drv.c
index 8408ef877b4b..38565beafe23 100644
--- a/drivers/media/dvb/frontends/stb0899_drv.c
+++ b/drivers/media/dvb/frontends/stb0899_drv.c
@@ -1431,7 +1431,7 @@ static void stb0899_set_iterations(struct stb0899_state *state)
1431 stb0899_write_s2reg(state, STB0899_S2FEC, STB0899_BASE_MAX_ITER, STB0899_OFF0_MAX_ITER, reg); 1431 stb0899_write_s2reg(state, STB0899_S2FEC, STB0899_BASE_MAX_ITER, STB0899_OFF0_MAX_ITER, reg);
1432} 1432}
1433 1433
1434static enum dvbfe_search stb0899_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) 1434static enum dvbfe_search stb0899_search(struct dvb_frontend *fe)
1435{ 1435{
1436 struct stb0899_state *state = fe->demodulator_priv; 1436 struct stb0899_state *state = fe->demodulator_priv;
1437 struct stb0899_params *i_params = &state->params; 1437 struct stb0899_params *i_params = &state->params;
@@ -1441,8 +1441,8 @@ static enum dvbfe_search stb0899_search(struct dvb_frontend *fe, struct dvb_fron
1441 1441
1442 u32 SearchRange, gain; 1442 u32 SearchRange, gain;
1443 1443
1444 i_params->freq = p->frequency; 1444 i_params->freq = props->frequency;
1445 i_params->srate = p->u.qpsk.symbol_rate; 1445 i_params->srate = props->symbol_rate;
1446 state->delsys = props->delivery_system; 1446 state->delsys = props->delivery_system;
1447 dprintk(state->verbose, FE_DEBUG, 1, "delivery system=%d", state->delsys); 1447 dprintk(state->verbose, FE_DEBUG, 1, "delivery system=%d", state->delsys);
1448 1448
@@ -1568,34 +1568,15 @@ static enum dvbfe_search stb0899_search(struct dvb_frontend *fe, struct dvb_fron
1568 1568
1569 return DVBFE_ALGO_SEARCH_ERROR; 1569 return DVBFE_ALGO_SEARCH_ERROR;
1570} 1570}
1571/*
1572 * stb0899_track
1573 * periodically check the signal level against a specified
1574 * threshold level and perform derotator centering.
1575 * called once we have a lock from a successful search
1576 * event.
1577 *
1578 * Will be called periodically called to maintain the
1579 * lock.
1580 *
1581 * Will be used to get parameters as well as info from
1582 * the decoded baseband header
1583 *
1584 * Once a new lock has established, the internal state
1585 * frequency (internal->freq) is updated
1586 */
1587static int stb0899_track(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
1588{
1589 return 0;
1590}
1591 1571
1592static int stb0899_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) 1572static int stb0899_get_frontend(struct dvb_frontend *fe)
1593{ 1573{
1574 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1594 struct stb0899_state *state = fe->demodulator_priv; 1575 struct stb0899_state *state = fe->demodulator_priv;
1595 struct stb0899_internal *internal = &state->internal; 1576 struct stb0899_internal *internal = &state->internal;
1596 1577
1597 dprintk(state->verbose, FE_DEBUG, 1, "Get params"); 1578 dprintk(state->verbose, FE_DEBUG, 1, "Get params");
1598 p->u.qpsk.symbol_rate = internal->srate; 1579 p->symbol_rate = internal->srate;
1599 1580
1600 return 0; 1581 return 0;
1601} 1582}
@@ -1606,10 +1587,9 @@ static enum dvbfe_algo stb0899_frontend_algo(struct dvb_frontend *fe)
1606} 1587}
1607 1588
1608static struct dvb_frontend_ops stb0899_ops = { 1589static struct dvb_frontend_ops stb0899_ops = {
1609 1590 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
1610 .info = { 1591 .info = {
1611 .name = "STB0899 Multistandard", 1592 .name = "STB0899 Multistandard",
1612 .type = FE_QPSK,
1613 .frequency_min = 950000, 1593 .frequency_min = 950000,
1614 .frequency_max = 2150000, 1594 .frequency_max = 2150000,
1615 .frequency_stepsize = 0, 1595 .frequency_stepsize = 0,
@@ -1632,8 +1612,7 @@ static struct dvb_frontend_ops stb0899_ops = {
1632 1612
1633 .get_frontend_algo = stb0899_frontend_algo, 1613 .get_frontend_algo = stb0899_frontend_algo,
1634 .search = stb0899_search, 1614 .search = stb0899_search,
1635 .track = stb0899_track, 1615 .get_frontend = stb0899_get_frontend,
1636 .get_frontend = stb0899_get_frontend,
1637 1616
1638 1617
1639 .read_status = stb0899_read_status, 1618 .read_status = stb0899_read_status,
diff --git a/drivers/media/dvb/frontends/stb6000.c b/drivers/media/dvb/frontends/stb6000.c
index ed699647050e..a0c3c526b132 100644
--- a/drivers/media/dvb/frontends/stb6000.c
+++ b/drivers/media/dvb/frontends/stb6000.c
@@ -75,9 +75,9 @@ static int stb6000_sleep(struct dvb_frontend *fe)
75 return (ret == 1) ? 0 : ret; 75 return (ret == 1) ? 0 : ret;
76} 76}
77 77
78static int stb6000_set_params(struct dvb_frontend *fe, 78static int stb6000_set_params(struct dvb_frontend *fe)
79 struct dvb_frontend_parameters *params)
80{ 79{
80 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
81 struct stb6000_priv *priv = fe->tuner_priv; 81 struct stb6000_priv *priv = fe->tuner_priv;
82 unsigned int n, m; 82 unsigned int n, m;
83 int ret; 83 int ret;
@@ -93,8 +93,8 @@ static int stb6000_set_params(struct dvb_frontend *fe,
93 93
94 dprintk("%s:\n", __func__); 94 dprintk("%s:\n", __func__);
95 95
96 freq_mhz = params->frequency / 1000; 96 freq_mhz = p->frequency / 1000;
97 bandwidth = params->u.qpsk.symbol_rate / 1000000; 97 bandwidth = p->symbol_rate / 1000000;
98 98
99 if (bandwidth > 31) 99 if (bandwidth > 31)
100 bandwidth = 31; 100 bandwidth = 31;
diff --git a/drivers/media/dvb/frontends/stb6100.c b/drivers/media/dvb/frontends/stb6100.c
index bc1a8af4f6e1..def88abb30bf 100644
--- a/drivers/media/dvb/frontends/stb6100.c
+++ b/drivers/media/dvb/frontends/stb6100.c
@@ -327,7 +327,7 @@ static int stb6100_set_frequency(struct dvb_frontend *fe, u32 frequency)
327 int rc; 327 int rc;
328 const struct stb6100_lkup *ptr; 328 const struct stb6100_lkup *ptr;
329 struct stb6100_state *state = fe->tuner_priv; 329 struct stb6100_state *state = fe->tuner_priv;
330 struct dvb_frontend_parameters p; 330 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
331 331
332 u32 srate = 0, fvco, nint, nfrac; 332 u32 srate = 0, fvco, nint, nfrac;
333 u8 regs[STB6100_NUMREGS]; 333 u8 regs[STB6100_NUMREGS];
@@ -337,9 +337,9 @@ static int stb6100_set_frequency(struct dvb_frontend *fe, u32 frequency)
337 337
338 if (fe->ops.get_frontend) { 338 if (fe->ops.get_frontend) {
339 dprintk(verbose, FE_DEBUG, 1, "Get frontend parameters"); 339 dprintk(verbose, FE_DEBUG, 1, "Get frontend parameters");
340 fe->ops.get_frontend(fe, &p); 340 fe->ops.get_frontend(fe);
341 } 341 }
342 srate = p.u.qpsk.symbol_rate; 342 srate = p->symbol_rate;
343 343
344 /* Set up tuner cleanly, LPF calibration on */ 344 /* Set up tuner cleanly, LPF calibration on */
345 rc = stb6100_write_reg(state, STB6100_FCCK, 0x4d | STB6100_FCCK_FCCK); 345 rc = stb6100_write_reg(state, STB6100_FCCK, 0x4d | STB6100_FCCK_FCCK);
diff --git a/drivers/media/dvb/frontends/stv0288.c b/drivers/media/dvb/frontends/stv0288.c
index 0aa3962ff18b..fb5548a82208 100644
--- a/drivers/media/dvb/frontends/stv0288.c
+++ b/drivers/media/dvb/frontends/stv0288.c
@@ -452,14 +452,7 @@ static int stv0288_set_property(struct dvb_frontend *fe, struct dtv_property *p)
452 return 0; 452 return 0;
453} 453}
454 454
455static int stv0288_get_property(struct dvb_frontend *fe, struct dtv_property *p) 455static int stv0288_set_frontend(struct dvb_frontend *fe)
456{
457 dprintk("%s(..)\n", __func__);
458 return 0;
459}
460
461static int stv0288_set_frontend(struct dvb_frontend *fe,
462 struct dvb_frontend_parameters *dfp)
463{ 456{
464 struct stv0288_state *state = fe->demodulator_priv; 457 struct stv0288_state *state = fe->demodulator_priv;
465 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 458 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
@@ -481,10 +474,8 @@ static int stv0288_set_frontend(struct dvb_frontend *fe,
481 state->config->set_ts_params(fe, 0); 474 state->config->set_ts_params(fe, 0);
482 475
483 /* only frequency & symbol_rate are used for tuner*/ 476 /* only frequency & symbol_rate are used for tuner*/
484 dfp->frequency = c->frequency;
485 dfp->u.qpsk.symbol_rate = c->symbol_rate;
486 if (fe->ops.tuner_ops.set_params) { 477 if (fe->ops.tuner_ops.set_params) {
487 fe->ops.tuner_ops.set_params(fe, dfp); 478 fe->ops.tuner_ops.set_params(fe);
488 if (fe->ops.i2c_gate_ctrl) 479 if (fe->ops.i2c_gate_ctrl)
489 fe->ops.i2c_gate_ctrl(fe, 0); 480 fe->ops.i2c_gate_ctrl(fe, 0);
490 } 481 }
@@ -545,10 +536,9 @@ static void stv0288_release(struct dvb_frontend *fe)
545} 536}
546 537
547static struct dvb_frontend_ops stv0288_ops = { 538static struct dvb_frontend_ops stv0288_ops = {
548 539 .delsys = { SYS_DVBS },
549 .info = { 540 .info = {
550 .name = "ST STV0288 DVB-S", 541 .name = "ST STV0288 DVB-S",
551 .type = FE_QPSK,
552 .frequency_min = 950000, 542 .frequency_min = 950000,
553 .frequency_max = 2150000, 543 .frequency_max = 2150000,
554 .frequency_stepsize = 1000, /* kHz for QPSK frontends */ 544 .frequency_stepsize = 1000, /* kHz for QPSK frontends */
@@ -578,7 +568,6 @@ static struct dvb_frontend_ops stv0288_ops = {
578 .set_voltage = stv0288_set_voltage, 568 .set_voltage = stv0288_set_voltage,
579 569
580 .set_property = stv0288_set_property, 570 .set_property = stv0288_set_property,
581 .get_property = stv0288_get_property,
582 .set_frontend = stv0288_set_frontend, 571 .set_frontend = stv0288_set_frontend,
583}; 572};
584 573
diff --git a/drivers/media/dvb/frontends/stv0297.c b/drivers/media/dvb/frontends/stv0297.c
index 84d88f33275e..85c157a1fe5e 100644
--- a/drivers/media/dvb/frontends/stv0297.c
+++ b/drivers/media/dvb/frontends/stv0297.c
@@ -404,8 +404,9 @@ static int stv0297_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
404 return 0; 404 return 0;
405} 405}
406 406
407static int stv0297_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) 407static int stv0297_set_frontend(struct dvb_frontend *fe)
408{ 408{
409 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
409 struct stv0297_state *state = fe->demodulator_priv; 410 struct stv0297_state *state = fe->demodulator_priv;
410 int u_threshold; 411 int u_threshold;
411 int initial_u; 412 int initial_u;
@@ -417,7 +418,7 @@ static int stv0297_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
417 unsigned long timeout; 418 unsigned long timeout;
418 fe_spectral_inversion_t inversion; 419 fe_spectral_inversion_t inversion;
419 420
420 switch (p->u.qam.modulation) { 421 switch (p->modulation) {
421 case QAM_16: 422 case QAM_16:
422 case QAM_32: 423 case QAM_32:
423 case QAM_64: 424 case QAM_64:
@@ -455,7 +456,7 @@ static int stv0297_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
455 456
456 stv0297_init(fe); 457 stv0297_init(fe);
457 if (fe->ops.tuner_ops.set_params) { 458 if (fe->ops.tuner_ops.set_params) {
458 fe->ops.tuner_ops.set_params(fe, p); 459 fe->ops.tuner_ops.set_params(fe);
459 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 460 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
460 } 461 }
461 462
@@ -519,16 +520,16 @@ static int stv0297_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
519 stv0297_writereg_mask(state, 0x69, 0x0f, 0x00); 520 stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
520 521
521 /* set parameters */ 522 /* set parameters */
522 stv0297_set_qam(state, p->u.qam.modulation); 523 stv0297_set_qam(state, p->modulation);
523 stv0297_set_symbolrate(state, p->u.qam.symbol_rate / 1000); 524 stv0297_set_symbolrate(state, p->symbol_rate / 1000);
524 stv0297_set_sweeprate(state, sweeprate, p->u.qam.symbol_rate / 1000); 525 stv0297_set_sweeprate(state, sweeprate, p->symbol_rate / 1000);
525 stv0297_set_carrieroffset(state, carrieroffset); 526 stv0297_set_carrieroffset(state, carrieroffset);
526 stv0297_set_inversion(state, inversion); 527 stv0297_set_inversion(state, inversion);
527 528
528 /* kick off lock */ 529 /* kick off lock */
529 /* Disable corner detection for higher QAMs */ 530 /* Disable corner detection for higher QAMs */
530 if (p->u.qam.modulation == QAM_128 || 531 if (p->modulation == QAM_128 ||
531 p->u.qam.modulation == QAM_256) 532 p->modulation == QAM_256)
532 stv0297_writereg_mask(state, 0x88, 0x08, 0x00); 533 stv0297_writereg_mask(state, 0x88, 0x08, 0x00);
533 else 534 else
534 stv0297_writereg_mask(state, 0x88, 0x08, 0x08); 535 stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
@@ -613,8 +614,9 @@ timeout:
613 return 0; 614 return 0;
614} 615}
615 616
616static int stv0297_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) 617static int stv0297_get_frontend(struct dvb_frontend *fe)
617{ 618{
619 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
618 struct stv0297_state *state = fe->demodulator_priv; 620 struct stv0297_state *state = fe->demodulator_priv;
619 int reg_00, reg_83; 621 int reg_00, reg_83;
620 622
@@ -625,24 +627,24 @@ static int stv0297_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
625 p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF; 627 p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
626 if (state->config->invert) 628 if (state->config->invert)
627 p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON; 629 p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
628 p->u.qam.symbol_rate = stv0297_get_symbolrate(state) * 1000; 630 p->symbol_rate = stv0297_get_symbolrate(state) * 1000;
629 p->u.qam.fec_inner = FEC_NONE; 631 p->fec_inner = FEC_NONE;
630 632
631 switch ((reg_00 >> 4) & 0x7) { 633 switch ((reg_00 >> 4) & 0x7) {
632 case 0: 634 case 0:
633 p->u.qam.modulation = QAM_16; 635 p->modulation = QAM_16;
634 break; 636 break;
635 case 1: 637 case 1:
636 p->u.qam.modulation = QAM_32; 638 p->modulation = QAM_32;
637 break; 639 break;
638 case 2: 640 case 2:
639 p->u.qam.modulation = QAM_128; 641 p->modulation = QAM_128;
640 break; 642 break;
641 case 3: 643 case 3:
642 p->u.qam.modulation = QAM_256; 644 p->modulation = QAM_256;
643 break; 645 break;
644 case 4: 646 case 4:
645 p->u.qam.modulation = QAM_64; 647 p->modulation = QAM_64;
646 break; 648 break;
647 } 649 }
648 650
@@ -688,10 +690,9 @@ error:
688} 690}
689 691
690static struct dvb_frontend_ops stv0297_ops = { 692static struct dvb_frontend_ops stv0297_ops = {
691 693 .delsys = { SYS_DVBC_ANNEX_A },
692 .info = { 694 .info = {
693 .name = "ST STV0297 DVB-C", 695 .name = "ST STV0297 DVB-C",
694 .type = FE_QAM,
695 .frequency_min = 47000000, 696 .frequency_min = 47000000,
696 .frequency_max = 862000000, 697 .frequency_max = 862000000,
697 .frequency_stepsize = 62500, 698 .frequency_stepsize = 62500,
diff --git a/drivers/media/dvb/frontends/stv0299.c b/drivers/media/dvb/frontends/stv0299.c
index 42684bec8883..057b5f8effc0 100644
--- a/drivers/media/dvb/frontends/stv0299.c
+++ b/drivers/media/dvb/frontends/stv0299.c
@@ -559,8 +559,9 @@ static int stv0299_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
559 return 0; 559 return 0;
560} 560}
561 561
562static int stv0299_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters * p) 562static int stv0299_set_frontend(struct dvb_frontend *fe)
563{ 563{
564 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
564 struct stv0299_state* state = fe->demodulator_priv; 565 struct stv0299_state* state = fe->demodulator_priv;
565 int invval = 0; 566 int invval = 0;
566 567
@@ -579,24 +580,25 @@ static int stv0299_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
579 stv0299_writeregI(state, 0x0c, (stv0299_readreg(state, 0x0c) & 0xfe) | invval); 580 stv0299_writeregI(state, 0x0c, (stv0299_readreg(state, 0x0c) & 0xfe) | invval);
580 581
581 if (fe->ops.tuner_ops.set_params) { 582 if (fe->ops.tuner_ops.set_params) {
582 fe->ops.tuner_ops.set_params(fe, p); 583 fe->ops.tuner_ops.set_params(fe);
583 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 584 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
584 } 585 }
585 586
586 stv0299_set_FEC (state, p->u.qpsk.fec_inner); 587 stv0299_set_FEC(state, p->fec_inner);
587 stv0299_set_symbolrate (fe, p->u.qpsk.symbol_rate); 588 stv0299_set_symbolrate(fe, p->symbol_rate);
588 stv0299_writeregI(state, 0x22, 0x00); 589 stv0299_writeregI(state, 0x22, 0x00);
589 stv0299_writeregI(state, 0x23, 0x00); 590 stv0299_writeregI(state, 0x23, 0x00);
590 591
591 state->tuner_frequency = p->frequency; 592 state->tuner_frequency = p->frequency;
592 state->fec_inner = p->u.qpsk.fec_inner; 593 state->fec_inner = p->fec_inner;
593 state->symbol_rate = p->u.qpsk.symbol_rate; 594 state->symbol_rate = p->symbol_rate;
594 595
595 return 0; 596 return 0;
596} 597}
597 598
598static int stv0299_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters * p) 599static int stv0299_get_frontend(struct dvb_frontend *fe)
599{ 600{
601 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
600 struct stv0299_state* state = fe->demodulator_priv; 602 struct stv0299_state* state = fe->demodulator_priv;
601 s32 derot_freq; 603 s32 derot_freq;
602 int invval; 604 int invval;
@@ -614,8 +616,8 @@ static int stv0299_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
614 if (state->config->invert) invval = (~invval) & 1; 616 if (state->config->invert) invval = (~invval) & 1;
615 p->inversion = invval ? INVERSION_ON : INVERSION_OFF; 617 p->inversion = invval ? INVERSION_ON : INVERSION_OFF;
616 618
617 p->u.qpsk.fec_inner = stv0299_get_fec (state); 619 p->fec_inner = stv0299_get_fec(state);
618 p->u.qpsk.symbol_rate = stv0299_get_symbolrate (state); 620 p->symbol_rate = stv0299_get_symbolrate(state);
619 621
620 return 0; 622 return 0;
621} 623}
@@ -646,14 +648,15 @@ static int stv0299_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
646static int stv0299_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings) 648static int stv0299_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
647{ 649{
648 struct stv0299_state* state = fe->demodulator_priv; 650 struct stv0299_state* state = fe->demodulator_priv;
651 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
649 652
650 fesettings->min_delay_ms = state->config->min_delay_ms; 653 fesettings->min_delay_ms = state->config->min_delay_ms;
651 if (fesettings->parameters.u.qpsk.symbol_rate < 10000000) { 654 if (p->symbol_rate < 10000000) {
652 fesettings->step_size = fesettings->parameters.u.qpsk.symbol_rate / 32000; 655 fesettings->step_size = p->symbol_rate / 32000;
653 fesettings->max_drift = 5000; 656 fesettings->max_drift = 5000;
654 } else { 657 } else {
655 fesettings->step_size = fesettings->parameters.u.qpsk.symbol_rate / 16000; 658 fesettings->step_size = p->symbol_rate / 16000;
656 fesettings->max_drift = fesettings->parameters.u.qpsk.symbol_rate / 2000; 659 fesettings->max_drift = p->symbol_rate / 2000;
657 } 660 }
658 return 0; 661 return 0;
659} 662}
@@ -705,10 +708,9 @@ error:
705} 708}
706 709
707static struct dvb_frontend_ops stv0299_ops = { 710static struct dvb_frontend_ops stv0299_ops = {
708 711 .delsys = { SYS_DVBS },
709 .info = { 712 .info = {
710 .name = "ST STV0299 DVB-S", 713 .name = "ST STV0299 DVB-S",
711 .type = FE_QPSK,
712 .frequency_min = 950000, 714 .frequency_min = 950000,
713 .frequency_max = 2150000, 715 .frequency_max = 2150000,
714 .frequency_stepsize = 125, /* kHz for QPSK frontends */ 716 .frequency_stepsize = 125, /* kHz for QPSK frontends */
diff --git a/drivers/media/dvb/frontends/stv0367.c b/drivers/media/dvb/frontends/stv0367.c
index e57ab53e2e27..fdd20c7737b5 100644
--- a/drivers/media/dvb/frontends/stv0367.c
+++ b/drivers/media/dvb/frontends/stv0367.c
@@ -1577,9 +1577,9 @@ int stv0367ter_init(struct dvb_frontend *fe)
1577 return 0; 1577 return 0;
1578} 1578}
1579 1579
1580static int stv0367ter_algo(struct dvb_frontend *fe, 1580static int stv0367ter_algo(struct dvb_frontend *fe)
1581 struct dvb_frontend_parameters *param)
1582{ 1581{
1582 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1583 struct stv0367_state *state = fe->demodulator_priv; 1583 struct stv0367_state *state = fe->demodulator_priv;
1584 struct stv0367ter_state *ter_state = state->ter_state; 1584 struct stv0367ter_state *ter_state = state->ter_state;
1585 int offset = 0, tempo = 0; 1585 int offset = 0, tempo = 0;
@@ -1591,7 +1591,7 @@ static int stv0367ter_algo(struct dvb_frontend *fe,
1591 1591
1592 dprintk("%s:\n", __func__); 1592 dprintk("%s:\n", __func__);
1593 1593
1594 ter_state->frequency = param->frequency; 1594 ter_state->frequency = p->frequency;
1595 ter_state->force = FE_TER_FORCENONE 1595 ter_state->force = FE_TER_FORCENONE
1596 + stv0367_readbits(state, F367TER_FORCE) * 2; 1596 + stv0367_readbits(state, F367TER_FORCE) * 2;
1597 ter_state->if_iq_mode = state->config->if_iq_mode; 1597 ter_state->if_iq_mode = state->config->if_iq_mode;
@@ -1620,7 +1620,7 @@ static int stv0367ter_algo(struct dvb_frontend *fe,
1620 1620
1621 usleep_range(5000, 7000); 1621 usleep_range(5000, 7000);
1622 1622
1623 switch (param->inversion) { 1623 switch (p->inversion) {
1624 case INVERSION_AUTO: 1624 case INVERSION_AUTO:
1625 default: 1625 default:
1626 dprintk("%s: inversion AUTO\n", __func__); 1626 dprintk("%s: inversion AUTO\n", __func__);
@@ -1636,10 +1636,10 @@ static int stv0367ter_algo(struct dvb_frontend *fe,
1636 case INVERSION_OFF: 1636 case INVERSION_OFF:
1637 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER) 1637 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1638 stv0367_writebits(state, F367TER_IQ_INVERT, 1638 stv0367_writebits(state, F367TER_IQ_INVERT,
1639 param->inversion); 1639 p->inversion);
1640 else 1640 else
1641 stv0367_writebits(state, F367TER_INV_SPECTR, 1641 stv0367_writebits(state, F367TER_INV_SPECTR,
1642 param->inversion); 1642 p->inversion);
1643 1643
1644 break; 1644 break;
1645 } 1645 }
@@ -1806,10 +1806,9 @@ static int stv0367ter_algo(struct dvb_frontend *fe,
1806 return 0; 1806 return 0;
1807} 1807}
1808 1808
1809static int stv0367ter_set_frontend(struct dvb_frontend *fe, 1809static int stv0367ter_set_frontend(struct dvb_frontend *fe)
1810 struct dvb_frontend_parameters *param)
1811{ 1810{
1812 struct dvb_ofdm_parameters *op = &param->u.ofdm; 1811 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1813 struct stv0367_state *state = fe->demodulator_priv; 1812 struct stv0367_state *state = fe->demodulator_priv;
1814 struct stv0367ter_state *ter_state = state->ter_state; 1813 struct stv0367ter_state *ter_state = state->ter_state;
1815 1814
@@ -1822,12 +1821,12 @@ static int stv0367ter_set_frontend(struct dvb_frontend *fe,
1822 if (fe->ops.tuner_ops.set_params) { 1821 if (fe->ops.tuner_ops.set_params) {
1823 if (fe->ops.i2c_gate_ctrl) 1822 if (fe->ops.i2c_gate_ctrl)
1824 fe->ops.i2c_gate_ctrl(fe, 1); 1823 fe->ops.i2c_gate_ctrl(fe, 1);
1825 fe->ops.tuner_ops.set_params(fe, param); 1824 fe->ops.tuner_ops.set_params(fe);
1826 if (fe->ops.i2c_gate_ctrl) 1825 if (fe->ops.i2c_gate_ctrl)
1827 fe->ops.i2c_gate_ctrl(fe, 0); 1826 fe->ops.i2c_gate_ctrl(fe, 0);
1828 } 1827 }
1829 1828
1830 switch (op->transmission_mode) { 1829 switch (p->transmission_mode) {
1831 default: 1830 default:
1832 case TRANSMISSION_MODE_AUTO: 1831 case TRANSMISSION_MODE_AUTO:
1833 case TRANSMISSION_MODE_2K: 1832 case TRANSMISSION_MODE_2K:
@@ -1841,34 +1840,34 @@ static int stv0367ter_set_frontend(struct dvb_frontend *fe,
1841 break; 1840 break;
1842 } 1841 }
1843 1842
1844 switch (op->guard_interval) { 1843 switch (p->guard_interval) {
1845 default: 1844 default:
1846 case GUARD_INTERVAL_1_32: 1845 case GUARD_INTERVAL_1_32:
1847 case GUARD_INTERVAL_1_16: 1846 case GUARD_INTERVAL_1_16:
1848 case GUARD_INTERVAL_1_8: 1847 case GUARD_INTERVAL_1_8:
1849 case GUARD_INTERVAL_1_4: 1848 case GUARD_INTERVAL_1_4:
1850 ter_state->guard = op->guard_interval; 1849 ter_state->guard = p->guard_interval;
1851 break; 1850 break;
1852 case GUARD_INTERVAL_AUTO: 1851 case GUARD_INTERVAL_AUTO:
1853 ter_state->guard = GUARD_INTERVAL_1_32; 1852 ter_state->guard = GUARD_INTERVAL_1_32;
1854 break; 1853 break;
1855 } 1854 }
1856 1855
1857 switch (op->bandwidth) { 1856 switch (p->bandwidth_hz) {
1858 case BANDWIDTH_6_MHZ: 1857 case 6000000:
1859 ter_state->bw = FE_TER_CHAN_BW_6M; 1858 ter_state->bw = FE_TER_CHAN_BW_6M;
1860 break; 1859 break;
1861 case BANDWIDTH_7_MHZ: 1860 case 7000000:
1862 ter_state->bw = FE_TER_CHAN_BW_7M; 1861 ter_state->bw = FE_TER_CHAN_BW_7M;
1863 break; 1862 break;
1864 case BANDWIDTH_8_MHZ: 1863 case 8000000:
1865 default: 1864 default:
1866 ter_state->bw = FE_TER_CHAN_BW_8M; 1865 ter_state->bw = FE_TER_CHAN_BW_8M;
1867 } 1866 }
1868 1867
1869 ter_state->hierarchy = FE_TER_HIER_NONE; 1868 ter_state->hierarchy = FE_TER_HIER_NONE;
1870 1869
1871 switch (param->inversion) { 1870 switch (p->inversion) {
1872 case INVERSION_OFF: 1871 case INVERSION_OFF:
1873 case INVERSION_ON: 1872 case INVERSION_ON:
1874 num_trials = 1; 1873 num_trials = 1;
@@ -1885,14 +1884,14 @@ static int stv0367ter_set_frontend(struct dvb_frontend *fe,
1885 1884
1886 while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) { 1885 while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1887 if (!ter_state->first_lock) { 1886 if (!ter_state->first_lock) {
1888 if (param->inversion == INVERSION_AUTO) 1887 if (p->inversion == INVERSION_AUTO)
1889 ter_state->sense = SenseTrials[index]; 1888 ter_state->sense = SenseTrials[index];
1890 1889
1891 } 1890 }
1892 stv0367ter_algo(fe,/* &pLook, result,*/ param); 1891 stv0367ter_algo(fe);
1893 1892
1894 if ((ter_state->state == FE_TER_LOCKOK) && 1893 if ((ter_state->state == FE_TER_LOCKOK) &&
1895 (param->inversion == INVERSION_AUTO) && 1894 (p->inversion == INVERSION_AUTO) &&
1896 (index == 1)) { 1895 (index == 1)) {
1897 /* invert spectrum sense */ 1896 /* invert spectrum sense */
1898 SenseTrials[index] = SenseTrials[0]; 1897 SenseTrials[index] = SenseTrials[0];
@@ -1927,50 +1926,48 @@ static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1927 return 0; 1926 return 0;
1928} 1927}
1929 1928
1930static int stv0367ter_get_frontend(struct dvb_frontend *fe, 1929static int stv0367ter_get_frontend(struct dvb_frontend *fe)
1931 struct dvb_frontend_parameters *param)
1932{ 1930{
1931 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1933 struct stv0367_state *state = fe->demodulator_priv; 1932 struct stv0367_state *state = fe->demodulator_priv;
1934 struct stv0367ter_state *ter_state = state->ter_state; 1933 struct stv0367ter_state *ter_state = state->ter_state;
1935 struct dvb_ofdm_parameters *op = &param->u.ofdm;
1936 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1937 1934
1938 int error = 0; 1935 int error = 0;
1939 enum stv0367_ter_mode mode; 1936 enum stv0367_ter_mode mode;
1940 int constell = 0,/* snr = 0,*/ Data = 0; 1937 int constell = 0,/* snr = 0,*/ Data = 0;
1941 1938
1942 param->frequency = stv0367_get_tuner_freq(fe); 1939 p->frequency = stv0367_get_tuner_freq(fe);
1943 if ((int)param->frequency < 0) 1940 if ((int)p->frequency < 0)
1944 param->frequency = c->frequency; 1941 p->frequency = -p->frequency;
1945 1942
1946 constell = stv0367_readbits(state, F367TER_TPS_CONST); 1943 constell = stv0367_readbits(state, F367TER_TPS_CONST);
1947 if (constell == 0) 1944 if (constell == 0)
1948 op->constellation = QPSK; 1945 p->modulation = QPSK;
1949 else if (constell == 1) 1946 else if (constell == 1)
1950 op->constellation = QAM_16; 1947 p->modulation = QAM_16;
1951 else 1948 else
1952 op->constellation = QAM_64; 1949 p->modulation = QAM_64;
1953 1950
1954 param->inversion = stv0367_readbits(state, F367TER_INV_SPECTR); 1951 p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1955 1952
1956 /* Get the Hierarchical mode */ 1953 /* Get the Hierarchical mode */
1957 Data = stv0367_readbits(state, F367TER_TPS_HIERMODE); 1954 Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1958 1955
1959 switch (Data) { 1956 switch (Data) {
1960 case 0: 1957 case 0:
1961 op->hierarchy_information = HIERARCHY_NONE; 1958 p->hierarchy = HIERARCHY_NONE;
1962 break; 1959 break;
1963 case 1: 1960 case 1:
1964 op->hierarchy_information = HIERARCHY_1; 1961 p->hierarchy = HIERARCHY_1;
1965 break; 1962 break;
1966 case 2: 1963 case 2:
1967 op->hierarchy_information = HIERARCHY_2; 1964 p->hierarchy = HIERARCHY_2;
1968 break; 1965 break;
1969 case 3: 1966 case 3:
1970 op->hierarchy_information = HIERARCHY_4; 1967 p->hierarchy = HIERARCHY_4;
1971 break; 1968 break;
1972 default: 1969 default:
1973 op->hierarchy_information = HIERARCHY_AUTO; 1970 p->hierarchy = HIERARCHY_AUTO;
1974 break; /* error */ 1971 break; /* error */
1975 } 1972 }
1976 1973
@@ -1982,22 +1979,22 @@ static int stv0367ter_get_frontend(struct dvb_frontend *fe,
1982 1979
1983 switch (Data) { 1980 switch (Data) {
1984 case 0: 1981 case 0:
1985 op->code_rate_HP = FEC_1_2; 1982 p->code_rate_HP = FEC_1_2;
1986 break; 1983 break;
1987 case 1: 1984 case 1:
1988 op->code_rate_HP = FEC_2_3; 1985 p->code_rate_HP = FEC_2_3;
1989 break; 1986 break;
1990 case 2: 1987 case 2:
1991 op->code_rate_HP = FEC_3_4; 1988 p->code_rate_HP = FEC_3_4;
1992 break; 1989 break;
1993 case 3: 1990 case 3:
1994 op->code_rate_HP = FEC_5_6; 1991 p->code_rate_HP = FEC_5_6;
1995 break; 1992 break;
1996 case 4: 1993 case 4:
1997 op->code_rate_HP = FEC_7_8; 1994 p->code_rate_HP = FEC_7_8;
1998 break; 1995 break;
1999 default: 1996 default:
2000 op->code_rate_HP = FEC_AUTO; 1997 p->code_rate_HP = FEC_AUTO;
2001 break; /* error */ 1998 break; /* error */
2002 } 1999 }
2003 2000
@@ -2005,19 +2002,19 @@ static int stv0367ter_get_frontend(struct dvb_frontend *fe,
2005 2002
2006 switch (mode) { 2003 switch (mode) {
2007 case FE_TER_MODE_2K: 2004 case FE_TER_MODE_2K:
2008 op->transmission_mode = TRANSMISSION_MODE_2K; 2005 p->transmission_mode = TRANSMISSION_MODE_2K;
2009 break; 2006 break;
2010/* case FE_TER_MODE_4K: 2007/* case FE_TER_MODE_4K:
2011 op->transmission_mode = TRANSMISSION_MODE_4K; 2008 p->transmission_mode = TRANSMISSION_MODE_4K;
2012 break;*/ 2009 break;*/
2013 case FE_TER_MODE_8K: 2010 case FE_TER_MODE_8K:
2014 op->transmission_mode = TRANSMISSION_MODE_8K; 2011 p->transmission_mode = TRANSMISSION_MODE_8K;
2015 break; 2012 break;
2016 default: 2013 default:
2017 op->transmission_mode = TRANSMISSION_MODE_AUTO; 2014 p->transmission_mode = TRANSMISSION_MODE_AUTO;
2018 } 2015 }
2019 2016
2020 op->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD); 2017 p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
2021 2018
2022 return error; 2019 return error;
2023} 2020}
@@ -2265,9 +2262,9 @@ static void stv0367_release(struct dvb_frontend *fe)
2265} 2262}
2266 2263
2267static struct dvb_frontend_ops stv0367ter_ops = { 2264static struct dvb_frontend_ops stv0367ter_ops = {
2265 .delsys = { SYS_DVBT },
2268 .info = { 2266 .info = {
2269 .name = "ST STV0367 DVB-T", 2267 .name = "ST STV0367 DVB-T",
2270 .type = FE_OFDM,
2271 .frequency_min = 47000000, 2268 .frequency_min = 47000000,
2272 .frequency_max = 862000000, 2269 .frequency_max = 862000000,
2273 .frequency_stepsize = 15625, 2270 .frequency_stepsize = 15625,
@@ -2822,9 +2819,8 @@ int stv0367cab_init(struct dvb_frontend *fe)
2822} 2819}
2823static 2820static
2824enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state, 2821enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2825 struct dvb_frontend_parameters *param) 2822 struct dtv_frontend_properties *p)
2826{ 2823{
2827 struct dvb_qam_parameters *op = &param->u.qam;
2828 struct stv0367cab_state *cab_state = state->cab_state; 2824 struct stv0367cab_state *cab_state = state->cab_state;
2829 enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC; 2825 enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
2830 u32 QAMFEC_Lock, QAM_Lock, u32_tmp, 2826 u32 QAMFEC_Lock, QAM_Lock, u32_tmp,
@@ -2839,7 +2835,7 @@ enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2839 /* A max lock time of 25 ms is allowed for delayed AGC */ 2835 /* A max lock time of 25 ms is allowed for delayed AGC */
2840 AGCTimeOut = 25; 2836 AGCTimeOut = 25;
2841 /* 100000 symbols needed by the TRL as a maximum value */ 2837 /* 100000 symbols needed by the TRL as a maximum value */
2842 TRLTimeOut = 100000000 / op->symbol_rate; 2838 TRLTimeOut = 100000000 / p->symbol_rate;
2843 /* CRLSymbols is the needed number of symbols to achieve a lock 2839 /* CRLSymbols is the needed number of symbols to achieve a lock
2844 within [-4%, +4%] of the symbol rate. 2840 within [-4%, +4%] of the symbol rate.
2845 CRL timeout is calculated 2841 CRL timeout is calculated
@@ -2849,7 +2845,7 @@ enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2849 A characterization must be performed 2845 A characterization must be performed
2850 with these echoes to get new timeout values. 2846 with these echoes to get new timeout values.
2851 */ 2847 */
2852 switch (op->modulation) { 2848 switch (p->modulation) {
2853 case QAM_16: 2849 case QAM_16:
2854 CRLSymbols = 150000; 2850 CRLSymbols = 150000;
2855 EQLTimeOut = 100; 2851 EQLTimeOut = 100;
@@ -2883,9 +2879,9 @@ enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2883 } else 2879 } else
2884#endif 2880#endif
2885 CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) / 2881 CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
2886 (op->symbol_rate / 1000); 2882 (p->symbol_rate / 1000);
2887 2883
2888 CRLTimeOut = (1000 * CRLTimeOut) / op->symbol_rate; 2884 CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
2889 /* Timeouts below 50ms are coerced */ 2885 /* Timeouts below 50ms are coerced */
2890 if (CRLTimeOut < 50) 2886 if (CRLTimeOut < 50)
2891 CRLTimeOut = 50; 2887 CRLTimeOut = 50;
@@ -2915,7 +2911,7 @@ enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2915 stv0367cab_set_derot_freq(state, cab_state->adc_clk, 2911 stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2916 (1000 * (s32)state->config->if_khz + cab_state->derot_offset)); 2912 (1000 * (s32)state->config->if_khz + cab_state->derot_offset));
2917 /* Disable the Allpass Filter when the symbol rate is out of range */ 2913 /* Disable the Allpass Filter when the symbol rate is out of range */
2918 if ((op->symbol_rate > 10800000) | (op->symbol_rate < 1800000)) { 2914 if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
2919 stv0367_writebits(state, F367CAB_ADJ_EN, 0); 2915 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2920 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0); 2916 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2921 } 2917 }
@@ -2999,7 +2995,7 @@ enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2999 2995
3000 if (QAMFEC_Lock) { 2996 if (QAMFEC_Lock) {
3001 signalType = FE_CAB_DATAOK; 2997 signalType = FE_CAB_DATAOK;
3002 cab_state->modulation = op->modulation; 2998 cab_state->modulation = p->modulation;
3003 cab_state->spect_inv = stv0367_readbits(state, 2999 cab_state->spect_inv = stv0367_readbits(state,
3004 F367CAB_QUAD_INV); 3000 F367CAB_QUAD_INV);
3005#if 0 3001#if 0
@@ -3081,20 +3077,19 @@ enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
3081 return signalType; 3077 return signalType;
3082} 3078}
3083 3079
3084static int stv0367cab_set_frontend(struct dvb_frontend *fe, 3080static int stv0367cab_set_frontend(struct dvb_frontend *fe)
3085 struct dvb_frontend_parameters *param)
3086{ 3081{
3082 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3087 struct stv0367_state *state = fe->demodulator_priv; 3083 struct stv0367_state *state = fe->demodulator_priv;
3088 struct stv0367cab_state *cab_state = state->cab_state; 3084 struct stv0367cab_state *cab_state = state->cab_state;
3089 struct dvb_qam_parameters *op = &param->u.qam;
3090 enum stv0367cab_mod QAMSize = 0; 3085 enum stv0367cab_mod QAMSize = 0;
3091 3086
3092 dprintk("%s: freq = %d, srate = %d\n", __func__, 3087 dprintk("%s: freq = %d, srate = %d\n", __func__,
3093 param->frequency, op->symbol_rate); 3088 p->frequency, p->symbol_rate);
3094 3089
3095 cab_state->derot_offset = 0; 3090 cab_state->derot_offset = 0;
3096 3091
3097 switch (op->modulation) { 3092 switch (p->modulation) {
3098 case QAM_16: 3093 case QAM_16:
3099 QAMSize = FE_CAB_MOD_QAM16; 3094 QAMSize = FE_CAB_MOD_QAM16;
3100 break; 3095 break;
@@ -3120,77 +3115,76 @@ static int stv0367cab_set_frontend(struct dvb_frontend *fe,
3120 if (fe->ops.tuner_ops.set_params) { 3115 if (fe->ops.tuner_ops.set_params) {
3121 if (fe->ops.i2c_gate_ctrl) 3116 if (fe->ops.i2c_gate_ctrl)
3122 fe->ops.i2c_gate_ctrl(fe, 1); 3117 fe->ops.i2c_gate_ctrl(fe, 1);
3123 fe->ops.tuner_ops.set_params(fe, param); 3118 fe->ops.tuner_ops.set_params(fe);
3124 if (fe->ops.i2c_gate_ctrl) 3119 if (fe->ops.i2c_gate_ctrl)
3125 fe->ops.i2c_gate_ctrl(fe, 0); 3120 fe->ops.i2c_gate_ctrl(fe, 0);
3126 } 3121 }
3127 3122
3128 stv0367cab_SetQamSize( 3123 stv0367cab_SetQamSize(
3129 state, 3124 state,
3130 op->symbol_rate, 3125 p->symbol_rate,
3131 QAMSize); 3126 QAMSize);
3132 3127
3133 stv0367cab_set_srate(state, 3128 stv0367cab_set_srate(state,
3134 cab_state->adc_clk, 3129 cab_state->adc_clk,
3135 cab_state->mclk, 3130 cab_state->mclk,
3136 op->symbol_rate, 3131 p->symbol_rate,
3137 QAMSize); 3132 QAMSize);
3138 /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */ 3133 /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
3139 cab_state->state = stv0367cab_algo(state, param); 3134 cab_state->state = stv0367cab_algo(state, p);
3140 return 0; 3135 return 0;
3141} 3136}
3142 3137
3143static int stv0367cab_get_frontend(struct dvb_frontend *fe, 3138static int stv0367cab_get_frontend(struct dvb_frontend *fe)
3144 struct dvb_frontend_parameters *param)
3145{ 3139{
3140 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3146 struct stv0367_state *state = fe->demodulator_priv; 3141 struct stv0367_state *state = fe->demodulator_priv;
3147 struct stv0367cab_state *cab_state = state->cab_state; 3142 struct stv0367cab_state *cab_state = state->cab_state;
3148 struct dvb_qam_parameters *op = &param->u.qam;
3149 3143
3150 enum stv0367cab_mod QAMSize; 3144 enum stv0367cab_mod QAMSize;
3151 3145
3152 dprintk("%s:\n", __func__); 3146 dprintk("%s:\n", __func__);
3153 3147
3154 op->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk); 3148 p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
3155 3149
3156 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE); 3150 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3157 switch (QAMSize) { 3151 switch (QAMSize) {
3158 case FE_CAB_MOD_QAM16: 3152 case FE_CAB_MOD_QAM16:
3159 op->modulation = QAM_16; 3153 p->modulation = QAM_16;
3160 break; 3154 break;
3161 case FE_CAB_MOD_QAM32: 3155 case FE_CAB_MOD_QAM32:
3162 op->modulation = QAM_32; 3156 p->modulation = QAM_32;
3163 break; 3157 break;
3164 case FE_CAB_MOD_QAM64: 3158 case FE_CAB_MOD_QAM64:
3165 op->modulation = QAM_64; 3159 p->modulation = QAM_64;
3166 break; 3160 break;
3167 case FE_CAB_MOD_QAM128: 3161 case FE_CAB_MOD_QAM128:
3168 op->modulation = QAM_128; 3162 p->modulation = QAM_128;
3169 break; 3163 break;
3170 case QAM_256: 3164 case QAM_256:
3171 op->modulation = QAM_256; 3165 p->modulation = QAM_256;
3172 break; 3166 break;
3173 default: 3167 default:
3174 break; 3168 break;
3175 } 3169 }
3176 3170
3177 param->frequency = stv0367_get_tuner_freq(fe); 3171 p->frequency = stv0367_get_tuner_freq(fe);
3178 3172
3179 dprintk("%s: tuner frequency = %d\n", __func__, param->frequency); 3173 dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
3180 3174
3181 if (state->config->if_khz == 0) { 3175 if (state->config->if_khz == 0) {
3182 param->frequency += 3176 p->frequency +=
3183 (stv0367cab_get_derot_freq(state, cab_state->adc_clk) - 3177 (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
3184 cab_state->adc_clk / 4000); 3178 cab_state->adc_clk / 4000);
3185 return 0; 3179 return 0;
3186 } 3180 }
3187 3181
3188 if (state->config->if_khz > cab_state->adc_clk / 1000) 3182 if (state->config->if_khz > cab_state->adc_clk / 1000)
3189 param->frequency += (state->config->if_khz 3183 p->frequency += (state->config->if_khz
3190 - stv0367cab_get_derot_freq(state, cab_state->adc_clk) 3184 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3191 - cab_state->adc_clk / 1000); 3185 - cab_state->adc_clk / 1000);
3192 else 3186 else
3193 param->frequency += (state->config->if_khz 3187 p->frequency += (state->config->if_khz
3194 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)); 3188 - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
3195 3189
3196 return 0; 3190 return 0;
@@ -3386,9 +3380,9 @@ static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
3386}; 3380};
3387 3381
3388static struct dvb_frontend_ops stv0367cab_ops = { 3382static struct dvb_frontend_ops stv0367cab_ops = {
3383 .delsys = { SYS_DVBC_ANNEX_A },
3389 .info = { 3384 .info = {
3390 .name = "ST STV0367 DVB-C", 3385 .name = "ST STV0367 DVB-C",
3391 .type = FE_QAM,
3392 .frequency_min = 47000000, 3386 .frequency_min = 47000000,
3393 .frequency_max = 862000000, 3387 .frequency_max = 862000000,
3394 .frequency_stepsize = 62500, 3388 .frequency_stepsize = 62500,
diff --git a/drivers/media/dvb/frontends/stv0900_core.c b/drivers/media/dvb/frontends/stv0900_core.c
index 0ca316d6fffa..7f1badaf0d03 100644
--- a/drivers/media/dvb/frontends/stv0900_core.c
+++ b/drivers/media/dvb/frontends/stv0900_core.c
@@ -973,22 +973,6 @@ static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
973 return DVBFE_ALGO_CUSTOM; 973 return DVBFE_ALGO_CUSTOM;
974} 974}
975 975
976static int stb0900_set_property(struct dvb_frontend *fe,
977 struct dtv_property *tvp)
978{
979 dprintk("%s(..)\n", __func__);
980
981 return 0;
982}
983
984static int stb0900_get_property(struct dvb_frontend *fe,
985 struct dtv_property *tvp)
986{
987 dprintk("%s(..)\n", __func__);
988
989 return 0;
990}
991
992void stv0900_start_search(struct stv0900_internal *intp, 976void stv0900_start_search(struct stv0900_internal *intp,
993 enum fe_stv0900_demod_num demod) 977 enum fe_stv0900_demod_num demod)
994{ 978{
@@ -1574,8 +1558,7 @@ static int stv0900_status(struct stv0900_internal *intp,
1574 return locked; 1558 return locked;
1575} 1559}
1576 1560
1577static enum dvbfe_search stv0900_search(struct dvb_frontend *fe, 1561static enum dvbfe_search stv0900_search(struct dvb_frontend *fe)
1578 struct dvb_frontend_parameters *params)
1579{ 1562{
1580 struct stv0900_state *state = fe->demodulator_priv; 1563 struct stv0900_state *state = fe->demodulator_priv;
1581 struct stv0900_internal *intp = state->internal; 1564 struct stv0900_internal *intp = state->internal;
@@ -1675,12 +1658,6 @@ static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
1675 return 0; 1658 return 0;
1676} 1659}
1677 1660
1678static int stv0900_track(struct dvb_frontend *fe,
1679 struct dvb_frontend_parameters *p)
1680{
1681 return 0;
1682}
1683
1684static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts) 1661static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
1685{ 1662{
1686 1663
@@ -1866,24 +1843,23 @@ static int stv0900_sleep(struct dvb_frontend *fe)
1866 return 0; 1843 return 0;
1867} 1844}
1868 1845
1869static int stv0900_get_frontend(struct dvb_frontend *fe, 1846static int stv0900_get_frontend(struct dvb_frontend *fe)
1870 struct dvb_frontend_parameters *p)
1871{ 1847{
1848 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1872 struct stv0900_state *state = fe->demodulator_priv; 1849 struct stv0900_state *state = fe->demodulator_priv;
1873 struct stv0900_internal *intp = state->internal; 1850 struct stv0900_internal *intp = state->internal;
1874 enum fe_stv0900_demod_num demod = state->demod; 1851 enum fe_stv0900_demod_num demod = state->demod;
1875 struct stv0900_signal_info p_result = intp->result[demod]; 1852 struct stv0900_signal_info p_result = intp->result[demod];
1876 1853
1877 p->frequency = p_result.locked ? p_result.frequency : 0; 1854 p->frequency = p_result.locked ? p_result.frequency : 0;
1878 p->u.qpsk.symbol_rate = p_result.locked ? p_result.symbol_rate : 0; 1855 p->symbol_rate = p_result.locked ? p_result.symbol_rate : 0;
1879 return 0; 1856 return 0;
1880} 1857}
1881 1858
1882static struct dvb_frontend_ops stv0900_ops = { 1859static struct dvb_frontend_ops stv0900_ops = {
1883 1860 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
1884 .info = { 1861 .info = {
1885 .name = "STV0900 frontend", 1862 .name = "STV0900 frontend",
1886 .type = FE_QPSK,
1887 .frequency_min = 950000, 1863 .frequency_min = 950000,
1888 .frequency_max = 2150000, 1864 .frequency_max = 2150000,
1889 .frequency_stepsize = 125, 1865 .frequency_stepsize = 125,
@@ -1907,10 +1883,7 @@ static struct dvb_frontend_ops stv0900_ops = {
1907 .diseqc_send_burst = stv0900_send_burst, 1883 .diseqc_send_burst = stv0900_send_burst,
1908 .diseqc_recv_slave_reply = stv0900_recv_slave_reply, 1884 .diseqc_recv_slave_reply = stv0900_recv_slave_reply,
1909 .set_tone = stv0900_set_tone, 1885 .set_tone = stv0900_set_tone,
1910 .set_property = stb0900_set_property,
1911 .get_property = stb0900_get_property,
1912 .search = stv0900_search, 1886 .search = stv0900_search,
1913 .track = stv0900_track,
1914 .read_status = stv0900_read_status, 1887 .read_status = stv0900_read_status,
1915 .read_ber = stv0900_read_ber, 1888 .read_ber = stv0900_read_ber,
1916 .read_signal_strength = stv0900_read_signal_strength, 1889 .read_signal_strength = stv0900_read_signal_strength,
diff --git a/drivers/media/dvb/frontends/stv090x.c b/drivers/media/dvb/frontends/stv090x.c
index ebda41936b90..4aef1877ed42 100644
--- a/drivers/media/dvb/frontends/stv090x.c
+++ b/drivers/media/dvb/frontends/stv090x.c
@@ -3427,17 +3427,17 @@ err:
3427 return -1; 3427 return -1;
3428} 3428}
3429 3429
3430static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) 3430static enum dvbfe_search stv090x_search(struct dvb_frontend *fe)
3431{ 3431{
3432 struct stv090x_state *state = fe->demodulator_priv; 3432 struct stv090x_state *state = fe->demodulator_priv;
3433 struct dtv_frontend_properties *props = &fe->dtv_property_cache; 3433 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3434 3434
3435 if (p->frequency == 0) 3435 if (props->frequency == 0)
3436 return DVBFE_ALGO_SEARCH_INVALID; 3436 return DVBFE_ALGO_SEARCH_INVALID;
3437 3437
3438 state->delsys = props->delivery_system; 3438 state->delsys = props->delivery_system;
3439 state->frequency = p->frequency; 3439 state->frequency = props->frequency;
3440 state->srate = p->u.qpsk.symbol_rate; 3440 state->srate = props->symbol_rate;
3441 state->search_mode = STV090x_SEARCH_AUTO; 3441 state->search_mode = STV090x_SEARCH_AUTO;
3442 state->algo = STV090x_COLD_SEARCH; 3442 state->algo = STV090x_COLD_SEARCH;
3443 state->fec = STV090x_PRERR; 3443 state->fec = STV090x_PRERR;
@@ -4712,10 +4712,9 @@ int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir, u8 value,
4712EXPORT_SYMBOL(stv090x_set_gpio); 4712EXPORT_SYMBOL(stv090x_set_gpio);
4713 4713
4714static struct dvb_frontend_ops stv090x_ops = { 4714static struct dvb_frontend_ops stv090x_ops = {
4715 4715 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
4716 .info = { 4716 .info = {
4717 .name = "STV090x Multistandard", 4717 .name = "STV090x Multistandard",
4718 .type = FE_QPSK,
4719 .frequency_min = 950000, 4718 .frequency_min = 950000,
4720 .frequency_max = 2150000, 4719 .frequency_max = 2150000,
4721 .frequency_stepsize = 0, 4720 .frequency_stepsize = 0,
@@ -4743,7 +4742,7 @@ static struct dvb_frontend_ops stv090x_ops = {
4743 .read_status = stv090x_read_status, 4742 .read_status = stv090x_read_status,
4744 .read_ber = stv090x_read_per, 4743 .read_ber = stv090x_read_per,
4745 .read_signal_strength = stv090x_read_signal_strength, 4744 .read_signal_strength = stv090x_read_signal_strength,
4746 .read_snr = stv090x_read_cnr 4745 .read_snr = stv090x_read_cnr,
4747}; 4746};
4748 4747
4749 4748
diff --git a/drivers/media/dvb/frontends/stv6110.c b/drivers/media/dvb/frontends/stv6110.c
index 2dca7c8e5148..20b5fa92c53e 100644
--- a/drivers/media/dvb/frontends/stv6110.c
+++ b/drivers/media/dvb/frontends/stv6110.c
@@ -347,8 +347,7 @@ static int stv6110_set_frequency(struct dvb_frontend *fe, u32 frequency)
347 return 0; 347 return 0;
348} 348}
349 349
350static int stv6110_set_params(struct dvb_frontend *fe, 350static int stv6110_set_params(struct dvb_frontend *fe)
351 struct dvb_frontend_parameters *params)
352{ 351{
353 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 352 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
354 u32 bandwidth = carrier_width(c->symbol_rate, c->rolloff); 353 u32 bandwidth = carrier_width(c->symbol_rate, c->rolloff);
diff --git a/drivers/media/dvb/frontends/tda10021.c b/drivers/media/dvb/frontends/tda10021.c
index 6ca533ea0f0e..1bff7f457e19 100644
--- a/drivers/media/dvb/frontends/tda10021.c
+++ b/drivers/media/dvb/frontends/tda10021.c
@@ -224,47 +224,86 @@ static int tda10021_init (struct dvb_frontend *fe)
224 return 0; 224 return 0;
225} 225}
226 226
227static int tda10021_set_parameters (struct dvb_frontend *fe, 227struct qam_params {
228 struct dvb_frontend_parameters *p) 228 u8 conf, agcref, lthr, mseth, aref;
229};
230
231static int tda10021_set_parameters(struct dvb_frontend *fe)
229{ 232{
233 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
234 u32 delsys = c->delivery_system;
235 unsigned qam = c->modulation;
236 bool is_annex_c;
237 u32 reg0x3d;
230 struct tda10021_state* state = fe->demodulator_priv; 238 struct tda10021_state* state = fe->demodulator_priv;
239 static const struct qam_params qam_params[] = {
240 /* Modulation Conf AGCref LTHR MSETH AREF */
241 [QPSK] = { 0x14, 0x78, 0x78, 0x8c, 0x96 },
242 [QAM_16] = { 0x00, 0x8c, 0x87, 0xa2, 0x91 },
243 [QAM_32] = { 0x04, 0x8c, 0x64, 0x74, 0x96 },
244 [QAM_64] = { 0x08, 0x6a, 0x46, 0x43, 0x6a },
245 [QAM_128] = { 0x0c, 0x78, 0x36, 0x34, 0x7e },
246 [QAM_256] = { 0x10, 0x5c, 0x26, 0x23, 0x6b },
247 };
248
249 switch (delsys) {
250 case SYS_DVBC_ANNEX_A:
251 is_annex_c = false;
252 break;
253 case SYS_DVBC_ANNEX_C:
254 is_annex_c = true;
255 break;
256 default:
257 return -EINVAL;
258 }
231 259
232 //table for QAM4-QAM256 ready QAM4 QAM16 QAM32 QAM64 QAM128 QAM256 260 /*
233 //CONF 261 * gcc optimizes the code bellow the same way as it would code:
234 static const u8 reg0x00 [] = { 0x14, 0x00, 0x04, 0x08, 0x0c, 0x10 }; 262 * "if (qam > 5) return -EINVAL;"
235 //AGCREF value 263 * Yet, the code is clearer, as it shows what QAM standards are
236 static const u8 reg0x01 [] = { 0x78, 0x8c, 0x8c, 0x6a, 0x78, 0x5c }; 264 * supported by the driver, and avoids the usage of magic numbers on
237 //LTHR value 265 * it.
238 static const u8 reg0x05 [] = { 0x78, 0x87, 0x64, 0x46, 0x36, 0x26 }; 266 */
239 //MSETH 267 switch (qam) {
240 static const u8 reg0x08 [] = { 0x8c, 0xa2, 0x74, 0x43, 0x34, 0x23 }; 268 case QPSK:
241 //AREF 269 case QAM_16:
242 static const u8 reg0x09 [] = { 0x96, 0x91, 0x96, 0x6a, 0x7e, 0x6b }; 270 case QAM_32:
243 271 case QAM_64:
244 int qam = p->u.qam.modulation; 272 case QAM_128:
245 273 case QAM_256:
246 if (qam < 0 || qam > 5) 274 break;
275 default:
247 return -EINVAL; 276 return -EINVAL;
277 }
248 278
249 if (p->inversion != INVERSION_ON && p->inversion != INVERSION_OFF) 279 if (c->inversion != INVERSION_ON && c->inversion != INVERSION_OFF)
250 return -EINVAL; 280 return -EINVAL;
251 281
252 //printk("tda10021: set frequency to %d qam=%d symrate=%d\n", p->frequency,qam,p->u.qam.symbol_rate); 282 /*printk("tda10021: set frequency to %d qam=%d symrate=%d\n", p->frequency,qam,p->symbol_rate);*/
253 283
254 if (fe->ops.tuner_ops.set_params) { 284 if (fe->ops.tuner_ops.set_params) {
255 fe->ops.tuner_ops.set_params(fe, p); 285 fe->ops.tuner_ops.set_params(fe);
256 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 286 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
257 } 287 }
258 288
259 tda10021_set_symbolrate (state, p->u.qam.symbol_rate); 289 tda10021_set_symbolrate(state, c->symbol_rate);
260 _tda10021_writereg (state, 0x34, state->pwm); 290 _tda10021_writereg(state, 0x34, state->pwm);
261 291
262 _tda10021_writereg (state, 0x01, reg0x01[qam]); 292 _tda10021_writereg(state, 0x01, qam_params[qam].agcref);
263 _tda10021_writereg (state, 0x05, reg0x05[qam]); 293 _tda10021_writereg(state, 0x05, qam_params[qam].lthr);
264 _tda10021_writereg (state, 0x08, reg0x08[qam]); 294 _tda10021_writereg(state, 0x08, qam_params[qam].mseth);
265 _tda10021_writereg (state, 0x09, reg0x09[qam]); 295 _tda10021_writereg(state, 0x09, qam_params[qam].aref);
266 296
267 tda10021_setup_reg0 (state, reg0x00[qam], p->inversion); 297 /*
298 * Bit 0 == 0 means roll-off = 0.15 (Annex A)
299 * == 1 means roll-off = 0.13 (Annex C)
300 */
301 reg0x3d = tda10021_readreg (state, 0x3d);
302 if (is_annex_c)
303 _tda10021_writereg (state, 0x3d, 0x01 | reg0x3d);
304 else
305 _tda10021_writereg (state, 0x3d, 0xfe & reg0x3d);
306 tda10021_setup_reg0(state, qam_params[qam].conf, c->inversion);
268 307
269 return 0; 308 return 0;
270} 309}
@@ -347,8 +386,9 @@ static int tda10021_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
347 return 0; 386 return 0;
348} 387}
349 388
350static int tda10021_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 389static int tda10021_get_frontend(struct dvb_frontend *fe)
351{ 390{
391 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
352 struct tda10021_state* state = fe->demodulator_priv; 392 struct tda10021_state* state = fe->demodulator_priv;
353 int sync; 393 int sync;
354 s8 afc = 0; 394 s8 afc = 0;
@@ -360,17 +400,17 @@ static int tda10021_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_pa
360 printk(sync & 2 ? "DVB: TDA10021(%d): AFC (%d) %dHz\n" : 400 printk(sync & 2 ? "DVB: TDA10021(%d): AFC (%d) %dHz\n" :
361 "DVB: TDA10021(%d): [AFC (%d) %dHz]\n", 401 "DVB: TDA10021(%d): [AFC (%d) %dHz]\n",
362 state->frontend.dvb->num, afc, 402 state->frontend.dvb->num, afc,
363 -((s32)p->u.qam.symbol_rate * afc) >> 10); 403 -((s32)p->symbol_rate * afc) >> 10);
364 } 404 }
365 405
366 p->inversion = ((state->reg0 & 0x20) == 0x20) ^ (state->config->invert != 0) ? INVERSION_ON : INVERSION_OFF; 406 p->inversion = ((state->reg0 & 0x20) == 0x20) ^ (state->config->invert != 0) ? INVERSION_ON : INVERSION_OFF;
367 p->u.qam.modulation = ((state->reg0 >> 2) & 7) + QAM_16; 407 p->modulation = ((state->reg0 >> 2) & 7) + QAM_16;
368 408
369 p->u.qam.fec_inner = FEC_NONE; 409 p->fec_inner = FEC_NONE;
370 p->frequency = ((p->frequency + 31250) / 62500) * 62500; 410 p->frequency = ((p->frequency + 31250) / 62500) * 62500;
371 411
372 if (sync & 2) 412 if (sync & 2)
373 p->frequency -= ((s32)p->u.qam.symbol_rate * afc) >> 10; 413 p->frequency -= ((s32)p->symbol_rate * afc) >> 10;
374 414
375 return 0; 415 return 0;
376} 416}
@@ -444,10 +484,9 @@ error:
444} 484}
445 485
446static struct dvb_frontend_ops tda10021_ops = { 486static struct dvb_frontend_ops tda10021_ops = {
447 487 .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBC_ANNEX_C },
448 .info = { 488 .info = {
449 .name = "Philips TDA10021 DVB-C", 489 .name = "Philips TDA10021 DVB-C",
450 .type = FE_QAM,
451 .frequency_stepsize = 62500, 490 .frequency_stepsize = 62500,
452 .frequency_min = 47000000, 491 .frequency_min = 47000000,
453 .frequency_max = 862000000, 492 .frequency_max = 862000000,
diff --git a/drivers/media/dvb/frontends/tda10023.c b/drivers/media/dvb/frontends/tda10023.c
index a3c34eecdee9..ca1e0d54b69a 100644
--- a/drivers/media/dvb/frontends/tda10023.c
+++ b/drivers/media/dvb/frontends/tda10023.c
@@ -298,42 +298,80 @@ static int tda10023_init (struct dvb_frontend *fe)
298 return 0; 298 return 0;
299} 299}
300 300
301static int tda10023_set_parameters (struct dvb_frontend *fe, 301struct qam_params {
302 struct dvb_frontend_parameters *p) 302 u8 qam, lockthr, mseth, aref, agcrefnyq, eragnyq_thd;
303};
304
305static int tda10023_set_parameters(struct dvb_frontend *fe)
303{ 306{
307 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
308 u32 delsys = c->delivery_system;
309 unsigned qam = c->modulation;
310 bool is_annex_c;
304 struct tda10023_state* state = fe->demodulator_priv; 311 struct tda10023_state* state = fe->demodulator_priv;
305 312 static const struct qam_params qam_params[] = {
306 static int qamvals[6][6] = { 313 /* Modulation QAM LOCKTHR MSETH AREF AGCREFNYQ ERAGCNYQ_THD */
307 // QAM LOCKTHR MSETH AREF AGCREFNYQ ERAGCNYQ_THD 314 [QPSK] = { (5<<2), 0x78, 0x8c, 0x96, 0x78, 0x4c },
308 { (5<<2), 0x78, 0x8c, 0x96, 0x78, 0x4c }, // 4 QAM 315 [QAM_16] = { (0<<2), 0x87, 0xa2, 0x91, 0x8c, 0x57 },
309 { (0<<2), 0x87, 0xa2, 0x91, 0x8c, 0x57 }, // 16 QAM 316 [QAM_32] = { (1<<2), 0x64, 0x74, 0x96, 0x8c, 0x57 },
310 { (1<<2), 0x64, 0x74, 0x96, 0x8c, 0x57 }, // 32 QAM 317 [QAM_64] = { (2<<2), 0x46, 0x43, 0x6a, 0x6a, 0x44 },
311 { (2<<2), 0x46, 0x43, 0x6a, 0x6a, 0x44 }, // 64 QAM 318 [QAM_128] = { (3<<2), 0x36, 0x34, 0x7e, 0x78, 0x4c },
312 { (3<<2), 0x36, 0x34, 0x7e, 0x78, 0x4c }, // 128 QAM 319 [QAM_256] = { (4<<2), 0x26, 0x23, 0x6c, 0x5c, 0x3c },
313 { (4<<2), 0x26, 0x23, 0x6c, 0x5c, 0x3c }, // 256 QAM
314 }; 320 };
315 321
316 int qam = p->u.qam.modulation; 322 switch (delsys) {
323 case SYS_DVBC_ANNEX_A:
324 is_annex_c = false;
325 break;
326 case SYS_DVBC_ANNEX_C:
327 is_annex_c = true;
328 break;
329 default:
330 return -EINVAL;
331 }
317 332
318 if (qam < 0 || qam > 5) 333 /*
334 * gcc optimizes the code bellow the same way as it would code:
335 * "if (qam > 5) return -EINVAL;"
336 * Yet, the code is clearer, as it shows what QAM standards are
337 * supported by the driver, and avoids the usage of magic numbers on
338 * it.
339 */
340 switch (qam) {
341 case QPSK:
342 case QAM_16:
343 case QAM_32:
344 case QAM_64:
345 case QAM_128:
346 case QAM_256:
347 break;
348 default:
319 return -EINVAL; 349 return -EINVAL;
350 }
320 351
321 if (fe->ops.tuner_ops.set_params) { 352 if (fe->ops.tuner_ops.set_params) {
322 fe->ops.tuner_ops.set_params(fe, p); 353 fe->ops.tuner_ops.set_params(fe);
323 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 354 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
324 } 355 }
325 356
326 tda10023_set_symbolrate (state, p->u.qam.symbol_rate); 357 tda10023_set_symbolrate(state, c->symbol_rate);
327 tda10023_writereg (state, 0x05, qamvals[qam][1]); 358 tda10023_writereg(state, 0x05, qam_params[qam].lockthr);
328 tda10023_writereg (state, 0x08, qamvals[qam][2]); 359 tda10023_writereg(state, 0x08, qam_params[qam].mseth);
329 tda10023_writereg (state, 0x09, qamvals[qam][3]); 360 tda10023_writereg(state, 0x09, qam_params[qam].aref);
330 tda10023_writereg (state, 0xb4, qamvals[qam][4]); 361 tda10023_writereg(state, 0xb4, qam_params[qam].agcrefnyq);
331 tda10023_writereg (state, 0xb6, qamvals[qam][5]); 362 tda10023_writereg(state, 0xb6, qam_params[qam].eragnyq_thd);
332 363#if 0
333// tda10023_writereg (state, 0x04, (p->inversion?0x12:0x32)); 364 tda10023_writereg(state, 0x04, (c->inversion ? 0x12 : 0x32));
334// tda10023_writebit (state, 0x04, 0x60, (p->inversion?0:0x20)); 365 tda10023_writebit(state, 0x04, 0x60, (c->inversion ? 0 : 0x20));
335 tda10023_writebit (state, 0x04, 0x40, 0x40); 366#endif
336 tda10023_setup_reg0 (state, qamvals[qam][0]); 367 tda10023_writebit(state, 0x04, 0x40, 0x40);
368
369 if (is_annex_c)
370 tda10023_writebit(state, 0x3d, 0xfc, 0x03);
371 else
372 tda10023_writebit(state, 0x3d, 0xfc, 0x02);
373
374 tda10023_setup_reg0(state, qam_params[qam].qam);
337 375
338 return 0; 376 return 0;
339} 377}
@@ -418,8 +456,9 @@ static int tda10023_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
418 return 0; 456 return 0;
419} 457}
420 458
421static int tda10023_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 459static int tda10023_get_frontend(struct dvb_frontend *fe)
422{ 460{
461 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
423 struct tda10023_state* state = fe->demodulator_priv; 462 struct tda10023_state* state = fe->demodulator_priv;
424 int sync,inv; 463 int sync,inv;
425 s8 afc = 0; 464 s8 afc = 0;
@@ -433,17 +472,17 @@ static int tda10023_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_pa
433 printk(sync & 2 ? "DVB: TDA10023(%d): AFC (%d) %dHz\n" : 472 printk(sync & 2 ? "DVB: TDA10023(%d): AFC (%d) %dHz\n" :
434 "DVB: TDA10023(%d): [AFC (%d) %dHz]\n", 473 "DVB: TDA10023(%d): [AFC (%d) %dHz]\n",
435 state->frontend.dvb->num, afc, 474 state->frontend.dvb->num, afc,
436 -((s32)p->u.qam.symbol_rate * afc) >> 10); 475 -((s32)p->symbol_rate * afc) >> 10);
437 } 476 }
438 477
439 p->inversion = (inv&0x20?0:1); 478 p->inversion = (inv&0x20?0:1);
440 p->u.qam.modulation = ((state->reg0 >> 2) & 7) + QAM_16; 479 p->modulation = ((state->reg0 >> 2) & 7) + QAM_16;
441 480
442 p->u.qam.fec_inner = FEC_NONE; 481 p->fec_inner = FEC_NONE;
443 p->frequency = ((p->frequency + 31250) / 62500) * 62500; 482 p->frequency = ((p->frequency + 31250) / 62500) * 62500;
444 483
445 if (sync & 2) 484 if (sync & 2)
446 p->frequency -= ((s32)p->u.qam.symbol_rate * afc) >> 10; 485 p->frequency -= ((s32)p->symbol_rate * afc) >> 10;
447 486
448 return 0; 487 return 0;
449} 488}
@@ -534,10 +573,9 @@ error:
534} 573}
535 574
536static struct dvb_frontend_ops tda10023_ops = { 575static struct dvb_frontend_ops tda10023_ops = {
537 576 .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBC_ANNEX_C },
538 .info = { 577 .info = {
539 .name = "Philips TDA10023 DVB-C", 578 .name = "Philips TDA10023 DVB-C",
540 .type = FE_QAM,
541 .frequency_stepsize = 62500, 579 .frequency_stepsize = 62500,
542 .frequency_min = 47000000, 580 .frequency_min = 47000000,
543 .frequency_max = 862000000, 581 .frequency_max = 862000000,
@@ -557,7 +595,6 @@ static struct dvb_frontend_ops tda10023_ops = {
557 595
558 .set_frontend = tda10023_set_parameters, 596 .set_frontend = tda10023_set_parameters,
559 .get_frontend = tda10023_get_frontend, 597 .get_frontend = tda10023_get_frontend,
560
561 .read_status = tda10023_read_status, 598 .read_status = tda10023_read_status,
562 .read_ber = tda10023_read_ber, 599 .read_ber = tda10023_read_ber,
563 .read_signal_strength = tda10023_read_signal_strength, 600 .read_signal_strength = tda10023_read_signal_strength,
diff --git a/drivers/media/dvb/frontends/tda10048.c b/drivers/media/dvb/frontends/tda10048.c
index 7f105946a434..71fb63299de7 100644
--- a/drivers/media/dvb/frontends/tda10048.c
+++ b/drivers/media/dvb/frontends/tda10048.c
@@ -153,7 +153,7 @@ struct tda10048_state {
153 u32 pll_pfactor; 153 u32 pll_pfactor;
154 u32 sample_freq; 154 u32 sample_freq;
155 155
156 enum fe_bandwidth bandwidth; 156 u32 bandwidth;
157}; 157};
158 158
159static struct init_tab { 159static struct init_tab {
@@ -341,21 +341,14 @@ static int tda10048_set_wref(struct dvb_frontend *fe, u32 sample_freq_hz,
341{ 341{
342 struct tda10048_state *state = fe->demodulator_priv; 342 struct tda10048_state *state = fe->demodulator_priv;
343 u64 t, z; 343 u64 t, z;
344 u32 b = 8000000;
345 344
346 dprintk(1, "%s()\n", __func__); 345 dprintk(1, "%s()\n", __func__);
347 346
348 if (sample_freq_hz == 0) 347 if (sample_freq_hz == 0)
349 return -EINVAL; 348 return -EINVAL;
350 349
351 if (bw == BANDWIDTH_6_MHZ)
352 b = 6000000;
353 else
354 if (bw == BANDWIDTH_7_MHZ)
355 b = 7000000;
356
357 /* WREF = (B / (7 * fs)) * 2^31 */ 350 /* WREF = (B / (7 * fs)) * 2^31 */
358 t = b * 10; 351 t = bw * 10;
359 /* avoid warning: this decimal constant is unsigned only in ISO C90 */ 352 /* avoid warning: this decimal constant is unsigned only in ISO C90 */
360 /* t *= 2147483648 on 32bit platforms */ 353 /* t *= 2147483648 on 32bit platforms */
361 t *= (2048 * 1024); 354 t *= (2048 * 1024);
@@ -378,25 +371,18 @@ static int tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz,
378{ 371{
379 struct tda10048_state *state = fe->demodulator_priv; 372 struct tda10048_state *state = fe->demodulator_priv;
380 u64 t; 373 u64 t;
381 u32 b = 8000000;
382 374
383 dprintk(1, "%s()\n", __func__); 375 dprintk(1, "%s()\n", __func__);
384 376
385 if (sample_freq_hz == 0) 377 if (sample_freq_hz == 0)
386 return -EINVAL; 378 return -EINVAL;
387 379
388 if (bw == BANDWIDTH_6_MHZ)
389 b = 6000000;
390 else
391 if (bw == BANDWIDTH_7_MHZ)
392 b = 7000000;
393
394 /* INVWREF = ((7 * fs) / B) * 2^5 */ 380 /* INVWREF = ((7 * fs) / B) * 2^5 */
395 t = sample_freq_hz; 381 t = sample_freq_hz;
396 t *= 7; 382 t *= 7;
397 t *= 32; 383 t *= 32;
398 t *= 10; 384 t *= 10;
399 do_div(t, b); 385 do_div(t, bw);
400 t += 5; 386 t += 5;
401 do_div(t, 10); 387 do_div(t, 10);
402 388
@@ -407,16 +393,16 @@ static int tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz,
407} 393}
408 394
409static int tda10048_set_bandwidth(struct dvb_frontend *fe, 395static int tda10048_set_bandwidth(struct dvb_frontend *fe,
410 enum fe_bandwidth bw) 396 u32 bw)
411{ 397{
412 struct tda10048_state *state = fe->demodulator_priv; 398 struct tda10048_state *state = fe->demodulator_priv;
413 dprintk(1, "%s(bw=%d)\n", __func__, bw); 399 dprintk(1, "%s(bw=%d)\n", __func__, bw);
414 400
415 /* Bandwidth setting may need to be adjusted */ 401 /* Bandwidth setting may need to be adjusted */
416 switch (bw) { 402 switch (bw) {
417 case BANDWIDTH_6_MHZ: 403 case 6000000:
418 case BANDWIDTH_7_MHZ: 404 case 7000000:
419 case BANDWIDTH_8_MHZ: 405 case 8000000:
420 tda10048_set_wref(fe, state->sample_freq, bw); 406 tda10048_set_wref(fe, state->sample_freq, bw);
421 tda10048_set_invwref(fe, state->sample_freq, bw); 407 tda10048_set_invwref(fe, state->sample_freq, bw);
422 break; 408 break;
@@ -430,7 +416,7 @@ static int tda10048_set_bandwidth(struct dvb_frontend *fe,
430 return 0; 416 return 0;
431} 417}
432 418
433static int tda10048_set_if(struct dvb_frontend *fe, enum fe_bandwidth bw) 419static int tda10048_set_if(struct dvb_frontend *fe, u32 bw)
434{ 420{
435 struct tda10048_state *state = fe->demodulator_priv; 421 struct tda10048_state *state = fe->demodulator_priv;
436 struct tda10048_config *config = &state->config; 422 struct tda10048_config *config = &state->config;
@@ -441,13 +427,13 @@ static int tda10048_set_if(struct dvb_frontend *fe, enum fe_bandwidth bw)
441 427
442 /* based on target bandwidth and clk we calculate pll factors */ 428 /* based on target bandwidth and clk we calculate pll factors */
443 switch (bw) { 429 switch (bw) {
444 case BANDWIDTH_6_MHZ: 430 case 6000000:
445 if_freq_khz = config->dtv6_if_freq_khz; 431 if_freq_khz = config->dtv6_if_freq_khz;
446 break; 432 break;
447 case BANDWIDTH_7_MHZ: 433 case 7000000:
448 if_freq_khz = config->dtv7_if_freq_khz; 434 if_freq_khz = config->dtv7_if_freq_khz;
449 break; 435 break;
450 case BANDWIDTH_8_MHZ: 436 case 8000000:
451 if_freq_khz = config->dtv8_if_freq_khz; 437 if_freq_khz = config->dtv8_if_freq_khz;
452 break; 438 break;
453 default: 439 default:
@@ -601,7 +587,7 @@ static int tda10048_set_inversion(struct dvb_frontend *fe, int inversion)
601 587
602/* Retrieve the demod settings */ 588/* Retrieve the demod settings */
603static int tda10048_get_tps(struct tda10048_state *state, 589static int tda10048_get_tps(struct tda10048_state *state,
604 struct dvb_ofdm_parameters *p) 590 struct dtv_frontend_properties *p)
605{ 591{
606 u8 val; 592 u8 val;
607 593
@@ -612,27 +598,27 @@ static int tda10048_get_tps(struct tda10048_state *state,
612 val = tda10048_readreg(state, TDA10048_OUT_CONF2); 598 val = tda10048_readreg(state, TDA10048_OUT_CONF2);
613 switch ((val & 0x60) >> 5) { 599 switch ((val & 0x60) >> 5) {
614 case 0: 600 case 0:
615 p->constellation = QPSK; 601 p->modulation = QPSK;
616 break; 602 break;
617 case 1: 603 case 1:
618 p->constellation = QAM_16; 604 p->modulation = QAM_16;
619 break; 605 break;
620 case 2: 606 case 2:
621 p->constellation = QAM_64; 607 p->modulation = QAM_64;
622 break; 608 break;
623 } 609 }
624 switch ((val & 0x18) >> 3) { 610 switch ((val & 0x18) >> 3) {
625 case 0: 611 case 0:
626 p->hierarchy_information = HIERARCHY_NONE; 612 p->hierarchy = HIERARCHY_NONE;
627 break; 613 break;
628 case 1: 614 case 1:
629 p->hierarchy_information = HIERARCHY_1; 615 p->hierarchy = HIERARCHY_1;
630 break; 616 break;
631 case 2: 617 case 2:
632 p->hierarchy_information = HIERARCHY_2; 618 p->hierarchy = HIERARCHY_2;
633 break; 619 break;
634 case 3: 620 case 3:
635 p->hierarchy_information = HIERARCHY_4; 621 p->hierarchy = HIERARCHY_4;
636 break; 622 break;
637 } 623 }
638 switch (val & 0x07) { 624 switch (val & 0x07) {
@@ -738,17 +724,17 @@ static int tda10048_output_mode(struct dvb_frontend *fe, int serial)
738 724
739/* Talk to the demod, set the FEC, GUARD, QAM settings etc */ 725/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
740/* TODO: Support manual tuning with specific params */ 726/* TODO: Support manual tuning with specific params */
741static int tda10048_set_frontend(struct dvb_frontend *fe, 727static int tda10048_set_frontend(struct dvb_frontend *fe)
742 struct dvb_frontend_parameters *p)
743{ 728{
729 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
744 struct tda10048_state *state = fe->demodulator_priv; 730 struct tda10048_state *state = fe->demodulator_priv;
745 731
746 dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency); 732 dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency);
747 733
748 /* Update the I/F pll's if the bandwidth changes */ 734 /* Update the I/F pll's if the bandwidth changes */
749 if (p->u.ofdm.bandwidth != state->bandwidth) { 735 if (p->bandwidth_hz != state->bandwidth) {
750 tda10048_set_if(fe, p->u.ofdm.bandwidth); 736 tda10048_set_if(fe, p->bandwidth_hz);
751 tda10048_set_bandwidth(fe, p->u.ofdm.bandwidth); 737 tda10048_set_bandwidth(fe, p->bandwidth_hz);
752 } 738 }
753 739
754 if (fe->ops.tuner_ops.set_params) { 740 if (fe->ops.tuner_ops.set_params) {
@@ -756,7 +742,7 @@ static int tda10048_set_frontend(struct dvb_frontend *fe,
756 if (fe->ops.i2c_gate_ctrl) 742 if (fe->ops.i2c_gate_ctrl)
757 fe->ops.i2c_gate_ctrl(fe, 1); 743 fe->ops.i2c_gate_ctrl(fe, 1);
758 744
759 fe->ops.tuner_ops.set_params(fe, p); 745 fe->ops.tuner_ops.set_params(fe);
760 746
761 if (fe->ops.i2c_gate_ctrl) 747 if (fe->ops.i2c_gate_ctrl)
762 fe->ops.i2c_gate_ctrl(fe, 0); 748 fe->ops.i2c_gate_ctrl(fe, 0);
@@ -797,8 +783,8 @@ static int tda10048_init(struct dvb_frontend *fe)
797 tda10048_set_inversion(fe, config->inversion); 783 tda10048_set_inversion(fe, config->inversion);
798 784
799 /* Establish default RF values */ 785 /* Establish default RF values */
800 tda10048_set_if(fe, BANDWIDTH_8_MHZ); 786 tda10048_set_if(fe, 8000000);
801 tda10048_set_bandwidth(fe, BANDWIDTH_8_MHZ); 787 tda10048_set_bandwidth(fe, 8000000);
802 788
803 /* Ensure we leave the gate closed */ 789 /* Ensure we leave the gate closed */
804 tda10048_i2c_gate_ctrl(fe, 0); 790 tda10048_i2c_gate_ctrl(fe, 0);
@@ -1042,9 +1028,9 @@ static int tda10048_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1042 return 0; 1028 return 0;
1043} 1029}
1044 1030
1045static int tda10048_get_frontend(struct dvb_frontend *fe, 1031static int tda10048_get_frontend(struct dvb_frontend *fe)
1046 struct dvb_frontend_parameters *p)
1047{ 1032{
1033 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1048 struct tda10048_state *state = fe->demodulator_priv; 1034 struct tda10048_state *state = fe->demodulator_priv;
1049 1035
1050 dprintk(1, "%s()\n", __func__); 1036 dprintk(1, "%s()\n", __func__);
@@ -1052,7 +1038,7 @@ static int tda10048_get_frontend(struct dvb_frontend *fe,
1052 p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1) 1038 p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1)
1053 & 0x20 ? INVERSION_ON : INVERSION_OFF; 1039 & 0x20 ? INVERSION_ON : INVERSION_OFF;
1054 1040
1055 return tda10048_get_tps(state, &p->u.ofdm); 1041 return tda10048_get_tps(state, p);
1056} 1042}
1057 1043
1058static int tda10048_get_tune_settings(struct dvb_frontend *fe, 1044static int tda10048_get_tune_settings(struct dvb_frontend *fe,
@@ -1126,7 +1112,7 @@ struct dvb_frontend *tda10048_attach(const struct tda10048_config *config,
1126 memcpy(&state->config, config, sizeof(*config)); 1112 memcpy(&state->config, config, sizeof(*config));
1127 state->i2c = i2c; 1113 state->i2c = i2c;
1128 state->fwloaded = config->no_firmware; 1114 state->fwloaded = config->no_firmware;
1129 state->bandwidth = BANDWIDTH_8_MHZ; 1115 state->bandwidth = 8000000;
1130 1116
1131 /* check if the demod is present */ 1117 /* check if the demod is present */
1132 if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048) 1118 if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048)
@@ -1152,11 +1138,11 @@ struct dvb_frontend *tda10048_attach(const struct tda10048_config *config,
1152 tda10048_establish_defaults(&state->frontend); 1138 tda10048_establish_defaults(&state->frontend);
1153 1139
1154 /* Set the xtal and freq defaults */ 1140 /* Set the xtal and freq defaults */
1155 if (tda10048_set_if(&state->frontend, BANDWIDTH_8_MHZ) != 0) 1141 if (tda10048_set_if(&state->frontend, 8000000) != 0)
1156 goto error; 1142 goto error;
1157 1143
1158 /* Default bandwidth */ 1144 /* Default bandwidth */
1159 if (tda10048_set_bandwidth(&state->frontend, BANDWIDTH_8_MHZ) != 0) 1145 if (tda10048_set_bandwidth(&state->frontend, 8000000) != 0)
1160 goto error; 1146 goto error;
1161 1147
1162 /* Leave the gate closed */ 1148 /* Leave the gate closed */
@@ -1171,10 +1157,9 @@ error:
1171EXPORT_SYMBOL(tda10048_attach); 1157EXPORT_SYMBOL(tda10048_attach);
1172 1158
1173static struct dvb_frontend_ops tda10048_ops = { 1159static struct dvb_frontend_ops tda10048_ops = {
1174 1160 .delsys = { SYS_DVBT },
1175 .info = { 1161 .info = {
1176 .name = "NXP TDA10048HN DVB-T", 1162 .name = "NXP TDA10048HN DVB-T",
1177 .type = FE_OFDM,
1178 .frequency_min = 177000000, 1163 .frequency_min = 177000000,
1179 .frequency_max = 858000000, 1164 .frequency_max = 858000000,
1180 .frequency_stepsize = 166666, 1165 .frequency_stepsize = 166666,
diff --git a/drivers/media/dvb/frontends/tda1004x.c b/drivers/media/dvb/frontends/tda1004x.c
index ea485d923550..ae6f22aae677 100644
--- a/drivers/media/dvb/frontends/tda1004x.c
+++ b/drivers/media/dvb/frontends/tda1004x.c
@@ -224,22 +224,22 @@ static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
224} 224}
225 225
226static int tda10045h_set_bandwidth(struct tda1004x_state *state, 226static int tda10045h_set_bandwidth(struct tda1004x_state *state,
227 fe_bandwidth_t bandwidth) 227 u32 bandwidth)
228{ 228{
229 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f }; 229 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
230 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb }; 230 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
231 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 }; 231 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
232 232
233 switch (bandwidth) { 233 switch (bandwidth) {
234 case BANDWIDTH_6_MHZ: 234 case 6000000:
235 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz)); 235 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
236 break; 236 break;
237 237
238 case BANDWIDTH_7_MHZ: 238 case 7000000:
239 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz)); 239 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
240 break; 240 break;
241 241
242 case BANDWIDTH_8_MHZ: 242 case 8000000:
243 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz)); 243 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
244 break; 244 break;
245 245
@@ -253,7 +253,7 @@ static int tda10045h_set_bandwidth(struct tda1004x_state *state,
253} 253}
254 254
255static int tda10046h_set_bandwidth(struct tda1004x_state *state, 255static int tda10046h_set_bandwidth(struct tda1004x_state *state,
256 fe_bandwidth_t bandwidth) 256 u32 bandwidth)
257{ 257{
258 static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 }; 258 static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
259 static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f }; 259 static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
@@ -270,7 +270,7 @@ static int tda10046h_set_bandwidth(struct tda1004x_state *state,
270 else 270 else
271 tda10046_clk53m = 1; 271 tda10046_clk53m = 1;
272 switch (bandwidth) { 272 switch (bandwidth) {
273 case BANDWIDTH_6_MHZ: 273 case 6000000:
274 if (tda10046_clk53m) 274 if (tda10046_clk53m)
275 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M, 275 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
276 sizeof(bandwidth_6mhz_53M)); 276 sizeof(bandwidth_6mhz_53M));
@@ -283,7 +283,7 @@ static int tda10046h_set_bandwidth(struct tda1004x_state *state,
283 } 283 }
284 break; 284 break;
285 285
286 case BANDWIDTH_7_MHZ: 286 case 7000000:
287 if (tda10046_clk53m) 287 if (tda10046_clk53m)
288 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M, 288 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
289 sizeof(bandwidth_7mhz_53M)); 289 sizeof(bandwidth_7mhz_53M));
@@ -296,7 +296,7 @@ static int tda10046h_set_bandwidth(struct tda1004x_state *state,
296 } 296 }
297 break; 297 break;
298 298
299 case BANDWIDTH_8_MHZ: 299 case 8000000:
300 if (tda10046_clk53m) 300 if (tda10046_clk53m)
301 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M, 301 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
302 sizeof(bandwidth_8mhz_53M)); 302 sizeof(bandwidth_8mhz_53M));
@@ -409,7 +409,7 @@ static int tda10045_fwupload(struct dvb_frontend* fe)
409 msleep(10); 409 msleep(10);
410 410
411 /* set parameters */ 411 /* set parameters */
412 tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ); 412 tda10045h_set_bandwidth(state, 8000000);
413 413
414 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN); 414 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
415 release_firmware(fw); 415 release_firmware(fw);
@@ -473,7 +473,7 @@ static void tda10046_init_plls(struct dvb_frontend* fe)
473 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f); 473 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
474 break; 474 break;
475 } 475 }
476 tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz 476 tda10046h_set_bandwidth(state, 8000000); /* default bandwidth 8 MHz */
477 /* let the PLLs settle */ 477 /* let the PLLs settle */
478 msleep(120); 478 msleep(120);
479} 479}
@@ -697,9 +697,9 @@ static int tda10046_init(struct dvb_frontend* fe)
697 return 0; 697 return 0;
698} 698}
699 699
700static int tda1004x_set_fe(struct dvb_frontend* fe, 700static int tda1004x_set_fe(struct dvb_frontend *fe)
701 struct dvb_frontend_parameters *fe_params)
702{ 701{
702 struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
703 struct tda1004x_state* state = fe->demodulator_priv; 703 struct tda1004x_state* state = fe->demodulator_priv;
704 int tmp; 704 int tmp;
705 int inversion; 705 int inversion;
@@ -718,7 +718,7 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
718 718
719 // set frequency 719 // set frequency
720 if (fe->ops.tuner_ops.set_params) { 720 if (fe->ops.tuner_ops.set_params) {
721 fe->ops.tuner_ops.set_params(fe, fe_params); 721 fe->ops.tuner_ops.set_params(fe);
722 if (fe->ops.i2c_gate_ctrl) 722 if (fe->ops.i2c_gate_ctrl)
723 fe->ops.i2c_gate_ctrl(fe, 0); 723 fe->ops.i2c_gate_ctrl(fe, 0);
724 } 724 }
@@ -726,37 +726,37 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
726 // Hardcoded to use auto as much as possible on the TDA10045 as it 726 // Hardcoded to use auto as much as possible on the TDA10045 as it
727 // is very unreliable if AUTO mode is _not_ used. 727 // is very unreliable if AUTO mode is _not_ used.
728 if (state->demod_type == TDA1004X_DEMOD_TDA10045) { 728 if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
729 fe_params->u.ofdm.code_rate_HP = FEC_AUTO; 729 fe_params->code_rate_HP = FEC_AUTO;
730 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO; 730 fe_params->guard_interval = GUARD_INTERVAL_AUTO;
731 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO; 731 fe_params->transmission_mode = TRANSMISSION_MODE_AUTO;
732 } 732 }
733 733
734 // Set standard params.. or put them to auto 734 // Set standard params.. or put them to auto
735 if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) || 735 if ((fe_params->code_rate_HP == FEC_AUTO) ||
736 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) || 736 (fe_params->code_rate_LP == FEC_AUTO) ||
737 (fe_params->u.ofdm.constellation == QAM_AUTO) || 737 (fe_params->modulation == QAM_AUTO) ||
738 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) { 738 (fe_params->hierarchy == HIERARCHY_AUTO)) {
739 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto 739 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
740 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits 740 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */
741 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits 741 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
742 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits 742 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
743 } else { 743 } else {
744 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto 744 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
745 745
746 // set HP FEC 746 // set HP FEC
747 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP); 747 tmp = tda1004x_encode_fec(fe_params->code_rate_HP);
748 if (tmp < 0) 748 if (tmp < 0)
749 return tmp; 749 return tmp;
750 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp); 750 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
751 751
752 // set LP FEC 752 // set LP FEC
753 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP); 753 tmp = tda1004x_encode_fec(fe_params->code_rate_LP);
754 if (tmp < 0) 754 if (tmp < 0)
755 return tmp; 755 return tmp;
756 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3); 756 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
757 757
758 // set constellation 758 /* set modulation */
759 switch (fe_params->u.ofdm.constellation) { 759 switch (fe_params->modulation) {
760 case QPSK: 760 case QPSK:
761 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0); 761 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
762 break; 762 break;
@@ -774,7 +774,7 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
774 } 774 }
775 775
776 // set hierarchy 776 // set hierarchy
777 switch (fe_params->u.ofdm.hierarchy_information) { 777 switch (fe_params->hierarchy) {
778 case HIERARCHY_NONE: 778 case HIERARCHY_NONE:
779 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5); 779 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
780 break; 780 break;
@@ -799,11 +799,11 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
799 // set bandwidth 799 // set bandwidth
800 switch (state->demod_type) { 800 switch (state->demod_type) {
801 case TDA1004X_DEMOD_TDA10045: 801 case TDA1004X_DEMOD_TDA10045:
802 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth); 802 tda10045h_set_bandwidth(state, fe_params->bandwidth_hz);
803 break; 803 break;
804 804
805 case TDA1004X_DEMOD_TDA10046: 805 case TDA1004X_DEMOD_TDA10046:
806 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth); 806 tda10046h_set_bandwidth(state, fe_params->bandwidth_hz);
807 break; 807 break;
808 } 808 }
809 809
@@ -825,7 +825,7 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
825 } 825 }
826 826
827 // set guard interval 827 // set guard interval
828 switch (fe_params->u.ofdm.guard_interval) { 828 switch (fe_params->guard_interval) {
829 case GUARD_INTERVAL_1_32: 829 case GUARD_INTERVAL_1_32:
830 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); 830 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
831 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); 831 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
@@ -856,7 +856,7 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
856 } 856 }
857 857
858 // set transmission mode 858 // set transmission mode
859 switch (fe_params->u.ofdm.transmission_mode) { 859 switch (fe_params->transmission_mode) {
860 case TRANSMISSION_MODE_2K: 860 case TRANSMISSION_MODE_2K:
861 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); 861 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
862 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4); 862 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
@@ -895,8 +895,9 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
895 return 0; 895 return 0;
896} 896}
897 897
898static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params) 898static int tda1004x_get_fe(struct dvb_frontend *fe)
899{ 899{
900 struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
900 struct tda1004x_state* state = fe->demodulator_priv; 901 struct tda1004x_state* state = fe->demodulator_priv;
901 902
902 dprintk("%s\n", __func__); 903 dprintk("%s\n", __func__);
@@ -913,13 +914,13 @@ static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_paramete
913 case TDA1004X_DEMOD_TDA10045: 914 case TDA1004X_DEMOD_TDA10045:
914 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) { 915 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
915 case 0x14: 916 case 0x14:
916 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; 917 fe_params->bandwidth_hz = 8000000;
917 break; 918 break;
918 case 0xdb: 919 case 0xdb:
919 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; 920 fe_params->bandwidth_hz = 7000000;
920 break; 921 break;
921 case 0x4f: 922 case 0x4f:
922 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; 923 fe_params->bandwidth_hz = 6000000;
923 break; 924 break;
924 } 925 }
925 break; 926 break;
@@ -927,73 +928,73 @@ static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_paramete
927 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) { 928 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
928 case 0x5c: 929 case 0x5c:
929 case 0x54: 930 case 0x54:
930 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; 931 fe_params->bandwidth_hz = 8000000;
931 break; 932 break;
932 case 0x6a: 933 case 0x6a:
933 case 0x60: 934 case 0x60:
934 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; 935 fe_params->bandwidth_hz = 7000000;
935 break; 936 break;
936 case 0x7b: 937 case 0x7b:
937 case 0x70: 938 case 0x70:
938 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; 939 fe_params->bandwidth_hz = 6000000;
939 break; 940 break;
940 } 941 }
941 break; 942 break;
942 } 943 }
943 944
944 // FEC 945 // FEC
945 fe_params->u.ofdm.code_rate_HP = 946 fe_params->code_rate_HP =
946 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7); 947 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
947 fe_params->u.ofdm.code_rate_LP = 948 fe_params->code_rate_LP =
948 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7); 949 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
949 950
950 // constellation 951 /* modulation */
951 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) { 952 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
952 case 0: 953 case 0:
953 fe_params->u.ofdm.constellation = QPSK; 954 fe_params->modulation = QPSK;
954 break; 955 break;
955 case 1: 956 case 1:
956 fe_params->u.ofdm.constellation = QAM_16; 957 fe_params->modulation = QAM_16;
957 break; 958 break;
958 case 2: 959 case 2:
959 fe_params->u.ofdm.constellation = QAM_64; 960 fe_params->modulation = QAM_64;
960 break; 961 break;
961 } 962 }
962 963
963 // transmission mode 964 // transmission mode
964 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; 965 fe_params->transmission_mode = TRANSMISSION_MODE_2K;
965 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10) 966 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
966 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; 967 fe_params->transmission_mode = TRANSMISSION_MODE_8K;
967 968
968 // guard interval 969 // guard interval
969 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) { 970 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
970 case 0: 971 case 0:
971 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; 972 fe_params->guard_interval = GUARD_INTERVAL_1_32;
972 break; 973 break;
973 case 1: 974 case 1:
974 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; 975 fe_params->guard_interval = GUARD_INTERVAL_1_16;
975 break; 976 break;
976 case 2: 977 case 2:
977 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; 978 fe_params->guard_interval = GUARD_INTERVAL_1_8;
978 break; 979 break;
979 case 3: 980 case 3:
980 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; 981 fe_params->guard_interval = GUARD_INTERVAL_1_4;
981 break; 982 break;
982 } 983 }
983 984
984 // hierarchy 985 // hierarchy
985 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) { 986 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
986 case 0: 987 case 0:
987 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE; 988 fe_params->hierarchy = HIERARCHY_NONE;
988 break; 989 break;
989 case 1: 990 case 1:
990 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1; 991 fe_params->hierarchy = HIERARCHY_1;
991 break; 992 break;
992 case 2: 993 case 2:
993 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2; 994 fe_params->hierarchy = HIERARCHY_2;
994 break; 995 break;
995 case 3: 996 case 3:
996 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4; 997 fe_params->hierarchy = HIERARCHY_4;
997 break; 998 break;
998 } 999 }
999 1000
@@ -1231,9 +1232,9 @@ static void tda1004x_release(struct dvb_frontend* fe)
1231} 1232}
1232 1233
1233static struct dvb_frontend_ops tda10045_ops = { 1234static struct dvb_frontend_ops tda10045_ops = {
1235 .delsys = { SYS_DVBT },
1234 .info = { 1236 .info = {
1235 .name = "Philips TDA10045H DVB-T", 1237 .name = "Philips TDA10045H DVB-T",
1236 .type = FE_OFDM,
1237 .frequency_min = 51000000, 1238 .frequency_min = 51000000,
1238 .frequency_max = 858000000, 1239 .frequency_max = 858000000,
1239 .frequency_stepsize = 166667, 1240 .frequency_stepsize = 166667,
@@ -1301,9 +1302,9 @@ struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1301} 1302}
1302 1303
1303static struct dvb_frontend_ops tda10046_ops = { 1304static struct dvb_frontend_ops tda10046_ops = {
1305 .delsys = { SYS_DVBT },
1304 .info = { 1306 .info = {
1305 .name = "Philips TDA10046H DVB-T", 1307 .name = "Philips TDA10046H DVB-T",
1306 .type = FE_OFDM,
1307 .frequency_min = 51000000, 1308 .frequency_min = 51000000,
1308 .frequency_max = 858000000, 1309 .frequency_max = 858000000,
1309 .frequency_stepsize = 166667, 1310 .frequency_stepsize = 166667,
diff --git a/drivers/media/dvb/frontends/tda10071.c b/drivers/media/dvb/frontends/tda10071.c
index 0c37434d19e2..a99205026751 100644
--- a/drivers/media/dvb/frontends/tda10071.c
+++ b/drivers/media/dvb/frontends/tda10071.c
@@ -636,8 +636,7 @@ error:
636 return ret; 636 return ret;
637} 637}
638 638
639static int tda10071_set_frontend(struct dvb_frontend *fe, 639static int tda10071_set_frontend(struct dvb_frontend *fe)
640 struct dvb_frontend_parameters *params)
641{ 640{
642 struct tda10071_priv *priv = fe->demodulator_priv; 641 struct tda10071_priv *priv = fe->demodulator_priv;
643 struct tda10071_cmd cmd; 642 struct tda10071_cmd cmd;
@@ -777,8 +776,7 @@ error:
777 return ret; 776 return ret;
778} 777}
779 778
780static int tda10071_get_frontend(struct dvb_frontend *fe, 779static int tda10071_get_frontend(struct dvb_frontend *fe)
781 struct dvb_frontend_parameters *p)
782{ 780{
783 struct tda10071_priv *priv = fe->demodulator_priv; 781 struct tda10071_priv *priv = fe->demodulator_priv;
784 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 782 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
@@ -1217,9 +1215,9 @@ error:
1217EXPORT_SYMBOL(tda10071_attach); 1215EXPORT_SYMBOL(tda10071_attach);
1218 1216
1219static struct dvb_frontend_ops tda10071_ops = { 1217static struct dvb_frontend_ops tda10071_ops = {
1218 .delsys = { SYS_DVBT, SYS_DVBT2 },
1220 .info = { 1219 .info = {
1221 .name = "NXP TDA10071", 1220 .name = "NXP TDA10071",
1222 .type = FE_QPSK,
1223 .frequency_min = 950000, 1221 .frequency_min = 950000,
1224 .frequency_max = 2150000, 1222 .frequency_max = 2150000,
1225 .frequency_tolerance = 5000, 1223 .frequency_tolerance = 5000,
diff --git a/drivers/media/dvb/frontends/tda10086.c b/drivers/media/dvb/frontends/tda10086.c
index f2c8faac6f36..fcfe2e080cb0 100644
--- a/drivers/media/dvb/frontends/tda10086.c
+++ b/drivers/media/dvb/frontends/tda10086.c
@@ -267,7 +267,7 @@ static int tda10086_send_burst (struct dvb_frontend* fe, fe_sec_mini_cmd_t minic
267} 267}
268 268
269static int tda10086_set_inversion(struct tda10086_state *state, 269static int tda10086_set_inversion(struct tda10086_state *state,
270 struct dvb_frontend_parameters *fe_params) 270 struct dtv_frontend_properties *fe_params)
271{ 271{
272 u8 invval = 0x80; 272 u8 invval = 0x80;
273 273
@@ -292,7 +292,7 @@ static int tda10086_set_inversion(struct tda10086_state *state,
292} 292}
293 293
294static int tda10086_set_symbol_rate(struct tda10086_state *state, 294static int tda10086_set_symbol_rate(struct tda10086_state *state,
295 struct dvb_frontend_parameters *fe_params) 295 struct dtv_frontend_properties *fe_params)
296{ 296{
297 u8 dfn = 0; 297 u8 dfn = 0;
298 u8 afs = 0; 298 u8 afs = 0;
@@ -303,7 +303,7 @@ static int tda10086_set_symbol_rate(struct tda10086_state *state,
303 u32 tmp; 303 u32 tmp;
304 u32 bdr; 304 u32 bdr;
305 u32 bdri; 305 u32 bdri;
306 u32 symbol_rate = fe_params->u.qpsk.symbol_rate; 306 u32 symbol_rate = fe_params->symbol_rate;
307 307
308 dprintk ("%s %i\n", __func__, symbol_rate); 308 dprintk ("%s %i\n", __func__, symbol_rate);
309 309
@@ -367,13 +367,13 @@ static int tda10086_set_symbol_rate(struct tda10086_state *state,
367} 367}
368 368
369static int tda10086_set_fec(struct tda10086_state *state, 369static int tda10086_set_fec(struct tda10086_state *state,
370 struct dvb_frontend_parameters *fe_params) 370 struct dtv_frontend_properties *fe_params)
371{ 371{
372 u8 fecval; 372 u8 fecval;
373 373
374 dprintk ("%s %i\n", __func__, fe_params->u.qpsk.fec_inner); 374 dprintk("%s %i\n", __func__, fe_params->fec_inner);
375 375
376 switch(fe_params->u.qpsk.fec_inner) { 376 switch (fe_params->fec_inner) {
377 case FEC_1_2: 377 case FEC_1_2:
378 fecval = 0x00; 378 fecval = 0x00;
379 break; 379 break;
@@ -409,9 +409,9 @@ static int tda10086_set_fec(struct tda10086_state *state,
409 return 0; 409 return 0;
410} 410}
411 411
412static int tda10086_set_frontend(struct dvb_frontend* fe, 412static int tda10086_set_frontend(struct dvb_frontend *fe)
413 struct dvb_frontend_parameters *fe_params)
414{ 413{
414 struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
415 struct tda10086_state *state = fe->demodulator_priv; 415 struct tda10086_state *state = fe->demodulator_priv;
416 int ret; 416 int ret;
417 u32 freq = 0; 417 u32 freq = 0;
@@ -425,7 +425,7 @@ static int tda10086_set_frontend(struct dvb_frontend* fe,
425 425
426 /* set params */ 426 /* set params */
427 if (fe->ops.tuner_ops.set_params) { 427 if (fe->ops.tuner_ops.set_params) {
428 fe->ops.tuner_ops.set_params(fe, fe_params); 428 fe->ops.tuner_ops.set_params(fe);
429 if (fe->ops.i2c_gate_ctrl) 429 if (fe->ops.i2c_gate_ctrl)
430 fe->ops.i2c_gate_ctrl(fe, 0); 430 fe->ops.i2c_gate_ctrl(fe, 0);
431 431
@@ -452,13 +452,14 @@ static int tda10086_set_frontend(struct dvb_frontend* fe,
452 tda10086_write_mask(state, 0x10, 0x40, 0x40); 452 tda10086_write_mask(state, 0x10, 0x40, 0x40);
453 tda10086_write_mask(state, 0x00, 0x01, 0x00); 453 tda10086_write_mask(state, 0x00, 0x01, 0x00);
454 454
455 state->symbol_rate = fe_params->u.qpsk.symbol_rate; 455 state->symbol_rate = fe_params->symbol_rate;
456 state->frequency = fe_params->frequency; 456 state->frequency = fe_params->frequency;
457 return 0; 457 return 0;
458} 458}
459 459
460static int tda10086_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params) 460static int tda10086_get_frontend(struct dvb_frontend *fe)
461{ 461{
462 struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
462 struct tda10086_state* state = fe->demodulator_priv; 463 struct tda10086_state* state = fe->demodulator_priv;
463 u8 val; 464 u8 val;
464 int tmp; 465 int tmp;
@@ -467,7 +468,7 @@ static int tda10086_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_pa
467 dprintk ("%s\n", __func__); 468 dprintk ("%s\n", __func__);
468 469
469 /* check for invalid symbol rate */ 470 /* check for invalid symbol rate */
470 if (fe_params->u.qpsk.symbol_rate < 500000) 471 if (fe_params->symbol_rate < 500000)
471 return -EINVAL; 472 return -EINVAL;
472 473
473 /* calculate the updated frequency (note: we convert from Hz->kHz) */ 474 /* calculate the updated frequency (note: we convert from Hz->kHz) */
@@ -516,34 +517,34 @@ static int tda10086_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_pa
516 tmp |= 0xffffff00; 517 tmp |= 0xffffff00;
517 tmp = (tmp * 480 * (1<<1)) / 128; 518 tmp = (tmp * 480 * (1<<1)) / 128;
518 tmp = ((state->symbol_rate/1000) * tmp) / (1000000/1000); 519 tmp = ((state->symbol_rate/1000) * tmp) / (1000000/1000);
519 fe_params->u.qpsk.symbol_rate = state->symbol_rate + tmp; 520 fe_params->symbol_rate = state->symbol_rate + tmp;
520 521
521 /* the FEC */ 522 /* the FEC */
522 val = (tda10086_read_byte(state, 0x0d) & 0x70) >> 4; 523 val = (tda10086_read_byte(state, 0x0d) & 0x70) >> 4;
523 switch(val) { 524 switch(val) {
524 case 0x00: 525 case 0x00:
525 fe_params->u.qpsk.fec_inner = FEC_1_2; 526 fe_params->fec_inner = FEC_1_2;
526 break; 527 break;
527 case 0x01: 528 case 0x01:
528 fe_params->u.qpsk.fec_inner = FEC_2_3; 529 fe_params->fec_inner = FEC_2_3;
529 break; 530 break;
530 case 0x02: 531 case 0x02:
531 fe_params->u.qpsk.fec_inner = FEC_3_4; 532 fe_params->fec_inner = FEC_3_4;
532 break; 533 break;
533 case 0x03: 534 case 0x03:
534 fe_params->u.qpsk.fec_inner = FEC_4_5; 535 fe_params->fec_inner = FEC_4_5;
535 break; 536 break;
536 case 0x04: 537 case 0x04:
537 fe_params->u.qpsk.fec_inner = FEC_5_6; 538 fe_params->fec_inner = FEC_5_6;
538 break; 539 break;
539 case 0x05: 540 case 0x05:
540 fe_params->u.qpsk.fec_inner = FEC_6_7; 541 fe_params->fec_inner = FEC_6_7;
541 break; 542 break;
542 case 0x06: 543 case 0x06:
543 fe_params->u.qpsk.fec_inner = FEC_7_8; 544 fe_params->fec_inner = FEC_7_8;
544 break; 545 break;
545 case 0x07: 546 case 0x07:
546 fe_params->u.qpsk.fec_inner = FEC_8_9; 547 fe_params->fec_inner = FEC_8_9;
547 break; 548 break;
548 } 549 }
549 550
@@ -664,29 +665,31 @@ static int tda10086_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
664 665
665static int tda10086_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings) 666static int tda10086_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
666{ 667{
667 if (fesettings->parameters.u.qpsk.symbol_rate > 20000000) { 668 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
669
670 if (p->symbol_rate > 20000000) {
668 fesettings->min_delay_ms = 50; 671 fesettings->min_delay_ms = 50;
669 fesettings->step_size = 2000; 672 fesettings->step_size = 2000;
670 fesettings->max_drift = 8000; 673 fesettings->max_drift = 8000;
671 } else if (fesettings->parameters.u.qpsk.symbol_rate > 12000000) { 674 } else if (p->symbol_rate > 12000000) {
672 fesettings->min_delay_ms = 100; 675 fesettings->min_delay_ms = 100;
673 fesettings->step_size = 1500; 676 fesettings->step_size = 1500;
674 fesettings->max_drift = 9000; 677 fesettings->max_drift = 9000;
675 } else if (fesettings->parameters.u.qpsk.symbol_rate > 8000000) { 678 } else if (p->symbol_rate > 8000000) {
676 fesettings->min_delay_ms = 100; 679 fesettings->min_delay_ms = 100;
677 fesettings->step_size = 1000; 680 fesettings->step_size = 1000;
678 fesettings->max_drift = 8000; 681 fesettings->max_drift = 8000;
679 } else if (fesettings->parameters.u.qpsk.symbol_rate > 4000000) { 682 } else if (p->symbol_rate > 4000000) {
680 fesettings->min_delay_ms = 100; 683 fesettings->min_delay_ms = 100;
681 fesettings->step_size = 500; 684 fesettings->step_size = 500;
682 fesettings->max_drift = 7000; 685 fesettings->max_drift = 7000;
683 } else if (fesettings->parameters.u.qpsk.symbol_rate > 2000000) { 686 } else if (p->symbol_rate > 2000000) {
684 fesettings->min_delay_ms = 200; 687 fesettings->min_delay_ms = 200;
685 fesettings->step_size = (fesettings->parameters.u.qpsk.symbol_rate / 8000); 688 fesettings->step_size = p->symbol_rate / 8000;
686 fesettings->max_drift = 14 * fesettings->step_size; 689 fesettings->max_drift = 14 * fesettings->step_size;
687 } else { 690 } else {
688 fesettings->min_delay_ms = 200; 691 fesettings->min_delay_ms = 200;
689 fesettings->step_size = (fesettings->parameters.u.qpsk.symbol_rate / 8000); 692 fesettings->step_size = p->symbol_rate / 8000;
690 fesettings->max_drift = 18 * fesettings->step_size; 693 fesettings->max_drift = 18 * fesettings->step_size;
691 } 694 }
692 695
@@ -701,10 +704,9 @@ static void tda10086_release(struct dvb_frontend* fe)
701} 704}
702 705
703static struct dvb_frontend_ops tda10086_ops = { 706static struct dvb_frontend_ops tda10086_ops = {
704 707 .delsys = { SYS_DVBS },
705 .info = { 708 .info = {
706 .name = "Philips TDA10086 DVB-S", 709 .name = "Philips TDA10086 DVB-S",
707 .type = FE_QPSK,
708 .frequency_min = 950000, 710 .frequency_min = 950000,
709 .frequency_max = 2150000, 711 .frequency_max = 2150000,
710 .frequency_stepsize = 125, /* kHz for QPSK frontends */ 712 .frequency_stepsize = 125, /* kHz for QPSK frontends */
diff --git a/drivers/media/dvb/frontends/tda18271c2dd.c b/drivers/media/dvb/frontends/tda18271c2dd.c
index 1b1bf200c55c..86da3d816498 100644
--- a/drivers/media/dvb/frontends/tda18271c2dd.c
+++ b/drivers/media/dvb/frontends/tda18271c2dd.c
@@ -1123,55 +1123,51 @@ static int release(struct dvb_frontend *fe)
1123 return 0; 1123 return 0;
1124} 1124}
1125 1125
1126/*
1127 * As defined on EN 300 429 Annex A and on ITU-T J.83 annex A, the DVB-C
1128 * roll-off factor is 0.15.
1129 * According with the specs, the amount of the needed bandwith is given by:
1130 * Bw = Symbol_rate * (1 + 0.15)
1131 * As such, the maximum symbol rate supported by 6 MHz is
1132 * max_symbol_rate = 6 MHz / 1.15 = 5217391 Bauds
1133 *NOTE: For ITU-T J.83 Annex C, the roll-off factor is 0.13. So:
1134 * max_symbol_rate = 6 MHz / 1.13 = 5309735 Baud
1135 * That means that an adjustment is needed for Japan,
1136 * but, as currently DRX-K is hardcoded to Annex A, let's stick
1137 * with 0.15 roll-off factor.
1138 */
1139#define MAX_SYMBOL_RATE_6MHz 5217391
1140 1126
1141static int set_params(struct dvb_frontend *fe, 1127static int set_params(struct dvb_frontend *fe)
1142 struct dvb_frontend_parameters *params)
1143{ 1128{
1144 struct tda_state *state = fe->tuner_priv; 1129 struct tda_state *state = fe->tuner_priv;
1145 int status = 0; 1130 int status = 0;
1146 int Standard; 1131 int Standard;
1132 u32 bw = fe->dtv_property_cache.bandwidth_hz;
1133 u32 delsys = fe->dtv_property_cache.delivery_system;
1147 1134
1148 state->m_Frequency = params->frequency; 1135 state->m_Frequency = fe->dtv_property_cache.frequency;
1149 1136
1150 if (fe->ops.info.type == FE_OFDM) 1137 switch (delsys) {
1151 switch (params->u.ofdm.bandwidth) { 1138 case SYS_DVBT:
1152 case BANDWIDTH_6_MHZ: 1139 case SYS_DVBT2:
1140 switch (bw) {
1141 case 6000000:
1153 Standard = HF_DVBT_6MHZ; 1142 Standard = HF_DVBT_6MHZ;
1154 break; 1143 break;
1155 case BANDWIDTH_7_MHZ: 1144 case 7000000:
1156 Standard = HF_DVBT_7MHZ; 1145 Standard = HF_DVBT_7MHZ;
1157 break; 1146 break;
1158 default: 1147 case 8000000:
1159 case BANDWIDTH_8_MHZ:
1160 Standard = HF_DVBT_8MHZ; 1148 Standard = HF_DVBT_8MHZ;
1161 break; 1149 break;
1150 default:
1151 return -EINVAL;
1162 } 1152 }
1163 else if (fe->ops.info.type == FE_QAM) { 1153 case SYS_DVBC_ANNEX_A:
1164 if (params->u.qam.symbol_rate <= MAX_SYMBOL_RATE_6MHz) 1154 case SYS_DVBC_ANNEX_C:
1155 if (bw <= 6000000)
1165 Standard = HF_DVBC_6MHZ; 1156 Standard = HF_DVBC_6MHZ;
1157 else if (bw <= 7000000)
1158 Standard = HF_DVBC_7MHZ;
1166 else 1159 else
1167 Standard = HF_DVBC_8MHZ; 1160 Standard = HF_DVBC_8MHZ;
1168 } else 1161 break;
1162 default:
1169 return -EINVAL; 1163 return -EINVAL;
1164 }
1170 do { 1165 do {
1171 status = RFTrackingFiltersCorrection(state, params->frequency); 1166 status = RFTrackingFiltersCorrection(state, state->m_Frequency);
1172 if (status < 0) 1167 if (status < 0)
1173 break; 1168 break;
1174 status = ChannelConfiguration(state, params->frequency, Standard); 1169 status = ChannelConfiguration(state, state->m_Frequency,
1170 Standard);
1175 if (status < 0) 1171 if (status < 0)
1176 break; 1172 break;
1177 1173
diff --git a/drivers/media/dvb/frontends/tda8083.c b/drivers/media/dvb/frontends/tda8083.c
index 9369f7442f27..15912c96926a 100644
--- a/drivers/media/dvb/frontends/tda8083.c
+++ b/drivers/media/dvb/frontends/tda8083.c
@@ -315,18 +315,19 @@ static int tda8083_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
315 return 0; 315 return 0;
316} 316}
317 317
318static int tda8083_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 318static int tda8083_set_frontend(struct dvb_frontend *fe)
319{ 319{
320 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
320 struct tda8083_state* state = fe->demodulator_priv; 321 struct tda8083_state* state = fe->demodulator_priv;
321 322
322 if (fe->ops.tuner_ops.set_params) { 323 if (fe->ops.tuner_ops.set_params) {
323 fe->ops.tuner_ops.set_params(fe, p); 324 fe->ops.tuner_ops.set_params(fe);
324 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 325 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
325 } 326 }
326 327
327 tda8083_set_inversion (state, p->inversion); 328 tda8083_set_inversion (state, p->inversion);
328 tda8083_set_fec (state, p->u.qpsk.fec_inner); 329 tda8083_set_fec(state, p->fec_inner);
329 tda8083_set_symbolrate (state, p->u.qpsk.symbol_rate); 330 tda8083_set_symbolrate(state, p->symbol_rate);
330 331
331 tda8083_writereg (state, 0x00, 0x3c); 332 tda8083_writereg (state, 0x00, 0x3c);
332 tda8083_writereg (state, 0x00, 0x04); 333 tda8083_writereg (state, 0x00, 0x04);
@@ -334,16 +335,17 @@ static int tda8083_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
334 return 0; 335 return 0;
335} 336}
336 337
337static int tda8083_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 338static int tda8083_get_frontend(struct dvb_frontend *fe)
338{ 339{
340 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
339 struct tda8083_state* state = fe->demodulator_priv; 341 struct tda8083_state* state = fe->demodulator_priv;
340 342
341 /* FIXME: get symbolrate & frequency offset...*/ 343 /* FIXME: get symbolrate & frequency offset...*/
342 /*p->frequency = ???;*/ 344 /*p->frequency = ???;*/
343 p->inversion = (tda8083_readreg (state, 0x0e) & 0x80) ? 345 p->inversion = (tda8083_readreg (state, 0x0e) & 0x80) ?
344 INVERSION_ON : INVERSION_OFF; 346 INVERSION_ON : INVERSION_OFF;
345 p->u.qpsk.fec_inner = tda8083_get_fec (state); 347 p->fec_inner = tda8083_get_fec(state);
346 /*p->u.qpsk.symbol_rate = tda8083_get_symbolrate (state);*/ 348 /*p->symbol_rate = tda8083_get_symbolrate (state);*/
347 349
348 return 0; 350 return 0;
349} 351}
@@ -438,10 +440,9 @@ error:
438} 440}
439 441
440static struct dvb_frontend_ops tda8083_ops = { 442static struct dvb_frontend_ops tda8083_ops = {
441 443 .delsys = { SYS_DVBS },
442 .info = { 444 .info = {
443 .name = "Philips TDA8083 DVB-S", 445 .name = "Philips TDA8083 DVB-S",
444 .type = FE_QPSK,
445 .frequency_min = 920000, /* TDA8060 */ 446 .frequency_min = 920000, /* TDA8060 */
446 .frequency_max = 2200000, /* TDA8060 */ 447 .frequency_max = 2200000, /* TDA8060 */
447 .frequency_stepsize = 125, /* kHz for QPSK frontends */ 448 .frequency_stepsize = 125, /* kHz for QPSK frontends */
diff --git a/drivers/media/dvb/frontends/tda826x.c b/drivers/media/dvb/frontends/tda826x.c
index 06c94800b940..04bbcc24de0a 100644
--- a/drivers/media/dvb/frontends/tda826x.c
+++ b/drivers/media/dvb/frontends/tda826x.c
@@ -71,8 +71,9 @@ static int tda826x_sleep(struct dvb_frontend *fe)
71 return (ret == 1) ? 0 : ret; 71 return (ret == 1) ? 0 : ret;
72} 72}
73 73
74static int tda826x_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) 74static int tda826x_set_params(struct dvb_frontend *fe)
75{ 75{
76 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
76 struct tda826x_priv *priv = fe->tuner_priv; 77 struct tda826x_priv *priv = fe->tuner_priv;
77 int ret; 78 int ret;
78 u32 div; 79 u32 div;
@@ -83,11 +84,11 @@ static int tda826x_set_params(struct dvb_frontend *fe, struct dvb_frontend_param
83 84
84 dprintk("%s:\n", __func__); 85 dprintk("%s:\n", __func__);
85 86
86 div = (params->frequency + (1000-1)) / 1000; 87 div = (p->frequency + (1000-1)) / 1000;
87 88
88 /* BW = ((1 + RO) * SR/2 + 5) * 1.3 [SR in MSPS, BW in MHz] */ 89 /* BW = ((1 + RO) * SR/2 + 5) * 1.3 [SR in MSPS, BW in MHz] */
89 /* with R0 = 0.35 and some transformations: */ 90 /* with R0 = 0.35 and some transformations: */
90 ksyms = params->u.qpsk.symbol_rate / 1000; 91 ksyms = p->symbol_rate / 1000;
91 bandwidth = (878 * ksyms + 6500000) / 1000000 + 1; 92 bandwidth = (878 * ksyms + 6500000) / 1000000 + 1;
92 if (bandwidth < 5) 93 if (bandwidth < 5)
93 bandwidth = 5; 94 bandwidth = 5;
diff --git a/drivers/media/dvb/frontends/tdhd1.h b/drivers/media/dvb/frontends/tdhd1.h
index 51f170678650..17750985db0c 100644
--- a/drivers/media/dvb/frontends/tdhd1.h
+++ b/drivers/media/dvb/frontends/tdhd1.h
@@ -40,24 +40,25 @@ static struct tda1004x_config alps_tdhd1_204a_config = {
40 .request_firmware = alps_tdhd1_204_request_firmware 40 .request_firmware = alps_tdhd1_204_request_firmware
41}; 41};
42 42
43static int alps_tdhd1_204a_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) 43static int alps_tdhd1_204a_tuner_set_params(struct dvb_frontend *fe)
44{ 44{
45 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
45 struct i2c_adapter *i2c = fe->tuner_priv; 46 struct i2c_adapter *i2c = fe->tuner_priv;
46 u8 data[4]; 47 u8 data[4];
47 struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) }; 48 struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) };
48 u32 div; 49 u32 div;
49 50
50 div = (params->frequency + 36166666) / 166666; 51 div = (p->frequency + 36166666) / 166666;
51 52
52 data[0] = (div >> 8) & 0x7f; 53 data[0] = (div >> 8) & 0x7f;
53 data[1] = div & 0xff; 54 data[1] = div & 0xff;
54 data[2] = 0x85; 55 data[2] = 0x85;
55 56
56 if (params->frequency >= 174000000 && params->frequency <= 230000000) 57 if (p->frequency >= 174000000 && p->frequency <= 230000000)
57 data[3] = 0x02; 58 data[3] = 0x02;
58 else if (params->frequency >= 470000000 && params->frequency <= 823000000) 59 else if (p->frequency >= 470000000 && p->frequency <= 823000000)
59 data[3] = 0x0C; 60 data[3] = 0x0C;
60 else if (params->frequency > 823000000 && params->frequency <= 862000000) 61 else if (p->frequency > 823000000 && p->frequency <= 862000000)
61 data[3] = 0x8C; 62 data[3] = 0x8C;
62 else 63 else
63 return -EINVAL; 64 return -EINVAL;
diff --git a/drivers/media/dvb/frontends/tua6100.c b/drivers/media/dvb/frontends/tua6100.c
index bcb95c2ef296..029384d1fddd 100644
--- a/drivers/media/dvb/frontends/tua6100.c
+++ b/drivers/media/dvb/frontends/tua6100.c
@@ -67,9 +67,9 @@ static int tua6100_sleep(struct dvb_frontend *fe)
67 return (ret == 1) ? 0 : ret; 67 return (ret == 1) ? 0 : ret;
68} 68}
69 69
70static int tua6100_set_params(struct dvb_frontend *fe, 70static int tua6100_set_params(struct dvb_frontend *fe)
71 struct dvb_frontend_parameters *params)
72{ 71{
72 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
73 struct tua6100_priv *priv = fe->tuner_priv; 73 struct tua6100_priv *priv = fe->tuner_priv;
74 u32 div; 74 u32 div;
75 u32 prediv; 75 u32 prediv;
@@ -85,36 +85,37 @@ static int tua6100_set_params(struct dvb_frontend *fe,
85#define _ri 4000000 85#define _ri 4000000
86 86
87 // setup register 0 87 // setup register 0
88 if (params->frequency < 2000000) { 88 if (c->frequency < 2000000)
89 reg0[1] = 0x03; 89 reg0[1] = 0x03;
90 } else { 90 else
91 reg0[1] = 0x07; 91 reg0[1] = 0x07;
92 }
93 92
94 // setup register 1 93 // setup register 1
95 if (params->frequency < 1630000) { 94 if (c->frequency < 1630000)
96 reg1[1] = 0x2c; 95 reg1[1] = 0x2c;
97 } else { 96 else
98 reg1[1] = 0x0c; 97 reg1[1] = 0x0c;
99 } 98
100 if (_P == 64) 99 if (_P == 64)
101 reg1[1] |= 0x40; 100 reg1[1] |= 0x40;
102 if (params->frequency >= 1525000) 101 if (c->frequency >= 1525000)
103 reg1[1] |= 0x80; 102 reg1[1] |= 0x80;
104 103
105 // register 2 104 // register 2
106 reg2[1] = (_R >> 8) & 0x03; 105 reg2[1] = (_R >> 8) & 0x03;
107 reg2[2] = _R; 106 reg2[2] = _R;
108 if (params->frequency < 1455000) { 107 if (c->frequency < 1455000)
109 reg2[1] |= 0x1c; 108 reg2[1] |= 0x1c;
110 } else if (params->frequency < 1630000) { 109 else if (c->frequency < 1630000)
111 reg2[1] |= 0x0c; 110 reg2[1] |= 0x0c;
112 } else { 111 else
113 reg2[1] |= 0x1c; 112 reg2[1] |= 0x1c;
114 }
115 113
116 // The N divisor ratio (note: params->frequency is in kHz, but we need it in Hz) 114 /*
117 prediv = (params->frequency * _R) / (_ri / 1000); 115 * The N divisor ratio (note: c->frequency is in kHz, but we
116 * need it in Hz)
117 */
118 prediv = (c->frequency * _R) / (_ri / 1000);
118 div = prediv / _P; 119 div = prediv / _P;
119 reg1[1] |= (div >> 9) & 0x03; 120 reg1[1] |= (div >> 9) & 0x03;
120 reg1[2] = div >> 1; 121 reg1[2] = div >> 1;
diff --git a/drivers/media/dvb/frontends/ves1820.c b/drivers/media/dvb/frontends/ves1820.c
index 550a07a8a997..bb42b563c42d 100644
--- a/drivers/media/dvb/frontends/ves1820.c
+++ b/drivers/media/dvb/frontends/ves1820.c
@@ -205,25 +205,26 @@ static int ves1820_init(struct dvb_frontend* fe)
205 return 0; 205 return 0;
206} 206}
207 207
208static int ves1820_set_parameters(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 208static int ves1820_set_parameters(struct dvb_frontend *fe)
209{ 209{
210 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
210 struct ves1820_state* state = fe->demodulator_priv; 211 struct ves1820_state* state = fe->demodulator_priv;
211 static const u8 reg0x00[] = { 0x00, 0x04, 0x08, 0x0c, 0x10 }; 212 static const u8 reg0x00[] = { 0x00, 0x04, 0x08, 0x0c, 0x10 };
212 static const u8 reg0x01[] = { 140, 140, 106, 100, 92 }; 213 static const u8 reg0x01[] = { 140, 140, 106, 100, 92 };
213 static const u8 reg0x05[] = { 135, 100, 70, 54, 38 }; 214 static const u8 reg0x05[] = { 135, 100, 70, 54, 38 };
214 static const u8 reg0x08[] = { 162, 116, 67, 52, 35 }; 215 static const u8 reg0x08[] = { 162, 116, 67, 52, 35 };
215 static const u8 reg0x09[] = { 145, 150, 106, 126, 107 }; 216 static const u8 reg0x09[] = { 145, 150, 106, 126, 107 };
216 int real_qam = p->u.qam.modulation - QAM_16; 217 int real_qam = p->modulation - QAM_16;
217 218
218 if (real_qam < 0 || real_qam > 4) 219 if (real_qam < 0 || real_qam > 4)
219 return -EINVAL; 220 return -EINVAL;
220 221
221 if (fe->ops.tuner_ops.set_params) { 222 if (fe->ops.tuner_ops.set_params) {
222 fe->ops.tuner_ops.set_params(fe, p); 223 fe->ops.tuner_ops.set_params(fe);
223 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 224 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
224 } 225 }
225 226
226 ves1820_set_symbolrate(state, p->u.qam.symbol_rate); 227 ves1820_set_symbolrate(state, p->symbol_rate);
227 ves1820_writereg(state, 0x34, state->pwm); 228 ves1820_writereg(state, 0x34, state->pwm);
228 229
229 ves1820_writereg(state, 0x01, reg0x01[real_qam]); 230 ves1820_writereg(state, 0x01, reg0x01[real_qam]);
@@ -309,8 +310,9 @@ static int ves1820_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
309 return 0; 310 return 0;
310} 311}
311 312
312static int ves1820_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 313static int ves1820_get_frontend(struct dvb_frontend *fe)
313{ 314{
315 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
314 struct ves1820_state* state = fe->demodulator_priv; 316 struct ves1820_state* state = fe->demodulator_priv;
315 int sync; 317 int sync;
316 s8 afc = 0; 318 s8 afc = 0;
@@ -320,7 +322,7 @@ static int ves1820_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
320 if (verbose) { 322 if (verbose) {
321 /* AFC only valid when carrier has been recovered */ 323 /* AFC only valid when carrier has been recovered */
322 printk(sync & 2 ? "ves1820: AFC (%d) %dHz\n" : 324 printk(sync & 2 ? "ves1820: AFC (%d) %dHz\n" :
323 "ves1820: [AFC (%d) %dHz]\n", afc, -((s32) p->u.qam.symbol_rate * afc) >> 10); 325 "ves1820: [AFC (%d) %dHz]\n", afc, -((s32) p->symbol_rate * afc) >> 10);
324 } 326 }
325 327
326 if (!state->config->invert) { 328 if (!state->config->invert) {
@@ -329,13 +331,13 @@ static int ves1820_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
329 p->inversion = (!(state->reg0 & 0x20)) ? INVERSION_ON : INVERSION_OFF; 331 p->inversion = (!(state->reg0 & 0x20)) ? INVERSION_ON : INVERSION_OFF;
330 } 332 }
331 333
332 p->u.qam.modulation = ((state->reg0 >> 2) & 7) + QAM_16; 334 p->modulation = ((state->reg0 >> 2) & 7) + QAM_16;
333 335
334 p->u.qam.fec_inner = FEC_NONE; 336 p->fec_inner = FEC_NONE;
335 337
336 p->frequency = ((p->frequency + 31250) / 62500) * 62500; 338 p->frequency = ((p->frequency + 31250) / 62500) * 62500;
337 if (sync & 2) 339 if (sync & 2)
338 p->frequency -= ((s32) p->u.qam.symbol_rate * afc) >> 10; 340 p->frequency -= ((s32) p->symbol_rate * afc) >> 10;
339 341
340 return 0; 342 return 0;
341} 343}
@@ -405,10 +407,9 @@ error:
405} 407}
406 408
407static struct dvb_frontend_ops ves1820_ops = { 409static struct dvb_frontend_ops ves1820_ops = {
408 410 .delsys = { SYS_DVBC_ANNEX_A },
409 .info = { 411 .info = {
410 .name = "VLSI VES1820 DVB-C", 412 .name = "VLSI VES1820 DVB-C",
411 .type = FE_QAM,
412 .frequency_stepsize = 62500, 413 .frequency_stepsize = 62500,
413 .frequency_min = 47000000, 414 .frequency_min = 47000000,
414 .frequency_max = 862000000, 415 .frequency_max = 862000000,
diff --git a/drivers/media/dvb/frontends/ves1x93.c b/drivers/media/dvb/frontends/ves1x93.c
index 8d7854c2fb0c..9c17eacaec24 100644
--- a/drivers/media/dvb/frontends/ves1x93.c
+++ b/drivers/media/dvb/frontends/ves1x93.c
@@ -46,6 +46,7 @@ struct ves1x93_state {
46 u8 *init_1x93_wtab; 46 u8 *init_1x93_wtab;
47 u8 tab_size; 47 u8 tab_size;
48 u8 demod_type; 48 u8 demod_type;
49 u32 frequency;
49}; 50};
50 51
51static int debug; 52static int debug;
@@ -384,31 +385,34 @@ static int ves1x93_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
384 return 0; 385 return 0;
385} 386}
386 387
387static int ves1x93_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 388static int ves1x93_set_frontend(struct dvb_frontend *fe)
388{ 389{
390 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
389 struct ves1x93_state* state = fe->demodulator_priv; 391 struct ves1x93_state* state = fe->demodulator_priv;
390 392
391 if (fe->ops.tuner_ops.set_params) { 393 if (fe->ops.tuner_ops.set_params) {
392 fe->ops.tuner_ops.set_params(fe, p); 394 fe->ops.tuner_ops.set_params(fe);
393 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 395 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
394 } 396 }
395 ves1x93_set_inversion (state, p->inversion); 397 ves1x93_set_inversion (state, p->inversion);
396 ves1x93_set_fec (state, p->u.qpsk.fec_inner); 398 ves1x93_set_fec(state, p->fec_inner);
397 ves1x93_set_symbolrate (state, p->u.qpsk.symbol_rate); 399 ves1x93_set_symbolrate(state, p->symbol_rate);
398 state->inversion = p->inversion; 400 state->inversion = p->inversion;
401 state->frequency = p->frequency;
399 402
400 return 0; 403 return 0;
401} 404}
402 405
403static int ves1x93_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 406static int ves1x93_get_frontend(struct dvb_frontend *fe)
404{ 407{
408 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
405 struct ves1x93_state* state = fe->demodulator_priv; 409 struct ves1x93_state* state = fe->demodulator_priv;
406 int afc; 410 int afc;
407 411
408 afc = ((int)((char)(ves1x93_readreg (state, 0x0a) << 1)))/2; 412 afc = ((int)((char)(ves1x93_readreg (state, 0x0a) << 1)))/2;
409 afc = (afc * (int)(p->u.qpsk.symbol_rate/1000/8))/16; 413 afc = (afc * (int)(p->symbol_rate/1000/8))/16;
410 414
411 p->frequency -= afc; 415 p->frequency = state->frequency - afc;
412 416
413 /* 417 /*
414 * inversion indicator is only valid 418 * inversion indicator is only valid
@@ -417,7 +421,7 @@ static int ves1x93_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
417 if (state->inversion == INVERSION_AUTO) 421 if (state->inversion == INVERSION_AUTO)
418 p->inversion = (ves1x93_readreg (state, 0x0f) & 2) ? 422 p->inversion = (ves1x93_readreg (state, 0x0f) & 2) ?
419 INVERSION_OFF : INVERSION_ON; 423 INVERSION_OFF : INVERSION_ON;
420 p->u.qpsk.fec_inner = ves1x93_get_fec (state); 424 p->fec_inner = ves1x93_get_fec(state);
421 /* XXX FIXME: timing offset !! */ 425 /* XXX FIXME: timing offset !! */
422 426
423 return 0; 427 return 0;
@@ -506,10 +510,9 @@ error:
506} 510}
507 511
508static struct dvb_frontend_ops ves1x93_ops = { 512static struct dvb_frontend_ops ves1x93_ops = {
509 513 .delsys = { SYS_DVBS },
510 .info = { 514 .info = {
511 .name = "VLSI VES1x93 DVB-S", 515 .name = "VLSI VES1x93 DVB-S",
512 .type = FE_QPSK,
513 .frequency_min = 950000, 516 .frequency_min = 950000,
514 .frequency_max = 2150000, 517 .frequency_max = 2150000,
515 .frequency_stepsize = 125, /* kHz for QPSK frontends */ 518 .frequency_stepsize = 125, /* kHz for QPSK frontends */
diff --git a/drivers/media/dvb/frontends/zl10036.c b/drivers/media/dvb/frontends/zl10036.c
index 81aa984c551f..0903d461b8fa 100644
--- a/drivers/media/dvb/frontends/zl10036.c
+++ b/drivers/media/dvb/frontends/zl10036.c
@@ -305,12 +305,12 @@ static int zl10036_set_gain_params(struct zl10036_state *state,
305 return zl10036_write(state, buf, sizeof(buf)); 305 return zl10036_write(state, buf, sizeof(buf));
306} 306}
307 307
308static int zl10036_set_params(struct dvb_frontend *fe, 308static int zl10036_set_params(struct dvb_frontend *fe)
309 struct dvb_frontend_parameters *params)
310{ 309{
310 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
311 struct zl10036_state *state = fe->tuner_priv; 311 struct zl10036_state *state = fe->tuner_priv;
312 int ret = 0; 312 int ret = 0;
313 u32 frequency = params->frequency; 313 u32 frequency = p->frequency;
314 u32 fbw; 314 u32 fbw;
315 int i; 315 int i;
316 u8 c; 316 u8 c;
@@ -326,7 +326,7 @@ static int zl10036_set_params(struct dvb_frontend *fe,
326 * fBW = (alpha*symbolrate)/(2*0.8) 326 * fBW = (alpha*symbolrate)/(2*0.8)
327 * 1.35 / (2*0.8) = 27 / 32 327 * 1.35 / (2*0.8) = 27 / 32
328 */ 328 */
329 fbw = (27 * params->u.qpsk.symbol_rate) / 32; 329 fbw = (27 * p->symbol_rate) / 32;
330 330
331 /* scale to kHz */ 331 /* scale to kHz */
332 fbw /= 1000; 332 fbw /= 1000;
@@ -353,7 +353,7 @@ static int zl10036_set_params(struct dvb_frontend *fe,
353 if (ret < 0) 353 if (ret < 0)
354 goto error; 354 goto error;
355 355
356 ret = zl10036_set_frequency(state, params->frequency); 356 ret = zl10036_set_frequency(state, p->frequency);
357 if (ret < 0) 357 if (ret < 0)
358 goto error; 358 goto error;
359 359
diff --git a/drivers/media/dvb/frontends/zl10039.c b/drivers/media/dvb/frontends/zl10039.c
index c085e58a94bf..eff9c5fde50a 100644
--- a/drivers/media/dvb/frontends/zl10039.c
+++ b/drivers/media/dvb/frontends/zl10039.c
@@ -176,9 +176,9 @@ static int zl10039_sleep(struct dvb_frontend *fe)
176 return 0; 176 return 0;
177} 177}
178 178
179static int zl10039_set_params(struct dvb_frontend *fe, 179static int zl10039_set_params(struct dvb_frontend *fe)
180 struct dvb_frontend_parameters *params)
181{ 180{
181 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
182 struct zl10039_state *state = fe->tuner_priv; 182 struct zl10039_state *state = fe->tuner_priv;
183 u8 buf[6]; 183 u8 buf[6];
184 u8 bf; 184 u8 bf;
@@ -188,12 +188,12 @@ static int zl10039_set_params(struct dvb_frontend *fe,
188 188
189 dprintk("%s\n", __func__); 189 dprintk("%s\n", __func__);
190 dprintk("Set frequency = %d, symbol rate = %d\n", 190 dprintk("Set frequency = %d, symbol rate = %d\n",
191 params->frequency, params->u.qpsk.symbol_rate); 191 c->frequency, c->symbol_rate);
192 192
193 /* Assumed 10.111 MHz crystal oscillator */ 193 /* Assumed 10.111 MHz crystal oscillator */
194 /* Cancelled num/den 80 to prevent overflow */ 194 /* Cancelled num/den 80 to prevent overflow */
195 div = (params->frequency * 1000) / 126387; 195 div = (c->frequency * 1000) / 126387;
196 fbw = (params->u.qpsk.symbol_rate * 27) / 32000; 196 fbw = (c->symbol_rate * 27) / 32000;
197 /* Cancelled num/den 10 to prevent overflow */ 197 /* Cancelled num/den 10 to prevent overflow */
198 bf = ((fbw * 5088) / 1011100) - 1; 198 bf = ((fbw * 5088) / 1011100) - 1;
199 199
diff --git a/drivers/media/dvb/frontends/zl10353.c b/drivers/media/dvb/frontends/zl10353.c
index adbbf6d3d044..ac7237891374 100644
--- a/drivers/media/dvb/frontends/zl10353.c
+++ b/drivers/media/dvb/frontends/zl10353.c
@@ -37,9 +37,9 @@ struct zl10353_state {
37 37
38 struct zl10353_config config; 38 struct zl10353_config config;
39 39
40 enum fe_bandwidth bandwidth; 40 u32 bandwidth;
41 u32 ucblocks; 41 u32 ucblocks;
42 u32 frequency; 42 u32 frequency;
43}; 43};
44 44
45static int debug; 45static int debug;
@@ -122,30 +122,17 @@ static void zl10353_dump_regs(struct dvb_frontend *fe)
122} 122}
123 123
124static void zl10353_calc_nominal_rate(struct dvb_frontend *fe, 124static void zl10353_calc_nominal_rate(struct dvb_frontend *fe,
125 enum fe_bandwidth bandwidth, 125 u32 bandwidth,
126 u16 *nominal_rate) 126 u16 *nominal_rate)
127{ 127{
128 struct zl10353_state *state = fe->demodulator_priv; 128 struct zl10353_state *state = fe->demodulator_priv;
129 u32 adc_clock = 450560; /* 45.056 MHz */ 129 u32 adc_clock = 450560; /* 45.056 MHz */
130 u64 value; 130 u64 value;
131 u8 bw; 131 u8 bw = bandwidth / 1000000;
132 132
133 if (state->config.adc_clock) 133 if (state->config.adc_clock)
134 adc_clock = state->config.adc_clock; 134 adc_clock = state->config.adc_clock;
135 135
136 switch (bandwidth) {
137 case BANDWIDTH_6_MHZ:
138 bw = 6;
139 break;
140 case BANDWIDTH_7_MHZ:
141 bw = 7;
142 break;
143 case BANDWIDTH_8_MHZ:
144 default:
145 bw = 8;
146 break;
147 }
148
149 value = (u64)10 * (1 << 23) / 7 * 125; 136 value = (u64)10 * (1 << 23) / 7 * 125;
150 value = (bw * value) + adc_clock / 2; 137 value = (bw * value) + adc_clock / 2;
151 do_div(value, adc_clock); 138 do_div(value, adc_clock);
@@ -192,16 +179,15 @@ static int zl10353_sleep(struct dvb_frontend *fe)
192 return 0; 179 return 0;
193} 180}
194 181
195static int zl10353_set_parameters(struct dvb_frontend *fe, 182static int zl10353_set_parameters(struct dvb_frontend *fe)
196 struct dvb_frontend_parameters *param)
197{ 183{
184 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
198 struct zl10353_state *state = fe->demodulator_priv; 185 struct zl10353_state *state = fe->demodulator_priv;
199 u16 nominal_rate, input_freq; 186 u16 nominal_rate, input_freq;
200 u8 pllbuf[6] = { 0x67 }, acq_ctl = 0; 187 u8 pllbuf[6] = { 0x67 }, acq_ctl = 0;
201 u16 tps = 0; 188 u16 tps = 0;
202 struct dvb_ofdm_parameters *op = &param->u.ofdm;
203 189
204 state->frequency = param->frequency; 190 state->frequency = c->frequency;
205 191
206 zl10353_single_write(fe, RESET, 0x80); 192 zl10353_single_write(fe, RESET, 0x80);
207 udelay(200); 193 udelay(200);
@@ -211,42 +197,44 @@ static int zl10353_set_parameters(struct dvb_frontend *fe,
211 197
212 zl10353_single_write(fe, AGC_TARGET, 0x28); 198 zl10353_single_write(fe, AGC_TARGET, 0x28);
213 199
214 if (op->transmission_mode != TRANSMISSION_MODE_AUTO) 200 if (c->transmission_mode != TRANSMISSION_MODE_AUTO)
215 acq_ctl |= (1 << 0); 201 acq_ctl |= (1 << 0);
216 if (op->guard_interval != GUARD_INTERVAL_AUTO) 202 if (c->guard_interval != GUARD_INTERVAL_AUTO)
217 acq_ctl |= (1 << 1); 203 acq_ctl |= (1 << 1);
218 zl10353_single_write(fe, ACQ_CTL, acq_ctl); 204 zl10353_single_write(fe, ACQ_CTL, acq_ctl);
219 205
220 switch (op->bandwidth) { 206 switch (c->bandwidth_hz) {
221 case BANDWIDTH_6_MHZ: 207 case 6000000:
222 /* These are extrapolated from the 7 and 8MHz values */ 208 /* These are extrapolated from the 7 and 8MHz values */
223 zl10353_single_write(fe, MCLK_RATIO, 0x97); 209 zl10353_single_write(fe, MCLK_RATIO, 0x97);
224 zl10353_single_write(fe, 0x64, 0x34); 210 zl10353_single_write(fe, 0x64, 0x34);
225 zl10353_single_write(fe, 0xcc, 0xdd); 211 zl10353_single_write(fe, 0xcc, 0xdd);
226 break; 212 break;
227 case BANDWIDTH_7_MHZ: 213 case 7000000:
228 zl10353_single_write(fe, MCLK_RATIO, 0x86); 214 zl10353_single_write(fe, MCLK_RATIO, 0x86);
229 zl10353_single_write(fe, 0x64, 0x35); 215 zl10353_single_write(fe, 0x64, 0x35);
230 zl10353_single_write(fe, 0xcc, 0x73); 216 zl10353_single_write(fe, 0xcc, 0x73);
231 break; 217 break;
232 case BANDWIDTH_8_MHZ:
233 default: 218 default:
219 c->bandwidth_hz = 8000000;
220 /* fall though */
221 case 8000000:
234 zl10353_single_write(fe, MCLK_RATIO, 0x75); 222 zl10353_single_write(fe, MCLK_RATIO, 0x75);
235 zl10353_single_write(fe, 0x64, 0x36); 223 zl10353_single_write(fe, 0x64, 0x36);
236 zl10353_single_write(fe, 0xcc, 0x73); 224 zl10353_single_write(fe, 0xcc, 0x73);
237 } 225 }
238 226
239 zl10353_calc_nominal_rate(fe, op->bandwidth, &nominal_rate); 227 zl10353_calc_nominal_rate(fe, c->bandwidth_hz, &nominal_rate);
240 zl10353_single_write(fe, TRL_NOMINAL_RATE_1, msb(nominal_rate)); 228 zl10353_single_write(fe, TRL_NOMINAL_RATE_1, msb(nominal_rate));
241 zl10353_single_write(fe, TRL_NOMINAL_RATE_0, lsb(nominal_rate)); 229 zl10353_single_write(fe, TRL_NOMINAL_RATE_0, lsb(nominal_rate));
242 state->bandwidth = op->bandwidth; 230 state->bandwidth = c->bandwidth_hz;
243 231
244 zl10353_calc_input_freq(fe, &input_freq); 232 zl10353_calc_input_freq(fe, &input_freq);
245 zl10353_single_write(fe, INPUT_FREQ_1, msb(input_freq)); 233 zl10353_single_write(fe, INPUT_FREQ_1, msb(input_freq));
246 zl10353_single_write(fe, INPUT_FREQ_0, lsb(input_freq)); 234 zl10353_single_write(fe, INPUT_FREQ_0, lsb(input_freq));
247 235
248 /* Hint at TPS settings */ 236 /* Hint at TPS settings */
249 switch (op->code_rate_HP) { 237 switch (c->code_rate_HP) {
250 case FEC_2_3: 238 case FEC_2_3:
251 tps |= (1 << 7); 239 tps |= (1 << 7);
252 break; 240 break;
@@ -266,7 +254,7 @@ static int zl10353_set_parameters(struct dvb_frontend *fe,
266 return -EINVAL; 254 return -EINVAL;
267 } 255 }
268 256
269 switch (op->code_rate_LP) { 257 switch (c->code_rate_LP) {
270 case FEC_2_3: 258 case FEC_2_3:
271 tps |= (1 << 4); 259 tps |= (1 << 4);
272 break; 260 break;
@@ -283,14 +271,14 @@ static int zl10353_set_parameters(struct dvb_frontend *fe,
283 case FEC_AUTO: 271 case FEC_AUTO:
284 break; 272 break;
285 case FEC_NONE: 273 case FEC_NONE:
286 if (op->hierarchy_information == HIERARCHY_AUTO || 274 if (c->hierarchy == HIERARCHY_AUTO ||
287 op->hierarchy_information == HIERARCHY_NONE) 275 c->hierarchy == HIERARCHY_NONE)
288 break; 276 break;
289 default: 277 default:
290 return -EINVAL; 278 return -EINVAL;
291 } 279 }
292 280
293 switch (op->constellation) { 281 switch (c->modulation) {
294 case QPSK: 282 case QPSK:
295 break; 283 break;
296 case QAM_AUTO: 284 case QAM_AUTO:
@@ -304,7 +292,7 @@ static int zl10353_set_parameters(struct dvb_frontend *fe,
304 return -EINVAL; 292 return -EINVAL;
305 } 293 }
306 294
307 switch (op->transmission_mode) { 295 switch (c->transmission_mode) {
308 case TRANSMISSION_MODE_2K: 296 case TRANSMISSION_MODE_2K:
309 case TRANSMISSION_MODE_AUTO: 297 case TRANSMISSION_MODE_AUTO:
310 break; 298 break;
@@ -315,7 +303,7 @@ static int zl10353_set_parameters(struct dvb_frontend *fe,
315 return -EINVAL; 303 return -EINVAL;
316 } 304 }
317 305
318 switch (op->guard_interval) { 306 switch (c->guard_interval) {
319 case GUARD_INTERVAL_1_32: 307 case GUARD_INTERVAL_1_32:
320 case GUARD_INTERVAL_AUTO: 308 case GUARD_INTERVAL_AUTO:
321 break; 309 break;
@@ -332,7 +320,7 @@ static int zl10353_set_parameters(struct dvb_frontend *fe,
332 return -EINVAL; 320 return -EINVAL;
333 } 321 }
334 322
335 switch (op->hierarchy_information) { 323 switch (c->hierarchy) {
336 case HIERARCHY_AUTO: 324 case HIERARCHY_AUTO:
337 case HIERARCHY_NONE: 325 case HIERARCHY_NONE:
338 break; 326 break;
@@ -362,12 +350,12 @@ static int zl10353_set_parameters(struct dvb_frontend *fe,
362 */ 350 */
363 if (state->config.no_tuner) { 351 if (state->config.no_tuner) {
364 if (fe->ops.tuner_ops.set_params) { 352 if (fe->ops.tuner_ops.set_params) {
365 fe->ops.tuner_ops.set_params(fe, param); 353 fe->ops.tuner_ops.set_params(fe);
366 if (fe->ops.i2c_gate_ctrl) 354 if (fe->ops.i2c_gate_ctrl)
367 fe->ops.i2c_gate_ctrl(fe, 0); 355 fe->ops.i2c_gate_ctrl(fe, 0);
368 } 356 }
369 } else if (fe->ops.tuner_ops.calc_regs) { 357 } else if (fe->ops.tuner_ops.calc_regs) {
370 fe->ops.tuner_ops.calc_regs(fe, param, pllbuf + 1, 5); 358 fe->ops.tuner_ops.calc_regs(fe, pllbuf + 1, 5);
371 pllbuf[1] <<= 1; 359 pllbuf[1] <<= 1;
372 zl10353_write(fe, pllbuf, sizeof(pllbuf)); 360 zl10353_write(fe, pllbuf, sizeof(pllbuf));
373 } 361 }
@@ -383,11 +371,10 @@ static int zl10353_set_parameters(struct dvb_frontend *fe,
383 return 0; 371 return 0;
384} 372}
385 373
386static int zl10353_get_parameters(struct dvb_frontend *fe, 374static int zl10353_get_parameters(struct dvb_frontend *fe)
387 struct dvb_frontend_parameters *param)
388{ 375{
376 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
389 struct zl10353_state *state = fe->demodulator_priv; 377 struct zl10353_state *state = fe->demodulator_priv;
390 struct dvb_ofdm_parameters *op = &param->u.ofdm;
391 int s6, s9; 378 int s6, s9;
392 u16 tps; 379 u16 tps;
393 static const u8 tps_fec_to_api[8] = { 380 static const u8 tps_fec_to_api[8] = {
@@ -411,66 +398,66 @@ static int zl10353_get_parameters(struct dvb_frontend *fe,
411 tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 | 398 tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 |
412 zl10353_read_register(state, TPS_RECEIVED_0); 399 zl10353_read_register(state, TPS_RECEIVED_0);
413 400
414 op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7]; 401 c->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
415 op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7]; 402 c->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
416 403
417 switch ((tps >> 13) & 3) { 404 switch ((tps >> 13) & 3) {
418 case 0: 405 case 0:
419 op->constellation = QPSK; 406 c->modulation = QPSK;
420 break; 407 break;
421 case 1: 408 case 1:
422 op->constellation = QAM_16; 409 c->modulation = QAM_16;
423 break; 410 break;
424 case 2: 411 case 2:
425 op->constellation = QAM_64; 412 c->modulation = QAM_64;
426 break; 413 break;
427 default: 414 default:
428 op->constellation = QAM_AUTO; 415 c->modulation = QAM_AUTO;
429 break; 416 break;
430 } 417 }
431 418
432 op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : 419 c->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K :
433 TRANSMISSION_MODE_2K; 420 TRANSMISSION_MODE_2K;
434 421
435 switch ((tps >> 2) & 3) { 422 switch ((tps >> 2) & 3) {
436 case 0: 423 case 0:
437 op->guard_interval = GUARD_INTERVAL_1_32; 424 c->guard_interval = GUARD_INTERVAL_1_32;
438 break; 425 break;
439 case 1: 426 case 1:
440 op->guard_interval = GUARD_INTERVAL_1_16; 427 c->guard_interval = GUARD_INTERVAL_1_16;
441 break; 428 break;
442 case 2: 429 case 2:
443 op->guard_interval = GUARD_INTERVAL_1_8; 430 c->guard_interval = GUARD_INTERVAL_1_8;
444 break; 431 break;
445 case 3: 432 case 3:
446 op->guard_interval = GUARD_INTERVAL_1_4; 433 c->guard_interval = GUARD_INTERVAL_1_4;
447 break; 434 break;
448 default: 435 default:
449 op->guard_interval = GUARD_INTERVAL_AUTO; 436 c->guard_interval = GUARD_INTERVAL_AUTO;
450 break; 437 break;
451 } 438 }
452 439
453 switch ((tps >> 10) & 7) { 440 switch ((tps >> 10) & 7) {
454 case 0: 441 case 0:
455 op->hierarchy_information = HIERARCHY_NONE; 442 c->hierarchy = HIERARCHY_NONE;
456 break; 443 break;
457 case 1: 444 case 1:
458 op->hierarchy_information = HIERARCHY_1; 445 c->hierarchy = HIERARCHY_1;
459 break; 446 break;
460 case 2: 447 case 2:
461 op->hierarchy_information = HIERARCHY_2; 448 c->hierarchy = HIERARCHY_2;
462 break; 449 break;
463 case 3: 450 case 3:
464 op->hierarchy_information = HIERARCHY_4; 451 c->hierarchy = HIERARCHY_4;
465 break; 452 break;
466 default: 453 default:
467 op->hierarchy_information = HIERARCHY_AUTO; 454 c->hierarchy = HIERARCHY_AUTO;
468 break; 455 break;
469 } 456 }
470 457
471 param->frequency = state->frequency; 458 c->frequency = state->frequency;
472 op->bandwidth = state->bandwidth; 459 c->bandwidth_hz = state->bandwidth;
473 param->inversion = INVERSION_AUTO; 460 c->inversion = INVERSION_AUTO;
474 461
475 return 0; 462 return 0;
476} 463}
@@ -651,10 +638,9 @@ error:
651} 638}
652 639
653static struct dvb_frontend_ops zl10353_ops = { 640static struct dvb_frontend_ops zl10353_ops = {
654 641 .delsys = { SYS_DVBT },
655 .info = { 642 .info = {
656 .name = "Zarlink ZL10353 DVB-T", 643 .name = "Zarlink ZL10353 DVB-T",
657 .type = FE_OFDM,
658 .frequency_min = 174000000, 644 .frequency_min = 174000000,
659 .frequency_max = 862000000, 645 .frequency_max = 862000000,
660 .frequency_stepsize = 166667, 646 .frequency_stepsize = 166667,