1 files changed, 20 insertions, 21 deletions

diff --git a/drivers/infiniband/hw/qib/qib_iba7322.c b/drivers/infiniband/hw/qib/qib_iba7322.c
index ef97b71c8f7d..f32b4628e991 100644
--- a/drivers/infiniband/hw/qib/qib_iba7322.c
+++ b/drivers/infiniband/hw/qib/qib_iba7322.c
@@ -6429,6 +6429,7 @@ static int qib_init_7322_variables(struct qib_devdata *dd)
         unsigned features, pidx, sbufcnt;
         int ret, mtu;
         u32 sbufs, updthresh;
+        resource_size_t vl15off;
 
         /* pport structs are contiguous, allocated after devdata */
         ppd = (struct qib_pportdata *)(dd + 1);
@@ -6677,29 +6678,27 @@ static int qib_init_7322_variables(struct qib_devdata *dd)
         qib_7322_config_ctxts(dd);
         qib_set_ctxtcnt(dd);
 
-        if (qib_wc_pat) {
-                resource_size_t vl15off;
-                /*
-                 * We do not set WC on the VL15 buffers to avoid
-                 * a rare problem with unaligned writes from
-                 * interrupt-flushed store buffers, so we need
-                 * to map those separately here.  We can't solve
-                 * this for the rarely used mtrr case.
-                 */
-                ret = init_chip_wc_pat(dd, 0);
-                if (ret)
-                        goto bail;
+        /*
+         * We do not set WC on the VL15 buffers to avoid
+         * a rare problem with unaligned writes from
+         * interrupt-flushed store buffers, so we need
+         * to map those separately here.  We can't solve
+         * this for the rarely used mtrr case.
+         */
+        ret = init_chip_wc_pat(dd, 0);
+        if (ret)
+                goto bail;
 
-                /* vl15 buffers start just after the 4k buffers */
-                vl15off = dd->physaddr + (dd->piobufbase >> 32) +
-                        dd->piobcnt4k * dd->align4k;
-                dd->piovl15base = ioremap_nocache(vl15off,
-                                                  NUM_VL15_BUFS * dd->align4k);
-                if (!dd->piovl15base) {
-                        ret = -ENOMEM;
-                        goto bail;
-                }
+        /* vl15 buffers start just after the 4k buffers */
+        vl15off = dd->physaddr + (dd->piobufbase >> 32) +
+                  dd->piobcnt4k * dd->align4k;
+        dd->piovl15base = ioremap_nocache(vl15off,
+                                          NUM_VL15_BUFS * dd->align4k);
+        if (!dd->piovl15base) {
+                ret = -ENOMEM;
+                goto bail;
         }
+
         qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
 
         ret = 0;