1 files changed, 21 insertions, 1 deletions

diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index f99eece4cc97..160942a9180e 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -366,7 +366,6 @@
 # define SCALER_DISPBKGND_FILL                  BIT(24)
 
 #define SCALER_DISPSTAT0                        0x00000048
-#define SCALER_DISPBASE0                        0x0000004c
 # define SCALER_DISPSTATX_MODE_MASK             VC4_MASK(31, 30)
 # define SCALER_DISPSTATX_MODE_SHIFT            30
 # define SCALER_DISPSTATX_MODE_DISABLED         0
@@ -375,6 +374,24 @@
 # define SCALER_DISPSTATX_MODE_EOF              3
 # define SCALER_DISPSTATX_FULL                  BIT(29)
 # define SCALER_DISPSTATX_EMPTY                 BIT(28)
+# define SCALER_DISPSTATX_FRAME_COUNT_MASK      VC4_MASK(17, 12)
+# define SCALER_DISPSTATX_FRAME_COUNT_SHIFT     12
+# define SCALER_DISPSTATX_LINE_MASK             VC4_MASK(11, 0)
+# define SCALER_DISPSTATX_LINE_SHIFT            0
+
+#define SCALER_DISPBASE0                        0x0000004c
+/* Last pixel in the COB (display FIFO memory) allocated to this HVS
+ * channel.  Must be 4-pixel aligned (and thus 4 pixels less than the
+ * next COB base).
+ */
+# define SCALER_DISPBASEX_TOP_MASK              VC4_MASK(31, 16)
+# define SCALER_DISPBASEX_TOP_SHIFT             16
+/* First pixel in the COB (display FIFO memory) allocated to this HVS
+ * channel.  Must be 4-pixel aligned.
+ */
+# define SCALER_DISPBASEX_BASE_MASK             VC4_MASK(15, 0)
+# define SCALER_DISPBASEX_BASE_SHIFT            0
+
 #define SCALER_DISPCTRL1                        0x00000050
 #define SCALER_DISPBKGND1                       0x00000054
 #define SCALER_DISPBKGNDX(x)                    (SCALER_DISPBKGND0 +        \
@@ -385,6 +402,9 @@
                                                  (x) * (SCALER_DISPSTAT1 - \
                                                         SCALER_DISPSTAT0))
 #define SCALER_DISPBASE1                        0x0000005c
+#define SCALER_DISPBASEX(x)                     (SCALER_DISPBASE0 +        \
+                                                 (x) * (SCALER_DISPBASE1 - \
+                                                        SCALER_DISPBASE0))
 #define SCALER_DISPCTRL2                        0x00000060
 #define SCALER_DISPCTRLX(x)                     (SCALER_DISPCTRL0 +        \
                                                  (x) * (SCALER_DISPCTRL1 - \