1 files changed, 5 insertions, 4 deletions

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index bcf516a8a2f1..a7fb2735d4a9 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -6203,6 +6203,9 @@ int si_irq_set(struct radeon_device *rdev)
 
         WREG32(CG_THERMAL_INT, thermal_int);
 
+        /* posting read */
+        RREG32(SRBM_STATUS);
+
         return 0;
 }
 
@@ -7127,8 +7130,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
 
         if (!vclk || !dclk) {
-                /* keep the Bypass mode, put PLL to sleep */
-                WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
+                /* keep the Bypass mode */
                 return 0;
         }
 
@@ -7144,8 +7146,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
         /* set VCO_MODE to 1 */
         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
 
-        /* toggle UPLL_SLEEP to 1 then back to 0 */
-        WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
+        /* disable sleep mode */
         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
 
         /* deassert UPLL_RESET */