diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.c')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 92 |
1 files changed, 91 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 64fb89ecbf74..3d73fe484f42 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
@@ -171,6 +171,9 @@ static struct radeon_asic r100_asic = { | |||
171 | .pm_finish = &r100_pm_finish, | 171 | .pm_finish = &r100_pm_finish, |
172 | .pm_init_profile = &r100_pm_init_profile, | 172 | .pm_init_profile = &r100_pm_init_profile, |
173 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | 173 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, |
174 | .pre_page_flip = &r100_pre_page_flip, | ||
175 | .page_flip = &r100_page_flip, | ||
176 | .post_page_flip = &r100_post_page_flip, | ||
174 | }; | 177 | }; |
175 | 178 | ||
176 | static struct radeon_asic r200_asic = { | 179 | static struct radeon_asic r200_asic = { |
@@ -215,6 +218,9 @@ static struct radeon_asic r200_asic = { | |||
215 | .pm_finish = &r100_pm_finish, | 218 | .pm_finish = &r100_pm_finish, |
216 | .pm_init_profile = &r100_pm_init_profile, | 219 | .pm_init_profile = &r100_pm_init_profile, |
217 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | 220 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, |
221 | .pre_page_flip = &r100_pre_page_flip, | ||
222 | .page_flip = &r100_page_flip, | ||
223 | .post_page_flip = &r100_post_page_flip, | ||
218 | }; | 224 | }; |
219 | 225 | ||
220 | static struct radeon_asic r300_asic = { | 226 | static struct radeon_asic r300_asic = { |
@@ -260,6 +266,9 @@ static struct radeon_asic r300_asic = { | |||
260 | .pm_finish = &r100_pm_finish, | 266 | .pm_finish = &r100_pm_finish, |
261 | .pm_init_profile = &r100_pm_init_profile, | 267 | .pm_init_profile = &r100_pm_init_profile, |
262 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | 268 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, |
269 | .pre_page_flip = &r100_pre_page_flip, | ||
270 | .page_flip = &r100_page_flip, | ||
271 | .post_page_flip = &r100_post_page_flip, | ||
263 | }; | 272 | }; |
264 | 273 | ||
265 | static struct radeon_asic r300_asic_pcie = { | 274 | static struct radeon_asic r300_asic_pcie = { |
@@ -304,6 +313,9 @@ static struct radeon_asic r300_asic_pcie = { | |||
304 | .pm_finish = &r100_pm_finish, | 313 | .pm_finish = &r100_pm_finish, |
305 | .pm_init_profile = &r100_pm_init_profile, | 314 | .pm_init_profile = &r100_pm_init_profile, |
306 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | 315 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, |
316 | .pre_page_flip = &r100_pre_page_flip, | ||
317 | .page_flip = &r100_page_flip, | ||
318 | .post_page_flip = &r100_post_page_flip, | ||
307 | }; | 319 | }; |
308 | 320 | ||
309 | static struct radeon_asic r420_asic = { | 321 | static struct radeon_asic r420_asic = { |
@@ -349,6 +361,9 @@ static struct radeon_asic r420_asic = { | |||
349 | .pm_finish = &r100_pm_finish, | 361 | .pm_finish = &r100_pm_finish, |
350 | .pm_init_profile = &r420_pm_init_profile, | 362 | .pm_init_profile = &r420_pm_init_profile, |
351 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | 363 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, |
364 | .pre_page_flip = &r100_pre_page_flip, | ||
365 | .page_flip = &r100_page_flip, | ||
366 | .post_page_flip = &r100_post_page_flip, | ||
352 | }; | 367 | }; |
353 | 368 | ||
354 | static struct radeon_asic rs400_asic = { | 369 | static struct radeon_asic rs400_asic = { |
@@ -394,6 +409,9 @@ static struct radeon_asic rs400_asic = { | |||
394 | .pm_finish = &r100_pm_finish, | 409 | .pm_finish = &r100_pm_finish, |
395 | .pm_init_profile = &r100_pm_init_profile, | 410 | .pm_init_profile = &r100_pm_init_profile, |
396 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | 411 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, |
412 | .pre_page_flip = &r100_pre_page_flip, | ||
413 | .page_flip = &r100_page_flip, | ||
414 | .post_page_flip = &r100_post_page_flip, | ||
397 | }; | 415 | }; |
398 | 416 | ||
399 | static struct radeon_asic rs600_asic = { | 417 | static struct radeon_asic rs600_asic = { |
@@ -439,6 +457,9 @@ static struct radeon_asic rs600_asic = { | |||
439 | .pm_finish = &rs600_pm_finish, | 457 | .pm_finish = &rs600_pm_finish, |
440 | .pm_init_profile = &r420_pm_init_profile, | 458 | .pm_init_profile = &r420_pm_init_profile, |
441 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | 459 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, |
460 | .pre_page_flip = &rs600_pre_page_flip, | ||
461 | .page_flip = &rs600_page_flip, | ||
462 | .post_page_flip = &rs600_post_page_flip, | ||
442 | }; | 463 | }; |
443 | 464 | ||
444 | static struct radeon_asic rs690_asic = { | 465 | static struct radeon_asic rs690_asic = { |
@@ -484,6 +505,9 @@ static struct radeon_asic rs690_asic = { | |||
484 | .pm_finish = &rs600_pm_finish, | 505 | .pm_finish = &rs600_pm_finish, |
485 | .pm_init_profile = &r420_pm_init_profile, | 506 | .pm_init_profile = &r420_pm_init_profile, |
486 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | 507 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, |
508 | .pre_page_flip = &rs600_pre_page_flip, | ||
509 | .page_flip = &rs600_page_flip, | ||
510 | .post_page_flip = &rs600_post_page_flip, | ||
487 | }; | 511 | }; |
488 | 512 | ||
489 | static struct radeon_asic rv515_asic = { | 513 | static struct radeon_asic rv515_asic = { |
@@ -529,6 +553,9 @@ static struct radeon_asic rv515_asic = { | |||
529 | .pm_finish = &rs600_pm_finish, | 553 | .pm_finish = &rs600_pm_finish, |
530 | .pm_init_profile = &r420_pm_init_profile, | 554 | .pm_init_profile = &r420_pm_init_profile, |
531 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | 555 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, |
556 | .pre_page_flip = &rs600_pre_page_flip, | ||
557 | .page_flip = &rs600_page_flip, | ||
558 | .post_page_flip = &rs600_post_page_flip, | ||
532 | }; | 559 | }; |
533 | 560 | ||
534 | static struct radeon_asic r520_asic = { | 561 | static struct radeon_asic r520_asic = { |
@@ -574,6 +601,9 @@ static struct radeon_asic r520_asic = { | |||
574 | .pm_finish = &rs600_pm_finish, | 601 | .pm_finish = &rs600_pm_finish, |
575 | .pm_init_profile = &r420_pm_init_profile, | 602 | .pm_init_profile = &r420_pm_init_profile, |
576 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | 603 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, |
604 | .pre_page_flip = &rs600_pre_page_flip, | ||
605 | .page_flip = &rs600_page_flip, | ||
606 | .post_page_flip = &rs600_post_page_flip, | ||
577 | }; | 607 | }; |
578 | 608 | ||
579 | static struct radeon_asic r600_asic = { | 609 | static struct radeon_asic r600_asic = { |
@@ -618,6 +648,9 @@ static struct radeon_asic r600_asic = { | |||
618 | .pm_finish = &rs600_pm_finish, | 648 | .pm_finish = &rs600_pm_finish, |
619 | .pm_init_profile = &r600_pm_init_profile, | 649 | .pm_init_profile = &r600_pm_init_profile, |
620 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | 650 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
651 | .pre_page_flip = &rs600_pre_page_flip, | ||
652 | .page_flip = &rs600_page_flip, | ||
653 | .post_page_flip = &rs600_post_page_flip, | ||
621 | }; | 654 | }; |
622 | 655 | ||
623 | static struct radeon_asic rs780_asic = { | 656 | static struct radeon_asic rs780_asic = { |
@@ -662,6 +695,9 @@ static struct radeon_asic rs780_asic = { | |||
662 | .pm_finish = &rs600_pm_finish, | 695 | .pm_finish = &rs600_pm_finish, |
663 | .pm_init_profile = &rs780_pm_init_profile, | 696 | .pm_init_profile = &rs780_pm_init_profile, |
664 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | 697 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
698 | .pre_page_flip = &rs600_pre_page_flip, | ||
699 | .page_flip = &rs600_page_flip, | ||
700 | .post_page_flip = &rs600_post_page_flip, | ||
665 | }; | 701 | }; |
666 | 702 | ||
667 | static struct radeon_asic rv770_asic = { | 703 | static struct radeon_asic rv770_asic = { |
@@ -706,6 +742,9 @@ static struct radeon_asic rv770_asic = { | |||
706 | .pm_finish = &rs600_pm_finish, | 742 | .pm_finish = &rs600_pm_finish, |
707 | .pm_init_profile = &r600_pm_init_profile, | 743 | .pm_init_profile = &r600_pm_init_profile, |
708 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | 744 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
745 | .pre_page_flip = &rs600_pre_page_flip, | ||
746 | .page_flip = &rv770_page_flip, | ||
747 | .post_page_flip = &rs600_post_page_flip, | ||
709 | }; | 748 | }; |
710 | 749 | ||
711 | static struct radeon_asic evergreen_asic = { | 750 | static struct radeon_asic evergreen_asic = { |
@@ -749,6 +788,52 @@ static struct radeon_asic evergreen_asic = { | |||
749 | .pm_finish = &evergreen_pm_finish, | 788 | .pm_finish = &evergreen_pm_finish, |
750 | .pm_init_profile = &r600_pm_init_profile, | 789 | .pm_init_profile = &r600_pm_init_profile, |
751 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | 790 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
791 | .pre_page_flip = &evergreen_pre_page_flip, | ||
792 | .page_flip = &evergreen_page_flip, | ||
793 | .post_page_flip = &evergreen_post_page_flip, | ||
794 | }; | ||
795 | |||
796 | static struct radeon_asic sumo_asic = { | ||
797 | .init = &evergreen_init, | ||
798 | .fini = &evergreen_fini, | ||
799 | .suspend = &evergreen_suspend, | ||
800 | .resume = &evergreen_resume, | ||
801 | .cp_commit = &r600_cp_commit, | ||
802 | .gpu_is_lockup = &evergreen_gpu_is_lockup, | ||
803 | .asic_reset = &evergreen_asic_reset, | ||
804 | .vga_set_state = &r600_vga_set_state, | ||
805 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, | ||
806 | .gart_set_page = &rs600_gart_set_page, | ||
807 | .ring_test = &r600_ring_test, | ||
808 | .ring_ib_execute = &r600_ring_ib_execute, | ||
809 | .irq_set = &evergreen_irq_set, | ||
810 | .irq_process = &evergreen_irq_process, | ||
811 | .get_vblank_counter = &evergreen_get_vblank_counter, | ||
812 | .fence_ring_emit = &r600_fence_ring_emit, | ||
813 | .cs_parse = &evergreen_cs_parse, | ||
814 | .copy_blit = &evergreen_copy_blit, | ||
815 | .copy_dma = &evergreen_copy_blit, | ||
816 | .copy = &evergreen_copy_blit, | ||
817 | .get_engine_clock = &radeon_atom_get_engine_clock, | ||
818 | .set_engine_clock = &radeon_atom_set_engine_clock, | ||
819 | .get_memory_clock = NULL, | ||
820 | .set_memory_clock = NULL, | ||
821 | .get_pcie_lanes = NULL, | ||
822 | .set_pcie_lanes = NULL, | ||
823 | .set_clock_gating = NULL, | ||
824 | .set_surface_reg = r600_set_surface_reg, | ||
825 | .clear_surface_reg = r600_clear_surface_reg, | ||
826 | .bandwidth_update = &evergreen_bandwidth_update, | ||
827 | .hpd_init = &evergreen_hpd_init, | ||
828 | .hpd_fini = &evergreen_hpd_fini, | ||
829 | .hpd_sense = &evergreen_hpd_sense, | ||
830 | .hpd_set_polarity = &evergreen_hpd_set_polarity, | ||
831 | .gui_idle = &r600_gui_idle, | ||
832 | .pm_misc = &evergreen_pm_misc, | ||
833 | .pm_prepare = &evergreen_pm_prepare, | ||
834 | .pm_finish = &evergreen_pm_finish, | ||
835 | .pm_init_profile = &rs780_pm_init_profile, | ||
836 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | ||
752 | }; | 837 | }; |
753 | 838 | ||
754 | int radeon_asic_init(struct radeon_device *rdev) | 839 | int radeon_asic_init(struct radeon_device *rdev) |
@@ -835,6 +920,9 @@ int radeon_asic_init(struct radeon_device *rdev) | |||
835 | case CHIP_HEMLOCK: | 920 | case CHIP_HEMLOCK: |
836 | rdev->asic = &evergreen_asic; | 921 | rdev->asic = &evergreen_asic; |
837 | break; | 922 | break; |
923 | case CHIP_PALM: | ||
924 | rdev->asic = &sumo_asic; | ||
925 | break; | ||
838 | default: | 926 | default: |
839 | /* FIXME: not supported yet */ | 927 | /* FIXME: not supported yet */ |
840 | return -EINVAL; | 928 | return -EINVAL; |
@@ -849,7 +937,9 @@ int radeon_asic_init(struct radeon_device *rdev) | |||
849 | if (rdev->flags & RADEON_SINGLE_CRTC) | 937 | if (rdev->flags & RADEON_SINGLE_CRTC) |
850 | rdev->num_crtc = 1; | 938 | rdev->num_crtc = 1; |
851 | else { | 939 | else { |
852 | if (ASIC_IS_DCE4(rdev)) | 940 | if (ASIC_IS_DCE41(rdev)) |
941 | rdev->num_crtc = 2; | ||
942 | else if (ASIC_IS_DCE4(rdev)) | ||
853 | rdev->num_crtc = 6; | 943 | rdev->num_crtc = 6; |
854 | else | 944 | else |
855 | rdev->num_crtc = 2; | 945 | rdev->num_crtc = 2; |