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path: root/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c')
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
index 324008e8fa9b..81dc280c0022 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
@@ -49,7 +49,7 @@ static const struct {
49 _(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) | 49 _(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) |
50 (1ULL << NVDEV_ENGINE_CE2)), 50 (1ULL << NVDEV_ENGINE_CE2)),
51 _(NVDEV_ENGINE_VP , 0), 51 _(NVDEV_ENGINE_VP , 0),
52 _(NVDEV_ENGINE_PPP , 0), 52 _(NVDEV_ENGINE_MSPPP , 0),
53 _(NVDEV_ENGINE_MSVLD , 0), 53 _(NVDEV_ENGINE_MSVLD , 0),
54 _(NVDEV_ENGINE_CE0 , 0), 54 _(NVDEV_ENGINE_CE0 , 0),
55 _(NVDEV_ENGINE_CE1 , 0), 55 _(NVDEV_ENGINE_CE1 , 0),
@@ -151,7 +151,7 @@ nve0_fifo_context_attach(struct nouveau_object *parent,
151 case NVDEV_ENGINE_GR : addr = 0x0210; break; 151 case NVDEV_ENGINE_GR : addr = 0x0210; break;
152 case NVDEV_ENGINE_MSVLD: addr = 0x0270; break; 152 case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
153 case NVDEV_ENGINE_VP : addr = 0x0250; break; 153 case NVDEV_ENGINE_VP : addr = 0x0250; break;
154 case NVDEV_ENGINE_PPP : addr = 0x0260; break; 154 case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
155 default: 155 default:
156 return -EINVAL; 156 return -EINVAL;
157 } 157 }
@@ -189,7 +189,7 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
189 case NVDEV_ENGINE_GR : addr = 0x0210; break; 189 case NVDEV_ENGINE_GR : addr = 0x0210; break;
190 case NVDEV_ENGINE_MSVLD: addr = 0x0270; break; 190 case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
191 case NVDEV_ENGINE_VP : addr = 0x0250; break; 191 case NVDEV_ENGINE_VP : addr = 0x0250; break;
192 case NVDEV_ENGINE_PPP : addr = 0x0260; break; 192 case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
193 default: 193 default:
194 return -EINVAL; 194 return -EINVAL;
195 } 195 }
@@ -417,7 +417,7 @@ nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn)
417 case NVDEV_ENGINE_GR : 417 case NVDEV_ENGINE_GR :
418 case NVDEV_ENGINE_CE2 : engn = 0; break; 418 case NVDEV_ENGINE_CE2 : engn = 0; break;
419 case NVDEV_ENGINE_MSVLD: engn = 1; break; 419 case NVDEV_ENGINE_MSVLD: engn = 1; break;
420 case NVDEV_ENGINE_PPP : engn = 2; break; 420 case NVDEV_ENGINE_MSPPP: engn = 2; break;
421 case NVDEV_ENGINE_VP : engn = 3; break; 421 case NVDEV_ENGINE_VP : engn = 3; break;
422 case NVDEV_ENGINE_CE0 : engn = 4; break; 422 case NVDEV_ENGINE_CE0 : engn = 4; break;
423 case NVDEV_ENGINE_CE1 : engn = 5; break; 423 case NVDEV_ENGINE_CE1 : engn = 5; break;
@@ -620,7 +620,7 @@ nve0_fifo_fault_engine[] = {
620 { 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO }, 620 { 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO },
621 { 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO }, 621 { 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO },
622 { 0x10, "MSVLD", NULL, NVDEV_ENGINE_MSVLD }, 622 { 0x10, "MSVLD", NULL, NVDEV_ENGINE_MSVLD },
623 { 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP }, 623 { 0x11, "MSPPP", NULL, NVDEV_ENGINE_MSPPP },
624 { 0x13, "PERF" }, 624 { 0x13, "PERF" },
625 { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP }, 625 { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP },
626 { 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 }, 626 { 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 },