1 files changed, 21 insertions, 24 deletions

diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.c b/drivers/gpu/drm/nouveau/nouveau_hw.c
index 7b613682e400..bed669a54a2d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_hw.c
+++ b/drivers/gpu/drm/nouveau/nouveau_hw.c
@@ -305,7 +305,7 @@ setPLL_double_lowregs(struct drm_device *dev, uint32_t NMNMreg,
         bool mpll = Preg == 0x4020;
         uint32_t oldPval = nvReadMC(dev, Preg);
         uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
-        uint32_t Pval = (oldPval & (mpll ? ~(0x11 << 16) : ~(1 << 16))) |
+        uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |
                         0xc << 28 | pv->log2P << 16;
         uint32_t saved4600 = 0;
         /* some cards have different maskc040s */
@@ -427,22 +427,12 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum pll_types plltype,
                        struct nouveau_pll_vals *pllvals)
 {
         struct drm_nouveau_private *dev_priv = dev->dev_private;
-        const uint32_t nv04_regs[MAX_PLL_TYPES] = { NV_PRAMDAC_NVPLL_COEFF,
-                                                    NV_PRAMDAC_MPLL_COEFF,
-                                                    NV_PRAMDAC_VPLL_COEFF,
-                                                    NV_RAMDAC_VPLL2 };
-        const uint32_t nv40_regs[MAX_PLL_TYPES] = { 0x4000,
-                                                    0x4020,
-                                                    NV_PRAMDAC_VPLL_COEFF,
-                                                    NV_RAMDAC_VPLL2 };
-        uint32_t reg1, pll1, pll2 = 0;
+        uint32_t reg1 = get_pll_register(dev, plltype), pll1, pll2 = 0;
         struct pll_lims pll_lim;
         int ret;
 
-        if (dev_priv->card_type < NV_40)
-                reg1 = nv04_regs[plltype];
-        else
-                reg1 = nv40_regs[plltype];
+        if (reg1 == 0)
+                return -ENOENT;
 
         pll1 = nvReadMC(dev, reg1);
 
@@ -491,8 +481,10 @@ int
 nouveau_hw_get_clock(struct drm_device *dev, enum pll_types plltype)
 {
         struct nouveau_pll_vals pllvals;
+        int ret;
 
-        if (plltype == MPLL && (dev->pci_device & 0x0ff0) == CHIPSET_NFORCE) {
+        if (plltype == PLL_MEMORY &&
+            (dev->pci_device & 0x0ff0) == CHIPSET_NFORCE) {
                 uint32_t mpllP;
 
                 pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
@@ -501,14 +493,17 @@ nouveau_hw_get_clock(struct drm_device *dev, enum pll_types plltype)
 
                 return 400000 / mpllP;
         } else
-        if (plltype == MPLL && (dev->pci_device & 0xff0) == CHIPSET_NFORCE2) {
+        if (plltype == PLL_MEMORY &&
+            (dev->pci_device & 0xff0) == CHIPSET_NFORCE2) {
                 uint32_t clock;
 
                 pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock);
                 return clock;
         }
 
-        nouveau_hw_get_pllvals(dev, plltype, &pllvals);
+        ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals);
+        if (ret)
+                return ret;
 
         return nouveau_hw_pllvals_to_clk(&pllvals);
 }
@@ -526,9 +521,9 @@ nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
         struct nouveau_pll_vals pv;
         uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
 
-        if (get_pll_limits(dev, head ? VPLL2 : VPLL1, &pll_lim))
+        if (get_pll_limits(dev, pllreg, &pll_lim))
                 return;
-        nouveau_hw_get_pllvals(dev, head ? VPLL2 : VPLL1, &pv);
+        nouveau_hw_get_pllvals(dev, pllreg, &pv);
 
         if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m &&
             pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n &&
@@ -661,7 +656,7 @@ nv_save_state_ramdac(struct drm_device *dev, int head,
         if (dev_priv->card_type >= NV_10)
                 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
 
-        nouveau_hw_get_pllvals(dev, head ? VPLL2 : VPLL1, &regp->pllvals);
+        nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, &regp->pllvals);
         state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT);
         if (nv_two_heads(dev))
                 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
@@ -866,10 +861,11 @@ nv_save_state_ext(struct drm_device *dev, int head,
         rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
         rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
 
-        if (dev_priv->card_type >= NV_30) {
+        if (dev_priv->card_type >= NV_20)
                 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
+
+        if (dev_priv->card_type >= NV_30)
                 rd_cio_state(dev, head, regp, 0x9f);
-        }
 
         rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
         rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
@@ -976,10 +972,11 @@ nv_load_state_ext(struct drm_device *dev, int head,
         wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
         wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
 
-        if (dev_priv->card_type >= NV_30) {
+        if (dev_priv->card_type >= NV_20)
                 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
+
+        if (dev_priv->card_type >= NV_30)
                 wr_cio_state(dev, head, regp, 0x9f);
-        }
 
         wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
         wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);