1 files changed, 154 insertions, 106 deletions

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index d70d96fe553b..1c6d227aae7c 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -391,20 +391,13 @@ static int i915_load_modeset_init(struct drm_device *dev)
         if (ret)
                 goto cleanup_vga_client;
 
-        /* Initialise stolen first so that we may reserve preallocated
-         * objects for the BIOS to KMS transition.
-         */
-        ret = i915_gem_init_stolen(dev);
-        if (ret)
-                goto cleanup_vga_switcheroo;
-
         intel_power_domains_init_hw(dev_priv, false);
 
         intel_csr_ucode_init(dev_priv);
 
         ret = intel_irq_install(dev_priv);
         if (ret)
-                goto cleanup_gem_stolen;
+                goto cleanup_csr;
 
         intel_setup_gmbus(dev);
 
@@ -458,9 +451,8 @@ cleanup_irq:
         intel_guc_ucode_fini(dev);
         drm_irq_uninstall(dev);
         intel_teardown_gmbus(dev);
-cleanup_gem_stolen:
-        i915_gem_cleanup_stolen(dev);
-cleanup_vga_switcheroo:
+cleanup_csr:
+        intel_csr_ucode_fini(dev_priv);
         vga_switcheroo_unregister_client(dev->pdev);
 cleanup_vga_client:
         vga_client_register(dev->pdev, NULL, NULL, NULL);
@@ -816,7 +808,41 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
                         DRM_INFO("Display fused off, disabling\n");
                         info->num_pipes = 0;
+                } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
+                        DRM_INFO("PipeC fused off\n");
+                        info->num_pipes -= 1;
                 }
+        } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
+                u32 dfsm = I915_READ(SKL_DFSM);
+                u8 disabled_mask = 0;
+                bool invalid;
+                int num_bits;
+
+                if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
+                        disabled_mask |= BIT(PIPE_A);
+                if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
+                        disabled_mask |= BIT(PIPE_B);
+                if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
+                        disabled_mask |= BIT(PIPE_C);
+
+                num_bits = hweight8(disabled_mask);
+
+                switch (disabled_mask) {
+                case BIT(PIPE_A):
+                case BIT(PIPE_B):
+                case BIT(PIPE_A) | BIT(PIPE_B):
+                case BIT(PIPE_A) | BIT(PIPE_C):
+                        invalid = true;
+                        break;
+                default:
+                        invalid = false;
+                }
+
+                if (num_bits > info->num_pipes || invalid)
+                        DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
+                                  disabled_mask);
+                else
+                        info->num_pipes -= num_bits;
         }
 
         /* Initialize slice/subslice/EU info */
@@ -855,6 +881,94 @@ static void intel_init_dpio(struct drm_i915_private *dev_priv)
         }
 }
 
+static int i915_workqueues_init(struct drm_i915_private *dev_priv)
+{
+        /*
+         * The i915 workqueue is primarily used for batched retirement of
+         * requests (and thus managing bo) once the task has been completed
+         * by the GPU. i915_gem_retire_requests() is called directly when we
+         * need high-priority retirement, such as waiting for an explicit
+         * bo.
+         *
+         * It is also used for periodic low-priority events, such as
+         * idle-timers and recording error state.
+         *
+         * All tasks on the workqueue are expected to acquire the dev mutex
+         * so there is no point in running more than one instance of the
+         * workqueue at any time.  Use an ordered one.
+         */
+        dev_priv->wq = alloc_ordered_workqueue("i915", 0);
+        if (dev_priv->wq == NULL)
+                goto out_err;
+
+        dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
+        if (dev_priv->hotplug.dp_wq == NULL)
+                goto out_free_wq;
+
+        dev_priv->gpu_error.hangcheck_wq =
+                alloc_ordered_workqueue("i915-hangcheck", 0);
+        if (dev_priv->gpu_error.hangcheck_wq == NULL)
+                goto out_free_dp_wq;
+
+        return 0;
+
+out_free_dp_wq:
+        destroy_workqueue(dev_priv->hotplug.dp_wq);
+out_free_wq:
+        destroy_workqueue(dev_priv->wq);
+out_err:
+        DRM_ERROR("Failed to allocate workqueues.\n");
+
+        return -ENOMEM;
+}
+
+static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
+{
+        destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
+        destroy_workqueue(dev_priv->hotplug.dp_wq);
+        destroy_workqueue(dev_priv->wq);
+}
+
+static int i915_mmio_setup(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = to_i915(dev);
+        int mmio_bar;
+        int mmio_size;
+
+        mmio_bar = IS_GEN2(dev) ? 1 : 0;
+        /*
+         * Before gen4, the registers and the GTT are behind different BARs.
+         * However, from gen4 onwards, the registers and the GTT are shared
+         * in the same BAR, so we want to restrict this ioremap from
+         * clobbering the GTT which we want ioremap_wc instead. Fortunately,
+         * the register BAR remains the same size for all the earlier
+         * generations up to Ironlake.
+         */
+        if (INTEL_INFO(dev)->gen < 5)
+                mmio_size = 512 * 1024;
+        else
+                mmio_size = 2 * 1024 * 1024;
+        dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
+        if (dev_priv->regs == NULL) {
+                DRM_ERROR("failed to map registers\n");
+
+                return -EIO;
+        }
+
+        /* Try to make sure MCHBAR is enabled before poking at it */
+        intel_setup_mchbar(dev);
+
+        return 0;
+}
+
+static void i915_mmio_cleanup(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = to_i915(dev);
+
+        intel_teardown_mchbar(dev);
+        pci_iounmap(dev->pdev, dev_priv->regs);
+}
+
 /**
  * i915_driver_load - setup chip and create an initial config
  * @dev: DRM device
@@ -870,7 +984,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 {
         struct drm_i915_private *dev_priv;
         struct intel_device_info *info, *device_info;
-        int ret = 0, mmio_bar, mmio_size;
+        int ret = 0;
         uint32_t aperture_size;
 
         info = (struct intel_device_info *) flags;
@@ -897,6 +1011,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
         mutex_init(&dev_priv->modeset_restore_lock);
         mutex_init(&dev_priv->av_mutex);
 
+        ret = i915_workqueues_init(dev_priv);
+        if (ret < 0)
+                goto out_free_priv;
+
         intel_pm_setup(dev);
 
         intel_runtime_pm_get(dev_priv);
@@ -915,28 +1033,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
         if (i915_get_bridge_dev(dev)) {
                 ret = -EIO;
-                goto free_priv;
+                goto out_runtime_pm_put;
         }
 
-        mmio_bar = IS_GEN2(dev) ? 1 : 0;
-        /* Before gen4, the registers and the GTT are behind different BARs.
-         * However, from gen4 onwards, the registers and the GTT are shared
-         * in the same BAR, so we want to restrict this ioremap from
-         * clobbering the GTT which we want ioremap_wc instead. Fortunately,
-         * the register BAR remains the same size for all the earlier
-         * generations up to Ironlake.
-         */
-        if (info->gen < 5)
-                mmio_size = 512*1024;
-        else
-                mmio_size = 2*1024*1024;
-
-        dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
-        if (!dev_priv->regs) {
-                DRM_ERROR("failed to map registers\n");
-                ret = -EIO;
+        ret = i915_mmio_setup(dev);
+        if (ret < 0)
                 goto put_bridge;
-        }
 
         /* This must be called before any calls to HAS_PCH_* */
         intel_detect_pch(dev);
@@ -945,7 +1047,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
         ret = i915_gem_gtt_init(dev);
         if (ret)
-                goto out_freecsr;
+                goto out_uncore_fini;
 
         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
          * otherwise the vga fbdev driver falls over. */
@@ -991,49 +1093,13 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
                                               aperture_size);
 
-        /* The i915 workqueue is primarily used for batched retirement of
-         * requests (and thus managing bo) once the task has been completed
-         * by the GPU. i915_gem_retire_requests() is called directly when we
-         * need high-priority retirement, such as waiting for an explicit
-         * bo.
-         *
-         * It is also used for periodic low-priority events, such as
-         * idle-timers and recording error state.
-         *
-         * All tasks on the workqueue are expected to acquire the dev mutex
-         * so there is no point in running more than one instance of the
-         * workqueue at any time.  Use an ordered one.
-         */
-        dev_priv->wq = alloc_ordered_workqueue("i915", 0);
-        if (dev_priv->wq == NULL) {
-                DRM_ERROR("Failed to create our workqueue.\n");
-                ret = -ENOMEM;
-                goto out_mtrrfree;
-        }
-
-        dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
-        if (dev_priv->hotplug.dp_wq == NULL) {
-                DRM_ERROR("Failed to create our dp workqueue.\n");
-                ret = -ENOMEM;
-                goto out_freewq;
-        }
-
-        dev_priv->gpu_error.hangcheck_wq =
-                alloc_ordered_workqueue("i915-hangcheck", 0);
-        if (dev_priv->gpu_error.hangcheck_wq == NULL) {
-                DRM_ERROR("Failed to create our hangcheck workqueue.\n");
-                ret = -ENOMEM;
-                goto out_freedpwq;
-        }
-
         intel_irq_init(dev_priv);
         intel_uncore_sanitize(dev);
 
-        /* Try to make sure MCHBAR is enabled before poking at it */
-        intel_setup_mchbar(dev);
         intel_opregion_setup(dev);
 
-        i915_gem_load(dev);
+        i915_gem_load_init(dev);
+        i915_gem_shrinker_init(dev_priv);
 
         /* On the 945G/GM, the chipset reports the MSI capability on the
          * integrated graphics even though the support isn't actually there
@@ -1046,8 +1112,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
          * be lost or delayed, but we use them anyways to avoid
          * stuck interrupts on some machines.
          */
-        if (!IS_I945G(dev) && !IS_I945GM(dev))
-                pci_enable_msi(dev->pdev);
+        if (!IS_I945G(dev) && !IS_I945GM(dev)) {
+                if (pci_enable_msi(dev->pdev) < 0)
+                        DRM_DEBUG_DRIVER("can't enable MSI");
+        }
 
         intel_device_info_runtime_init(dev);
 
@@ -1097,38 +1165,29 @@ out_power_well:
         intel_power_domains_fini(dev_priv);
         drm_vblank_cleanup(dev);
 out_gem_unload:
-        WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
-        unregister_shrinker(&dev_priv->mm.shrinker);
+        i915_gem_shrinker_cleanup(dev_priv);
 
         if (dev->pdev->msi_enabled)
                 pci_disable_msi(dev->pdev);
 
         intel_teardown_mchbar(dev);
         pm_qos_remove_request(&dev_priv->pm_qos);
-        destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
-out_freedpwq:
-        destroy_workqueue(dev_priv->hotplug.dp_wq);
-out_freewq:
-        destroy_workqueue(dev_priv->wq);
-out_mtrrfree:
         arch_phys_wc_del(dev_priv->gtt.mtrr);
         io_mapping_free(dev_priv->gtt.mappable);
 out_gtt:
         i915_global_gtt_cleanup(dev);
-out_freecsr:
-        intel_csr_ucode_fini(dev_priv);
+out_uncore_fini:
         intel_uncore_fini(dev);
-        pci_iounmap(dev->pdev, dev_priv->regs);
+        i915_mmio_cleanup(dev);
 put_bridge:
         pci_dev_put(dev_priv->bridge_dev);
-free_priv:
-        kmem_cache_destroy(dev_priv->requests);
-        kmem_cache_destroy(dev_priv->vmas);
-        kmem_cache_destroy(dev_priv->objects);
-
+        i915_gem_load_cleanup(dev);
+out_runtime_pm_put:
         intel_runtime_pm_put(dev_priv);
-
+        i915_workqueues_cleanup(dev_priv);
+out_free_priv:
         kfree(dev_priv);
+
         return ret;
 }
 
@@ -1153,8 +1212,7 @@ int i915_driver_unload(struct drm_device *dev)
 
         i915_teardown_sysfs(dev);
 
-        WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
-        unregister_shrinker(&dev_priv->mm.shrinker);
+        i915_gem_shrinker_cleanup(dev_priv);
 
         io_mapping_free(dev_priv->gtt.mappable);
         arch_phys_wc_del(dev_priv->gtt.mtrr);
@@ -1182,6 +1240,8 @@ int i915_driver_unload(struct drm_device *dev)
         vga_switcheroo_unregister_client(dev->pdev);
         vga_client_register(dev->pdev, NULL, NULL, NULL);
 
+        intel_csr_ucode_fini(dev_priv);
+
         /* Free error state after interrupts are fully disabled. */
         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
         i915_destroy_error_state(dev);
@@ -1200,27 +1260,17 @@ int i915_driver_unload(struct drm_device *dev)
         i915_gem_context_fini(dev);
         mutex_unlock(&dev->struct_mutex);
         intel_fbc_cleanup_cfb(dev_priv);
-        i915_gem_cleanup_stolen(dev);
 
-        intel_csr_ucode_fini(dev_priv);
-
-        intel_teardown_mchbar(dev);
-
-        destroy_workqueue(dev_priv->hotplug.dp_wq);
-        destroy_workqueue(dev_priv->wq);
-        destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
         pm_qos_remove_request(&dev_priv->pm_qos);
 
         i915_global_gtt_cleanup(dev);
 
         intel_uncore_fini(dev);
-        if (dev_priv->regs != NULL)
-                pci_iounmap(dev->pdev, dev_priv->regs);
+        i915_mmio_cleanup(dev);
 
-        kmem_cache_destroy(dev_priv->requests);
-        kmem_cache_destroy(dev_priv->vmas);
-        kmem_cache_destroy(dev_priv->objects);
+        i915_gem_load_cleanup(dev);
         pci_dev_put(dev_priv->bridge_dev);
+        i915_workqueues_cleanup(dev_priv);
         kfree(dev_priv);
 
         return 0;
@@ -1261,8 +1311,6 @@ void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
         i915_gem_context_close(dev, file);
         i915_gem_release(dev, file);
         mutex_unlock(&dev->struct_mutex);
-
-        intel_modeset_preclose(dev, file);
 }
 
 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)