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path: root/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
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Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c')
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c984
1 files changed, 984 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
new file mode 100644
index 000000000000..de618ead9db8
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -0,0 +1,984 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "smumgr.h"
25#include "smu74.h"
26#include "smu_ucode_xfer_vi.h"
27#include "polaris10_smumgr.h"
28#include "smu74_discrete.h"
29#include "smu/smu_7_1_3_d.h"
30#include "smu/smu_7_1_3_sh_mask.h"
31#include "gmc/gmc_8_1_d.h"
32#include "gmc/gmc_8_1_sh_mask.h"
33#include "oss/oss_3_0_d.h"
34#include "gca/gfx_8_0_d.h"
35#include "bif/bif_5_0_d.h"
36#include "bif/bif_5_0_sh_mask.h"
37#include "polaris10_pwrvirus.h"
38#include "ppatomctrl.h"
39#include "pp_debug.h"
40#include "cgs_common.h"
41
42#define POLARIS10_SMC_SIZE 0x20000
43#define VOLTAGE_SCALE 4
44
45/* Microcode file is stored in this buffer */
46#define BUFFER_SIZE 80000
47#define MAX_STRING_SIZE 15
48#define BUFFER_SIZETWO 131072 /* 128 *1024 */
49
50#define SMC_RAM_END 0x40000
51
52static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
53 /* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */
54 /* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
55 { 0x3c0fd047, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x30750000, 0, 0, 0, 0, 0, 0, 0 } },
56 { 0xa00fd047, 0x01, 0x04, 0x1e00, 0x00800510, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x409c0000, 0, 0, 0, 0, 0, 0, 0 } },
57 { 0x0410d047, 0x01, 0x00, 0x1e00, 0x00600410, 0x87020000, 0, 0, 0x0e, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x50c30000, 0, 0, 0, 0, 0, 0, 0 } },
58 { 0x6810d047, 0x01, 0x00, 0x1e00, 0x00800410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x60ea0000, 0, 0, 0, 0, 0, 0, 0 } },
59 { 0xcc10d047, 0x01, 0x00, 0x1e00, 0x00e00410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xe8fd0000, 0, 0, 0, 0, 0, 0, 0 } },
60 { 0x3011d047, 0x01, 0x00, 0x1e00, 0x00400510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x70110100, 0, 0, 0, 0, 0, 0, 0 } },
61 { 0x9411d047, 0x01, 0x00, 0x1e00, 0x00a00510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xf8240100, 0, 0, 0, 0, 0, 0, 0 } },
62 { 0xf811d047, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x80380100, 0, 0, 0, 0, 0, 0, 0 } }
63};
64
65static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 =
66 {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00,
67 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00};
68
69/**
70* Set the address for reading/writing the SMC SRAM space.
71* @param smumgr the address of the powerplay hardware manager.
72* @param smcAddress the address in the SMC RAM to access.
73*/
74static int polaris10_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit)
75{
76 PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
77 PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
78
79 cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr);
80 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
81
82 return 0;
83}
84
85/**
86* Copy bytes from SMC RAM space into driver memory.
87*
88* @param smumgr the address of the powerplay SMU manager.
89* @param smc_start_address the start address in the SMC RAM to copy bytes from
90* @param src the byte array to copy the bytes to.
91* @param byte_count the number of bytes to copy.
92*/
93int polaris10_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
94{
95 uint32_t data;
96 uint32_t addr;
97 uint8_t *dest_byte;
98 uint8_t i, data_byte[4] = {0};
99 uint32_t *pdata = (uint32_t *)&data_byte;
100
101 PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1;);
102 PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1);
103
104 addr = smc_start_address;
105
106 while (byte_count >= 4) {
107 polaris10_read_smc_sram_dword(smumgr, addr, &data, limit);
108
109 *dest = PP_SMC_TO_HOST_UL(data);
110
111 dest += 1;
112 byte_count -= 4;
113 addr += 4;
114 }
115
116 if (byte_count) {
117 polaris10_read_smc_sram_dword(smumgr, addr, &data, limit);
118 *pdata = PP_SMC_TO_HOST_UL(data);
119 /* Cast dest into byte type in dest_byte. This way, we don't overflow if the allocated memory is not 4-byte aligned. */
120 dest_byte = (uint8_t *)dest;
121 for (i = 0; i < byte_count; i++)
122 dest_byte[i] = data_byte[i];
123 }
124
125 return 0;
126}
127
128/**
129* Copy bytes from an array into the SMC RAM space.
130*
131* @param pSmuMgr the address of the powerplay SMU manager.
132* @param smc_start_address the start address in the SMC RAM to copy bytes to.
133* @param src the byte array to copy the bytes from.
134* @param byte_count the number of bytes to copy.
135*/
136int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
137 const uint8_t *src, uint32_t byte_count, uint32_t limit)
138{
139 int result;
140 uint32_t data = 0;
141 uint32_t original_data;
142 uint32_t addr = 0;
143 uint32_t extra_shift;
144
145 PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1);
146 PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1);
147
148 addr = smc_start_address;
149
150 while (byte_count >= 4) {
151 /* Bytes are written into the SMC addres space with the MSB first. */
152 data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
153
154 result = polaris10_set_smc_sram_address(smumgr, addr, limit);
155
156 if (0 != result)
157 return result;
158
159 cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
160
161 src += 4;
162 byte_count -= 4;
163 addr += 4;
164 }
165
166 if (0 != byte_count) {
167
168 data = 0;
169
170 result = polaris10_set_smc_sram_address(smumgr, addr, limit);
171
172 if (0 != result)
173 return result;
174
175
176 original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
177
178 extra_shift = 8 * (4 - byte_count);
179
180 while (byte_count > 0) {
181 /* Bytes are written into the SMC addres space with the MSB first. */
182 data = (0x100 * data) + *src++;
183 byte_count--;
184 }
185
186 data <<= extra_shift;
187
188 data |= (original_data & ~((~0UL) << extra_shift));
189
190 result = polaris10_set_smc_sram_address(smumgr, addr, limit);
191
192 if (0 != result)
193 return result;
194
195 cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
196 }
197
198 return 0;
199}
200
201
202static int polaris10_program_jump_on_start(struct pp_smumgr *smumgr)
203{
204 static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
205
206 polaris10_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
207
208 return 0;
209}
210
211/**
212* Return if the SMC is currently running.
213*
214* @param smumgr the address of the powerplay hardware manager.
215*/
216bool polaris10_is_smc_ram_running(struct pp_smumgr *smumgr)
217{
218 return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
219 && (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
220}
221
222/**
223* Send a message to the SMC, and wait for its response.
224*
225* @param smumgr the address of the powerplay hardware manager.
226* @param msg the message to send.
227* @return The response that came from the SMC.
228*/
229int polaris10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
230{
231 if (!polaris10_is_smc_ram_running(smumgr))
232 return -1;
233
234 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
235
236 if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
237 printk("Failed to send Previous Message.\n");
238
239
240 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
241
242 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
243
244 if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
245 printk("Failed to send Message.\n");
246
247 return 0;
248}
249
250
251/**
252* Send a message to the SMC, and do not wait for its response.
253*
254* @param smumgr the address of the powerplay hardware manager.
255* @param msg the message to send.
256* @return Always return 0.
257*/
258int polaris10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg)
259{
260 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
261
262 return 0;
263}
264
265/**
266* Send a message to the SMC with parameter
267*
268* @param smumgr: the address of the powerplay hardware manager.
269* @param msg: the message to send.
270* @param parameter: the parameter to send
271* @return The response that came from the SMC.
272*/
273int polaris10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
274{
275 if (!polaris10_is_smc_ram_running(smumgr)) {
276 return -1;
277 }
278
279 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
280
281 cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
282
283 return polaris10_send_msg_to_smc(smumgr, msg);
284}
285
286
287/**
288* Send a message to the SMC with parameter, do not wait for response
289*
290* @param smumgr: the address of the powerplay hardware manager.
291* @param msg: the message to send.
292* @param parameter: the parameter to send
293* @return The response that came from the SMC.
294*/
295int polaris10_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
296{
297 cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
298
299 return polaris10_send_msg_to_smc_without_waiting(smumgr, msg);
300}
301
302int polaris10_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
303{
304 cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
305
306 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
307
308 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
309
310 if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
311 printk("Failed to send Message.\n");
312
313 return 0;
314}
315
316/**
317* Wait until the SMC is doing nithing. Doing nothing means that the SMC is either turned off or it is sitting on the STOP instruction.
318*
319* @param smumgr the address of the powerplay hardware manager.
320* @param msg the message to send.
321* @return The response that came from the SMC.
322*/
323int polaris10_wait_for_smc_inactive(struct pp_smumgr *smumgr)
324{
325 /* If the SMC is not even on it qualifies as inactive. */
326 if (!polaris10_is_smc_ram_running(smumgr))
327 return -1;
328
329 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
330 return 0;
331}
332
333
334/**
335* Upload the SMC firmware to the SMC microcontroller.
336*
337* @param smumgr the address of the powerplay hardware manager.
338* @param pFirmware the data structure containing the various sections of the firmware.
339*/
340static int polaris10_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit)
341{
342 uint32_t byte_count = length;
343
344 PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -1);
345
346 cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000);
347 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
348
349 for (; byte_count >= 4; byte_count -= 4)
350 cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++);
351
352 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
353
354 PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -1);
355
356 return 0;
357}
358
359static enum cgs_ucode_id polaris10_convert_fw_type_to_cgs(uint32_t fw_type)
360{
361 enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
362
363 switch (fw_type) {
364 case UCODE_ID_SMU:
365 result = CGS_UCODE_ID_SMU;
366 break;
367 case UCODE_ID_SMU_SK:
368 result = CGS_UCODE_ID_SMU_SK;
369 break;
370 case UCODE_ID_SDMA0:
371 result = CGS_UCODE_ID_SDMA0;
372 break;
373 case UCODE_ID_SDMA1:
374 result = CGS_UCODE_ID_SDMA1;
375 break;
376 case UCODE_ID_CP_CE:
377 result = CGS_UCODE_ID_CP_CE;
378 break;
379 case UCODE_ID_CP_PFP:
380 result = CGS_UCODE_ID_CP_PFP;
381 break;
382 case UCODE_ID_CP_ME:
383 result = CGS_UCODE_ID_CP_ME;
384 break;
385 case UCODE_ID_CP_MEC:
386 result = CGS_UCODE_ID_CP_MEC;
387 break;
388 case UCODE_ID_CP_MEC_JT1:
389 result = CGS_UCODE_ID_CP_MEC_JT1;
390 break;
391 case UCODE_ID_CP_MEC_JT2:
392 result = CGS_UCODE_ID_CP_MEC_JT2;
393 break;
394 case UCODE_ID_RLC_G:
395 result = CGS_UCODE_ID_RLC_G;
396 break;
397 default:
398 break;
399 }
400
401 return result;
402}
403
404static int polaris10_upload_smu_firmware_image(struct pp_smumgr *smumgr)
405{
406 int result = 0;
407 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
408
409 struct cgs_firmware_info info = {0};
410
411 if (smu_data->security_hard_key == 1)
412 cgs_get_firmware_info(smumgr->device,
413 polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
414 else
415 cgs_get_firmware_info(smumgr->device,
416 polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
417
418 /* TO DO cgs_init_samu_load_smu(smumgr->device, (uint32_t *)info.kptr, info.image_size, smu_data->post_initial_boot);*/
419 result = polaris10_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, POLARIS10_SMC_SIZE);
420
421 return result;
422}
423
424/**
425* Read a 32bit value from the SMC SRAM space.
426* ALL PARAMETERS ARE IN HOST BYTE ORDER.
427* @param smumgr the address of the powerplay hardware manager.
428* @param smcAddress the address in the SMC RAM to access.
429* @param value and output parameter for the data read from the SMC SRAM.
430*/
431int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
432{
433 int result;
434
435 result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit);
436
437 if (result)
438 return result;
439
440 *value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
441 return 0;
442}
443
444/**
445* Write a 32bit value to the SMC SRAM space.
446* ALL PARAMETERS ARE IN HOST BYTE ORDER.
447* @param smumgr the address of the powerplay hardware manager.
448* @param smc_addr the address in the SMC RAM to access.
449* @param value to write to the SMC SRAM.
450*/
451int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
452{
453 int result;
454
455 result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit);
456
457 if (result)
458 return result;
459
460 cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, value);
461
462 return 0;
463}
464
465
466int polaris10_smu_fini(struct pp_smumgr *smumgr)
467{
468 if (smumgr->backend) {
469 kfree(smumgr->backend);
470 smumgr->backend = NULL;
471 }
472 return 0;
473}
474
475/* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */
476static uint32_t polaris10_get_mask_for_firmware_type(uint32_t fw_type)
477{
478 uint32_t result = 0;
479
480 switch (fw_type) {
481 case UCODE_ID_SDMA0:
482 result = UCODE_ID_SDMA0_MASK;
483 break;
484 case UCODE_ID_SDMA1:
485 result = UCODE_ID_SDMA1_MASK;
486 break;
487 case UCODE_ID_CP_CE:
488 result = UCODE_ID_CP_CE_MASK;
489 break;
490 case UCODE_ID_CP_PFP:
491 result = UCODE_ID_CP_PFP_MASK;
492 break;
493 case UCODE_ID_CP_ME:
494 result = UCODE_ID_CP_ME_MASK;
495 break;
496 case UCODE_ID_CP_MEC_JT1:
497 case UCODE_ID_CP_MEC_JT2:
498 result = UCODE_ID_CP_MEC_MASK;
499 break;
500 case UCODE_ID_RLC_G:
501 result = UCODE_ID_RLC_G_MASK;
502 break;
503 default:
504 printk("UCode type is out of range! \n");
505 result = 0;
506 }
507
508 return result;
509}
510
511/* Populate one firmware image to the data structure */
512
513static int polaris10_populate_single_firmware_entry(struct pp_smumgr *smumgr,
514 uint32_t fw_type,
515 struct SMU_Entry *entry)
516{
517 int result = 0;
518 struct cgs_firmware_info info = {0};
519
520 result = cgs_get_firmware_info(smumgr->device,
521 polaris10_convert_fw_type_to_cgs(fw_type),
522 &info);
523
524 if (!result) {
525 entry->version = info.version;
526 entry->id = (uint16_t)fw_type;
527 entry->image_addr_high = smu_upper_32_bits(info.mc_addr);
528 entry->image_addr_low = smu_lower_32_bits(info.mc_addr);
529 entry->meta_data_addr_high = 0;
530 entry->meta_data_addr_low = 0;
531 entry->data_size_byte = info.image_size;
532 entry->num_register_entries = 0;
533 }
534
535 if (fw_type == UCODE_ID_RLC_G)
536 entry->flags = 1;
537 else
538 entry->flags = 0;
539
540 return 0;
541}
542
543static int polaris10_request_smu_load_fw(struct pp_smumgr *smumgr)
544{
545 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
546 uint32_t fw_to_load;
547
548 int result = 0;
549 struct SMU_DRAMData_TOC *toc;
550
551 if (!smumgr->reload_fw) {
552 printk(KERN_INFO "[ powerplay ] skip reloading...\n");
553 return 0;
554 }
555
556 if (smu_data->soft_regs_start)
557 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
558 smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus),
559 0x0);
560
561 polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high);
562 polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low);
563
564 toc = (struct SMU_DRAMData_TOC *)smu_data->header;
565 toc->num_entries = 0;
566 toc->structure_version = 1;
567
568 PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
569 PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
570 PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
571 PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
572 PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
573 PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
574 PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
575 PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
576 PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
577
578 polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
579 polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
580
581 fw_to_load = UCODE_ID_RLC_G_MASK
582 + UCODE_ID_SDMA0_MASK
583 + UCODE_ID_SDMA1_MASK
584 + UCODE_ID_CP_CE_MASK
585 + UCODE_ID_CP_ME_MASK
586 + UCODE_ID_CP_PFP_MASK
587 + UCODE_ID_CP_MEC_MASK;
588
589 if (polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load))
590 printk(KERN_ERR "Fail to Request SMU Load uCode");
591
592 return result;
593}
594
595/* Check if the FW has been loaded, SMU will not return if loading has not finished. */
596static int polaris10_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type)
597{
598 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
599 uint32_t fw_mask = polaris10_get_mask_for_firmware_type(fw_type);
600 uint32_t ret;
601 /* Check SOFT_REGISTERS_TABLE_28.UcodeLoadStatus */
602 ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11,
603 smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus),
604 fw_mask, fw_mask);
605
606 return ret;
607}
608
609static int polaris10_reload_firmware(struct pp_smumgr *smumgr)
610{
611 return smumgr->smumgr_funcs->start_smu(smumgr);
612}
613
614static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
615{
616 int i;
617 int result = -1;
618 uint32_t reg, data;
619
620 const PWR_Command_Table *pvirus = pwr_virus_table;
621 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
622
623
624 for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
625 switch (pvirus->command) {
626 case PwrCmdWrite:
627 reg = pvirus->reg;
628 data = pvirus->data;
629 cgs_write_register(smumgr->device, reg, data);
630 break;
631
632 case PwrCmdEnd:
633 result = 0;
634 break;
635
636 default:
637 printk("Table Exit with Invalid Command!");
638 smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
639 result = -1;
640 break;
641 }
642 pvirus++;
643 }
644
645 return result;
646}
647
648static int polaris10_perform_btc(struct pp_smumgr *smumgr)
649{
650 int result = 0;
651 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
652
653 if (0 != smu_data->avfs.avfs_btc_param) {
654 if (0 != polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
655 printk("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
656 result = -1;
657 }
658 }
659 if (smu_data->avfs.avfs_btc_param > 1) {
660 /* Soft-Reset to reset the engine before loading uCode */
661 /* halt */
662 cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000);
663 /* reset everything */
664 cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
665 cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0);
666 }
667 return result;
668}
669
670
671int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
672{
673 uint32_t vr_config;
674 uint32_t dpm_table_start;
675
676 uint16_t u16_boot_mvdd;
677 uint32_t graphics_level_address, vr_config_address, graphics_level_size;
678
679 graphics_level_size = sizeof(avfs_graphics_level_polaris10);
680 u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
681
682 PP_ASSERT_WITH_CODE(0 == polaris10_read_smc_sram_dword(smumgr,
683 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
684 &dpm_table_start, 0x40000),
685 "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
686 return -1);
687
688 /* Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
689 vr_config = 0x01000500; /* Real value:0x50001 */
690
691 vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
692
693 PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, vr_config_address,
694 (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
695 "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
696 return -1);
697
698 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
699
700 PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
701 (uint8_t *)(&avfs_graphics_level_polaris10),
702 graphics_level_size, 0x40000),
703 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
704 return -1);
705
706 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
707
708 PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
709 (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
710 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
711 return -1);
712
713 /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
714
715 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
716
717 PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
718 (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
719 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
720 return -1);
721
722 return 0;
723}
724
725int polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
726{
727 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
728
729 switch (smu_data->avfs.avfs_btc_status) {
730 case AVFS_BTC_COMPLETED_PREVIOUSLY:
731 break;
732
733 case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */
734
735 smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED;
736 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(smumgr),
737 "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
738 return -1);
739
740 if (smu_data->avfs.avfs_btc_param > 1) {
741 printk("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
742 smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
743 PP_ASSERT_WITH_CODE(-1 == polaris10_setup_pwr_virus(smumgr),
744 "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
745 return -1);
746 }
747
748 smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
749 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(smumgr),
750 "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
751 return -1);
752
753 break;
754
755 case AVFS_BTC_DISABLED:
756 case AVFS_BTC_NOTSUPPORTED:
757 break;
758
759 default:
760 printk("[AVFS] Something is broken. See log!");
761 break;
762 }
763
764 return 0;
765}
766
767static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
768{
769 int result = 0;
770
771 /* Wait for smc boot up */
772 /* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
773
774 /* Assert reset */
775 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
776 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
777
778 result = polaris10_upload_smu_firmware_image(smumgr);
779 if (result != 0)
780 return result;
781
782 /* Clear status */
783 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
784
785 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
786 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
787
788 /* De-assert reset */
789 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
790 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
791
792
793 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
794
795
796 /* Call Test SMU message with 0x20000 offset to trigger SMU start */
797 polaris10_send_msg_to_smc_offset(smumgr);
798
799 /* Wait done bit to be set */
800 /* Check pass/failed indicator */
801
802 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
803
804 if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
805 SMU_STATUS, SMU_PASS))
806 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
807
808 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
809
810 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
811 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
812
813 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
814 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
815
816 /* Wait for firmware to initialize */
817 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
818
819 return result;
820}
821
822static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
823{
824 int result = 0;
825
826 /* wait for smc boot up */
827 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
828
829 /* Clear firmware interrupt enable flag */
830 /* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
831 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
832 ixFIRMWARE_FLAGS, 0);
833
834 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
835 SMC_SYSCON_RESET_CNTL,
836 rst_reg, 1);
837
838 result = polaris10_upload_smu_firmware_image(smumgr);
839 if (result != 0)
840 return result;
841
842 /* Set smc instruct start point at 0x0 */
843 polaris10_program_jump_on_start(smumgr);
844
845 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
846 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
847
848 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
849 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
850
851 /* Wait for firmware to initialize */
852
853 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
854 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
855
856 return result;
857}
858
859static int polaris10_start_smu(struct pp_smumgr *smumgr)
860{
861 int result = 0;
862 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
863 bool SMU_VFT_INTACT;
864
865 /* Only start SMC if SMC RAM is not running */
866 if (!polaris10_is_smc_ram_running(smumgr)) {
867 SMU_VFT_INTACT = false;
868 smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
869 smu_data->security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
870
871 /* Check if SMU is running in protected mode */
872 if (smu_data->protected_mode == 0) {
873 result = polaris10_start_smu_in_non_protection_mode(smumgr);
874 } else {
875 result = polaris10_start_smu_in_protection_mode(smumgr);
876
877 /* If failed, try with different security Key. */
878 if (result != 0) {
879 smu_data->security_hard_key ^= 1;
880 result = polaris10_start_smu_in_protection_mode(smumgr);
881 }
882 }
883
884 if (result != 0)
885 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
886
887 polaris10_avfs_event_mgr(smumgr, true);
888 } else
889 SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
890
891 smu_data->post_initial_boot = true;
892 polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT);
893 /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
894 polaris10_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
895 &(smu_data->soft_regs_start), 0x40000);
896
897 result = polaris10_request_smu_load_fw(smumgr);
898
899 return result;
900}
901
902static int polaris10_smu_init(struct pp_smumgr *smumgr)
903{
904 struct polaris10_smumgr *smu_data;
905 uint8_t *internal_buf;
906 uint64_t mc_addr = 0;
907 /* Allocate memory for backend private data */
908 smu_data = (struct polaris10_smumgr *)(smumgr->backend);
909 smu_data->header_buffer.data_size =
910 ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
911 smu_data->smu_buffer.data_size = 200*4096;
912 smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED;
913/* Allocate FW image data structure and header buffer and
914 * send the header buffer address to SMU */
915 smu_allocate_memory(smumgr->device,
916 smu_data->header_buffer.data_size,
917 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
918 PAGE_SIZE,
919 &mc_addr,
920 &smu_data->header_buffer.kaddr,
921 &smu_data->header_buffer.handle);
922
923 smu_data->header = smu_data->header_buffer.kaddr;
924 smu_data->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
925 smu_data->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
926
927 PP_ASSERT_WITH_CODE((NULL != smu_data->header),
928 "Out of memory.",
929 kfree(smumgr->backend);
930 cgs_free_gpu_mem(smumgr->device,
931 (cgs_handle_t)smu_data->header_buffer.handle);
932 return -1);
933
934/* Allocate buffer for SMU internal buffer and send the address to SMU.
935 * Iceland SMU does not need internal buffer.*/
936 smu_allocate_memory(smumgr->device,
937 smu_data->smu_buffer.data_size,
938 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
939 PAGE_SIZE,
940 &mc_addr,
941 &smu_data->smu_buffer.kaddr,
942 &smu_data->smu_buffer.handle);
943
944 internal_buf = smu_data->smu_buffer.kaddr;
945 smu_data->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
946 smu_data->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
947
948 PP_ASSERT_WITH_CODE((NULL != internal_buf),
949 "Out of memory.",
950 kfree(smumgr->backend);
951 cgs_free_gpu_mem(smumgr->device,
952 (cgs_handle_t)smu_data->smu_buffer.handle);
953 return -1;);
954
955 return 0;
956}
957
958static const struct pp_smumgr_func ellsemere_smu_funcs = {
959 .smu_init = polaris10_smu_init,
960 .smu_fini = polaris10_smu_fini,
961 .start_smu = polaris10_start_smu,
962 .check_fw_load_finish = polaris10_check_fw_load_finish,
963 .request_smu_load_fw = polaris10_reload_firmware,
964 .request_smu_load_specific_fw = NULL,
965 .send_msg_to_smc = polaris10_send_msg_to_smc,
966 .send_msg_to_smc_with_parameter = polaris10_send_msg_to_smc_with_parameter,
967 .download_pptable_settings = NULL,
968 .upload_pptable_settings = NULL,
969};
970
971int polaris10_smum_init(struct pp_smumgr *smumgr)
972{
973 struct polaris10_smumgr *polaris10_smu = NULL;
974
975 polaris10_smu = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
976
977 if (polaris10_smu == NULL)
978 return -1;
979
980 smumgr->backend = polaris10_smu;
981 smumgr->smumgr_funcs = &ellsemere_smu_funcs;
982
983 return 0;
984}
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-05 12:55:29 -0400