1 files changed, 127 insertions, 101 deletions

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 1400bc420881..64ee78f7d41e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -1296,7 +1296,6 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
         }
 
         mem_level->MclkFrequency = clock;
-        mem_level->StutterEnable = 0;
         mem_level->EnabledForThrottle = 1;
         mem_level->EnabledForActivity = 0;
         mem_level->UpHyst = 0;
@@ -1304,7 +1303,6 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
         mem_level->VoltageDownHyst = 0;
         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
         mem_level->StutterEnable = false;
-
         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
 
         data->display_timing.num_existing_displays = info.display_count;
@@ -1363,7 +1361,7 @@ static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
          * a higher state by default such that we are not effected by
          * up threshold or and MCLK DPM latency.
          */
-        levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
+        levels[0].ActivityLevel = 0x1f;
         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
 
         data->smc_state_table.MemoryDpmLevelCount =
@@ -1761,12 +1759,9 @@ static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
 
 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
 {
-        uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
-                        volt_with_cks, value;
-        uint16_t clock_freq_u16;
+        uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-        uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
-                        volt_offset = 0;
+        uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
         struct phm_ppt_v1_information *table_info =
                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
@@ -1778,50 +1773,38 @@ static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
          */
         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-                        ixSMU_EFUSE_0 + (146 * 4));
-        efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-                        ixSMU_EFUSE_0 + (148 * 4));
+                        ixSMU_EFUSE_0 + (67 * 4));
         efuse &= 0xFF000000;
         efuse = efuse >> 24;
-        efuse2 &= 0xF;
-
-        if (efuse2 == 1)
-                ro = (2300 - 1350) * efuse / 255 + 1350;
-        else
-                ro = (2500 - 1000) * efuse / 255 + 1000;
 
-        if (ro >= 1660)
-                type = 0;
-        else
-                type = 1;
+        if (hwmgr->chip_id == CHIP_POLARIS10) {
+                min = 1000;
+                max = 2300;
+        } else {
+                min = 1100;
+                max = 2100;
+        }
 
-        /* Populate Stretch amount */
-        data->smc_state_table.ClockStretcherAmount = stretch_amount;
+        ro = efuse * (max -min)/255 + min;
 
         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
         for (i = 0; i < sclk_table->count; i++) {
                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
                                 sclk_table->entries[i].cks_enable << i;
-                volt_without_cks = (uint32_t)((14041 *
-                        (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
-                        (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
-                volt_with_cks = (uint32_t)((13946 *
-                        (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
-                        (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
+
+                volt_without_cks =  (uint32_t)(((ro - 40) * 1000 - 2753594 - sclk_table->entries[i].clk/100 * 136418 /1000) / \
+                                        (sclk_table->entries[i].clk/100 * 1132925 /10000 - 242418)/100);
+
+                volt_with_cks = (uint32_t)((ro * 1000 -2396351 - sclk_table->entries[i].clk/100 * 329021/1000) / \
+                                (sclk_table->entries[i].clk/10000 * 649434 /1000  - 18005)/10);
+
                 if (volt_without_cks >= volt_with_cks)
                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
                                         sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
+
                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
         }
 
-        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-                        STRETCH_ENABLE, 0x0);
-        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-                        masterReset, 0x1);
-        /* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */
-        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-                        masterReset, 0x0);
-
         /* Populate CKS Lookup Table */
         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
                 stretch_amount2 = 0;
@@ -1835,69 +1818,6 @@ static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
                                 return -EINVAL);
         }
 
-        value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-                        ixPWR_CKS_CNTL);
-        value &= 0xFFC2FF87;
-        data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
-                        polaris10_clock_stretcher_lookup_table[stretch_amount2][0];
-        data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
-                        polaris10_clock_stretcher_lookup_table[stretch_amount2][1];
-        clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
-                        GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100);
-        if (polaris10_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16
-        && polaris10_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) {
-                /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
-                value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
-                /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
-                value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
-                /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
-                value |= (polaris10_clock_stretch_amount_conversion
-                                [polaris10_clock_stretcher_lookup_table[stretch_amount2][3]]
-                                 [stretch_amount]) << 3;
-        }
-        CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq);
-        CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq);
-        data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
-                        polaris10_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
-        data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
-                        (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
-
-        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-                        ixPWR_CKS_CNTL, value);
-
-        /* Populate DDT Lookup Table */
-        for (i = 0; i < 4; i++) {
-                /* Assign the minimum and maximum VID stored
-                 * in the last row of Clock Stretcher Voltage Table.
-                 */
-                data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID =
-                                (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][2];
-                data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID =
-                                (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][3];
-                /* Loop through each SCLK and check the frequency
-                 * to see if it lies within the frequency for clock stretcher.
-                 */
-                for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
-                        cks_setting = 0;
-                        clock_freq = PP_SMC_TO_HOST_UL(
-                                        data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency);
-                        /* Check the allowed frequency against the sclk level[j].
-                         *  Sclk's endianness has already been converted,
-                         *  and it's in 10Khz unit,
-                         *  as opposed to Data table, which is in Mhz unit.
-                         */
-                        if (clock_freq >= (polaris10_clock_stretcher_ddt_table[type][i][0]) * 100) {
-                                cks_setting |= 0x2;
-                                if (clock_freq < (polaris10_clock_stretcher_ddt_table[type][i][1]) * 100)
-                                        cks_setting |= 0x1;
-                        }
-                        data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting
-                                                        |= cks_setting << (j * 2);
-                }
-                CONVERT_FROM_HOST_TO_SMC_US(
-                        data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting);
-        }
-
         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
         value &= 0xFFFFFFFE;
         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
@@ -1956,6 +1876,90 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
         return 0;
 }
 
+
+int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
+{
+        struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+        SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
+        int result = 0;
+        struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
+        AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
+        AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
+        uint32_t tmp, i;
+        struct pp_smumgr *smumgr = hwmgr->smumgr;
+        struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
+
+        struct phm_ppt_v1_information *table_info =
+                        (struct phm_ppt_v1_information *)hwmgr->pptable;
+        struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
+                        table_info->vdd_dep_on_sclk;
+
+
+        if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+                return result;
+
+        result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
+
+        if (0 == result) {
+                table->BTCGB_VDROOP_TABLE[0].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
+                table->BTCGB_VDROOP_TABLE[0].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
+                table->BTCGB_VDROOP_TABLE[0].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
+                table->BTCGB_VDROOP_TABLE[1].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
+                table->BTCGB_VDROOP_TABLE[1].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
+                table->BTCGB_VDROOP_TABLE[1].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
+                table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
+                table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
+                table->AVFSGB_VDROOP_TABLE[0].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
+                table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
+                table->AVFSGB_VDROOP_TABLE[0].m2_shift  = 12;
+                table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
+                table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
+                table->AVFSGB_VDROOP_TABLE[1].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
+                table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
+                table->AVFSGB_VDROOP_TABLE[1].m2_shift  = 12;
+                table->MaxVoltage                = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
+                AVFS_meanNsigma.Aconstant[0]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
+                AVFS_meanNsigma.Aconstant[1]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
+                AVFS_meanNsigma.Aconstant[2]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
+                AVFS_meanNsigma.DC_tol_sigma      = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
+                AVFS_meanNsigma.Platform_mean     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
+                AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
+                AVFS_meanNsigma.Platform_sigma     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
+
+                for (i = 0; i < NUM_VFT_COLUMNS; i++) {
+                        AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
+                        AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
+                }
+
+                result = polaris10_read_smc_sram_dword(smumgr,
+                                SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
+                                &tmp, data->sram_end);
+
+                polaris10_copy_bytes_to_smc(smumgr,
+                                        tmp,
+                                        (uint8_t *)&AVFS_meanNsigma,
+                                        sizeof(AVFS_meanNsigma_t),
+                                        data->sram_end);
+
+                result = polaris10_read_smc_sram_dword(smumgr,
+                                SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
+                                &tmp, data->sram_end);
+                polaris10_copy_bytes_to_smc(smumgr,
+                                        tmp,
+                                        (uint8_t *)&AVFS_SclkOffset,
+                                        sizeof(AVFS_Sclk_Offset_t),
+                                        data->sram_end);
+
+                data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
+                                                (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
+                                                (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
+                                                (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
+                data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
+        }
+        return result;
+}
+
+
 /**
 * Initializes the SMC table and uploads it
 *
@@ -2056,6 +2060,10 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
                                 "Failed to populate Clock Stretcher Data Table!",
                                 return result);
         }
+
+        result = polaris10_populate_avfs_parameters(hwmgr);
+        PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
+
         table->CurrSclkPllRange = 0xff;
         table->GraphicsVoltageChangeEnable  = 1;
         table->GraphicsThermThrottleEnable  = 1;
@@ -2252,6 +2260,9 @@ static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
 {
         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+        uint32_t soft_register_value = 0;
+        uint32_t handshake_disables_offset = data->soft_regs_start
+                                + offsetof(SMU74_SoftRegisters, HandshakeDisables);
 
         /* enable SCLK dpm */
         if (!data->sclk_dpm_key_disabled)
@@ -2262,6 +2273,12 @@ static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
 
         /* enable MCLK dpm */
         if (0 == data->mclk_dpm_key_disabled) {
+/* Disable UVD - SMU handshake for MCLK. */
+                soft_register_value = cgs_read_ind_register(hwmgr->device,
+                                        CGS_IND_REG__SMC, handshake_disables_offset);
+                soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
+                cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+                                handshake_disables_offset, soft_register_value);
 
                 PP_ASSERT_WITH_CODE(
                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
@@ -2269,7 +2286,6 @@ static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
                                 "Failed to enable MCLK DPM during DPM Start Function!",
                                 return -1);
 
-
                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
 
                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
@@ -2606,6 +2622,7 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 
         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
+
         if (hwmgr->chip_id == CHIP_POLARIS11)
                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                                         PHM_PlatformCaps_SPLLShutdownSupport);
@@ -2938,6 +2955,11 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
 
+        data->enable_tdc_limit_feature = true;
+        data->enable_pkg_pwr_tracking_feature = true;
+        data->force_pcie_gen = PP_PCIEGenInvalid;
+        data->mclk_stutter_mode_threshold = 40000;
+
         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
                 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
@@ -2962,6 +2984,10 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
         }
 
+        if (table_info->cac_dtp_table->usClockStretchAmount != 0)
+                phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                                        PHM_PlatformCaps_ClockStretcher);
+
         polaris10_set_features_platform_caps(hwmgr);
 
         polaris10_init_dpm_defaults(hwmgr);