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path: root/drivers/clk/tegra/clk-tegra114.c
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Diffstat (limited to 'drivers/clk/tegra/clk-tegra114.c')
-rw-r--r--drivers/clk/tegra/clk-tegra114.c36
1 files changed, 24 insertions, 12 deletions
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 2d3b3dc5c1ec..be40856a6fa4 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1558,7 +1558,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1558 1558
1559 /* audio0 */ 1559 /* audio0 */
1560 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1560 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1561 ARRAY_SIZE(mux_audio_sync_clk), 0, 1561 ARRAY_SIZE(mux_audio_sync_clk),
1562 CLK_SET_RATE_NO_REPARENT,
1562 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, 1563 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0,
1563 NULL); 1564 NULL);
1564 clks[audio0_mux] = clk; 1565 clks[audio0_mux] = clk;
@@ -1570,7 +1571,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1570 1571
1571 /* audio1 */ 1572 /* audio1 */
1572 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1573 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1573 ARRAY_SIZE(mux_audio_sync_clk), 0, 1574 ARRAY_SIZE(mux_audio_sync_clk),
1575 CLK_SET_RATE_NO_REPARENT,
1574 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, 1576 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0,
1575 NULL); 1577 NULL);
1576 clks[audio1_mux] = clk; 1578 clks[audio1_mux] = clk;
@@ -1582,7 +1584,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1582 1584
1583 /* audio2 */ 1585 /* audio2 */
1584 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1586 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1585 ARRAY_SIZE(mux_audio_sync_clk), 0, 1587 ARRAY_SIZE(mux_audio_sync_clk),
1588 CLK_SET_RATE_NO_REPARENT,
1586 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, 1589 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0,
1587 NULL); 1590 NULL);
1588 clks[audio2_mux] = clk; 1591 clks[audio2_mux] = clk;
@@ -1594,7 +1597,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1594 1597
1595 /* audio3 */ 1598 /* audio3 */
1596 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1599 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1597 ARRAY_SIZE(mux_audio_sync_clk), 0, 1600 ARRAY_SIZE(mux_audio_sync_clk),
1601 CLK_SET_RATE_NO_REPARENT,
1598 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, 1602 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0,
1599 NULL); 1603 NULL);
1600 clks[audio3_mux] = clk; 1604 clks[audio3_mux] = clk;
@@ -1606,7 +1610,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1606 1610
1607 /* audio4 */ 1611 /* audio4 */
1608 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1612 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1609 ARRAY_SIZE(mux_audio_sync_clk), 0, 1613 ARRAY_SIZE(mux_audio_sync_clk),
1614 CLK_SET_RATE_NO_REPARENT,
1610 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, 1615 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0,
1611 NULL); 1616 NULL);
1612 clks[audio4_mux] = clk; 1617 clks[audio4_mux] = clk;
@@ -1618,7 +1623,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1618 1623
1619 /* spdif */ 1624 /* spdif */
1620 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1625 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1621 ARRAY_SIZE(mux_audio_sync_clk), 0, 1626 ARRAY_SIZE(mux_audio_sync_clk),
1627 CLK_SET_RATE_NO_REPARENT,
1622 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, 1628 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0,
1623 NULL); 1629 NULL);
1624 clks[spdif_mux] = clk; 1630 clks[spdif_mux] = clk;
@@ -1713,7 +1719,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1713 1719
1714 /* clk_out_1 */ 1720 /* clk_out_1 */
1715 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1721 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1716 ARRAY_SIZE(clk_out1_parents), 0, 1722 ARRAY_SIZE(clk_out1_parents),
1723 CLK_SET_RATE_NO_REPARENT,
1717 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1724 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1718 &clk_out_lock); 1725 &clk_out_lock);
1719 clks[clk_out_1_mux] = clk; 1726 clks[clk_out_1_mux] = clk;
@@ -1725,7 +1732,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1725 1732
1726 /* clk_out_2 */ 1733 /* clk_out_2 */
1727 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1734 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1728 ARRAY_SIZE(clk_out2_parents), 0, 1735 ARRAY_SIZE(clk_out2_parents),
1736 CLK_SET_RATE_NO_REPARENT,
1729 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1737 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1730 &clk_out_lock); 1738 &clk_out_lock);
1731 clks[clk_out_2_mux] = clk; 1739 clks[clk_out_2_mux] = clk;
@@ -1737,7 +1745,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1737 1745
1738 /* clk_out_3 */ 1746 /* clk_out_3 */
1739 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1747 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1740 ARRAY_SIZE(clk_out3_parents), 0, 1748 ARRAY_SIZE(clk_out3_parents),
1749 CLK_SET_RATE_NO_REPARENT,
1741 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1750 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1742 &clk_out_lock); 1751 &clk_out_lock);
1743 clks[clk_out_3_mux] = clk; 1752 clks[clk_out_3_mux] = clk;
@@ -2055,7 +2064,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2055 2064
2056 /* dsia */ 2065 /* dsia */
2057 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 2066 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
2058 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 2067 ARRAY_SIZE(mux_plld_out0_plld2_out0),
2068 CLK_SET_RATE_NO_REPARENT,
2059 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 2069 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
2060 clks[dsia_mux] = clk; 2070 clks[dsia_mux] = clk;
2061 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, 2071 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
@@ -2065,7 +2075,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2065 2075
2066 /* dsib */ 2076 /* dsib */
2067 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 2077 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
2068 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 2078 ARRAY_SIZE(mux_plld_out0_plld2_out0),
2079 CLK_SET_RATE_NO_REPARENT,
2069 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 2080 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
2070 clks[dsib_mux] = clk; 2081 clks[dsib_mux] = clk;
2071 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, 2082 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
@@ -2102,7 +2113,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2102 2113
2103 /* emc */ 2114 /* emc */
2104 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 2115 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
2105 ARRAY_SIZE(mux_pllmcp_clkm), 0, 2116 ARRAY_SIZE(mux_pllmcp_clkm),
2117 CLK_SET_RATE_NO_REPARENT,
2106 clk_base + CLK_SOURCE_EMC, 2118 clk_base + CLK_SOURCE_EMC,
2107 29, 3, 0, NULL); 2119 29, 3, 0, NULL);
2108 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 2120 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 01:58:26 -0400