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-rw-r--r--arch/powerpc/Makefile18
-rw-r--r--arch/powerpc/boot/dts/b4420qds.dts2
-rw-r--r--arch/powerpc/boot/dts/b4860qds.dts2
-rw-r--r--arch/powerpc/boot/dts/b4qds.dtsi (renamed from arch/powerpc/boot/dts/b4qds.dts)0
-rw-r--r--arch/powerpc/boot/dts/fsl/b4si-post.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi149
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-post.dtsi2
-rw-r--r--arch/powerpc/boot/dts/p1020rdb-pd.dts280
-rw-r--r--arch/powerpc/configs/85xx/p1023rds_defconfig1
-rw-r--r--arch/powerpc/configs/corenet32_smp_defconfig1
-rw-r--r--arch/powerpc/configs/corenet64_smp_defconfig1
-rw-r--r--arch/powerpc/configs/mpc83xx_defconfig1
-rw-r--r--arch/powerpc/configs/mpc85xx_defconfig1
-rw-r--r--arch/powerpc/configs/mpc85xx_smp_defconfig1
-rw-r--r--arch/powerpc/include/asm/epapr_hcalls.h6
-rw-r--r--arch/powerpc/include/asm/mpic.h7
-rw-r--r--arch/powerpc/include/asm/perf_event_fsl_emb.h2
-rw-r--r--arch/powerpc/include/asm/ppc-opcode.h47
-rw-r--r--arch/powerpc/include/asm/reg_fsl_emb.h24
-rw-r--r--arch/powerpc/kernel/cpu_setup_fsl_booke.S2
-rw-r--r--arch/powerpc/kernel/cputable.c2
-rw-r--r--arch/powerpc/kernel/epapr_paravirt.c28
-rw-r--r--arch/powerpc/kernel/setup_32.c4
-rw-r--r--arch/powerpc/kernel/setup_64.c3
-rw-r--r--arch/powerpc/kernel/swsusp_booke.S8
-rw-r--r--arch/powerpc/kernel/traps.c3
-rw-r--r--arch/powerpc/kvm/emulate.c45
-rw-r--r--arch/powerpc/oprofile/op_model_fsl_emb.c30
-rw-r--r--arch/powerpc/perf/Makefile2
-rw-r--r--arch/powerpc/perf/core-fsl-emb.c30
-rw-r--r--arch/powerpc/perf/e6500-pmu.c121
-rw-r--r--arch/powerpc/platforms/85xx/corenet_ds.c6
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_rdb.c22
-rw-r--r--arch/powerpc/sysdev/fsl_msi.c137
-rw-r--r--arch/powerpc/sysdev/fsl_msi.h10
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c184
-rw-r--r--arch/powerpc/sysdev/fsl_pci.h6
37 files changed, 1047 insertions, 143 deletions
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index 967fd23ace78..23c1b7972d2e 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -98,7 +98,7 @@ CFLAGS-$(CONFIG_POWER7_CPU) += $(call cc-option,-mcpu=power7)
98CFLAGS-$(CONFIG_TUNE_CELL) += $(call cc-option,-mtune=cell) 98CFLAGS-$(CONFIG_TUNE_CELL) += $(call cc-option,-mtune=cell)
99 99
100KBUILD_CPPFLAGS += -Iarch/$(ARCH) 100KBUILD_CPPFLAGS += -Iarch/$(ARCH)
101KBUILD_AFLAGS += -Iarch/$(ARCH) 101KBUILD_AFLAGS += -msoft-float -Iarch/$(ARCH)
102KBUILD_CFLAGS += -msoft-float -pipe -Iarch/$(ARCH) $(CFLAGS-y) 102KBUILD_CFLAGS += -msoft-float -pipe -Iarch/$(ARCH) $(CFLAGS-y)
103CPP = $(CC) -E $(KBUILD_CFLAGS) 103CPP = $(CC) -E $(KBUILD_CFLAGS)
104 104
@@ -132,6 +132,21 @@ ifeq ($(CONFIG_6xx),y)
132KBUILD_CFLAGS += -mcpu=powerpc 132KBUILD_CFLAGS += -mcpu=powerpc
133endif 133endif
134 134
135ifeq ($(CONFIG_E500),y)
136ifeq ($(CONFIG_64BIT),y)
137KBUILD_CFLAGS += -mcpu=e5500
138KBUILD_AFLAGS += -mcpu=e5500
139else
140ifeq ($(CONFIG_PPC_E500MC),y)
141KBUILD_CFLAGS += -mcpu=e500mc
142KBUILD_AFLAGS += -mcpu=e500mc
143else
144KBUILD_CFLAGS += -mcpu=8540
145KBUILD_AFLAGS += -mcpu=8540
146endif
147endif
148endif
149
135# Work around a gcc code-gen bug with -fno-omit-frame-pointer. 150# Work around a gcc code-gen bug with -fno-omit-frame-pointer.
136ifeq ($(CONFIG_FUNCTION_TRACER),y) 151ifeq ($(CONFIG_FUNCTION_TRACER),y)
137KBUILD_CFLAGS += -mno-sched-epilog 152KBUILD_CFLAGS += -mno-sched-epilog
@@ -139,7 +154,6 @@ endif
139 154
140cpu-as-$(CONFIG_4xx) += -Wa,-m405 155cpu-as-$(CONFIG_4xx) += -Wa,-m405
141cpu-as-$(CONFIG_ALTIVEC) += -Wa,-maltivec 156cpu-as-$(CONFIG_ALTIVEC) += -Wa,-maltivec
142cpu-as-$(CONFIG_E500) += -Wa,-me500
143cpu-as-$(CONFIG_E200) += -Wa,-me200 157cpu-as-$(CONFIG_E200) += -Wa,-me200
144 158
145KBUILD_AFLAGS += $(cpu-as-y) 159KBUILD_AFLAGS += $(cpu-as-y)
diff --git a/arch/powerpc/boot/dts/b4420qds.dts b/arch/powerpc/boot/dts/b4420qds.dts
index 923156d03b30..508dbdf33c81 100644
--- a/arch/powerpc/boot/dts/b4420qds.dts
+++ b/arch/powerpc/boot/dts/b4420qds.dts
@@ -33,7 +33,7 @@
33 */ 33 */
34 34
35/include/ "fsl/b4420si-pre.dtsi" 35/include/ "fsl/b4420si-pre.dtsi"
36/include/ "b4qds.dts" 36/include/ "b4qds.dtsi"
37 37
38/ { 38/ {
39 model = "fsl,B4420QDS"; 39 model = "fsl,B4420QDS";
diff --git a/arch/powerpc/boot/dts/b4860qds.dts b/arch/powerpc/boot/dts/b4860qds.dts
index 78907f38bb77..6bb3707ffe3d 100644
--- a/arch/powerpc/boot/dts/b4860qds.dts
+++ b/arch/powerpc/boot/dts/b4860qds.dts
@@ -33,7 +33,7 @@
33 */ 33 */
34 34
35/include/ "fsl/b4860si-pre.dtsi" 35/include/ "fsl/b4860si-pre.dtsi"
36/include/ "b4qds.dts" 36/include/ "b4qds.dtsi"
37 37
38/ { 38/ {
39 model = "fsl,B4860QDS"; 39 model = "fsl,B4860QDS";
diff --git a/arch/powerpc/boot/dts/b4qds.dts b/arch/powerpc/boot/dts/b4qds.dtsi
index e6d2f8f90544..e6d2f8f90544 100644
--- a/arch/powerpc/boot/dts/b4qds.dts
+++ b/arch/powerpc/boot/dts/b4qds.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 73991547c69b..4c617bf8cdb2 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -204,7 +204,7 @@
204 }; 204 };
205 }; 205 };
206 206
207/include/ "qoriq-mpic.dtsi" 207/include/ "qoriq-mpic4.3.dtsi"
208 208
209 guts: global-utilities@e0000 { 209 guts: global-utilities@e0000 {
210 compatible = "fsl,b4-device-config"; 210 compatible = "fsl,b4-device-config";
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
new file mode 100644
index 000000000000..64f713c24825
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
@@ -0,0 +1,149 @@
1/*
2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35mpic: pic@40000 {
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
39 reg = <0x40000 0x40000>;
40 compatible = "fsl,mpic";
41 device_type = "open-pic";
42 clock-frequency = <0x0>;
43};
44
45timer@41100 {
46 compatible = "fsl,mpic-global-timer";
47 reg = <0x41100 0x100 0x41300 4>;
48 interrupts = <0 0 3 0
49 1 0 3 0
50 2 0 3 0
51 3 0 3 0>;
52};
53
54msi0: msi@41600 {
55 compatible = "fsl,mpic-msi-v4.3";
56 reg = <0x41600 0x200 0x44148 4>;
57 interrupts = <
58 0xe0 0 0 0
59 0xe1 0 0 0
60 0xe2 0 0 0
61 0xe3 0 0 0
62 0xe4 0 0 0
63 0xe5 0 0 0
64 0xe6 0 0 0
65 0xe7 0 0 0
66 0x100 0 0 0
67 0x101 0 0 0
68 0x102 0 0 0
69 0x103 0 0 0
70 0x104 0 0 0
71 0x105 0 0 0
72 0x106 0 0 0
73 0x107 0 0 0>;
74};
75
76msi1: msi@41800 {
77 compatible = "fsl,mpic-msi-v4.3";
78 reg = <0x41800 0x200 0x45148 4>;
79 interrupts = <
80 0xe8 0 0 0
81 0xe9 0 0 0
82 0xea 0 0 0
83 0xeb 0 0 0
84 0xec 0 0 0
85 0xed 0 0 0
86 0xee 0 0 0
87 0xef 0 0 0
88 0x108 0 0 0
89 0x109 0 0 0
90 0x10a 0 0 0
91 0x10b 0 0 0
92 0x10c 0 0 0
93 0x10d 0 0 0
94 0x10e 0 0 0
95 0x10f 0 0 0>;
96};
97
98msi2: msi@41a00 {
99 compatible = "fsl,mpic-msi-v4.3";
100 reg = <0x41a00 0x200 0x46148 4>;
101 interrupts = <
102 0xf0 0 0 0
103 0xf1 0 0 0
104 0xf2 0 0 0
105 0xf3 0 0 0
106 0xf4 0 0 0
107 0xf5 0 0 0
108 0xf6 0 0 0
109 0xf7 0 0 0
110 0x110 0 0 0
111 0x111 0 0 0
112 0x112 0 0 0
113 0x113 0 0 0
114 0x114 0 0 0
115 0x115 0 0 0
116 0x116 0 0 0
117 0x117 0 0 0>;
118};
119
120msi3: msi@41c00 {
121 compatible = "fsl,mpic-msi-v4.3";
122 reg = <0x41c00 0x200 0x47148 4>;
123 interrupts = <
124 0xf8 0 0 0
125 0xf9 0 0 0
126 0xfa 0 0 0
127 0xfb 0 0 0
128 0xfc 0 0 0
129 0xfd 0 0 0
130 0xfe 0 0 0
131 0xff 0 0 0
132 0x118 0 0 0
133 0x119 0 0 0
134 0x11a 0 0 0
135 0x11b 0 0 0
136 0x11c 0 0 0
137 0x11d 0 0 0
138 0x11e 0 0 0
139 0x11f 0 0 0>;
140};
141
142timer@42100 {
143 compatible = "fsl,mpic-global-timer";
144 reg = <0x42100 0x100 0x42300 4>;
145 interrupts = <4 0 3 0
146 5 0 3 0
147 6 0 3 0
148 7 0 3 0>;
149};
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index bd611a9cad32..510afa362de1 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -358,7 +358,7 @@
358 16 2 1 30>; 358 16 2 1 30>;
359 }; 359 };
360 360
361/include/ "qoriq-mpic.dtsi" 361/include/ "qoriq-mpic4.3.dtsi"
362 362
363 guts: global-utilities@e0000 { 363 guts: global-utilities@e0000 {
364 compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0"; 364 compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
diff --git a/arch/powerpc/boot/dts/p1020rdb-pd.dts b/arch/powerpc/boot/dts/p1020rdb-pd.dts
new file mode 100644
index 000000000000..987017ea36b6
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pd.dts
@@ -0,0 +1,280 @@
1/*
2 * P1020 RDB-PD Device Tree Source (32-bit address map)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1020si-pre.dtsi"
36/ {
37 model = "fsl,P1020RDB-PD";
38 compatible = "fsl,P1020RDB-PD";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@ffe05000 {
45 reg = <0x0 0xffe05000 0x0 0x1000>;
46
47 /* NOR, NAND flash, L2 switch and CPLD */
48 ranges = <0x0 0x0 0x0 0xec000000 0x04000000
49 0x1 0x0 0x0 0xff800000 0x00040000
50 0x2 0x0 0x0 0xffa00000 0x00020000
51 0x3 0x0 0x0 0xffb00000 0x00020000>;
52
53 nor@0,0 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 compatible = "cfi-flash";
57 reg = <0x0 0x0 0x4000000>;
58 bank-width = <2>;
59 device-width = <1>;
60
61 partition@0 {
62 /* 128KB for DTB Image */
63 reg = <0x0 0x00020000>;
64 label = "NOR DTB Image";
65 };
66
67 partition@20000 {
68 /* 3.875 MB for Linux Kernel Image */
69 reg = <0x00020000 0x003e0000>;
70 label = "NOR Linux Kernel Image";
71 };
72
73 partition@400000 {
74 /* 58MB for Root file System */
75 reg = <0x00400000 0x03a00000>;
76 label = "NOR Root File System";
77 };
78
79 partition@3e00000 {
80 /* This location must not be altered */
81 /* 1M for Vitesse 7385 Switch firmware */
82 reg = <0x3e00000 0x00100000>;
83 label = "NOR Vitesse-7385 Firmware";
84 read-only;
85 };
86
87 partition@3f00000 {
88 /* This location must not be altered */
89 /* 512KB for u-boot Bootloader Image */
90 /* 512KB for u-boot Environment Variables */
91 reg = <0x03f00000 0x00100000>;
92 label = "NOR U-Boot Image";
93 read-only;
94 };
95 };
96
97 nand@1,0 {
98 #address-cells = <1>;
99 #size-cells = <1>;
100 compatible = "fsl,p1020-fcm-nand",
101 "fsl,elbc-fcm-nand";
102 reg = <0x1 0x0 0x40000>;
103
104 partition@0 {
105 /* This location must not be altered */
106 /* 1MB for u-boot Bootloader Image */
107 reg = <0x0 0x00100000>;
108 label = "NAND U-Boot Image";
109 read-only;
110 };
111
112 partition@100000 {
113 /* 1MB for DTB Image */
114 reg = <0x00100000 0x00100000>;
115 label = "NAND DTB Image";
116 };
117
118 partition@200000 {
119 /* 4MB for Linux Kernel Image */
120 reg = <0x00200000 0x00400000>;
121 label = "NAND Linux Kernel Image";
122 };
123
124 partition@600000 {
125 /* 122MB for File System Image */
126 reg = <0x00600000 0x07a00000>;
127 label = "NAND File System Image";
128 };
129 };
130
131 cpld@2,0 {
132 compatible = "fsl,p1020rdb-pd-cpld";
133 reg = <0x2 0x0 0x20000>;
134 };
135
136 L2switch@3,0 {
137 #address-cells = <1>;
138 #size-cells = <1>;
139 compatible = "vitesse-7385";
140 reg = <0x3 0x0 0x20000>;
141 };
142 };
143
144 soc: soc@ffe00000 {
145 ranges = <0x0 0x0 0xffe00000 0x100000>;
146
147 i2c@3000 {
148 rtc@68 {
149 compatible = "dallas,ds1339";
150 reg = <0x68>;
151 };
152 };
153
154 spi@7000 {
155 flash@0 {
156 #address-cells = <1>;
157 #size-cells = <1>;
158 compatible = "spansion,s25sl12801";
159 reg = <0>;
160 /* input clock */
161 spi-max-frequency = <40000000>;
162
163 partition@0 {
164 /* 512KB for u-boot Bootloader Image */
165 reg = <0x0 0x00080000>;
166 label = "SPI U-Boot Image";
167 read-only;
168 };
169
170 partition@80000 {
171 /* 512KB for DTB Image*/
172 reg = <0x00080000 0x00080000>;
173 label = "SPI DTB Image";
174 };
175
176 partition@100000 {
177 /* 4MB for Linux Kernel Image */
178 reg = <0x00100000 0x00400000>;
179 label = "SPI Linux Kernel Image";
180 };
181
182 partition@500000 {
183 /* 11MB for FS System Image */
184 reg = <0x00500000 0x00b00000>;
185 label = "SPI File System Image";
186 };
187 };
188
189 slic@0 {
190 compatible = "zarlink,le88266";
191 reg = <1>;
192 spi-max-frequency = <8000000>;
193 };
194
195 slic@1 {
196 compatible = "zarlink,le88266";
197 reg = <2>;
198 spi-max-frequency = <8000000>;
199 };
200 };
201
202 mdio@24000 {
203 phy0: ethernet-phy@0 {
204 interrupts = <3 1 0 0>;
205 reg = <0x0>;
206 };
207
208 phy1: ethernet-phy@1 {
209 interrupts = <2 1 0 0>;
210 reg = <0x1>;
211 };
212 };
213
214 mdio@25000 {
215 tbi1: tbi-phy@11 {
216 reg = <0x11>;
217 device_type = "tbi-phy";
218 };
219 };
220
221 mdio@26000 {
222 tbi2: tbi-phy@11 {
223 reg = <0x11>;
224 device_type = "tbi-phy";
225 };
226 };
227
228 enet0: ethernet@b0000 {
229 fixed-link = <1 1 1000 0 0>;
230 phy-connection-type = "rgmii-id";
231 };
232
233 enet1: ethernet@b1000 {
234 phy-handle = <&phy0>;
235 tbi-handle = <&tbi1>;
236 phy-connection-type = "sgmii";
237 };
238
239 enet2: ethernet@b2000 {
240 phy-handle = <&phy1>;
241 phy-connection-type = "rgmii-id";
242 };
243
244 usb@22000 {
245 phy_type = "ulpi";
246 };
247 };
248
249 pci0: pcie@ffe09000 {
250 reg = <0x0 0xffe09000 0x0 0x1000>;
251 ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000
252 0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
253 pcie@0 {
254 ranges = <0x2000000 0x0 0xa0000000
255 0x2000000 0x0 0xa0000000
256 0x0 0x20000000
257
258 0x1000000 0x0 0x0
259 0x1000000 0x0 0x0
260 0x0 0x100000>;
261 };
262 };
263
264 pci1: pcie@ffe0a000 {
265 reg = <0x0 0xffe0a000 0x0 0x1000>;
266 ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
267 0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
268 pcie@0 {
269 ranges = <0x2000000 0x0 0x80000000
270 0x2000000 0x0 0x80000000
271 0x0 0x20000000
272
273 0x1000000 0x0 0x0
274 0x1000000 0x0 0x0
275 0x0 0x100000>;
276 };
277 };
278};
279
280/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/configs/85xx/p1023rds_defconfig b/arch/powerpc/configs/85xx/p1023rds_defconfig
index b80bcc69d1f7..18badca726c6 100644
--- a/arch/powerpc/configs/85xx/p1023rds_defconfig
+++ b/arch/powerpc/configs/85xx/p1023rds_defconfig
@@ -63,6 +63,7 @@ CONFIG_IPV6=y
63CONFIG_IP_SCTP=m 63CONFIG_IP_SCTP=m
64CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 64CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
65CONFIG_DEVTMPFS=y 65CONFIG_DEVTMPFS=y
66CONFIG_DEVTMPFS_MOUNT=y
66CONFIG_PROC_DEVICETREE=y 67CONFIG_PROC_DEVICETREE=y
67CONFIG_BLK_DEV_LOOP=y 68CONFIG_BLK_DEV_LOOP=y
68CONFIG_BLK_DEV_RAM=y 69CONFIG_BLK_DEV_RAM=y
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index 60027c2a7034..3dfab4c40c76 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -70,6 +70,7 @@ CONFIG_IPV6=y
70CONFIG_IP_SCTP=m 70CONFIG_IP_SCTP=m
71CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 71CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
72CONFIG_DEVTMPFS=y 72CONFIG_DEVTMPFS=y
73CONFIG_DEVTMPFS_MOUNT=y
73CONFIG_MTD=y 74CONFIG_MTD=y
74CONFIG_MTD_CMDLINE_PARTS=y 75CONFIG_MTD_CMDLINE_PARTS=y
75CONFIG_MTD_CHAR=y 76CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 6c8b020806ff..4b76e3545965 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -59,6 +59,7 @@ CONFIG_IPV6=y
59CONFIG_IP_SCTP=m 59CONFIG_IP_SCTP=m
60CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 60CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
61CONFIG_DEVTMPFS=y 61CONFIG_DEVTMPFS=y
62CONFIG_DEVTMPFS_MOUNT=y
62CONFIG_MTD=y 63CONFIG_MTD=y
63CONFIG_MTD_PARTITIONS=y 64CONFIG_MTD_PARTITIONS=y
64CONFIG_MTD_OF_PARTS=y 65CONFIG_MTD_OF_PARTS=y
diff --git a/arch/powerpc/configs/mpc83xx_defconfig b/arch/powerpc/configs/mpc83xx_defconfig
index 09116c6a6719..23fec79964cf 100644
--- a/arch/powerpc/configs/mpc83xx_defconfig
+++ b/arch/powerpc/configs/mpc83xx_defconfig
@@ -42,6 +42,7 @@ CONFIG_INET_ESP=y
42# CONFIG_IPV6 is not set 42# CONFIG_IPV6 is not set
43CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 43CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
44CONFIG_DEVTMPFS=y 44CONFIG_DEVTMPFS=y
45CONFIG_DEVTMPFS_MOUNT=y
45# CONFIG_FW_LOADER is not set 46# CONFIG_FW_LOADER is not set
46CONFIG_MTD=y 47CONFIG_MTD=y
47CONFIG_MTD_CHAR=y 48CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 5a58882e351e..b90c7af2ca1e 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -78,6 +78,7 @@ CONFIG_IPV6=y
78CONFIG_IP_SCTP=m 78CONFIG_IP_SCTP=m
79CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 79CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
80CONFIG_DEVTMPFS=y 80CONFIG_DEVTMPFS=y
81CONFIG_DEVTMPFS_MOUNT=y
81CONFIG_MTD=y 82CONFIG_MTD=y
82CONFIG_MTD_PARTITIONS=y 83CONFIG_MTD_PARTITIONS=y
83CONFIG_MTD_OF_PARTS=y 84CONFIG_MTD_OF_PARTS=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 152fa05b15e4..9ced85188534 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -81,6 +81,7 @@ CONFIG_IPV6=y
81CONFIG_IP_SCTP=m 81CONFIG_IP_SCTP=m
82CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 82CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
83CONFIG_DEVTMPFS=y 83CONFIG_DEVTMPFS=y
84CONFIG_DEVTMPFS_MOUNT=y
84CONFIG_MTD=y 85CONFIG_MTD=y
85CONFIG_MTD_PARTITIONS=y 86CONFIG_MTD_PARTITIONS=y
86CONFIG_MTD_OF_PARTS=y 87CONFIG_MTD_OF_PARTS=y
diff --git a/arch/powerpc/include/asm/epapr_hcalls.h b/arch/powerpc/include/asm/epapr_hcalls.h
index d3d634274d2c..86b0ac79990c 100644
--- a/arch/powerpc/include/asm/epapr_hcalls.h
+++ b/arch/powerpc/include/asm/epapr_hcalls.h
@@ -105,6 +105,12 @@
105extern bool epapr_paravirt_enabled; 105extern bool epapr_paravirt_enabled;
106extern u32 epapr_hypercall_start[]; 106extern u32 epapr_hypercall_start[];
107 107
108#ifdef CONFIG_EPAPR_PARAVIRT
109int __init epapr_paravirt_early_init(void);
110#else
111static inline int epapr_paravirt_early_init(void) { return 0; }
112#endif
113
108/* 114/*
109 * We use "uintptr_t" to define a register because it's guaranteed to be a 115 * We use "uintptr_t" to define a register because it's guaranteed to be a
110 * 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit 116 * 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index 4a1ac9fbf186..754f93d208fa 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -396,7 +396,14 @@ extern struct bus_type mpic_subsys;
396#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */ 396#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
397 397
398/* Get the version of primary MPIC */ 398/* Get the version of primary MPIC */
399#ifdef CONFIG_MPIC
399extern u32 fsl_mpic_primary_get_version(void); 400extern u32 fsl_mpic_primary_get_version(void);
401#else
402static inline u32 fsl_mpic_primary_get_version(void)
403{
404 return 0;
405}
406#endif
400 407
401/* Allocate the controller structure and setup the linux irq descs 408/* Allocate the controller structure and setup the linux irq descs
402 * for the range if interrupts passed in. No HW initialization is 409 * for the range if interrupts passed in. No HW initialization is
diff --git a/arch/powerpc/include/asm/perf_event_fsl_emb.h b/arch/powerpc/include/asm/perf_event_fsl_emb.h
index 718a9fa94e68..a58165450f6f 100644
--- a/arch/powerpc/include/asm/perf_event_fsl_emb.h
+++ b/arch/powerpc/include/asm/perf_event_fsl_emb.h
@@ -13,7 +13,7 @@
13#include <linux/types.h> 13#include <linux/types.h>
14#include <asm/hw_irq.h> 14#include <asm/hw_irq.h>
15 15
16#define MAX_HWEVENTS 4 16#define MAX_HWEVENTS 6
17 17
18/* event flags */ 18/* event flags */
19#define FSL_EMB_EVENT_VALID 1 19#define FSL_EMB_EVENT_VALID 1
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index eccfc161e58e..d7fe9f5b46d4 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -81,6 +81,53 @@
81#define __REGA0_R30 30 81#define __REGA0_R30 30
82#define __REGA0_R31 31 82#define __REGA0_R31 31
83 83
84/* opcode and xopcode for instructions */
85#define OP_TRAP 3
86#define OP_TRAP_64 2
87
88#define OP_31_XOP_TRAP 4
89#define OP_31_XOP_LWZX 23
90#define OP_31_XOP_DCBST 54
91#define OP_31_XOP_LWZUX 55
92#define OP_31_XOP_TRAP_64 68
93#define OP_31_XOP_DCBF 86
94#define OP_31_XOP_LBZX 87
95#define OP_31_XOP_STWX 151
96#define OP_31_XOP_STBX 215
97#define OP_31_XOP_LBZUX 119
98#define OP_31_XOP_STBUX 247
99#define OP_31_XOP_LHZX 279
100#define OP_31_XOP_LHZUX 311
101#define OP_31_XOP_MFSPR 339
102#define OP_31_XOP_LHAX 343
103#define OP_31_XOP_LHAUX 375
104#define OP_31_XOP_STHX 407
105#define OP_31_XOP_STHUX 439
106#define OP_31_XOP_MTSPR 467
107#define OP_31_XOP_DCBI 470
108#define OP_31_XOP_LWBRX 534
109#define OP_31_XOP_TLBSYNC 566
110#define OP_31_XOP_STWBRX 662
111#define OP_31_XOP_LHBRX 790
112#define OP_31_XOP_STHBRX 918
113
114#define OP_LWZ 32
115#define OP_LD 58
116#define OP_LWZU 33
117#define OP_LBZ 34
118#define OP_LBZU 35
119#define OP_STW 36
120#define OP_STWU 37
121#define OP_STD 62
122#define OP_STB 38
123#define OP_STBU 39
124#define OP_LHZ 40
125#define OP_LHZU 41
126#define OP_LHA 42
127#define OP_LHAU 43
128#define OP_STH 44
129#define OP_STHU 45
130
84/* sorted alphabetically */ 131/* sorted alphabetically */
85#define PPC_INST_BHRBE 0x7c00025c 132#define PPC_INST_BHRBE 0x7c00025c
86#define PPC_INST_CLRBHRB 0x7c00035c 133#define PPC_INST_CLRBHRB 0x7c00035c
diff --git a/arch/powerpc/include/asm/reg_fsl_emb.h b/arch/powerpc/include/asm/reg_fsl_emb.h
index 77bb71cfd991..0e3ddf5177f6 100644
--- a/arch/powerpc/include/asm/reg_fsl_emb.h
+++ b/arch/powerpc/include/asm/reg_fsl_emb.h
@@ -17,12 +17,16 @@
17/* Freescale Book E Performance Monitor APU Registers */ 17/* Freescale Book E Performance Monitor APU Registers */
18#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */ 18#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
19#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */ 19#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
20#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */ 20#define PMRN_PMC2 0x012 /* Performance Monitor Counter 2 */
21#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */ 21#define PMRN_PMC3 0x013 /* Performance Monitor Counter 3 */
22#define PMRN_PMC4 0x014 /* Performance Monitor Counter 4 */
23#define PMRN_PMC5 0x015 /* Performance Monitor Counter 5 */
22#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */ 24#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
23#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */ 25#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
24#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */ 26#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
25#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */ 27#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
28#define PMRN_PMLCA4 0x094 /* PM Local Control A4 */
29#define PMRN_PMLCA5 0x095 /* PM Local Control A5 */
26 30
27#define PMLCA_FC 0x80000000 /* Freeze Counter */ 31#define PMLCA_FC 0x80000000 /* Freeze Counter */
28#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */ 32#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
@@ -30,14 +34,18 @@
30#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */ 34#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
31#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */ 35#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
32#define PMLCA_CE 0x04000000 /* Condition Enable */ 36#define PMLCA_CE 0x04000000 /* Condition Enable */
37#define PMLCA_FGCS1 0x00000002 /* Freeze in guest state */
38#define PMLCA_FGCS0 0x00000001 /* Freeze in hypervisor state */
33 39
34#define PMLCA_EVENT_MASK 0x00ff0000 /* Event field */ 40#define PMLCA_EVENT_MASK 0x01ff0000 /* Event field */
35#define PMLCA_EVENT_SHIFT 16 41#define PMLCA_EVENT_SHIFT 16
36 42
37#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */ 43#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
38#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */ 44#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
39#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */ 45#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
40#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */ 46#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
47#define PMRN_PMLCB4 0x114 /* PM Local Control B4 */
48#define PMRN_PMLCB5 0x115 /* PM Local Control B5 */
41 49
42#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshold Multiple Field */ 50#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshold Multiple Field */
43#define PMLCB_THRESHMUL_SHIFT 8 51#define PMLCB_THRESHMUL_SHIFT 8
@@ -55,16 +63,22 @@
55 63
56#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */ 64#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
57#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */ 65#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
58#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */ 66#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 2 */
59#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */ 67#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 3 */
68#define PMRN_UPMC4 0x004 /* User Performance Monitor Counter 4 */
69#define PMRN_UPMC5 0x005 /* User Performance Monitor Counter 5 */
60#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */ 70#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
61#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */ 71#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
62#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */ 72#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
63#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */ 73#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
74#define PMRN_UPMLCA4 0x084 /* User PM Local Control A4 */
75#define PMRN_UPMLCA5 0x085 /* User PM Local Control A5 */
64#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */ 76#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
65#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */ 77#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
66#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */ 78#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
67#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */ 79#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
80#define PMRN_UPMLCB4 0x104 /* User PM Local Control B4 */
81#define PMRN_UPMLCB5 0x105 /* User PM Local Control B5 */
68#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */ 82#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
69 83
70 84
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 0b9af015bedc..bfb18c7290b7 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -75,7 +75,7 @@ _GLOBAL(__setup_cpu_e500v2)
75 bl __e500_icache_setup 75 bl __e500_icache_setup
76 bl __e500_dcache_setup 76 bl __e500_dcache_setup
77 bl __setup_e500_ivors 77 bl __setup_e500_ivors
78#ifdef CONFIG_FSL_RIO 78#if defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI)
79 /* Ensure that RFXE is set */ 79 /* Ensure that RFXE is set */
80 mfspr r3,SPRN_HID1 80 mfspr r3,SPRN_HID1
81 oris r3,r3,HID1_RFXE@h 81 oris r3,r3,HID1_RFXE@h
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 22973a74df73..597d954e5860 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -2105,7 +2105,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
2105 MMU_FTR_USE_TLBILX, 2105 MMU_FTR_USE_TLBILX,
2106 .icache_bsize = 64, 2106 .icache_bsize = 64,
2107 .dcache_bsize = 64, 2107 .dcache_bsize = 64,
2108 .num_pmcs = 4, 2108 .num_pmcs = 6,
2109 .oprofile_cpu_type = "ppc/e6500", 2109 .oprofile_cpu_type = "ppc/e6500",
2110 .oprofile_type = PPC_OPROFILE_FSL_EMB, 2110 .oprofile_type = PPC_OPROFILE_FSL_EMB,
2111 .cpu_setup = __setup_cpu_e6500, 2111 .cpu_setup = __setup_cpu_e6500,
diff --git a/arch/powerpc/kernel/epapr_paravirt.c b/arch/powerpc/kernel/epapr_paravirt.c
index d44a571e45a7..6300c13bbde4 100644
--- a/arch/powerpc/kernel/epapr_paravirt.c
+++ b/arch/powerpc/kernel/epapr_paravirt.c
@@ -30,22 +30,20 @@ extern u32 epapr_ev_idle_start[];
30 30
31bool epapr_paravirt_enabled; 31bool epapr_paravirt_enabled;
32 32
33static int __init epapr_paravirt_init(void) 33static int __init early_init_dt_scan_epapr(unsigned long node,
34 const char *uname,
35 int depth, void *data)
34{ 36{
35 struct device_node *hyper_node;
36 const u32 *insts; 37 const u32 *insts;
37 int len, i; 38 unsigned long len;
39 int i;
38 40
39 hyper_node = of_find_node_by_path("/hypervisor"); 41 insts = of_get_flat_dt_prop(node, "hcall-instructions", &len);
40 if (!hyper_node)
41 return -ENODEV;
42
43 insts = of_get_property(hyper_node, "hcall-instructions", &len);
44 if (!insts) 42 if (!insts)
45 return -ENODEV; 43 return 0;
46 44
47 if (len % 4 || len > (4 * 4)) 45 if (len % 4 || len > (4 * 4))
48 return -ENODEV; 46 return -1;
49 47
50 for (i = 0; i < (len / 4); i++) { 48 for (i = 0; i < (len / 4); i++) {
51 patch_instruction(epapr_hypercall_start + i, insts[i]); 49 patch_instruction(epapr_hypercall_start + i, insts[i]);
@@ -55,13 +53,19 @@ static int __init epapr_paravirt_init(void)
55 } 53 }
56 54
57#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64) 55#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
58 if (of_get_property(hyper_node, "has-idle", NULL)) 56 if (of_get_flat_dt_prop(node, "has-idle", NULL))
59 ppc_md.power_save = epapr_ev_idle; 57 ppc_md.power_save = epapr_ev_idle;
60#endif 58#endif
61 59
62 epapr_paravirt_enabled = true; 60 epapr_paravirt_enabled = true;
63 61
62 return 1;
63}
64
65int __init epapr_paravirt_early_init(void)
66{
67 of_scan_flat_dt(early_init_dt_scan_epapr, NULL);
68
64 return 0; 69 return 0;
65} 70}
66 71
67early_initcall(epapr_paravirt_init);
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index a8f54ecb091f..a4bbcae72578 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -38,6 +38,7 @@
38#include <asm/serial.h> 38#include <asm/serial.h>
39#include <asm/udbg.h> 39#include <asm/udbg.h>
40#include <asm/mmu_context.h> 40#include <asm/mmu_context.h>
41#include <asm/epapr_hcalls.h>
41 42
42#include "setup.h" 43#include "setup.h"
43 44
@@ -128,6 +129,8 @@ notrace void __init machine_init(u64 dt_ptr)
128 /* Do some early initialization based on the flat device tree */ 129 /* Do some early initialization based on the flat device tree */
129 early_init_devtree(__va(dt_ptr)); 130 early_init_devtree(__va(dt_ptr));
130 131
132 epapr_paravirt_early_init();
133
131 early_init_mmu(); 134 early_init_mmu();
132 135
133 probe_machine(); 136 probe_machine();
@@ -326,5 +329,4 @@ void __init setup_arch(char **cmdline_p)
326 329
327 /* Initialize the MMU context management stuff */ 330 /* Initialize the MMU context management stuff */
328 mmu_context_init(); 331 mmu_context_init();
329
330} 332}
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 389fb8077cc9..f03770e0fc8d 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -66,6 +66,7 @@
66#include <asm/code-patching.h> 66#include <asm/code-patching.h>
67#include <asm/kvm_ppc.h> 67#include <asm/kvm_ppc.h>
68#include <asm/hugetlb.h> 68#include <asm/hugetlb.h>
69#include <asm/epapr_hcalls.h>
69 70
70#include "setup.h" 71#include "setup.h"
71 72
@@ -215,6 +216,8 @@ void __init early_setup(unsigned long dt_ptr)
215 */ 216 */
216 early_init_devtree(__va(dt_ptr)); 217 early_init_devtree(__va(dt_ptr));
217 218
219 epapr_paravirt_early_init();
220
218 /* Now we know the logical id of our boot cpu, setup the paca. */ 221 /* Now we know the logical id of our boot cpu, setup the paca. */
219 setup_paca(&paca[boot_cpuid]); 222 setup_paca(&paca[boot_cpuid]);
220 fixup_boot_paca(); 223 fixup_boot_paca();
diff --git a/arch/powerpc/kernel/swsusp_booke.S b/arch/powerpc/kernel/swsusp_booke.S
index 11a39307dd71..0f204053e5b5 100644
--- a/arch/powerpc/kernel/swsusp_booke.S
+++ b/arch/powerpc/kernel/swsusp_booke.S
@@ -141,6 +141,14 @@ _GLOBAL(swsusp_arch_resume)
141 lis r11,swsusp_save_area@h 141 lis r11,swsusp_save_area@h
142 ori r11,r11,swsusp_save_area@l 142 ori r11,r11,swsusp_save_area@l
143 143
144 /*
145 * Mappings from virtual addresses to physical addresses may be
146 * different than they were prior to restoring hibernation state.
147 * Invalidate the TLB so that the boot CPU is using the new
148 * mappings.
149 */
150 bl _tlbil_all
151
144 lwz r4,SL_SPRG0(r11) 152 lwz r4,SL_SPRG0(r11)
145 mtsprg 0,r4 153 mtsprg 0,r4
146 lwz r4,SL_SPRG1(r11) 154 lwz r4,SL_SPRG1(r11)
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index bf33c22e38a4..f58eaf23e8f1 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -62,6 +62,7 @@
62#include <asm/switch_to.h> 62#include <asm/switch_to.h>
63#include <asm/tm.h> 63#include <asm/tm.h>
64#include <asm/debug.h> 64#include <asm/debug.h>
65#include <sysdev/fsl_pci.h>
65 66
66#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) 67#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
67int (*__debugger)(struct pt_regs *regs) __read_mostly; 68int (*__debugger)(struct pt_regs *regs) __read_mostly;
@@ -567,6 +568,8 @@ int machine_check_e500(struct pt_regs *regs)
567 if (reason & MCSR_BUS_RBERR) { 568 if (reason & MCSR_BUS_RBERR) {
568 if (fsl_rio_mcheck_exception(regs)) 569 if (fsl_rio_mcheck_exception(regs))
569 return 1; 570 return 1;
571 if (fsl_pci_mcheck_exception(regs))
572 return 1;
570 } 573 }
571 574
572 printk("Machine check in kernel mode.\n"); 575 printk("Machine check in kernel mode.\n");
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index 2c52ada30775..751cd45f65a0 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
@@ -30,53 +30,10 @@
30#include <asm/byteorder.h> 30#include <asm/byteorder.h>
31#include <asm/kvm_ppc.h> 31#include <asm/kvm_ppc.h>
32#include <asm/disassemble.h> 32#include <asm/disassemble.h>
33#include <asm/ppc-opcode.h>
33#include "timing.h" 34#include "timing.h"
34#include "trace.h" 35#include "trace.h"
35 36
36#define OP_TRAP 3
37#define OP_TRAP_64 2
38
39#define OP_31_XOP_TRAP 4
40#define OP_31_XOP_LWZX 23
41#define OP_31_XOP_DCBST 54
42#define OP_31_XOP_TRAP_64 68
43#define OP_31_XOP_DCBF 86
44#define OP_31_XOP_LBZX 87
45#define OP_31_XOP_STWX 151
46#define OP_31_XOP_STBX 215
47#define OP_31_XOP_LBZUX 119
48#define OP_31_XOP_STBUX 247
49#define OP_31_XOP_LHZX 279
50#define OP_31_XOP_LHZUX 311
51#define OP_31_XOP_MFSPR 339
52#define OP_31_XOP_LHAX 343
53#define OP_31_XOP_STHX 407
54#define OP_31_XOP_STHUX 439
55#define OP_31_XOP_MTSPR 467
56#define OP_31_XOP_DCBI 470
57#define OP_31_XOP_LWBRX 534
58#define OP_31_XOP_TLBSYNC 566
59#define OP_31_XOP_STWBRX 662
60#define OP_31_XOP_LHBRX 790
61#define OP_31_XOP_STHBRX 918
62
63#define OP_LWZ 32
64#define OP_LD 58
65#define OP_LWZU 33
66#define OP_LBZ 34
67#define OP_LBZU 35
68#define OP_STW 36
69#define OP_STWU 37
70#define OP_STD 62
71#define OP_STB 38
72#define OP_STBU 39
73#define OP_LHZ 40
74#define OP_LHZU 41
75#define OP_LHA 42
76#define OP_LHAU 43
77#define OP_STH 44
78#define OP_STHU 45
79
80void kvmppc_emulate_dec(struct kvm_vcpu *vcpu) 37void kvmppc_emulate_dec(struct kvm_vcpu *vcpu)
81{ 38{
82 unsigned long dec_nsec; 39 unsigned long dec_nsec;
diff --git a/arch/powerpc/oprofile/op_model_fsl_emb.c b/arch/powerpc/oprofile/op_model_fsl_emb.c
index ccc1daa33aed..2a82d3ed464d 100644
--- a/arch/powerpc/oprofile/op_model_fsl_emb.c
+++ b/arch/powerpc/oprofile/op_model_fsl_emb.c
@@ -46,6 +46,12 @@ static inline u32 get_pmlca(int ctr)
46 case 3: 46 case 3:
47 pmlca = mfpmr(PMRN_PMLCA3); 47 pmlca = mfpmr(PMRN_PMLCA3);
48 break; 48 break;
49 case 4:
50 pmlca = mfpmr(PMRN_PMLCA4);
51 break;
52 case 5:
53 pmlca = mfpmr(PMRN_PMLCA5);
54 break;
49 default: 55 default:
50 panic("Bad ctr number\n"); 56 panic("Bad ctr number\n");
51 } 57 }
@@ -68,6 +74,12 @@ static inline void set_pmlca(int ctr, u32 pmlca)
68 case 3: 74 case 3:
69 mtpmr(PMRN_PMLCA3, pmlca); 75 mtpmr(PMRN_PMLCA3, pmlca);
70 break; 76 break;
77 case 4:
78 mtpmr(PMRN_PMLCA4, pmlca);
79 break;
80 case 5:
81 mtpmr(PMRN_PMLCA5, pmlca);
82 break;
71 default: 83 default:
72 panic("Bad ctr number\n"); 84 panic("Bad ctr number\n");
73 } 85 }
@@ -84,6 +96,10 @@ static inline unsigned int ctr_read(unsigned int i)
84 return mfpmr(PMRN_PMC2); 96 return mfpmr(PMRN_PMC2);
85 case 3: 97 case 3:
86 return mfpmr(PMRN_PMC3); 98 return mfpmr(PMRN_PMC3);
99 case 4:
100 return mfpmr(PMRN_PMC4);
101 case 5:
102 return mfpmr(PMRN_PMC5);
87 default: 103 default:
88 return 0; 104 return 0;
89 } 105 }
@@ -104,6 +120,12 @@ static inline void ctr_write(unsigned int i, unsigned int val)
104 case 3: 120 case 3:
105 mtpmr(PMRN_PMC3, val); 121 mtpmr(PMRN_PMC3, val);
106 break; 122 break;
123 case 4:
124 mtpmr(PMRN_PMC4, val);
125 break;
126 case 5:
127 mtpmr(PMRN_PMC5, val);
128 break;
107 default: 129 default:
108 break; 130 break;
109 } 131 }
@@ -133,6 +155,14 @@ static void init_pmc_stop(int ctr)
133 mtpmr(PMRN_PMLCA3, pmlca); 155 mtpmr(PMRN_PMLCA3, pmlca);
134 mtpmr(PMRN_PMLCB3, pmlcb); 156 mtpmr(PMRN_PMLCB3, pmlcb);
135 break; 157 break;
158 case 4:
159 mtpmr(PMRN_PMLCA4, pmlca);
160 mtpmr(PMRN_PMLCB4, pmlcb);
161 break;
162 case 5:
163 mtpmr(PMRN_PMLCA5, pmlca);
164 mtpmr(PMRN_PMLCB5, pmlcb);
165 break;
136 default: 166 default:
137 panic("Bad ctr number!\n"); 167 panic("Bad ctr number!\n");
138 } 168 }
diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile
index 510fae10513d..60d71eea919c 100644
--- a/arch/powerpc/perf/Makefile
+++ b/arch/powerpc/perf/Makefile
@@ -9,7 +9,7 @@ obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o power5-pmu.o \
9obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o 9obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o
10 10
11obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o 11obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o
12obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o 12obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o e6500-pmu.o
13 13
14obj-$(CONFIG_PPC64) += $(obj64-y) 14obj-$(CONFIG_PPC64) += $(obj64-y)
15obj-$(CONFIG_PPC32) += $(obj32-y) 15obj-$(CONFIG_PPC32) += $(obj32-y)
diff --git a/arch/powerpc/perf/core-fsl-emb.c b/arch/powerpc/perf/core-fsl-emb.c
index 106c53354675..d35ae52c69dc 100644
--- a/arch/powerpc/perf/core-fsl-emb.c
+++ b/arch/powerpc/perf/core-fsl-emb.c
@@ -70,6 +70,12 @@ static unsigned long read_pmc(int idx)
70 case 3: 70 case 3:
71 val = mfpmr(PMRN_PMC3); 71 val = mfpmr(PMRN_PMC3);
72 break; 72 break;
73 case 4:
74 val = mfpmr(PMRN_PMC4);
75 break;
76 case 5:
77 val = mfpmr(PMRN_PMC5);
78 break;
73 default: 79 default:
74 printk(KERN_ERR "oops trying to read PMC%d\n", idx); 80 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
75 val = 0; 81 val = 0;
@@ -95,6 +101,12 @@ static void write_pmc(int idx, unsigned long val)
95 case 3: 101 case 3:
96 mtpmr(PMRN_PMC3, val); 102 mtpmr(PMRN_PMC3, val);
97 break; 103 break;
104 case 4:
105 mtpmr(PMRN_PMC4, val);
106 break;
107 case 5:
108 mtpmr(PMRN_PMC5, val);
109 break;
98 default: 110 default:
99 printk(KERN_ERR "oops trying to write PMC%d\n", idx); 111 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
100 } 112 }
@@ -120,6 +132,12 @@ static void write_pmlca(int idx, unsigned long val)
120 case 3: 132 case 3:
121 mtpmr(PMRN_PMLCA3, val); 133 mtpmr(PMRN_PMLCA3, val);
122 break; 134 break;
135 case 4:
136 mtpmr(PMRN_PMLCA4, val);
137 break;
138 case 5:
139 mtpmr(PMRN_PMLCA5, val);
140 break;
123 default: 141 default:
124 printk(KERN_ERR "oops trying to write PMLCA%d\n", idx); 142 printk(KERN_ERR "oops trying to write PMLCA%d\n", idx);
125 } 143 }
@@ -145,6 +163,12 @@ static void write_pmlcb(int idx, unsigned long val)
145 case 3: 163 case 3:
146 mtpmr(PMRN_PMLCB3, val); 164 mtpmr(PMRN_PMLCB3, val);
147 break; 165 break;
166 case 4:
167 mtpmr(PMRN_PMLCB4, val);
168 break;
169 case 5:
170 mtpmr(PMRN_PMLCB5, val);
171 break;
148 default: 172 default:
149 printk(KERN_ERR "oops trying to write PMLCB%d\n", idx); 173 printk(KERN_ERR "oops trying to write PMLCB%d\n", idx);
150 } 174 }
@@ -462,6 +486,12 @@ static int fsl_emb_pmu_event_init(struct perf_event *event)
462 int num_restricted; 486 int num_restricted;
463 int i; 487 int i;
464 488
489 if (ppmu->n_counter > MAX_HWEVENTS) {
490 WARN(1, "No. of perf counters (%d) is higher than max array size(%d)\n",
491 ppmu->n_counter, MAX_HWEVENTS);
492 ppmu->n_counter = MAX_HWEVENTS;
493 }
494
465 switch (event->attr.type) { 495 switch (event->attr.type) {
466 case PERF_TYPE_HARDWARE: 496 case PERF_TYPE_HARDWARE:
467 ev = event->attr.config; 497 ev = event->attr.config;
diff --git a/arch/powerpc/perf/e6500-pmu.c b/arch/powerpc/perf/e6500-pmu.c
new file mode 100644
index 000000000000..3d877aa777b5
--- /dev/null
+++ b/arch/powerpc/perf/e6500-pmu.c
@@ -0,0 +1,121 @@
1/*
2 * Performance counter support for e6500 family processors.
3 *
4 * Author: Priyanka Jain, Priyanka.Jain@freescale.com
5 * Based on e500-pmu.c
6 * Copyright 2013 Freescale Semiconductor, Inc.
7 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <linux/string.h>
16#include <linux/perf_event.h>
17#include <asm/reg.h>
18#include <asm/cputable.h>
19
20/*
21 * Map of generic hardware event types to hardware events
22 * Zero if unsupported
23 */
24static int e6500_generic_events[] = {
25 [PERF_COUNT_HW_CPU_CYCLES] = 1,
26 [PERF_COUNT_HW_INSTRUCTIONS] = 2,
27 [PERF_COUNT_HW_CACHE_MISSES] = 221,
28 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 12,
29 [PERF_COUNT_HW_BRANCH_MISSES] = 15,
30};
31
32#define C(x) PERF_COUNT_HW_CACHE_##x
33
34/*
35 * Table of generalized cache-related events.
36 * 0 means not supported, -1 means nonsensical, other values
37 * are event codes.
38 */
39static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
40 [C(L1D)] = {
41 /*RESULT_ACCESS RESULT_MISS */
42 [C(OP_READ)] = { 27, 222 },
43 [C(OP_WRITE)] = { 28, 223 },
44 [C(OP_PREFETCH)] = { 29, 0 },
45 },
46 [C(L1I)] = {
47 /*RESULT_ACCESS RESULT_MISS */
48 [C(OP_READ)] = { 2, 254 },
49 [C(OP_WRITE)] = { -1, -1 },
50 [C(OP_PREFETCH)] = { 37, 0 },
51 },
52 /*
53 * Assuming LL means L2, it's not a good match for this model.
54 * It does not have separate read/write events (but it does have
55 * separate instruction/data events).
56 */
57 [C(LL)] = {
58 /*RESULT_ACCESS RESULT_MISS */
59 [C(OP_READ)] = { 0, 0 },
60 [C(OP_WRITE)] = { 0, 0 },
61 [C(OP_PREFETCH)] = { 0, 0 },
62 },
63 /*
64 * There are data/instruction MMU misses, but that's a miss on
65 * the chip's internal level-one TLB which is probably not
66 * what the user wants. Instead, unified level-two TLB misses
67 * are reported here.
68 */
69 [C(DTLB)] = {
70 /*RESULT_ACCESS RESULT_MISS */
71 [C(OP_READ)] = { 26, 66 },
72 [C(OP_WRITE)] = { -1, -1 },
73 [C(OP_PREFETCH)] = { -1, -1 },
74 },
75 [C(BPU)] = {
76 /*RESULT_ACCESS RESULT_MISS */
77 [C(OP_READ)] = { 12, 15 },
78 [C(OP_WRITE)] = { -1, -1 },
79 [C(OP_PREFETCH)] = { -1, -1 },
80 },
81 [C(NODE)] = {
82 /* RESULT_ACCESS RESULT_MISS */
83 [C(OP_READ)] = { -1, -1 },
84 [C(OP_WRITE)] = { -1, -1 },
85 [C(OP_PREFETCH)] = { -1, -1 },
86 },
87};
88
89static int num_events = 512;
90
91/* Upper half of event id is PMLCb, for threshold events */
92static u64 e6500_xlate_event(u64 event_id)
93{
94 u32 event_low = (u32)event_id;
95 if (event_low >= num_events ||
96 (event_id & (FSL_EMB_EVENT_THRESHMUL | FSL_EMB_EVENT_THRESH)))
97 return 0;
98
99 return FSL_EMB_EVENT_VALID;
100}
101
102static struct fsl_emb_pmu e6500_pmu = {
103 .name = "e6500 family",
104 .n_counter = 6,
105 .n_restricted = 0,
106 .xlate_event = e6500_xlate_event,
107 .n_generic = ARRAY_SIZE(e6500_generic_events),
108 .generic_events = e6500_generic_events,
109 .cache_events = &e6500_cache_events,
110};
111
112static int init_e6500_pmu(void)
113{
114 if (!cur_cpu_spec->oprofile_cpu_type ||
115 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/e6500"))
116 return -ENODEV;
117
118 return register_fsl_emb_pmu(&e6500_pmu);
119}
120
121early_initcall(init_e6500_pmu);
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
index c59c617eee93..aa3690bae415 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -53,12 +53,6 @@ void __init corenet_ds_setup_arch(void)
53{ 53{
54 mpc85xx_smp_init(); 54 mpc85xx_smp_init();
55 55
56#if defined(CONFIG_PCI) && defined(CONFIG_PPC64)
57 pci_devs_phb_init();
58#endif
59
60 fsl_pci_assign_primary();
61
62 swiotlb_detect_4g(); 56 swiotlb_detect_4g();
63 57
64 pr_info("%s board from Freescale Semiconductor\n", ppc_md.name); 58 pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index ede8771d6f02..53b6fb0a3d56 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -160,6 +160,7 @@ machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices);
160machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices); 160machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
161machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices); 161machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices);
162machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices); 162machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
163machine_arch_initcall(p1020_rdb_pd, mpc85xx_common_publish_devices);
163machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices); 164machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
164machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices); 165machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
165machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices); 166machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices);
@@ -193,6 +194,13 @@ static int __init p1020_rdb_pc_probe(void)
193 return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PC"); 194 return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PC");
194} 195}
195 196
197static int __init p1020_rdb_pd_probe(void)
198{
199 unsigned long root = of_get_flat_dt_root();
200
201 return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PD");
202}
203
196static int __init p1021_rdb_pc_probe(void) 204static int __init p1021_rdb_pc_probe(void)
197{ 205{
198 unsigned long root = of_get_flat_dt_root(); 206 unsigned long root = of_get_flat_dt_root();
@@ -351,6 +359,20 @@ define_machine(p1020_rdb_pc) {
351 .progress = udbg_progress, 359 .progress = udbg_progress,
352}; 360};
353 361
362define_machine(p1020_rdb_pd) {
363 .name = "P1020RDB-PD",
364 .probe = p1020_rdb_pd_probe,
365 .setup_arch = mpc85xx_rdb_setup_arch,
366 .init_IRQ = mpc85xx_rdb_pic_init,
367#ifdef CONFIG_PCI
368 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
369#endif
370 .get_irq = mpic_get_irq,
371 .restart = fsl_rstcr_restart,
372 .calibrate_decr = generic_calibrate_decr,
373 .progress = udbg_progress,
374};
375
354define_machine(p1024_rdb) { 376define_machine(p1024_rdb) {
355 .name = "P1024 RDB", 377 .name = "P1024 RDB",
356 .probe = p1024_rdb_probe, 378 .probe = p1024_rdb_probe,
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index ab02db3d02d8..77efbaec7b9c 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -28,6 +28,18 @@
28#include "fsl_msi.h" 28#include "fsl_msi.h"
29#include "fsl_pci.h" 29#include "fsl_pci.h"
30 30
31#define MSIIR_OFFSET_MASK 0xfffff
32#define MSIIR_IBS_SHIFT 0
33#define MSIIR_SRS_SHIFT 5
34#define MSIIR1_IBS_SHIFT 4
35#define MSIIR1_SRS_SHIFT 0
36#define MSI_SRS_MASK 0xf
37#define MSI_IBS_MASK 0x1f
38
39#define msi_hwirq(msi, msir_index, intr_index) \
40 ((msir_index) << (msi)->srs_shift | \
41 ((intr_index) << (msi)->ibs_shift))
42
31static LIST_HEAD(msi_head); 43static LIST_HEAD(msi_head);
32 44
33struct fsl_msi_feature { 45struct fsl_msi_feature {
@@ -80,18 +92,19 @@ static const struct irq_domain_ops fsl_msi_host_ops = {
80 92
81static int fsl_msi_init_allocator(struct fsl_msi *msi_data) 93static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
82{ 94{
83 int rc; 95 int rc, hwirq;
84 96
85 rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS, 97 rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS_MAX,
86 msi_data->irqhost->of_node); 98 msi_data->irqhost->of_node);
87 if (rc) 99 if (rc)
88 return rc; 100 return rc;
89 101
90 rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap); 102 /*
91 if (rc < 0) { 103 * Reserve all the hwirqs
92 msi_bitmap_free(&msi_data->bitmap); 104 * The available hwirqs will be released in fsl_msi_setup_hwirq()
93 return rc; 105 */
94 } 106 for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++)
107 msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);
95 108
96 return 0; 109 return 0;
97} 110}
@@ -144,8 +157,9 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
144 157
145 msg->data = hwirq; 158 msg->data = hwirq;
146 159
147 pr_debug("%s: allocated srs: %d, ibs: %d\n", 160 pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__,
148 __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG); 161 (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK,
162 (hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK);
149} 163}
150 164
151static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) 165static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
@@ -255,7 +269,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
255 269
256 msir_index = cascade_data->index; 270 msir_index = cascade_data->index;
257 271
258 if (msir_index >= NR_MSI_REG) 272 if (msir_index >= NR_MSI_REG_MAX)
259 cascade_irq = NO_IRQ; 273 cascade_irq = NO_IRQ;
260 274
261 irqd_set_chained_irq_inprogress(idata); 275 irqd_set_chained_irq_inprogress(idata);
@@ -285,8 +299,8 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
285 intr_index = ffs(msir_value) - 1; 299 intr_index = ffs(msir_value) - 1;
286 300
287 cascade_irq = irq_linear_revmap(msi_data->irqhost, 301 cascade_irq = irq_linear_revmap(msi_data->irqhost,
288 msir_index * IRQS_PER_MSI_REG + 302 msi_hwirq(msi_data, msir_index,
289 intr_index + have_shift); 303 intr_index + have_shift));
290 if (cascade_irq != NO_IRQ) 304 if (cascade_irq != NO_IRQ)
291 generic_handle_irq(cascade_irq); 305 generic_handle_irq(cascade_irq);
292 have_shift += intr_index + 1; 306 have_shift += intr_index + 1;
@@ -316,7 +330,7 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
316 330
317 if (msi->list.prev != NULL) 331 if (msi->list.prev != NULL)
318 list_del(&msi->list); 332 list_del(&msi->list);
319 for (i = 0; i < NR_MSI_REG; i++) { 333 for (i = 0; i < NR_MSI_REG_MAX; i++) {
320 virq = msi->msi_virqs[i]; 334 virq = msi->msi_virqs[i];
321 if (virq != NO_IRQ) { 335 if (virq != NO_IRQ) {
322 cascade_data = irq_get_handler_data(virq); 336 cascade_data = irq_get_handler_data(virq);
@@ -339,7 +353,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
339 int offset, int irq_index) 353 int offset, int irq_index)
340{ 354{
341 struct fsl_msi_cascade_data *cascade_data = NULL; 355 struct fsl_msi_cascade_data *cascade_data = NULL;
342 int virt_msir; 356 int virt_msir, i;
343 357
344 virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index); 358 virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
345 if (virt_msir == NO_IRQ) { 359 if (virt_msir == NO_IRQ) {
@@ -360,6 +374,11 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
360 irq_set_handler_data(virt_msir, cascade_data); 374 irq_set_handler_data(virt_msir, cascade_data);
361 irq_set_chained_handler(virt_msir, fsl_msi_cascade); 375 irq_set_chained_handler(virt_msir, fsl_msi_cascade);
362 376
377 /* Release the hwirqs corresponding to this MSI register */
378 for (i = 0; i < IRQS_PER_MSI_REG; i++)
379 msi_bitmap_free_hwirqs(&msi->bitmap,
380 msi_hwirq(msi, offset, i), 1);
381
363 return 0; 382 return 0;
364} 383}
365 384
@@ -368,14 +387,12 @@ static int fsl_of_msi_probe(struct platform_device *dev)
368{ 387{
369 const struct of_device_id *match; 388 const struct of_device_id *match;
370 struct fsl_msi *msi; 389 struct fsl_msi *msi;
371 struct resource res; 390 struct resource res, msiir;
372 int err, i, j, irq_index, count; 391 int err, i, j, irq_index, count;
373 int rc;
374 const u32 *p; 392 const u32 *p;
375 const struct fsl_msi_feature *features; 393 const struct fsl_msi_feature *features;
376 int len; 394 int len;
377 u32 offset; 395 u32 offset;
378 static const u32 all_avail[] = { 0, NR_MSI_IRQS };
379 396
380 match = of_match_device(fsl_of_msi_ids, &dev->dev); 397 match = of_match_device(fsl_of_msi_ids, &dev->dev);
381 if (!match) 398 if (!match)
@@ -392,7 +409,7 @@ static int fsl_of_msi_probe(struct platform_device *dev)
392 platform_set_drvdata(dev, msi); 409 platform_set_drvdata(dev, msi);
393 410
394 msi->irqhost = irq_domain_add_linear(dev->dev.of_node, 411 msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
395 NR_MSI_IRQS, &fsl_msi_host_ops, msi); 412 NR_MSI_IRQS_MAX, &fsl_msi_host_ops, msi);
396 413
397 if (msi->irqhost == NULL) { 414 if (msi->irqhost == NULL) {
398 dev_err(&dev->dev, "No memory for MSI irqhost\n"); 415 dev_err(&dev->dev, "No memory for MSI irqhost\n");
@@ -421,6 +438,16 @@ static int fsl_of_msi_probe(struct platform_device *dev)
421 } 438 }
422 msi->msiir_offset = 439 msi->msiir_offset =
423 features->msiir_offset + (res.start & 0xfffff); 440 features->msiir_offset + (res.start & 0xfffff);
441
442 /*
443 * First read the MSIIR/MSIIR1 offset from dts
444 * On failure use the hardcode MSIIR offset
445 */
446 if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
447 msi->msiir_offset = features->msiir_offset +
448 (res.start & MSIIR_OFFSET_MASK);
449 else
450 msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK;
424 } 451 }
425 452
426 msi->feature = features->fsl_pic_ip; 453 msi->feature = features->fsl_pic_ip;
@@ -431,42 +458,66 @@ static int fsl_of_msi_probe(struct platform_device *dev)
431 */ 458 */
432 msi->phandle = dev->dev.of_node->phandle; 459 msi->phandle = dev->dev.of_node->phandle;
433 460
434 rc = fsl_msi_init_allocator(msi); 461 err = fsl_msi_init_allocator(msi);
435 if (rc) { 462 if (err) {
436 dev_err(&dev->dev, "Error allocating MSI bitmap\n"); 463 dev_err(&dev->dev, "Error allocating MSI bitmap\n");
437 goto error_out; 464 goto error_out;
438 } 465 }
439 466
440 p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len); 467 p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
441 if (p && len % (2 * sizeof(u32)) != 0) {
442 dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
443 __func__);
444 err = -EINVAL;
445 goto error_out;
446 }
447 468
448 if (!p) { 469 if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3")) {
449 p = all_avail; 470 msi->srs_shift = MSIIR1_SRS_SHIFT;
450 len = sizeof(all_avail); 471 msi->ibs_shift = MSIIR1_IBS_SHIFT;
451 } 472 if (p)
473 dev_warn(&dev->dev, "%s: dose not support msi-available-ranges property\n",
474 __func__);
475
476 for (irq_index = 0; irq_index < NR_MSI_REG_MSIIR1;
477 irq_index++) {
478 err = fsl_msi_setup_hwirq(msi, dev,
479 irq_index, irq_index);
480 if (err)
481 goto error_out;
482 }
483 } else {
484 static const u32 all_avail[] =
485 { 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG };
452 486
453 for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) { 487 msi->srs_shift = MSIIR_SRS_SHIFT;
454 if (p[i * 2] % IRQS_PER_MSI_REG || 488 msi->ibs_shift = MSIIR_IBS_SHIFT;
455 p[i * 2 + 1] % IRQS_PER_MSI_REG) { 489
456 printk(KERN_WARNING "%s: %s: msi available range of %u at %u is not IRQ-aligned\n", 490 if (p && len % (2 * sizeof(u32)) != 0) {
457 __func__, dev->dev.of_node->full_name, 491 dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
458 p[i * 2 + 1], p[i * 2]); 492 __func__);
459 err = -EINVAL; 493 err = -EINVAL;
460 goto error_out; 494 goto error_out;
461 } 495 }
462 496
463 offset = p[i * 2] / IRQS_PER_MSI_REG; 497 if (!p) {
464 count = p[i * 2 + 1] / IRQS_PER_MSI_REG; 498 p = all_avail;
499 len = sizeof(all_avail);
500 }
465 501
466 for (j = 0; j < count; j++, irq_index++) { 502 for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
467 err = fsl_msi_setup_hwirq(msi, dev, offset + j, irq_index); 503 if (p[i * 2] % IRQS_PER_MSI_REG ||
468 if (err) 504 p[i * 2 + 1] % IRQS_PER_MSI_REG) {
505 pr_warn("%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
506 __func__, dev->dev.of_node->full_name,
507 p[i * 2 + 1], p[i * 2]);
508 err = -EINVAL;
469 goto error_out; 509 goto error_out;
510 }
511
512 offset = p[i * 2] / IRQS_PER_MSI_REG;
513 count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
514
515 for (j = 0; j < count; j++, irq_index++) {
516 err = fsl_msi_setup_hwirq(msi, dev, offset + j,
517 irq_index);
518 if (err)
519 goto error_out;
520 }
470 } 521 }
471 } 522 }
472 523
@@ -509,6 +560,10 @@ static const struct of_device_id fsl_of_msi_ids[] = {
509 .data = &mpic_msi_feature, 560 .data = &mpic_msi_feature,
510 }, 561 },
511 { 562 {
563 .compatible = "fsl,mpic-msi-v4.3",
564 .data = &mpic_msi_feature,
565 },
566 {
512 .compatible = "fsl,ipic-msi", 567 .compatible = "fsl,ipic-msi",
513 .data = &ipic_msi_feature, 568 .data = &ipic_msi_feature,
514 }, 569 },
diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h
index 8225f8653f78..df9aa9fe0933 100644
--- a/arch/powerpc/sysdev/fsl_msi.h
+++ b/arch/powerpc/sysdev/fsl_msi.h
@@ -16,9 +16,11 @@
16#include <linux/of.h> 16#include <linux/of.h>
17#include <asm/msi_bitmap.h> 17#include <asm/msi_bitmap.h>
18 18
19#define NR_MSI_REG 8 19#define NR_MSI_REG_MSIIR 8 /* MSIIR can index 8 MSI registers */
20#define NR_MSI_REG_MSIIR1 16 /* MSIIR1 can index 16 MSI registers */
21#define NR_MSI_REG_MAX NR_MSI_REG_MSIIR1
20#define IRQS_PER_MSI_REG 32 22#define IRQS_PER_MSI_REG 32
21#define NR_MSI_IRQS (NR_MSI_REG * IRQS_PER_MSI_REG) 23#define NR_MSI_IRQS_MAX (NR_MSI_REG_MAX * IRQS_PER_MSI_REG)
22 24
23#define FSL_PIC_IP_MASK 0x0000000F 25#define FSL_PIC_IP_MASK 0x0000000F
24#define FSL_PIC_IP_MPIC 0x00000001 26#define FSL_PIC_IP_MPIC 0x00000001
@@ -31,9 +33,11 @@ struct fsl_msi {
31 unsigned long cascade_irq; 33 unsigned long cascade_irq;
32 34
33 u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */ 35 u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
36 u32 ibs_shift; /* Shift of interrupt bit select */
37 u32 srs_shift; /* Shift of the shared interrupt register select */
34 void __iomem *msi_regs; 38 void __iomem *msi_regs;
35 u32 feature; 39 u32 feature;
36 int msi_virqs[NR_MSI_REG]; 40 int msi_virqs[NR_MSI_REG_MAX];
37 41
38 struct msi_bitmap bitmap; 42 struct msi_bitmap bitmap;
39 43
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 46ac1ddea683..ccfb50ddfe38 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -26,11 +26,15 @@
26#include <linux/memblock.h> 26#include <linux/memblock.h>
27#include <linux/log2.h> 27#include <linux/log2.h>
28#include <linux/slab.h> 28#include <linux/slab.h>
29#include <linux/uaccess.h>
29 30
30#include <asm/io.h> 31#include <asm/io.h>
31#include <asm/prom.h> 32#include <asm/prom.h>
32#include <asm/pci-bridge.h> 33#include <asm/pci-bridge.h>
34#include <asm/ppc-pci.h>
33#include <asm/machdep.h> 35#include <asm/machdep.h>
36#include <asm/disassemble.h>
37#include <asm/ppc-opcode.h>
34#include <sysdev/fsl_soc.h> 38#include <sysdev/fsl_soc.h>
35#include <sysdev/fsl_pci.h> 39#include <sysdev/fsl_pci.h>
36 40
@@ -64,7 +68,7 @@ static int fsl_pcie_check_link(struct pci_controller *hose)
64 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { 68 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
65 if (hose->ops->read == fsl_indirect_read_config) { 69 if (hose->ops->read == fsl_indirect_read_config) {
66 struct pci_bus bus; 70 struct pci_bus bus;
67 bus.number = 0; 71 bus.number = hose->first_busno;
68 bus.sysdata = hose; 72 bus.sysdata = hose;
69 bus.ops = hose->ops; 73 bus.ops = hose->ops;
70 indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val); 74 indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
@@ -297,10 +301,10 @@ static void setup_pci_atmu(struct pci_controller *hose)
297 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 301 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
298 /* Size window to exact size if power-of-two or one size up */ 302 /* Size window to exact size if power-of-two or one size up */
299 if ((1ull << mem_log) != mem) { 303 if ((1ull << mem_log) != mem) {
304 mem_log++;
300 if ((1ull << mem_log) > mem) 305 if ((1ull << mem_log) > mem)
301 pr_info("%s: Setting PCI inbound window " 306 pr_info("%s: Setting PCI inbound window "
302 "greater than memory size\n", name); 307 "greater than memory size\n", name);
303 mem_log++;
304 } 308 }
305 309
306 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); 310 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
@@ -373,7 +377,9 @@ static void setup_pci_atmu(struct pci_controller *hose)
373 } 377 }
374 378
375 if (hose->dma_window_size < mem) { 379 if (hose->dma_window_size < mem) {
376#ifndef CONFIG_SWIOTLB 380#ifdef CONFIG_SWIOTLB
381 ppc_swiotlb_enable = 1;
382#else
377 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to " 383 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
378 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", 384 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
379 name); 385 name);
@@ -868,6 +874,160 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
868 return 0; 874 return 0;
869} 875}
870 876
877#ifdef CONFIG_E500
878static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
879{
880 unsigned int rd, ra, rb, d;
881
882 rd = get_rt(inst);
883 ra = get_ra(inst);
884 rb = get_rb(inst);
885 d = get_d(inst);
886
887 switch (get_op(inst)) {
888 case 31:
889 switch (get_xop(inst)) {
890 case OP_31_XOP_LWZX:
891 case OP_31_XOP_LWBRX:
892 regs->gpr[rd] = 0xffffffff;
893 break;
894
895 case OP_31_XOP_LWZUX:
896 regs->gpr[rd] = 0xffffffff;
897 regs->gpr[ra] += regs->gpr[rb];
898 break;
899
900 case OP_31_XOP_LBZX:
901 regs->gpr[rd] = 0xff;
902 break;
903
904 case OP_31_XOP_LBZUX:
905 regs->gpr[rd] = 0xff;
906 regs->gpr[ra] += regs->gpr[rb];
907 break;
908
909 case OP_31_XOP_LHZX:
910 case OP_31_XOP_LHBRX:
911 regs->gpr[rd] = 0xffff;
912 break;
913
914 case OP_31_XOP_LHZUX:
915 regs->gpr[rd] = 0xffff;
916 regs->gpr[ra] += regs->gpr[rb];
917 break;
918
919 case OP_31_XOP_LHAX:
920 regs->gpr[rd] = ~0UL;
921 break;
922
923 case OP_31_XOP_LHAUX:
924 regs->gpr[rd] = ~0UL;
925 regs->gpr[ra] += regs->gpr[rb];
926 break;
927
928 default:
929 return 0;
930 }
931 break;
932
933 case OP_LWZ:
934 regs->gpr[rd] = 0xffffffff;
935 break;
936
937 case OP_LWZU:
938 regs->gpr[rd] = 0xffffffff;
939 regs->gpr[ra] += (s16)d;
940 break;
941
942 case OP_LBZ:
943 regs->gpr[rd] = 0xff;
944 break;
945
946 case OP_LBZU:
947 regs->gpr[rd] = 0xff;
948 regs->gpr[ra] += (s16)d;
949 break;
950
951 case OP_LHZ:
952 regs->gpr[rd] = 0xffff;
953 break;
954
955 case OP_LHZU:
956 regs->gpr[rd] = 0xffff;
957 regs->gpr[ra] += (s16)d;
958 break;
959
960 case OP_LHA:
961 regs->gpr[rd] = ~0UL;
962 break;
963
964 case OP_LHAU:
965 regs->gpr[rd] = ~0UL;
966 regs->gpr[ra] += (s16)d;
967 break;
968
969 default:
970 return 0;
971 }
972
973 return 1;
974}
975
976static int is_in_pci_mem_space(phys_addr_t addr)
977{
978 struct pci_controller *hose;
979 struct resource *res;
980 int i;
981
982 list_for_each_entry(hose, &hose_list, list_node) {
983 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
984 continue;
985
986 for (i = 0; i < 3; i++) {
987 res = &hose->mem_resources[i];
988 if ((res->flags & IORESOURCE_MEM) &&
989 addr >= res->start && addr <= res->end)
990 return 1;
991 }
992 }
993 return 0;
994}
995
996int fsl_pci_mcheck_exception(struct pt_regs *regs)
997{
998 u32 inst;
999 int ret;
1000 phys_addr_t addr = 0;
1001
1002 /* Let KVM/QEMU deal with the exception */
1003 if (regs->msr & MSR_GS)
1004 return 0;
1005
1006#ifdef CONFIG_PHYS_64BIT
1007 addr = mfspr(SPRN_MCARU);
1008 addr <<= 32;
1009#endif
1010 addr += mfspr(SPRN_MCAR);
1011
1012 if (is_in_pci_mem_space(addr)) {
1013 if (user_mode(regs)) {
1014 pagefault_disable();
1015 ret = get_user(regs->nip, &inst);
1016 pagefault_enable();
1017 } else {
1018 ret = probe_kernel_address(regs->nip, inst);
1019 }
1020
1021 if (mcheck_handle_load(regs, inst)) {
1022 regs->nip += 4;
1023 return 1;
1024 }
1025 }
1026
1027 return 0;
1028}
1029#endif
1030
871#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 1031#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
872static const struct of_device_id pci_ids[] = { 1032static const struct of_device_id pci_ids[] = {
873 { .compatible = "fsl,mpc8540-pci", }, 1033 { .compatible = "fsl,mpc8540-pci", },
@@ -928,28 +1088,10 @@ static int fsl_pci_probe(struct platform_device *pdev)
928{ 1088{
929 int ret; 1089 int ret;
930 struct device_node *node; 1090 struct device_node *node;
931#ifdef CONFIG_SWIOTLB
932 struct pci_controller *hose;
933#endif
934 1091
935 node = pdev->dev.of_node; 1092 node = pdev->dev.of_node;
936 ret = fsl_add_bridge(pdev, fsl_pci_primary == node); 1093 ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
937 1094
938#ifdef CONFIG_SWIOTLB
939 if (ret == 0) {
940 hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
941
942 /*
943 * if we couldn't map all of DRAM via the dma windows
944 * we need SWIOTLB to handle buffers located outside of
945 * dma capable memory region
946 */
947 if (memblock_end_of_DRAM() - 1 > hose->dma_window_base_cur +
948 hose->dma_window_size)
949 ppc_swiotlb_enable = 1;
950 }
951#endif
952
953 mpc85xx_pci_err_probe(pdev); 1095 mpc85xx_pci_err_probe(pdev);
954 1096
955 return 0; 1097 return 0;
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index 72b5625330e2..defc422a375f 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -126,5 +126,11 @@ static inline int mpc85xx_pci_err_probe(struct platform_device *op)
126} 126}
127#endif 127#endif
128 128
129#ifdef CONFIG_FSL_PCI
130extern int fsl_pci_mcheck_exception(struct pt_regs *);
131#else
132static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
133#endif
134
129#endif /* __POWERPC_FSL_PCI_H */ 135#endif /* __POWERPC_FSL_PCI_H */
130#endif /* __KERNEL__ */ 136#endif /* __KERNEL__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-01 04:03:49 -0500