diff options
Diffstat (limited to 'arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c')
-rw-r--r-- | arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c | 41 |
1 files changed, 16 insertions, 25 deletions
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c index e64458a833e2..352f29d9226f 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c | |||
@@ -77,7 +77,7 @@ static inline void cic_wmb(void) | |||
77 | dummy_read++; | 77 | dummy_read++; |
78 | } | 78 | } |
79 | 79 | ||
80 | static inline void unmask_cic_irq(unsigned int irq) | 80 | static void unmask_cic_irq(struct irq_data *d) |
81 | { | 81 | { |
82 | volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG; | 82 | volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG; |
83 | int vpe; | 83 | int vpe; |
@@ -89,18 +89,18 @@ static inline void unmask_cic_irq(unsigned int irq) | |||
89 | * Make sure we have IRQ affinity. It may have changed while | 89 | * Make sure we have IRQ affinity. It may have changed while |
90 | * we were processing the IRQ. | 90 | * we were processing the IRQ. |
91 | */ | 91 | */ |
92 | if (!cpumask_test_cpu(smp_processor_id(), irq_desc[irq].affinity)) | 92 | if (!cpumask_test_cpu(smp_processor_id(), d->affinity)) |
93 | return; | 93 | return; |
94 | #endif | 94 | #endif |
95 | 95 | ||
96 | vpe = get_current_vpe(); | 96 | vpe = get_current_vpe(); |
97 | LOCK_VPE(flags, mtflags); | 97 | LOCK_VPE(flags, mtflags); |
98 | cic_msk_reg[vpe] |= (1 << (irq - MSP_CIC_INTBASE)); | 98 | cic_msk_reg[vpe] |= (1 << (d->irq - MSP_CIC_INTBASE)); |
99 | UNLOCK_VPE(flags, mtflags); | 99 | UNLOCK_VPE(flags, mtflags); |
100 | cic_wmb(); | 100 | cic_wmb(); |
101 | } | 101 | } |
102 | 102 | ||
103 | static inline void mask_cic_irq(unsigned int irq) | 103 | static void mask_cic_irq(struct irq_data *d) |
104 | { | 104 | { |
105 | volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG; | 105 | volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG; |
106 | int vpe = get_current_vpe(); | 106 | int vpe = get_current_vpe(); |
@@ -108,33 +108,27 @@ static inline void mask_cic_irq(unsigned int irq) | |||
108 | unsigned long flags, mtflags; | 108 | unsigned long flags, mtflags; |
109 | #endif | 109 | #endif |
110 | LOCK_VPE(flags, mtflags); | 110 | LOCK_VPE(flags, mtflags); |
111 | cic_msk_reg[vpe] &= ~(1 << (irq - MSP_CIC_INTBASE)); | 111 | cic_msk_reg[vpe] &= ~(1 << (d->irq - MSP_CIC_INTBASE)); |
112 | UNLOCK_VPE(flags, mtflags); | 112 | UNLOCK_VPE(flags, mtflags); |
113 | cic_wmb(); | 113 | cic_wmb(); |
114 | } | 114 | } |
115 | static inline void msp_cic_irq_ack(unsigned int irq) | 115 | static void msp_cic_irq_ack(struct irq_data *d) |
116 | { | 116 | { |
117 | mask_cic_irq(irq); | 117 | mask_cic_irq(d); |
118 | /* | 118 | /* |
119 | * Only really necessary for 18, 16-14 and sometimes 3:0 | 119 | * Only really necessary for 18, 16-14 and sometimes 3:0 |
120 | * (since these can be edge sensitive) but it doesn't | 120 | * (since these can be edge sensitive) but it doesn't |
121 | * hurt for the others | 121 | * hurt for the others |
122 | */ | 122 | */ |
123 | *CIC_STS_REG = (1 << (irq - MSP_CIC_INTBASE)); | 123 | *CIC_STS_REG = (1 << (d->irq - MSP_CIC_INTBASE)); |
124 | smtc_im_ack_irq(irq); | 124 | smtc_im_ack_irq(d->irq); |
125 | } | ||
126 | |||
127 | static void msp_cic_irq_end(unsigned int irq) | ||
128 | { | ||
129 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | ||
130 | unmask_cic_irq(irq); | ||
131 | } | 125 | } |
132 | 126 | ||
133 | /*Note: Limiting to VSMP . Not tested in SMTC */ | 127 | /*Note: Limiting to VSMP . Not tested in SMTC */ |
134 | 128 | ||
135 | #ifdef CONFIG_MIPS_MT_SMP | 129 | #ifdef CONFIG_MIPS_MT_SMP |
136 | static inline int msp_cic_irq_set_affinity(unsigned int irq, | 130 | static int msp_cic_irq_set_affinity(struct irq_data *d, |
137 | const struct cpumask *cpumask) | 131 | const struct cpumask *cpumask, bool force) |
138 | { | 132 | { |
139 | int cpu; | 133 | int cpu; |
140 | unsigned long flags; | 134 | unsigned long flags; |
@@ -163,13 +157,12 @@ static inline int msp_cic_irq_set_affinity(unsigned int irq, | |||
163 | 157 | ||
164 | static struct irq_chip msp_cic_irq_controller = { | 158 | static struct irq_chip msp_cic_irq_controller = { |
165 | .name = "MSP_CIC", | 159 | .name = "MSP_CIC", |
166 | .mask = mask_cic_irq, | 160 | .irq_mask = mask_cic_irq, |
167 | .mask_ack = msp_cic_irq_ack, | 161 | .irq_mask_ack = msp_cic_irq_ack, |
168 | .unmask = unmask_cic_irq, | 162 | .irq_unmask = unmask_cic_irq, |
169 | .ack = msp_cic_irq_ack, | 163 | .irq_ack = msp_cic_irq_ack, |
170 | .end = msp_cic_irq_end, | ||
171 | #ifdef CONFIG_MIPS_MT_SMP | 164 | #ifdef CONFIG_MIPS_MT_SMP |
172 | .set_affinity = msp_cic_irq_set_affinity, | 165 | .irq_set_affinity = msp_cic_irq_set_affinity, |
173 | #endif | 166 | #endif |
174 | }; | 167 | }; |
175 | 168 | ||
@@ -220,7 +213,5 @@ void msp_cic_irq_dispatch(void) | |||
220 | do_IRQ(ffs(pending) + MSP_CIC_INTBASE - 1); | 213 | do_IRQ(ffs(pending) + MSP_CIC_INTBASE - 1); |
221 | } else{ | 214 | } else{ |
222 | spurious_interrupt(); | 215 | spurious_interrupt(); |
223 | /* Re-enable the CIC cascaded interrupt. */ | ||
224 | irq_desc[MSP_INT_CIC].chip->end(MSP_INT_CIC); | ||
225 | } | 216 | } |
226 | } | 217 | } |