2 files changed, 10 insertions, 20 deletions

diff --git a/arch/ia64/include/asm/barrier.h b/arch/ia64/include/asm/barrier.h
index 209c4b817c95..588f1614cafc 100644
--- a/arch/ia64/include/asm/barrier.h
+++ b/arch/ia64/include/asm/barrier.h
@@ -42,34 +42,24 @@
 #define dma_rmb()       mb()
 #define dma_wmb()       mb()
 
-#ifdef CONFIG_SMP
-# define smp_mb()       mb()
-#else
-# define smp_mb()       barrier()
-#endif
+# define __smp_mb()     mb()
 
-#define smp_rmb()       smp_mb()
-#define smp_wmb()       smp_mb()
-
-#define read_barrier_depends()          do { } while (0)
-#define smp_read_barrier_depends()      do { } while (0)
-
-#define smp_mb__before_atomic() barrier()
-#define smp_mb__after_atomic()  barrier()
+#define __smp_mb__before_atomic()       barrier()
+#define __smp_mb__after_atomic()        barrier()
 
 /*
  * IA64 GCC turns volatile stores into st.rel and volatile loads into ld.acq no
  * need for asm trickery!
  */
 
-#define smp_store_release(p, v)                                         \
+#define __smp_store_release(p, v)                                               \
 do {                                                                    \
         compiletime_assert_atomic_type(*p);                             \
         barrier();                                                      \
         WRITE_ONCE(*p, v);                                              \
 } while (0)
 
-#define smp_load_acquire(p)                                             \
+#define __smp_load_acquire(p)                                           \
 ({                                                                      \
         typeof(*p) ___p1 = READ_ONCE(*p);                               \
         compiletime_assert_atomic_type(*p);                             \
@@ -77,12 +67,12 @@ do {									\
         ___p1;                                                          \
 })
 
-#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0)
-
 /*
  * The group barrier in front of the rsm & ssm are necessary to ensure
  * that none of the previous instructions in the same group are
  * affected by the rsm/ssm.
  */
 
+#include <asm-generic/barrier.h>
+
 #endif /* _ASM_IA64_BARRIER_H */
diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c
index d2fae054d988..90fde5b8669d 100644
--- a/arch/ia64/kernel/iosapic.c
+++ b/arch/ia64/kernel/iosapic.c
@@ -256,7 +256,7 @@ set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask)
 }
 
 static void
-nop (struct irq_data *data)
+iosapic_nop (struct irq_data *data)
 {
         /* do nothing... */
 }
@@ -415,7 +415,7 @@ iosapic_unmask_level_irq (struct irq_data *data)
 #define iosapic_shutdown_level_irq      mask_irq
 #define iosapic_enable_level_irq        unmask_irq
 #define iosapic_disable_level_irq       mask_irq
-#define iosapic_ack_level_irq           nop
+#define iosapic_ack_level_irq           iosapic_nop
 
 static struct irq_chip irq_type_iosapic_level = {
         .name =                 "IO-SAPIC-level",
@@ -453,7 +453,7 @@ iosapic_ack_edge_irq (struct irq_data *data)
 }
 
 #define iosapic_enable_edge_irq         unmask_irq
-#define iosapic_disable_edge_irq        nop
+#define iosapic_disable_edge_irq        iosapic_nop
 
 static struct irq_chip irq_type_iosapic_edge = {
         .name =                 "IO-SAPIC-edge",