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-rw-r--r--arch/arm/mach-zynq/timer.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index 2b23d0fae934..7b2e04776a54 100644
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -36,7 +36,8 @@
36 36
37#define XTTCPS_CNT_CNTRL_DISABLE_MASK 0x1 37#define XTTCPS_CNT_CNTRL_DISABLE_MASK 0x1
38 38
39/* Setup the timers to use pre-scaling, using a fixed value for now that will 39/*
40 * Setup the timers to use pre-scaling, using a fixed value for now that will
40 * work across most input frequency, but it may need to be more dynamic 41 * work across most input frequency, but it may need to be more dynamic
41 */ 42 */
42#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ 43#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
@@ -89,8 +90,10 @@ static void xttcps_set_interval(struct xttcps_timer *timer,
89 90
90 __raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET); 91 __raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);
91 92
92 /* Reset the counter (0x10) so that it starts from 0, one-shot 93 /*
93 mode makes this needed for timing to be right. */ 94 * Reset the counter (0x10) so that it starts from 0, one-shot
95 * mode makes this needed for timing to be right.
96 */
94 ctrl_reg |= CNT_CNTRL_RESET; 97 ctrl_reg |= CNT_CNTRL_RESET;
95 ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK; 98 ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
96 __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); 99 __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);