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-rw-r--r--arch/arm/mach-s3c2440/clock.c44
-rw-r--r--arch/arm/mach-s3c2440/mach-anubis.c22
-rw-r--r--arch/arm/mach-s3c2440/mach-at2440evb.c22
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris.c24
-rw-r--r--arch/arm/mach-s3c2440/mach-rx1950.c18
-rw-r--r--arch/arm/mach-s3c2440/mach-rx3715.c19
6 files changed, 57 insertions, 92 deletions
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index f9e6bdaf41d2..c9879af42b08 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -34,6 +34,7 @@
34#include <linux/mutex.h> 34#include <linux/mutex.h>
35#include <linux/clk.h> 35#include <linux/clk.h>
36#include <linux/io.h> 36#include <linux/io.h>
37#include <linux/serial_core.h>
37 38
38#include <mach/hardware.h> 39#include <mach/hardware.h>
39#include <linux/atomic.h> 40#include <linux/atomic.h>
@@ -43,6 +44,7 @@
43 44
44#include <plat/clock.h> 45#include <plat/clock.h>
45#include <plat/cpu.h> 46#include <plat/cpu.h>
47#include <plat/regs-serial.h>
46 48
47/* S3C2440 extended clock support */ 49/* S3C2440 extended clock support */
48 50
@@ -108,6 +110,46 @@ static struct clk s3c2440_clk_ac97 = {
108 .ctrlbit = S3C2440_CLKCON_CAMERA, 110 .ctrlbit = S3C2440_CLKCON_CAMERA,
109}; 111};
110 112
113static unsigned long s3c2440_fclk_n_getrate(struct clk *clk)
114{
115 unsigned long ucon0, ucon1, ucon2, divisor;
116
117 /* the fun of calculating the uart divisors on the s3c2440 */
118 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
119 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
120 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
121
122 ucon0 &= S3C2440_UCON0_DIVMASK;
123 ucon1 &= S3C2440_UCON1_DIVMASK;
124 ucon2 &= S3C2440_UCON2_DIVMASK;
125
126 if (ucon0 != 0)
127 divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
128 else if (ucon1 != 0)
129 divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
130 else if (ucon2 != 0)
131 divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
132 else
133 /* manual calims 44, seems to be 9 */
134 divisor = 9;
135
136 return clk_get_rate(clk->parent) / divisor;
137}
138
139static struct clk s3c2440_clk_fclk_n = {
140 .name = "fclk_n",
141 .parent = &clk_f,
142 .ops = &(struct clk_ops) {
143 .get_rate = s3c2440_fclk_n_getrate,
144 },
145};
146
147static struct clk_lookup s3c2440_clk_lookup[] = {
148 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
149 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
150 CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
151};
152
111static int s3c2440_clk_add(struct sys_device *sysdev) 153static int s3c2440_clk_add(struct sys_device *sysdev)
112{ 154{
113 struct clk *clock_upll; 155 struct clk *clock_upll;
@@ -126,10 +168,12 @@ static int s3c2440_clk_add(struct sys_device *sysdev)
126 s3c2440_clk_cam.parent = clock_h; 168 s3c2440_clk_cam.parent = clock_h;
127 s3c2440_clk_ac97.parent = clock_p; 169 s3c2440_clk_ac97.parent = clock_p;
128 s3c2440_clk_cam_upll.parent = clock_upll; 170 s3c2440_clk_cam_upll.parent = clock_upll;
171 s3c24xx_register_clock(&s3c2440_clk_fclk_n);
129 172
130 s3c24xx_register_clock(&s3c2440_clk_ac97); 173 s3c24xx_register_clock(&s3c2440_clk_ac97);
131 s3c24xx_register_clock(&s3c2440_clk_cam); 174 s3c24xx_register_clock(&s3c2440_clk_cam);
132 s3c24xx_register_clock(&s3c2440_clk_cam_upll); 175 s3c24xx_register_clock(&s3c2440_clk_cam_upll);
176 clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));
133 177
134 clk_disable(&s3c2440_clk_ac97); 178 clk_disable(&s3c2440_clk_ac97);
135 clk_disable(&s3c2440_clk_cam); 179 clk_disable(&s3c2440_clk_cam);
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 74f92fc3fd04..d8f36c0a16ad 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -96,22 +96,6 @@ static struct map_desc anubis_iodesc[] __initdata = {
96#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB 96#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
97#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE 97#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
98 98
99static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
100 [0] = {
101 .name = "uclk",
102 .divisor = 1,
103 .min_baud = 0,
104 .max_baud = 0,
105 },
106 [1] = {
107 .name = "pclk",
108 .divisor = 1,
109 .min_baud = 0,
110 .max_baud = 0,
111 }
112};
113
114
115static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = { 99static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
116 [0] = { 100 [0] = {
117 .hwport = 0, 101 .hwport = 0,
@@ -119,8 +103,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
119 .ucon = UCON, 103 .ucon = UCON,
120 .ulcon = ULCON, 104 .ulcon = ULCON,
121 .ufcon = UFCON, 105 .ufcon = UFCON,
122 .clocks = anubis_serial_clocks, 106 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
123 .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
124 }, 107 },
125 [1] = { 108 [1] = {
126 .hwport = 2, 109 .hwport = 2,
@@ -128,8 +111,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
128 .ucon = UCON, 111 .ucon = UCON,
129 .ulcon = ULCON, 112 .ulcon = ULCON,
130 .ufcon = UFCON, 113 .ufcon = UFCON,
131 .clocks = anubis_serial_clocks, 114 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
132 .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
133 }, 115 },
134}; 116};
135 117
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 38887ee0c784..aa86ca8fa1e9 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -57,22 +57,6 @@ static struct map_desc at2440evb_iodesc[] __initdata = {
57#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) 57#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
58#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) 58#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
59 59
60static struct s3c24xx_uart_clksrc at2440evb_serial_clocks[] = {
61 [0] = {
62 .name = "uclk",
63 .divisor = 1,
64 .min_baud = 0,
65 .max_baud = 0,
66 },
67 [1] = {
68 .name = "pclk",
69 .divisor = 1,
70 .min_baud = 0,
71 .max_baud = 0,
72 }
73};
74
75
76static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = { 60static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
77 [0] = { 61 [0] = {
78 .hwport = 0, 62 .hwport = 0,
@@ -80,8 +64,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
80 .ucon = UCON, 64 .ucon = UCON,
81 .ulcon = ULCON, 65 .ulcon = ULCON,
82 .ufcon = UFCON, 66 .ufcon = UFCON,
83 .clocks = at2440evb_serial_clocks, 67 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
84 .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
85 }, 68 },
86 [1] = { 69 [1] = {
87 .hwport = 1, 70 .hwport = 1,
@@ -89,8 +72,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
89 .ucon = UCON, 72 .ucon = UCON,
90 .ulcon = ULCON, 73 .ulcon = ULCON,
91 .ufcon = UFCON, 74 .ufcon = UFCON,
92 .clocks = at2440evb_serial_clocks, 75 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
93 .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
94 }, 76 },
95}; 77};
96 78
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index dc142ebf8cba..d7e47b2b6ec9 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -100,21 +100,6 @@ static struct map_desc osiris_iodesc[] __initdata = {
100#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB 100#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
101#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE 101#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
102 102
103static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
104 [0] = {
105 .name = "uclk",
106 .divisor = 1,
107 .min_baud = 0,
108 .max_baud = 0,
109 },
110 [1] = {
111 .name = "pclk",
112 .divisor = 1,
113 .min_baud = 0,
114 .max_baud = 0,
115 }
116};
117
118static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { 103static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
119 [0] = { 104 [0] = {
120 .hwport = 0, 105 .hwport = 0,
@@ -122,8 +107,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
122 .ucon = UCON, 107 .ucon = UCON,
123 .ulcon = ULCON, 108 .ulcon = ULCON,
124 .ufcon = UFCON, 109 .ufcon = UFCON,
125 .clocks = osiris_serial_clocks, 110 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
126 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
127 }, 111 },
128 [1] = { 112 [1] = {
129 .hwport = 1, 113 .hwport = 1,
@@ -131,8 +115,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
131 .ucon = UCON, 115 .ucon = UCON,
132 .ulcon = ULCON, 116 .ulcon = ULCON,
133 .ufcon = UFCON, 117 .ufcon = UFCON,
134 .clocks = osiris_serial_clocks, 118 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
135 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
136 }, 119 },
137 [2] = { 120 [2] = {
138 .hwport = 2, 121 .hwport = 2,
@@ -140,8 +123,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
140 .ucon = UCON, 123 .ucon = UCON,
141 .ulcon = ULCON, 124 .ulcon = ULCON,
142 .ufcon = UFCON, 125 .ufcon = UFCON,
143 .clocks = osiris_serial_clocks, 126 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
144 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
145 } 127 }
146}; 128};
147 129
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 0d3453bf567c..4267cd56bfe7 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -68,15 +68,6 @@
68static struct map_desc rx1950_iodesc[] __initdata = { 68static struct map_desc rx1950_iodesc[] __initdata = {
69}; 69};
70 70
71static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = {
72 [0] = {
73 .name = "fclk",
74 .divisor = 0x0a,
75 .min_baud = 0,
76 .max_baud = 0,
77 },
78};
79
80static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { 71static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
81 [0] = { 72 [0] = {
82 .hwport = 0, 73 .hwport = 0,
@@ -84,8 +75,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
84 .ucon = 0x3c5, 75 .ucon = 0x3c5,
85 .ulcon = 0x03, 76 .ulcon = 0x03,
86 .ufcon = 0x51, 77 .ufcon = 0x51,
87 .clocks = rx1950_serial_clocks, 78 .clk_sel = S3C2410_UCON_CLKSEL3,
88 .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
89 }, 79 },
90 [1] = { 80 [1] = {
91 .hwport = 1, 81 .hwport = 1,
@@ -93,8 +83,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
93 .ucon = 0x3c5, 83 .ucon = 0x3c5,
94 .ulcon = 0x03, 84 .ulcon = 0x03,
95 .ufcon = 0x51, 85 .ufcon = 0x51,
96 .clocks = rx1950_serial_clocks, 86 .clk_sel = S3C2410_UCON_CLKSEL3,
97 .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
98 }, 87 },
99 /* IR port */ 88 /* IR port */
100 [2] = { 89 [2] = {
@@ -103,8 +92,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
103 .ucon = 0x3c5, 92 .ucon = 0x3c5,
104 .ulcon = 0x43, 93 .ulcon = 0x43,
105 .ufcon = 0xf1, 94 .ufcon = 0xf1,
106 .clocks = rx1950_serial_clocks, 95 .clk_sel = S3C2410_UCON_CLKSEL3,
107 .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
108 }, 96 },
109}; 97};
110 98
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index e19499c2f909..3d5e2e67971e 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -67,16 +67,6 @@ static struct map_desc rx3715_iodesc[] __initdata = {
67 }, 67 },
68}; 68};
69 69
70
71static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
72 [0] = {
73 .name = "fclk",
74 .divisor = 0,
75 .min_baud = 0,
76 .max_baud = 0,
77 }
78};
79
80static struct s3c2410_uartcfg rx3715_uartcfgs[] = { 70static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
81 [0] = { 71 [0] = {
82 .hwport = 0, 72 .hwport = 0,
@@ -84,8 +74,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
84 .ucon = 0x3c5, 74 .ucon = 0x3c5,
85 .ulcon = 0x03, 75 .ulcon = 0x03,
86 .ufcon = 0x51, 76 .ufcon = 0x51,
87 .clocks = rx3715_serial_clocks, 77 .clk_sel = S3C2410_UCON_CLKSEL3,
88 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
89 }, 78 },
90 [1] = { 79 [1] = {
91 .hwport = 1, 80 .hwport = 1,
@@ -93,8 +82,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
93 .ucon = 0x3c5, 82 .ucon = 0x3c5,
94 .ulcon = 0x03, 83 .ulcon = 0x03,
95 .ufcon = 0x00, 84 .ufcon = 0x00,
96 .clocks = rx3715_serial_clocks, 85 .clk_sel = S3C2410_UCON_CLKSEL3,
97 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
98 }, 86 },
99 /* IR port */ 87 /* IR port */
100 [2] = { 88 [2] = {
@@ -103,8 +91,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
103 .ucon = 0x3c5, 91 .ucon = 0x3c5,
104 .ulcon = 0x43, 92 .ulcon = 0x43,
105 .ufcon = 0x51, 93 .ufcon = 0x51,
106 .clocks = rx3715_serial_clocks, 94 .clk_sel = S3C2410_UCON_CLKSEL3,
107 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
108 } 95 }
109}; 96};
110 97
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-03 05:59:47 -0500