diff options
Diffstat (limited to 'arch/arm/mach-highbank/sysregs.h')
-rw-r--r-- | arch/arm/mach-highbank/sysregs.h | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/arch/arm/mach-highbank/sysregs.h b/arch/arm/mach-highbank/sysregs.h index e13e8ea7c6cb..70af9d13fcef 100644 --- a/arch/arm/mach-highbank/sysregs.h +++ b/arch/arm/mach-highbank/sysregs.h | |||
@@ -44,28 +44,43 @@ static inline void highbank_set_core_pwr(void) | |||
44 | writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu)); | 44 | writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu)); |
45 | } | 45 | } |
46 | 46 | ||
47 | static inline void hignbank_set_pwr_suspend(void) | 47 | static inline void highbank_clear_core_pwr(void) |
48 | { | ||
49 | int cpu = cpu_logical_map(smp_processor_id()); | ||
50 | if (scu_base_addr) | ||
51 | scu_power_mode(scu_base_addr, SCU_PM_NORMAL); | ||
52 | else | ||
53 | writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu)); | ||
54 | } | ||
55 | |||
56 | static inline void highbank_set_pwr_suspend(void) | ||
48 | { | 57 | { |
49 | writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ); | 58 | writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ); |
50 | highbank_set_core_pwr(); | 59 | highbank_set_core_pwr(); |
51 | } | 60 | } |
52 | 61 | ||
53 | static inline void hignbank_set_pwr_shutdown(void) | 62 | static inline void highbank_set_pwr_shutdown(void) |
54 | { | 63 | { |
55 | writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ); | 64 | writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ); |
56 | highbank_set_core_pwr(); | 65 | highbank_set_core_pwr(); |
57 | } | 66 | } |
58 | 67 | ||
59 | static inline void hignbank_set_pwr_soft_reset(void) | 68 | static inline void highbank_set_pwr_soft_reset(void) |
60 | { | 69 | { |
61 | writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ); | 70 | writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ); |
62 | highbank_set_core_pwr(); | 71 | highbank_set_core_pwr(); |
63 | } | 72 | } |
64 | 73 | ||
65 | static inline void hignbank_set_pwr_hard_reset(void) | 74 | static inline void highbank_set_pwr_hard_reset(void) |
66 | { | 75 | { |
67 | writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ); | 76 | writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ); |
68 | highbank_set_core_pwr(); | 77 | highbank_set_core_pwr(); |
69 | } | 78 | } |
70 | 79 | ||
80 | static inline void highbank_clear_pwr_request(void) | ||
81 | { | ||
82 | writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ); | ||
83 | highbank_clear_core_pwr(); | ||
84 | } | ||
85 | |||
71 | #endif | 86 | #endif |