diff options
Diffstat (limited to 'arch/arm/boot/dts/socfpga.dtsi')
-rw-r--r-- | arch/arm/boot/dts/socfpga.dtsi | 46 |
1 files changed, 39 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 80f924deed37..314e589cfa00 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi | |||
@@ -164,7 +164,7 @@ | |||
164 | dbg_base_clk: dbg_base_clk { | 164 | dbg_base_clk: dbg_base_clk { |
165 | #clock-cells = <0>; | 165 | #clock-cells = <0>; |
166 | compatible = "altr,socfpga-perip-clk"; | 166 | compatible = "altr,socfpga-perip-clk"; |
167 | clocks = <&main_pll>; | 167 | clocks = <&main_pll>, <&osc1>; |
168 | div-reg = <0xe8 0 9>; | 168 | div-reg = <0xe8 0 9>; |
169 | reg = <0x50>; | 169 | reg = <0x50>; |
170 | }; | 170 | }; |
@@ -318,7 +318,7 @@ | |||
318 | l3_sp_clk: l3_sp_clk { | 318 | l3_sp_clk: l3_sp_clk { |
319 | #clock-cells = <0>; | 319 | #clock-cells = <0>; |
320 | compatible = "altr,socfpga-gate-clk"; | 320 | compatible = "altr,socfpga-gate-clk"; |
321 | clocks = <&mainclk>; | 321 | clocks = <&l3_mp_clk>; |
322 | div-reg = <0x64 2 2>; | 322 | div-reg = <0x64 2 2>; |
323 | }; | 323 | }; |
324 | 324 | ||
@@ -349,7 +349,7 @@ | |||
349 | dbg_clk: dbg_clk { | 349 | dbg_clk: dbg_clk { |
350 | #clock-cells = <0>; | 350 | #clock-cells = <0>; |
351 | compatible = "altr,socfpga-gate-clk"; | 351 | compatible = "altr,socfpga-gate-clk"; |
352 | clocks = <&dbg_base_clk>; | 352 | clocks = <&dbg_at_clk>; |
353 | div-reg = <0x68 2 2>; | 353 | div-reg = <0x68 2 2>; |
354 | clk-gate = <0x60 5>; | 354 | clk-gate = <0x60 5>; |
355 | }; | 355 | }; |
@@ -481,8 +481,37 @@ | |||
481 | clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; | 481 | clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; |
482 | clk-gate = <0xa0 11>; | 482 | clk-gate = <0xa0 11>; |
483 | }; | 483 | }; |
484 | |||
485 | ddr_dqs_clk_gate: ddr_dqs_clk_gate { | ||
486 | #clock-cells = <0>; | ||
487 | compatible = "altr,socfpga-gate-clk"; | ||
488 | clocks = <&ddr_dqs_clk>; | ||
489 | clk-gate = <0xd8 0>; | ||
490 | }; | ||
491 | |||
492 | ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { | ||
493 | #clock-cells = <0>; | ||
494 | compatible = "altr,socfpga-gate-clk"; | ||
495 | clocks = <&ddr_2x_dqs_clk>; | ||
496 | clk-gate = <0xd8 1>; | ||
497 | }; | ||
498 | |||
499 | ddr_dq_clk_gate: ddr_dq_clk_gate { | ||
500 | #clock-cells = <0>; | ||
501 | compatible = "altr,socfpga-gate-clk"; | ||
502 | clocks = <&ddr_dq_clk>; | ||
503 | clk-gate = <0xd8 2>; | ||
504 | }; | ||
505 | |||
506 | h2f_user2_clk: h2f_user2_clk { | ||
507 | #clock-cells = <0>; | ||
508 | compatible = "altr,socfpga-gate-clk"; | ||
509 | clocks = <&h2f_usr2_clk>; | ||
510 | clk-gate = <0xd8 3>; | ||
511 | }; | ||
512 | |||
484 | }; | 513 | }; |
485 | }; | 514 | }; |
486 | 515 | ||
487 | gmac0: ethernet@ff700000 { | 516 | gmac0: ethernet@ff700000 { |
488 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; | 517 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; |
@@ -565,7 +594,7 @@ | |||
565 | #size-cells = <0>; | 594 | #size-cells = <0>; |
566 | compatible = "snps,dw-apb-gpio"; | 595 | compatible = "snps,dw-apb-gpio"; |
567 | reg = <0xff708000 0x1000>; | 596 | reg = <0xff708000 0x1000>; |
568 | clocks = <&per_base_clk>; | 597 | clocks = <&l4_mp_clk>; |
569 | status = "disabled"; | 598 | status = "disabled"; |
570 | 599 | ||
571 | porta: gpio-controller@0 { | 600 | porta: gpio-controller@0 { |
@@ -585,7 +614,7 @@ | |||
585 | #size-cells = <0>; | 614 | #size-cells = <0>; |
586 | compatible = "snps,dw-apb-gpio"; | 615 | compatible = "snps,dw-apb-gpio"; |
587 | reg = <0xff709000 0x1000>; | 616 | reg = <0xff709000 0x1000>; |
588 | clocks = <&per_base_clk>; | 617 | clocks = <&l4_mp_clk>; |
589 | status = "disabled"; | 618 | status = "disabled"; |
590 | 619 | ||
591 | portb: gpio-controller@0 { | 620 | portb: gpio-controller@0 { |
@@ -605,7 +634,7 @@ | |||
605 | #size-cells = <0>; | 634 | #size-cells = <0>; |
606 | compatible = "snps,dw-apb-gpio"; | 635 | compatible = "snps,dw-apb-gpio"; |
607 | reg = <0xff70a000 0x1000>; | 636 | reg = <0xff70a000 0x1000>; |
608 | clocks = <&per_base_clk>; | 637 | clocks = <&l4_mp_clk>; |
609 | status = "disabled"; | 638 | status = "disabled"; |
610 | 639 | ||
611 | portc: gpio-controller@0 { | 640 | portc: gpio-controller@0 { |
@@ -639,6 +668,8 @@ | |||
639 | cache-level = <2>; | 668 | cache-level = <2>; |
640 | arm,tag-latency = <1 1 1>; | 669 | arm,tag-latency = <1 1 1>; |
641 | arm,data-latency = <2 1 1>; | 670 | arm,data-latency = <2 1 1>; |
671 | prefetch-data = <1>; | ||
672 | prefetch-instr = <1>; | ||
642 | }; | 673 | }; |
643 | 674 | ||
644 | mmc: dwmmc0@ff704000 { | 675 | mmc: dwmmc0@ff704000 { |
@@ -752,6 +783,7 @@ | |||
752 | #reset-cells = <1>; | 783 | #reset-cells = <1>; |
753 | compatible = "altr,rst-mgr"; | 784 | compatible = "altr,rst-mgr"; |
754 | reg = <0xffd05000 0x1000>; | 785 | reg = <0xffd05000 0x1000>; |
786 | altr,modrst-offset = <0x10>; | ||
755 | }; | 787 | }; |
756 | 788 | ||
757 | usbphy0: usbphy@0 { | 789 | usbphy0: usbphy@0 { |