diff options
Diffstat (limited to 'arch/arc/Kconfig')
-rw-r--r-- | arch/arc/Kconfig | 39 |
1 files changed, 38 insertions, 1 deletions
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 68350aa3d297..52f5c072f6da 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig | |||
@@ -116,9 +116,42 @@ config CPU_BIG_ENDIAN | |||
116 | help | 116 | help |
117 | Build kernel for Big Endian Mode of ARC CPU | 117 | Build kernel for Big Endian Mode of ARC CPU |
118 | 118 | ||
119 | config SMP | ||
120 | bool "Symmetric Multi-Processing (Incomplete)" | ||
121 | default n | ||
122 | select USE_GENERIC_SMP_HELPERS | ||
123 | help | ||
124 | This enables support for systems with more than one CPU. If you have | ||
125 | a system with only one CPU, like most personal computers, say N. If | ||
126 | you have a system with more than one CPU, say Y. | ||
127 | |||
128 | if SMP | ||
129 | |||
130 | config ARC_HAS_COH_CACHES | ||
131 | def_bool n | ||
132 | |||
133 | config ARC_HAS_COH_LLSC | ||
134 | def_bool n | ||
135 | |||
136 | config ARC_HAS_COH_RTSC | ||
137 | def_bool n | ||
138 | |||
139 | config ARC_HAS_REENTRANT_IRQ_LV2 | ||
140 | def_bool n | ||
141 | |||
142 | endif | ||
143 | |||
144 | config NR_CPUS | ||
145 | int "Maximum number of CPUs (2-32)" | ||
146 | range 2 32 | ||
147 | depends on SMP | ||
148 | default "2" | ||
149 | |||
119 | menuconfig ARC_CACHE | 150 | menuconfig ARC_CACHE |
120 | bool "Enable Cache Support" | 151 | bool "Enable Cache Support" |
121 | default y | 152 | default y |
153 | # if SMP, cache enabled ONLY if ARC implementation has cache coherency | ||
154 | depends on !SMP || ARC_HAS_COH_CACHES | ||
122 | 155 | ||
123 | if ARC_CACHE | 156 | if ARC_CACHE |
124 | 157 | ||
@@ -213,6 +246,8 @@ config ARC_COMPACT_IRQ_LEVELS | |||
213 | default n | 246 | default n |
214 | # Timer HAS to be high priority, for any other high priority config | 247 | # Timer HAS to be high priority, for any other high priority config |
215 | select ARC_IRQ3_LV2 | 248 | select ARC_IRQ3_LV2 |
249 | # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy | ||
250 | depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2 | ||
216 | 251 | ||
217 | if ARC_COMPACT_IRQ_LEVELS | 252 | if ARC_COMPACT_IRQ_LEVELS |
218 | 253 | ||
@@ -261,6 +296,8 @@ config ARC_HAS_RTSC | |||
261 | bool "Insn: RTSC (64-bit r/o cycle counter)" | 296 | bool "Insn: RTSC (64-bit r/o cycle counter)" |
262 | default y | 297 | default y |
263 | depends on ARC_CPU_REL_4_10 | 298 | depends on ARC_CPU_REL_4_10 |
299 | # if SMP, enable RTSC only if counter is coherent across cores | ||
300 | depends on !SMP || ARC_HAS_COH_RTSC | ||
264 | 301 | ||
265 | endmenu # "ARC CPU Configuration" | 302 | endmenu # "ARC CPU Configuration" |
266 | 303 | ||
@@ -309,7 +346,7 @@ menuconfig ARC_DBG | |||
309 | 346 | ||
310 | config ARC_DBG_TLB_PARANOIA | 347 | config ARC_DBG_TLB_PARANOIA |
311 | bool "Paranoia Checks in Low Level TLB Handlers" | 348 | bool "Paranoia Checks in Low Level TLB Handlers" |
312 | depends on ARC_DBG | 349 | depends on ARC_DBG && !SMP |
313 | default n | 350 | default n |
314 | 351 | ||
315 | config ARC_DBG_TLB_MISS_COUNT | 352 | config ARC_DBG_TLB_MISS_COUNT |