3 files changed, 241 insertions, 4 deletions

diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index 2da059a4790c..cc56021eb60b 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -11,13 +11,14 @@ have PPIs or SGIs.
 Main node required properties:
 
 - compatible : should be one of:
-        "arm,gic-400"
+        "arm,arm1176jzf-devchip-gic"
+        "arm,arm11mp-gic"
         "arm,cortex-a15-gic"
-        "arm,cortex-a9-gic"
         "arm,cortex-a7-gic"
-        "arm,arm11mp-gic"
+        "arm,cortex-a9-gic"
+        "arm,gic-400"
+        "arm,pl390"
         "brcm,brahma-b15-gic"
-        "arm,arm1176jzf-devchip-gic"
         "qcom,msm-8660-qgic"
         "qcom,msm-qgic2"
 - interrupt-controller : Identifies the node as an interrupt controller
@@ -58,6 +59,21 @@ Optional
   regions, used when the GIC doesn't have banked registers. The offset is
   cpu-offset * cpu-nr.
 
+- clocks        : List of phandle and clock-specific pairs, one for each entry
+  in clock-names.
+- clock-names   : List of names for the GIC clock input(s). Valid clock names
+  depend on the GIC variant:
+        "ic_clk" (for "arm,arm11mp-gic")
+        "PERIPHCLKEN" (for "arm,cortex-a15-gic")
+        "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic")
+        "clk" (for "arm,gic-400")
+        "gclk" (for "arm,pl390")
+
+- power-domains : A phandle and PM domain specifier as defined by bindings of
+                  the power controller specified by phandle, used when the GIC
+                  is part of a Power or Clock Domain.
+
+
 Example:
 
         intc: interrupt-controller@fff11000 {
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
index 63633bdea7e4..ae5054c27c99 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
@@ -10,6 +10,7 @@ Required properties:
     - "renesas,irqc-r8a7792" (R-Car V2H)
     - "renesas,irqc-r8a7793" (R-Car M2-N)
     - "renesas,irqc-r8a7794" (R-Car E2)
+    - "renesas,intc-ex-r8a7795" (R-Car H3)
 - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
   interrupts.txt in this directory
 - clocks: Must contain a reference to the functional clock.
diff --git a/Documentation/devicetree/bindings/pci/pci-msi.txt b/Documentation/devicetree/bindings/pci/pci-msi.txt
new file mode 100644
index 000000000000..9b3cc817d181
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/pci-msi.txt
@@ -0,0 +1,220 @@
+This document describes the generic device tree binding for describing the
+relationship between PCI devices and MSI controllers.
+
+Each PCI device under a root complex is uniquely identified by its Requester ID
+(AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
+Function number.
+
+For the purpose of this document, when treated as a numeric value, a RID is
+formatted such that:
+
+* Bits [15:8] are the Bus number.
+* Bits [7:3] are the Device number.
+* Bits [2:0] are the Function number.
+* Any other bits required for padding must be zero.
+
+MSIs may be distinguished in part through the use of sideband data accompanying
+writes. In the case of PCI devices, this sideband data may be derived from the
+Requester ID. A mechanism is required to associate a device with both the MSI
+controllers it can address, and the sideband data that will be associated with
+its writes to those controllers.
+
+For generic MSI bindings, see
+Documentation/devicetree/bindings/interrupt-controller/msi.txt.
+
+
+PCI root complex
+================
+
+Optional properties
+-------------------
+
+- msi-map: Maps a Requester ID to an MSI controller and associated
+  msi-specifier data. The property is an arbitrary number of tuples of
+  (rid-base,msi-controller,msi-base,length), where:
+
+  * rid-base is a single cell describing the first RID matched by the entry.
+
+  * msi-controller is a single phandle to an MSI controller
+
+  * msi-base is an msi-specifier describing the msi-specifier produced for the
+    first RID matched by the entry.
+
+  * length is a single cell describing how many consecutive RIDs are matched
+    following the rid-base.
+
+  Any RID r in the interval [rid-base, rid-base + length) is associated with
+  the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
+
+- msi-map-mask: A mask to be applied to each Requester ID prior to being mapped
+  to an msi-specifier per the msi-map property.
+
+- msi-parent: Describes the MSI parent of the root complex itself. Where
+  the root complex and MSI controller do not pass sideband data with MSI
+  writes, this property may be used to describe the MSI controller(s)
+  used by PCI devices under the root complex, if defined as such in the
+  binding for the root complex.
+
+
+Example (1)
+===========
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        msi: msi-controller@a {
+                reg = <0xa 0x1>;
+                compatible = "vendor,some-controller";
+                msi-controller;
+                #msi-cells = <1>;
+        };
+
+        pci: pci@f {
+                reg = <0xf 0x1>;
+                compatible = "vendor,pcie-root-complex";
+                device_type = "pci";
+
+                /*
+                 * The sideband data provided to the MSI controller is
+                 * the RID, identity-mapped.
+                 */
+                msi-map = <0x0 &msi_a 0x0 0x10000>,
+        };
+};
+
+
+Example (2)
+===========
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        msi: msi-controller@a {
+                reg = <0xa 0x1>;
+                compatible = "vendor,some-controller";
+                msi-controller;
+                #msi-cells = <1>;
+        };
+
+        pci: pci@f {
+                reg = <0xf 0x1>;
+                compatible = "vendor,pcie-root-complex";
+                device_type = "pci";
+
+                /*
+                 * The sideband data provided to the MSI controller is
+                 * the RID, masked to only the device and function bits.
+                 */
+                msi-map = <0x0 &msi_a 0x0 0x100>,
+                msi-map-mask = <0xff>
+        };
+};
+
+
+Example (3)
+===========
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        msi: msi-controller@a {
+                reg = <0xa 0x1>;
+                compatible = "vendor,some-controller";
+                msi-controller;
+                #msi-cells = <1>;
+        };
+
+        pci: pci@f {
+                reg = <0xf 0x1>;
+                compatible = "vendor,pcie-root-complex";
+                device_type = "pci";
+
+                /*
+                 * The sideband data provided to the MSI controller is
+                 * the RID, but the high bit of the bus number is
+                 * ignored.
+                 */
+                msi-map = <0x0000 &msi 0x0000 0x8000>,
+                          <0x8000 &msi 0x0000 0x8000>;
+        };
+};
+
+
+Example (4)
+===========
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        msi: msi-controller@a {
+                reg = <0xa 0x1>;
+                compatible = "vendor,some-controller";
+                msi-controller;
+                #msi-cells = <1>;
+        };
+
+        pci: pci@f {
+                reg = <0xf 0x1>;
+                compatible = "vendor,pcie-root-complex";
+                device_type = "pci";
+
+                /*
+                 * The sideband data provided to the MSI controller is
+                 * the RID, but the high bit of the bus number is
+                 * negated.
+                 */
+                msi-map = <0x0000 &msi 0x8000 0x8000>,
+                          <0x8000 &msi 0x0000 0x8000>;
+        };
+};
+
+
+Example (5)
+===========
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        msi_a: msi-controller@a {
+                reg = <0xa 0x1>;
+                compatible = "vendor,some-controller";
+                msi-controller;
+                #msi-cells = <1>;
+        };
+
+        msi_b: msi-controller@b {
+                reg = <0xb 0x1>;
+                compatible = "vendor,some-controller";
+                msi-controller;
+                #msi-cells = <1>;
+        };
+
+        msi_c: msi-controller@c {
+                reg = <0xc 0x1>;
+                compatible = "vendor,some-controller";
+                msi-controller;
+                #msi-cells = <1>;
+        };
+
+        pci: pci@c {
+                reg = <0xf 0x1>;
+                compatible = "vendor,pcie-root-complex";
+                device_type = "pci";
+
+                /*
+                 * The sideband data provided to MSI controller a is the
+                 * RID, but the high bit of the bus number is negated.
+                 * The sideband data provided to MSI controller b is the
+                 * RID, identity-mapped.
+                 * MSI controller c is not addressable.
+                 */
+                msi-map = <0x0000 &msi_a 0x8000 0x08000>,
+                          <0x8000 &msi_a 0x0000 0x08000>,
+                          <0x0000 &msi_b 0x0000 0x10000>;
+        };
+};