diff options
Diffstat (limited to 'Documentation/devicetree/bindings/reset/uniphier-reset.txt')
-rw-r--r-- | Documentation/devicetree/bindings/reset/uniphier-reset.txt | 62 |
1 files changed, 31 insertions, 31 deletions
diff --git a/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/Documentation/devicetree/bindings/reset/uniphier-reset.txt index e6bbfccd56c3..5020524cddeb 100644 --- a/Documentation/devicetree/bindings/reset/uniphier-reset.txt +++ b/Documentation/devicetree/bindings/reset/uniphier-reset.txt | |||
@@ -6,25 +6,25 @@ System reset | |||
6 | 6 | ||
7 | Required properties: | 7 | Required properties: |
8 | - compatible: should be one of the following: | 8 | - compatible: should be one of the following: |
9 | "socionext,uniphier-sld3-reset" - for PH1-sLD3 SoC. | 9 | "socionext,uniphier-sld3-reset" - for sLD3 SoC. |
10 | "socionext,uniphier-ld4-reset" - for PH1-LD4 SoC. | 10 | "socionext,uniphier-ld4-reset" - for LD4 SoC. |
11 | "socionext,uniphier-pro4-reset" - for PH1-Pro4 SoC. | 11 | "socionext,uniphier-pro4-reset" - for Pro4 SoC. |
12 | "socionext,uniphier-sld8-reset" - for PH1-sLD8 SoC. | 12 | "socionext,uniphier-sld8-reset" - for sLD8 SoC. |
13 | "socionext,uniphier-pro5-reset" - for PH1-Pro5 SoC. | 13 | "socionext,uniphier-pro5-reset" - for Pro5 SoC. |
14 | "socionext,uniphier-pxs2-reset" - for ProXstream2/PH1-LD6b SoC. | 14 | "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC. |
15 | "socionext,uniphier-ld11-reset" - for PH1-LD11 SoC. | 15 | "socionext,uniphier-ld11-reset" - for LD11 SoC. |
16 | "socionext,uniphier-ld20-reset" - for PH1-LD20 SoC. | 16 | "socionext,uniphier-ld20-reset" - for LD20 SoC. |
17 | - #reset-cells: should be 1. | 17 | - #reset-cells: should be 1. |
18 | 18 | ||
19 | Example: | 19 | Example: |
20 | 20 | ||
21 | sysctrl@61840000 { | 21 | sysctrl@61840000 { |
22 | compatible = "socionext,uniphier-ld20-sysctrl", | 22 | compatible = "socionext,uniphier-ld11-sysctrl", |
23 | "simple-mfd", "syscon"; | 23 | "simple-mfd", "syscon"; |
24 | reg = <0x61840000 0x4000>; | 24 | reg = <0x61840000 0x4000>; |
25 | 25 | ||
26 | reset { | 26 | reset { |
27 | compatible = "socionext,uniphier-ld20-reset"; | 27 | compatible = "socionext,uniphier-ld11-reset"; |
28 | #reset-cells = <1>; | 28 | #reset-cells = <1>; |
29 | }; | 29 | }; |
30 | 30 | ||
@@ -32,30 +32,30 @@ Example: | |||
32 | }; | 32 | }; |
33 | 33 | ||
34 | 34 | ||
35 | Media I/O (MIO) reset | 35 | Media I/O (MIO) reset, SD reset |
36 | --------------------- | 36 | ------------------------------- |
37 | 37 | ||
38 | Required properties: | 38 | Required properties: |
39 | - compatible: should be one of the following: | 39 | - compatible: should be one of the following: |
40 | "socionext,uniphier-sld3-mio-reset" - for PH1-sLD3 SoC. | 40 | "socionext,uniphier-sld3-mio-reset" - for sLD3 SoC. |
41 | "socionext,uniphier-ld4-mio-reset" - for PH1-LD4 SoC. | 41 | "socionext,uniphier-ld4-mio-reset" - for LD4 SoC. |
42 | "socionext,uniphier-pro4-mio-reset" - for PH1-Pro4 SoC. | 42 | "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC. |
43 | "socionext,uniphier-sld8-mio-reset" - for PH1-sLD8 SoC. | 43 | "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC. |
44 | "socionext,uniphier-pro5-mio-reset" - for PH1-Pro5 SoC. | 44 | "socionext,uniphier-pro5-sd-reset" - for Pro5 SoC. |
45 | "socionext,uniphier-pxs2-mio-reset" - for ProXstream2/PH1-LD6b SoC. | 45 | "socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC. |
46 | "socionext,uniphier-ld11-mio-reset" - for PH1-LD11 SoC. | 46 | "socionext,uniphier-ld11-mio-reset" - for LD11 SoC. |
47 | "socionext,uniphier-ld20-mio-reset" - for PH1-LD20 SoC. | 47 | "socionext,uniphier-ld20-sd-reset" - for LD20 SoC. |
48 | - #reset-cells: should be 1. | 48 | - #reset-cells: should be 1. |
49 | 49 | ||
50 | Example: | 50 | Example: |
51 | 51 | ||
52 | mioctrl@59810000 { | 52 | mioctrl@59810000 { |
53 | compatible = "socionext,uniphier-ld20-mioctrl", | 53 | compatible = "socionext,uniphier-ld11-mioctrl", |
54 | "simple-mfd", "syscon"; | 54 | "simple-mfd", "syscon"; |
55 | reg = <0x59810000 0x800>; | 55 | reg = <0x59810000 0x800>; |
56 | 56 | ||
57 | reset { | 57 | reset { |
58 | compatible = "socionext,uniphier-ld20-mio-reset"; | 58 | compatible = "socionext,uniphier-ld11-mio-reset"; |
59 | #reset-cells = <1>; | 59 | #reset-cells = <1>; |
60 | }; | 60 | }; |
61 | 61 | ||
@@ -68,24 +68,24 @@ Peripheral reset | |||
68 | 68 | ||
69 | Required properties: | 69 | Required properties: |
70 | - compatible: should be one of the following: | 70 | - compatible: should be one of the following: |
71 | "socionext,uniphier-ld4-peri-reset" - for PH1-LD4 SoC. | 71 | "socionext,uniphier-ld4-peri-reset" - for LD4 SoC. |
72 | "socionext,uniphier-pro4-peri-reset" - for PH1-Pro4 SoC. | 72 | "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC. |
73 | "socionext,uniphier-sld8-peri-reset" - for PH1-sLD8 SoC. | 73 | "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC. |
74 | "socionext,uniphier-pro5-peri-reset" - for PH1-Pro5 SoC. | 74 | "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC. |
75 | "socionext,uniphier-pxs2-peri-reset" - for ProXstream2/PH1-LD6b SoC. | 75 | "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC. |
76 | "socionext,uniphier-ld11-peri-reset" - for PH1-LD11 SoC. | 76 | "socionext,uniphier-ld11-peri-reset" - for LD11 SoC. |
77 | "socionext,uniphier-ld20-peri-reset" - for PH1-LD20 SoC. | 77 | "socionext,uniphier-ld20-peri-reset" - for LD20 SoC. |
78 | - #reset-cells: should be 1. | 78 | - #reset-cells: should be 1. |
79 | 79 | ||
80 | Example: | 80 | Example: |
81 | 81 | ||
82 | perictrl@59820000 { | 82 | perictrl@59820000 { |
83 | compatible = "socionext,uniphier-ld20-perictrl", | 83 | compatible = "socionext,uniphier-ld11-perictrl", |
84 | "simple-mfd", "syscon"; | 84 | "simple-mfd", "syscon"; |
85 | reg = <0x59820000 0x200>; | 85 | reg = <0x59820000 0x200>; |
86 | 86 | ||
87 | reset { | 87 | reset { |
88 | compatible = "socionext,uniphier-ld20-peri-reset"; | 88 | compatible = "socionext,uniphier-ld11-peri-reset"; |
89 | #reset-cells = <1>; | 89 | #reset-cells = <1>; |
90 | }; | 90 | }; |
91 | 91 | ||