diff options
| -rw-r--r-- | drivers/bcma/driver_chipcommon_b.c | 9 | ||||
| -rw-r--r-- | include/linux/bcma/bcma_driver_chipcommon.h | 3 |
2 files changed, 8 insertions, 4 deletions
diff --git a/drivers/bcma/driver_chipcommon_b.c b/drivers/bcma/driver_chipcommon_b.c index c20b5f4ff290..57f10b58b47c 100644 --- a/drivers/bcma/driver_chipcommon_b.c +++ b/drivers/bcma/driver_chipcommon_b.c | |||
| @@ -33,11 +33,12 @@ static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask, | |||
| 33 | void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value) | 33 | void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value) |
| 34 | { | 34 | { |
| 35 | struct bcma_bus *bus = ccb->core->bus; | 35 | struct bcma_bus *bus = ccb->core->bus; |
| 36 | void __iomem *mii = ccb->mii; | ||
| 36 | 37 | ||
| 37 | writel(offset, ccb->mii + 0x00); | 38 | writel(offset, mii + BCMA_CCB_MII_MNG_CTL); |
| 38 | bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100); | 39 | bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100); |
| 39 | writel(value, ccb->mii + 0x04); | 40 | writel(value, mii + BCMA_CCB_MII_MNG_CMD_DATA); |
| 40 | bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100); | 41 | bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100); |
| 41 | } | 42 | } |
| 42 | EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write); | 43 | EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write); |
| 43 | 44 | ||
diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h index a5ac2cad5cb7..b20e3d56253f 100644 --- a/include/linux/bcma/bcma_driver_chipcommon.h +++ b/include/linux/bcma/bcma_driver_chipcommon.h | |||
| @@ -504,6 +504,9 @@ | |||
| 504 | #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 | 504 | #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 |
| 505 | #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 | 505 | #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 |
| 506 | 506 | ||
| 507 | #define BCMA_CCB_MII_MNG_CTL 0x0000 | ||
| 508 | #define BCMA_CCB_MII_MNG_CMD_DATA 0x0004 | ||
| 509 | |||
| 507 | /* BCM4331 ChipControl numbers. */ | 510 | /* BCM4331 ChipControl numbers. */ |
| 508 | #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */ | 511 | #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */ |
| 509 | #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */ | 512 | #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */ |
