4 files changed, 25 insertions, 9 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1e2dda88a483..d01a50e8e57c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1184,6 +1184,7 @@ struct intel_gen6_power_mgmt {
         bool interrupts_enabled;
         u32 pm_iir;
 
+        /* PM interrupt bits that should never be masked */
         u32 pm_intr_keep;
 
         /* Frequencies are stored in potentially platform dependent multiples.
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8462817a7dae..c128fdbd24e4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -371,7 +371,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
         spin_lock_irq(&dev_priv->irq_lock);
         dev_priv->rps.interrupts_enabled = false;
 
-        I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
+        I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
 
         __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
@@ -4500,7 +4500,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
                 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
 
         if (INTEL_INFO(dev_priv)->gen >= 8)
-                dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+                dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC;
 
         INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
                           i915_hangcheck_elapsed);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a29d707f0932..70d96162def6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7067,7 +7067,7 @@ enum {
 #define VLV_RCEDATA                             _MMIO(0xA0BC)
 #define GEN6_RC6pp_THRESHOLD                    _MMIO(0xA0C0)
 #define GEN6_PMINTRMSK                          _MMIO(0xA168)
-#define   GEN8_PMINTR_REDIRECT_TO_NON_DISP      (1<<31)
+#define   GEN8_PMINTR_REDIRECT_TO_GUC             (1<<31)
 #define GEN8_MISC_CTRL0                         _MMIO(0xA180)
 #define VLV_PWRDWNUPCTL                         _MMIO(0xA294)
 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS           _MMIO(0xA0C4)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 853928f21596..00217481f1fa 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -134,13 +134,28 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
         I915_WRITE(GUC_WD_VECS_IER, ~irqs);
 
         /*
-         * If GuC has routed PM interrupts to itself, don't keep it.
-         * and keep other interrupts those are unmasked by GuC.
-        */
+         * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
+         * (unmasked) PM interrupts to the GuC. All other bits of this
+         * register *disable* generation of a specific interrupt.
+         *
+         * 'pm_intr_keep' indicates bits that are NOT to be set when
+         * writing to the PM interrupt mask register, i.e. interrupts
+         * that must not be disabled.
+         *
+         * If the GuC is handling these interrupts, then we must not let
+         * the PM code disable ANY interrupt that the GuC is expecting.
+         * So for each ENABLED (0) bit in this register, we must SET the
+         * bit in pm_intr_keep so that it's left enabled for the GuC.
+         *
+         * OTOH the REDIRECT_TO_GUC bit is initially SET in pm_intr_keep
+         * (so interrupts go to the DISPLAY unit at first); but here we
+         * need to CLEAR that bit, which will result in the register bit
+         * being left SET!
+         */
         tmp = I915_READ(GEN6_PMINTRMSK);
-        if (tmp & GEN8_PMINTR_REDIRECT_TO_NON_DISP) {
-                dev_priv->rps.pm_intr_keep |= ~(tmp & ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
-                dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+        if (tmp & GEN8_PMINTR_REDIRECT_TO_GUC) {
+                dev_priv->rps.pm_intr_keep |= ~tmp;
+                dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_GUC;
         }
 }