aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--drivers/net/ethernet/freescale/fec.c9
-rw-r--r--drivers/net/ethernet/freescale/fec.h4
2 files changed, 10 insertions, 3 deletions
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index 236cc892ec3e..7b25e9cf13f6 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -476,6 +476,7 @@ fec_restart(struct net_device *ndev, int duplex)
476 } else { 476 } else {
477#ifdef FEC_MIIGSK_ENR 477#ifdef FEC_MIIGSK_ENR
478 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { 478 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
479 u32 cfgr;
479 /* disable the gasket and wait */ 480 /* disable the gasket and wait */
480 writel(0, fep->hwp + FEC_MIIGSK_ENR); 481 writel(0, fep->hwp + FEC_MIIGSK_ENR);
481 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 482 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
@@ -486,9 +487,11 @@ fec_restart(struct net_device *ndev, int duplex)
486 * RMII, 50 MHz, no loopback, no echo 487 * RMII, 50 MHz, no loopback, no echo
487 * MII, 25 MHz, no loopback, no echo 488 * MII, 25 MHz, no loopback, no echo
488 */ 489 */
489 writel((fep->phy_interface == PHY_INTERFACE_MODE_RMII) ? 490 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
490 1 : 0, fep->hwp + FEC_MIIGSK_CFGR); 491 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
491 492 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
493 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
494 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
492 495
493 /* re-enable the gasket */ 496 /* re-enable the gasket */
494 writel(2, fep->hwp + FEC_MIIGSK_ENR); 497 writel(2, fep->hwp + FEC_MIIGSK_ENR);
diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h
index 8b2c6d797e6d..8408c627b195 100644
--- a/drivers/net/ethernet/freescale/fec.h
+++ b/drivers/net/ethernet/freescale/fec.h
@@ -47,6 +47,10 @@
47#define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ 47#define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
48#define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ 48#define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
49 49
50#define BM_MIIGSK_CFGR_MII 0x00
51#define BM_MIIGSK_CFGR_RMII 0x01
52#define BM_MIIGSK_CFGR_FRCONT_10M 0x40
53
50#else 54#else
51 55
52#define FEC_ECNTRL 0x000 /* Ethernet control reg */ 56#define FEC_ECNTRL 0x000 /* Ethernet control reg */