3 files changed, 478 insertions, 0 deletions

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index b1541f40fd8d..ac8b0e968b6b 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -173,6 +173,18 @@ config PWM_LP3943
           To compile this driver as a module, choose M here: the module
           will be called pwm-lp3943.
 
+config PWM_LPC18XX_SCT
+        tristate "LPC18xx/43xx PWM/SCT support"
+        depends on ARCH_LPC18XX
+        help
+          Generic PWM framework driver for NXP LPC18xx PWM/SCT which
+          supports 16 channels.
+          A maximum of 15 channels can be requested simultaneously and
+          must have the same period.
+
+          To compile this driver as a module, choose M here: the module
+          will be called pwm-lpc18xx-sct.
+
 config PWM_LPC32XX
         tristate "LPC32XX PWM support"
         depends on ARCH_LPC32XX
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index ec50eb5b5a8f..cd9abef2d5b1 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PWM_IMG)		+= pwm-img.o
 obj-$(CONFIG_PWM_IMX)           += pwm-imx.o
 obj-$(CONFIG_PWM_JZ4740)        += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)        += pwm-lp3943.o
+obj-$(CONFIG_PWM_LPC18XX_SCT)   += pwm-lpc18xx-sct.o
 obj-$(CONFIG_PWM_LPC32XX)       += pwm-lpc32xx.o
 obj-$(CONFIG_PWM_LPSS)          += pwm-lpss.o
 obj-$(CONFIG_PWM_LPSS_PCI)      += pwm-lpss-pci.o
diff --git a/drivers/pwm/pwm-lpc18xx-sct.c b/drivers/pwm/pwm-lpc18xx-sct.c
new file mode 100644
index 000000000000..9163085101bc
--- /dev/null
+++ b/drivers/pwm/pwm-lpc18xx-sct.c
@@ -0,0 +1,465 @@
+/*
+ * NXP LPC18xx State Configurable Timer - Pulse Width Modulator driver
+ *
+ * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * Notes
+ * =====
+ * NXP LPC18xx provides a State Configurable Timer (SCT) which can be configured
+ * as a Pulse Width Modulator.
+ *
+ * SCT supports 16 outputs, 16 events and 16 registers. Each event will be
+ * triggered when its related register matches the SCT counter value, and it
+ * will set or clear a selected output.
+ *
+ * One of the events is preselected to generate the period, thus the maximum
+ * number of simultaneous channels is limited to 15. Notice that period is
+ * global to all the channels, thus PWM driver will refuse setting different
+ * values to it, unless there's only one channel requested.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+
+/* LPC18xx SCT registers */
+#define LPC18XX_PWM_CONFIG              0x000
+#define LPC18XX_PWM_CONFIG_UNIFY        BIT(0)
+#define LPC18XX_PWM_CONFIG_NORELOAD     BIT(7)
+
+#define LPC18XX_PWM_CTRL                0x004
+#define LPC18XX_PWM_CTRL_HALT           BIT(2)
+#define LPC18XX_PWM_BIDIR               BIT(4)
+#define LPC18XX_PWM_PRE_SHIFT           5
+#define LPC18XX_PWM_PRE_MASK            (0xff << LPC18XX_PWM_PRE_SHIFT)
+#define LPC18XX_PWM_PRE(x)              (x << LPC18XX_PWM_PRE_SHIFT)
+
+#define LPC18XX_PWM_LIMIT               0x008
+
+#define LPC18XX_PWM_RES_BASE            0x058
+#define LPC18XX_PWM_RES_SHIFT(_ch)      (_ch * 2)
+#define LPC18XX_PWM_RES(_ch, _action)   (_action << LPC18XX_PWM_RES_SHIFT(_ch))
+#define LPC18XX_PWM_RES_MASK(_ch)       (0x3 << LPC18XX_PWM_RES_SHIFT(_ch))
+
+#define LPC18XX_PWM_MATCH_BASE          0x100
+#define LPC18XX_PWM_MATCH(_ch)          (LPC18XX_PWM_MATCH_BASE + _ch * 4)
+
+#define LPC18XX_PWM_MATCHREL_BASE       0x200
+#define LPC18XX_PWM_MATCHREL(_ch)       (LPC18XX_PWM_MATCHREL_BASE + _ch * 4)
+
+#define LPC18XX_PWM_EVSTATEMSK_BASE     0x300
+#define LPC18XX_PWM_EVSTATEMSK(_ch)     (LPC18XX_PWM_EVSTATEMSK_BASE + _ch * 8)
+#define LPC18XX_PWM_EVSTATEMSK_ALL      0xffffffff
+
+#define LPC18XX_PWM_EVCTRL_BASE         0x304
+#define LPC18XX_PWM_EVCTRL(_ev)         (LPC18XX_PWM_EVCTRL_BASE + _ev * 8)
+
+#define LPC18XX_PWM_EVCTRL_MATCH(_ch)   _ch
+
+#define LPC18XX_PWM_EVCTRL_COMB_SHIFT   12
+#define LPC18XX_PWM_EVCTRL_COMB_MATCH   (0x1 << LPC18XX_PWM_EVCTRL_COMB_SHIFT)
+
+#define LPC18XX_PWM_OUTPUTSET_BASE      0x500
+#define LPC18XX_PWM_OUTPUTSET(_ch)      (LPC18XX_PWM_OUTPUTSET_BASE + _ch * 8)
+
+#define LPC18XX_PWM_OUTPUTCL_BASE       0x504
+#define LPC18XX_PWM_OUTPUTCL(_ch)       (LPC18XX_PWM_OUTPUTCL_BASE + _ch * 8)
+
+/* LPC18xx SCT unified counter */
+#define LPC18XX_PWM_TIMER_MAX           0xffffffff
+
+/* LPC18xx SCT events */
+#define LPC18XX_PWM_EVENT_PERIOD        0
+#define LPC18XX_PWM_EVENT_MAX           16
+
+/* SCT conflict resolution */
+enum lpc18xx_pwm_res_action {
+        LPC18XX_PWM_RES_NONE,
+        LPC18XX_PWM_RES_SET,
+        LPC18XX_PWM_RES_CLEAR,
+        LPC18XX_PWM_RES_TOGGLE,
+};
+
+struct lpc18xx_pwm_data {
+        unsigned int duty_event;
+};
+
+struct lpc18xx_pwm_chip {
+        struct device *dev;
+        struct pwm_chip chip;
+        void __iomem *base;
+        struct clk *pwm_clk;
+        unsigned long clk_rate;
+        unsigned int period_ns;
+        unsigned int min_period_ns;
+        unsigned int max_period_ns;
+        unsigned int period_event;
+        unsigned long event_map;
+        struct mutex res_lock;
+        struct mutex period_lock;
+};
+
+static inline struct lpc18xx_pwm_chip *
+to_lpc18xx_pwm_chip(struct pwm_chip *chip)
+{
+        return container_of(chip, struct lpc18xx_pwm_chip, chip);
+}
+
+static inline void lpc18xx_pwm_writel(struct lpc18xx_pwm_chip *lpc18xx_pwm,
+                                      u32 reg, u32 val)
+{
+        writel(val, lpc18xx_pwm->base + reg);
+}
+
+static inline u32 lpc18xx_pwm_readl(struct lpc18xx_pwm_chip *lpc18xx_pwm,
+                                    u32 reg)
+{
+        return readl(lpc18xx_pwm->base + reg);
+}
+
+static void lpc18xx_pwm_set_conflict_res(struct lpc18xx_pwm_chip *lpc18xx_pwm,
+                                         struct pwm_device *pwm,
+                                         enum lpc18xx_pwm_res_action action)
+{
+        u32 val;
+
+        mutex_lock(&lpc18xx_pwm->res_lock);
+
+        /*
+         * Simultaneous set and clear may happen on an output, that is the case
+         * when duty_ns == period_ns. LPC18xx SCT allows to set a conflict
+         * resolution action to be taken in such a case.
+         */
+        val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_RES_BASE);
+        val &= ~LPC18XX_PWM_RES_MASK(pwm->hwpwm);
+        val |= LPC18XX_PWM_RES(pwm->hwpwm, action);
+        lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_RES_BASE, val);
+
+        mutex_unlock(&lpc18xx_pwm->res_lock);
+}
+
+static void lpc18xx_pwm_config_period(struct pwm_chip *chip, int period_ns)
+{
+        struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
+        u64 val;
+
+        val = (u64)period_ns * lpc18xx_pwm->clk_rate;
+        do_div(val, NSEC_PER_SEC);
+
+        lpc18xx_pwm_writel(lpc18xx_pwm,
+                           LPC18XX_PWM_MATCH(lpc18xx_pwm->period_event),
+                           (u32)val - 1);
+
+        lpc18xx_pwm_writel(lpc18xx_pwm,
+                           LPC18XX_PWM_MATCHREL(lpc18xx_pwm->period_event),
+                           (u32)val - 1);
+}
+
+static void lpc18xx_pwm_config_duty(struct pwm_chip *chip,
+                                    struct pwm_device *pwm, int duty_ns)
+{
+        struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
+        struct lpc18xx_pwm_data *lpc18xx_data = pwm_get_chip_data(pwm);
+        u64 val;
+
+        val = (u64)duty_ns * lpc18xx_pwm->clk_rate;
+        do_div(val, NSEC_PER_SEC);
+
+        lpc18xx_pwm_writel(lpc18xx_pwm,
+                           LPC18XX_PWM_MATCH(lpc18xx_data->duty_event),
+                           (u32)val);