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-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt56
-rw-r--r--arch/arm64/boot/dts/Makefile1
-rw-r--r--arch/arm64/boot/dts/nvidia/Makefile7
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra132-norrin.dts1130
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra132.dtsi990
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi45
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2371-0000.dts9
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts9
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi50
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2571.dts1302
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi1272
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi1270
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210.dtsi805
-rw-r--r--include/dt-bindings/clock/tegra210-car.h401
14 files changed, 7347 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt
new file mode 100644
index 000000000000..26f237f641b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt
@@ -0,0 +1,56 @@
1NVIDIA Tegra210 Clock And Reset Controller
2
3This binding uses the common clock binding:
4Documentation/devicetree/bindings/clock/clock-bindings.txt
5
6The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
7for muxing and gating Tegra's clocks, and setting their rates.
8
9Required properties :
10- compatible : Should be "nvidia,tegra210-car"
11- reg : Should contain CAR registers location and length
12- clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in".
14- #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the
16 CAR. The assignments may be found in header file
17 <dt-bindings/clock/tegra210-car.h>.
18- #reset-cells : Should be 1.
19 In clock consumers, this cell represents the bit number in the CAR's
20 array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
21
22Example SoC include file:
23
24/ {
25 tegra_car: clock {
26 compatible = "nvidia,tegra210-car";
27 reg = <0x60006000 0x1000>;
28 #clock-cells = <1>;
29 #reset-cells = <1>;
30 };
31
32 usb@c5004000 {
33 clocks = <&tegra_car TEGRA210_CLK_USB2>;
34 };
35};
36
37Example board file:
38
39/ {
40 clocks {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 clk_32k: clock@1 {
46 compatible = "fixed-clock";
47 reg = <1>;
48 #clock-cells = <0>;
49 clock-frequency = <32768>;
50 };
51 };
52
53 &tegra_car {
54 clocks = <&clk_32k>;
55 };
56};
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index eb3c42d97175..193617f4cd08 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -9,6 +9,7 @@ dts-dirs += freescale
9dts-dirs += hisilicon 9dts-dirs += hisilicon
10dts-dirs += marvell 10dts-dirs += marvell
11dts-dirs += mediatek 11dts-dirs += mediatek
12dts-dirs += nvidia
12dts-dirs += qcom 13dts-dirs += qcom
13dts-dirs += rockchip 14dts-dirs += rockchip
14dts-dirs += sprd 15dts-dirs += sprd
diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
new file mode 100644
index 000000000000..a7e865da1005
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/Makefile
@@ -0,0 +1,7 @@
1dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb
2dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
3dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
4dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
5
6always := $(dtb-y)
7clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
new file mode 100644
index 000000000000..7dfe1c085966
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
@@ -0,0 +1,1130 @@
1/dts-v1/;
2
3#include <dt-bindings/input/input.h>
4#include "tegra132.dtsi"
5
6/ {
7 model = "NVIDIA Tegra132 Norrin";
8 compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124";
9
10 aliases {
11 rtc0 = "/i2c@0,7000d000/as3722@40";
12 rtc1 = "/rtc@0,7000e000";
13 };
14
15 memory {
16 device_type = "memory";
17 reg = <0x0 0x80000000 0x0 0x80000000>;
18 };
19
20 host1x@0,50000000 {
21 hdmi@0,54280000 {
22 status = "disabled";
23
24 vdd-supply = <&vdd_3v3_hdmi>;
25 pll-supply = <&vdd_hdmi_pll>;
26 hdmi-supply = <&vdd_5v0_hdmi>;
27
28 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
29 nvidia,hpd-gpio =
30 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
31 };
32
33 sor@0,54540000 {
34 status = "okay";
35
36 nvidia,dpaux = <&dpaux>;
37 nvidia,panel = <&panel>;
38 };
39
40 dpaux: dpaux@0,545c0000 {
41 vdd-supply = <&vdd_3v3_panel>;
42 status = "okay";
43 };
44 };
45
46 gpu@0,57000000 {
47 status = "okay";
48
49 vdd-supply = <&vdd_gpu>;
50 };
51
52 pinmux@0,70000868 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinmux_default>;
55
56 pinmux_default: pinmux@0 {
57 dap_mclk1_pw4 {
58 nvidia,pins = "dap_mclk1_pw4";
59 nvidia,function = "extperiph1";
60 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
61 nvidia,tristate = <TEGRA_PIN_DISABLE>;
62 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
63 };
64 dap2_din_pa4 {
65 nvidia,pins = "dap2_din_pa4";
66 nvidia,function = "i2s1";
67 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
68 nvidia,tristate = <TEGRA_PIN_DISABLE>;
69 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
70 };
71 dap2_dout_pa5 {
72 nvidia,pins = "dap2_dout_pa5",
73 "dap2_fs_pa2",
74 "dap2_sclk_pa3";
75 nvidia,function = "i2s1";
76 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
77 nvidia,tristate = <TEGRA_PIN_DISABLE>;
78 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
79 };
80 dap3_dout_pp2 {
81 nvidia,pins = "dap3_dout_pp2";
82 nvidia,function = "i2s2";
83 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
84 nvidia,tristate = <TEGRA_PIN_DISABLE>;
85 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
86 };
87 dvfs_pwm_px0 {
88 nvidia,pins = "dvfs_pwm_px0",
89 "dvfs_clk_px2";
90 nvidia,function = "cldvfs";
91 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
92 nvidia,tristate = <TEGRA_PIN_DISABLE>;
93 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
94 };
95 ulpi_clk_py0 {
96 nvidia,pins = "ulpi_clk_py0",
97 "ulpi_nxt_py2",
98 "ulpi_stp_py3";
99 nvidia,function = "spi1";
100 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
101 nvidia,tristate = <TEGRA_PIN_DISABLE>;
102 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
103 };
104 ulpi_dir_py1 {
105 nvidia,pins = "ulpi_dir_py1";
106 nvidia,function = "spi1";
107 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
108 nvidia,tristate = <TEGRA_PIN_DISABLE>;
109 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
110 };
111 cam_i2c_scl_pbb1 {
112 nvidia,pins = "cam_i2c_scl_pbb1",
113 "cam_i2c_sda_pbb2";
114 nvidia,function = "i2c3";
115 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
116 nvidia,tristate = <TEGRA_PIN_DISABLE>;
117 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
118 nvidia,lock = <TEGRA_PIN_DISABLE>;
119 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
120 };
121 gen2_i2c_scl_pt5 {
122 nvidia,pins = "gen2_i2c_scl_pt5",
123 "gen2_i2c_sda_pt6";
124 nvidia,function = "i2c2";
125 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
126 nvidia,tristate = <TEGRA_PIN_DISABLE>;
127 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
128 nvidia,lock = <TEGRA_PIN_DISABLE>;
129 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
130 };
131 pj7 {
132 nvidia,pins = "pj7";
133 nvidia,function = "uartd";
134 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
135 nvidia,tristate = <TEGRA_PIN_DISABLE>;
136 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
137 };
138 spdif_in_pk6 {
139 nvidia,pins = "spdif_in_pk6";
140 nvidia,function = "spdif";
141 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
142 nvidia,tristate = <TEGRA_PIN_DISABLE>;
143 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
144 };
145 pk7 {
146 nvidia,pins = "pk7";
147 nvidia,function = "uartd";
148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
150 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
151 };
152 pg4 {
153 nvidia,pins = "pg4",
154 "pg5",
155 "pg6",
156 "pi3";
157 nvidia,function = "spi4";
158 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
159 nvidia,tristate = <TEGRA_PIN_DISABLE>;
160 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
161 };
162 pg7 {
163 nvidia,pins = "pg7";
164 nvidia,function = "spi4";
165 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166 nvidia,tristate = <TEGRA_PIN_DISABLE>;
167 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
168 };
169 ph1 {
170 nvidia,pins = "ph1";
171 nvidia,function = "pwm1";
172 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
173 nvidia,tristate = <TEGRA_PIN_DISABLE>;
174 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
175 };
176 pk0 {
177 nvidia,pins = "pk0",
178 "kb_row15_ps7",
179 "clk_32k_out_pa0";
180 nvidia,function = "soc";
181 nvidia,pull = <TEGRA_PIN_PULL_UP>;
182 nvidia,tristate = <TEGRA_PIN_DISABLE>;
183 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
184 };
185 sdmmc1_clk_pz0 {
186 nvidia,pins = "sdmmc1_clk_pz0";
187 nvidia,function = "sdmmc1";
188 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
189 nvidia,tristate = <TEGRA_PIN_DISABLE>;
190 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
191 };
192 sdmmc1_cmd_pz1 {
193 nvidia,pins = "sdmmc1_cmd_pz1",
194 "sdmmc1_dat0_py7",
195 "sdmmc1_dat1_py6",
196 "sdmmc1_dat2_py5",
197 "sdmmc1_dat3_py4";
198 nvidia,function = "sdmmc1";
199 nvidia,pull = <TEGRA_PIN_PULL_UP>;
200 nvidia,tristate = <TEGRA_PIN_DISABLE>;
201 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
202 };
203 sdmmc3_clk_pa6 {
204 nvidia,pins = "sdmmc3_clk_pa6";
205 nvidia,function = "sdmmc3";
206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
207 nvidia,tristate = <TEGRA_PIN_DISABLE>;
208 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
209 };
210 sdmmc3_cmd_pa7 {
211 nvidia,pins = "sdmmc3_cmd_pa7",
212 "sdmmc3_dat0_pb7",
213 "sdmmc3_dat1_pb6",
214 "sdmmc3_dat2_pb5",
215 "sdmmc3_dat3_pb4",
216 "kb_col4_pq4",
217 "sdmmc3_clk_lb_out_pee4",
218 "sdmmc3_clk_lb_in_pee5",
219 "sdmmc3_cd_n_pv2";
220 nvidia,function = "sdmmc3";
221 nvidia,pull = <TEGRA_PIN_PULL_UP>;
222 nvidia,tristate = <TEGRA_PIN_DISABLE>;
223 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
224 };
225 sdmmc4_clk_pcc4 {
226 nvidia,pins = "sdmmc4_clk_pcc4";
227 nvidia,function = "sdmmc4";
228 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
229 nvidia,tristate = <TEGRA_PIN_DISABLE>;
230 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
231 };
232 sdmmc4_cmd_pt7 {
233 nvidia,pins = "sdmmc4_cmd_pt7",
234 "sdmmc4_dat0_paa0",
235 "sdmmc4_dat1_paa1",
236 "sdmmc4_dat2_paa2",
237 "sdmmc4_dat3_paa3",
238 "sdmmc4_dat4_paa4",
239 "sdmmc4_dat5_paa5",
240 "sdmmc4_dat6_paa6",
241 "sdmmc4_dat7_paa7";
242 nvidia,function = "sdmmc4";
243 nvidia,pull = <TEGRA_PIN_PULL_UP>;
244 nvidia,tristate = <TEGRA_PIN_DISABLE>;
245 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
246 };
247 mic_det_l {
248 nvidia,pins = "kb_row7_pr7";
249 nvidia,function = "rsvd2";
250 nvidia,pull = <TEGRA_PIN_PULL_UP>;
251 nvidia,tristate = <TEGRA_PIN_DISABLE>;
252 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
253 };
254 kb_row10_ps2 {
255 nvidia,pins = "kb_row10_ps2";
256 nvidia,function = "uarta";
257 nvidia,pull = <TEGRA_PIN_PULL_UP>;
258 nvidia,tristate = <TEGRA_PIN_DISABLE>;
259 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
260 };
261 kb_row9_ps1 {
262 nvidia,pins = "kb_row9_ps1";
263 nvidia,function = "uarta";
264 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
265 nvidia,tristate = <TEGRA_PIN_DISABLE>;
266 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
267 };
268 pwr_i2c_scl_pz6 {
269 nvidia,pins = "pwr_i2c_scl_pz6",
270 "pwr_i2c_sda_pz7";
271 nvidia,function = "i2cpwr";
272 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
273 nvidia,tristate = <TEGRA_PIN_DISABLE>;
274 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
275 nvidia,lock = <TEGRA_PIN_DISABLE>;
276 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
277 };
278 jtag_rtck {
279 nvidia,pins = "jtag_rtck";
280 nvidia,function = "rtck";
281 nvidia,pull = <TEGRA_PIN_PULL_UP>;
282 nvidia,tristate = <TEGRA_PIN_DISABLE>;
283 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
284 };
285 clk_32k_in {
286 nvidia,pins = "clk_32k_in";
287 nvidia,function = "clk";
288 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
289 nvidia,tristate = <TEGRA_PIN_DISABLE>;
290 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
291 };
292 core_pwr_req {
293 nvidia,pins = "core_pwr_req";
294 nvidia,function = "pwron";
295 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
296 nvidia,tristate = <TEGRA_PIN_DISABLE>;
297 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
298 };
299 cpu_pwr_req {
300 nvidia,pins = "cpu_pwr_req";
301 nvidia,function = "cpu";
302 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
303 nvidia,tristate = <TEGRA_PIN_DISABLE>;
304 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
305 };
306 kb_col0_ap {
307 nvidia,pins = "kb_col0_pq0";
308 nvidia,function = "rsvd4";
309 nvidia,pull = <TEGRA_PIN_PULL_UP>;
310 nvidia,tristate = <TEGRA_PIN_DISABLE>;
311 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
312 };
313 en_vdd_sd {
314 nvidia,pins = "kb_row0_pr0";
315 nvidia,function = "rsvd4";
316 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
317 nvidia,tristate = <TEGRA_PIN_DISABLE>;
318 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
319 };
320 lid_open {
321 nvidia,pins = "kb_row4_pr4";
322 nvidia,function = "rsvd3";
323 nvidia,pull = <TEGRA_PIN_PULL_UP>;
324 nvidia,tristate = <TEGRA_PIN_DISABLE>;
325 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
326 };
327 pwr_int_n {
328 nvidia,pins = "pwr_int_n";
329 nvidia,function = "pmi";
330 nvidia,pull = <TEGRA_PIN_PULL_UP>;
331 nvidia,tristate = <TEGRA_PIN_DISABLE>;
332 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
333 };
334 reset_out_n {
335 nvidia,pins = "reset_out_n";
336 nvidia,function = "reset_out_n";
337 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
338 nvidia,tristate = <TEGRA_PIN_DISABLE>;
339 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
340 };
341 clk3_out_pee0 {
342 nvidia,pins = "clk3_out_pee0";
343 nvidia,function = "extperiph3";
344 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
345 nvidia,tristate = <TEGRA_PIN_DISABLE>;
346 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
347 };
348 gen1_i2c_scl_pc4 {
349 nvidia,pins = "gen1_i2c_scl_pc4",
350 "gen1_i2c_sda_pc5";
351 nvidia,function = "i2c1";
352 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
353 nvidia,tristate = <TEGRA_PIN_DISABLE>;
354 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
355 nvidia,lock = <TEGRA_PIN_DISABLE>;
356 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
357 };
358 hdmi_cec_pee3 {
359 nvidia,pins = "hdmi_cec_pee3";
360 nvidia,function = "cec";
361 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
362 nvidia,tristate = <TEGRA_PIN_DISABLE>;
363 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
364 nvidia,lock = <TEGRA_PIN_DISABLE>;
365 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
366 };
367 hdmi_int_pn7 {
368 nvidia,pins = "hdmi_int_pn7";
369 nvidia,function = "rsvd1";
370 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
371 nvidia,tristate = <TEGRA_PIN_DISABLE>;
372 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
373 };
374 ddc_scl_pv4 {
375 nvidia,pins = "ddc_scl_pv4",
376 "ddc_sda_pv5";
377 nvidia,function = "i2c4";
378 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
379 nvidia,tristate = <TEGRA_PIN_DISABLE>;
380 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
381 nvidia,lock = <TEGRA_PIN_DISABLE>;
382 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
383 };
384 usb_vbus_en0_pn4 {
385 nvidia,pins = "usb_vbus_en0_pn4",
386 "usb_vbus_en1_pn5",
387 "usb_vbus_en2_pff1";
388 nvidia,function = "usb";
389 nvidia,pull = <TEGRA_PIN_PULL_UP>;
390 nvidia,tristate = <TEGRA_PIN_ENABLE>;
391 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
392 nvidia,lock = <TEGRA_PIN_DISABLE>;
393 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
394 };
395 drive_sdio1 {
396 nvidia,pins = "drive_sdio1";
397 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
398 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
399 nvidia,pull-down-strength = <36>;
400 nvidia,pull-up-strength = <20>;
401 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
402 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
403 };
404 drive_sdio3 {
405 nvidia,pins = "drive_sdio3";
406 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
407 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
408 nvidia,pull-down-strength = <22>;
409 nvidia,pull-up-strength = <36>;
410 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
411 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
412 };
413 drive_gma {
414 nvidia,pins = "drive_gma";
415 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
416 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
417 nvidia,pull-down-strength = <2>;
418 nvidia,pull-up-strength = <1>;
419 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
420 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
421 nvidia,drive-type = <1>;
422 };
423 ac_ok {
424 nvidia,pins = "pj0";
425 nvidia,function = "gmi";
426 nvidia,pull = <TEGRA_PIN_PULL_UP>;
427 nvidia,tristate = <TEGRA_PIN_ENABLE>;
428 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
429 };
430 codec_irq_l {
431 nvidia,pins = "ph4";
432 nvidia,function = "gmi";
433 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
434 nvidia,tristate = <TEGRA_PIN_DISABLE>;
435 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
436 };
437 lcd_bl_en {
438 nvidia,pins = "ph2";
439 nvidia,function = "gmi";
440 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
441 nvidia,tristate = <TEGRA_PIN_DISABLE>;
442 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
443 };
444 touch_irq_l {
445 nvidia,pins = "gpio_w3_aud_pw3";
446 nvidia,function = "spi6";
447 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
448 nvidia,tristate = <TEGRA_PIN_DISABLE>;
449 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
450 };
451 tpm_davint_l {
452 nvidia,pins = "ph6";
453 nvidia,function = "gmi";
454 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
455 nvidia,tristate = <TEGRA_PIN_DISABLE>;
456 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
457 };
458 ts_irq_l {
459 nvidia,pins = "pk2";
460 nvidia,function = "gmi";
461 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
462 nvidia,tristate = <TEGRA_PIN_DISABLE>;
463 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
464 };
465 ts_reset_l {
466 nvidia,pins = "pk4";
467 nvidia,function = "gmi";
468 nvidia,pull = <1>;
469 nvidia,tristate = <TEGRA_PIN_DISABLE>;
470 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
471 };
472 ts_shdn_l {
473 nvidia,pins = "pk1";
474 nvidia,function = "gmi";
475 nvidia,pull = <TEGRA_PIN_PULL_UP>;
476 nvidia,tristate = <TEGRA_PIN_DISABLE>;
477 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
478 };
479 ph7 {
480 nvidia,pins = "ph7";
481 nvidia,function = "gmi";
482 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
483 nvidia,tristate = <TEGRA_PIN_DISABLE>;
484 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
485 };
486 sensor_irq_l {
487 nvidia,pins = "pi6";
488 nvidia,function = "gmi";
489 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
490 nvidia,tristate = <TEGRA_PIN_DISABLE>;
491 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
492 };
493 wifi_en {
494 nvidia,pins = "gpio_x7_aud_px7";
495 nvidia,function = "rsvd4";
496 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
497 nvidia,tristate = <TEGRA_PIN_DISABLE>;
498 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
499 };
500 chromeos_write_protect {
501 nvidia,pins = "kb_row1_pr1";
502 nvidia,function = "rsvd4";
503 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
504 nvidia,tristate = <TEGRA_PIN_DISABLE>;
505 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
506 };
507 hp_det_l {
508 nvidia,pins = "pi7";
509 nvidia,function = "rsvd1";
510 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
511 nvidia,tristate = <TEGRA_PIN_DISABLE>;
512 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
513 };
514 soc_warm_reset_l {
515 nvidia,pins = "pi5";
516 nvidia,function = "gmi";
517 nvidia,pull = <TEGRA_PIN_PULL_UP>;
518 nvidia,tristate = <TEGRA_PIN_DISABLE>;
519 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
520 };
521 };
522 };
523
524 serial@0,70006000 {
525 status = "okay";
526 };
527
528 pwm: pwm@0,7000a000 {
529 status = "okay";
530 };
531
532 /* HDMI DDC */
533 hdmi_ddc: i2c@0,7000c700 {
534 status = "okay";
535 clock-frequency = <100000>;
536 };
537
538 i2c@0,7000d000 {
539 status = "okay";
540 clock-frequency = <400000>;
541
542 as3722: pmic@40 {
543 compatible = "ams,as3722";
544 reg = <0x40>;
545 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
546
547 ams,system-power-controller;
548
549 #interrupt-cells = <2>;
550 interrupt-controller;
551
552 #gpio-cells = <2>;
553 gpio-controller;
554
555 pinctrl-names = "default";
556 pinctrl-0 = <&as3722_default>;
557
558 as3722_default: pinmux@0 {
559 gpio0 {
560 pins = "gpio0";
561 function = "gpio";
562 bias-pull-down;
563 };
564
565 gpio1 {
566 pins = "gpio1";
567 function = "gpio";
568 bias-pull-up;
569 };
570
571 gpio2_4_7 {
572 pins = "gpio2", "gpio4", "gpio7";
573 function = "gpio";
574 bias-pull-up;
575 };
576
577 gpio3 {
578 pins = "gpio3";
579 function = "gpio";
580 bias-high-impedance;
581 };
582
583 gpio5 {
584 pins = "gpio5";
585 function = "clk32k-out";
586 bias-pull-down;
587 };
588
589 gpio6 {
590 pins = "gpio6";
591 function = "clk32k-out";
592 bias-pull-down;
593 };
594 };
595
596 regulators {
597 vsup-sd2-supply = <&vdd_5v0_sys>;
598 vsup-sd3-supply = <&vdd_5v0_sys>;
599 vsup-sd4-supply = <&vdd_5v0_sys>;
600 vsup-sd5-supply = <&vdd_5v0_sys>;
601 vin-ldo0-supply = <&vdd_1v35_lp0>;
602 vin-ldo1-6-supply = <&vdd_3v3_sys>;
603 vin-ldo2-5-7-supply = <&vddio_1v8>;
604 vin-ldo3-4-supply = <&vdd_3v3_sys>;
605 vin-ldo9-10-supply = <&vdd_5v0_sys>;
606 vin-ldo11-supply = <&vdd_3v3_run>;
607
608 sd0 {
609 regulator-name = "+VDD_CPU_AP";
610 regulator-min-microvolt = <700000>;
611 regulator-max-microvolt = <1350000>;
612 regulator-max-microamp = <3500000>;
613 regulator-always-on;
614 regulator-boot-on;
615 ams,ext-control = <2>;
616 };
617
618 sd1 {
619 regulator-name = "+VDD_CORE";
620 regulator-min-microvolt = <700000>;
621 regulator-max-microvolt = <1350000>;
622 regulator-max-microamp = <4000000>;
623 regulator-always-on;
624 regulator-boot-on;
625 ams,ext-control = <1>;
626 };
627
628 vdd_1v35_lp0: sd2 {
629 regulator-name = "+1.35V_LP0(sd2)";
630 regulator-min-microvolt = <1350000>;
631 regulator-max-microvolt = <1350000>;
632 regulator-always-on;
633 regulator-boot-on;
634 };
635
636 sd3 {
637 regulator-name = "+1.35V_LP0(sd3)";
638 regulator-min-microvolt = <1350000>;
639 regulator-max-microvolt = <1350000>;
640 regulator-always-on;
641 regulator-boot-on;
642 };
643
644 vdd_1v05_run: sd4 {
645 regulator-name = "+1.05V_RUN";
646 regulator-min-microvolt = <1050000>;
647 regulator-max-microvolt = <1050000>;
648 };
649
650 vddio_1v8: sd5 {
651 regulator-name = "+1.8V_VDDIO";
652 regulator-min-microvolt = <1800000>;
653 regulator-max-microvolt = <1800000>;
654 regulator-always-on;
655 regulator-boot-on;
656 };
657
658 vdd_gpu: sd6 {
659 regulator-name = "+VDD_GPU_AP";
660 regulator-min-microvolt = <800000>;
661 regulator-max-microvolt = <1200000>;
662 regulator-min-microamp = <3500000>;
663 regulator-max-microamp = <3500000>;
664 regulator-always-on;
665 regulator-boot-on;
666 };
667
668 ldo0 {
669 regulator-name = "+1.05_RUN_AVDD";
670 regulator-min-microvolt = <1050000>;
671 regulator-max-microvolt = <1050000>;
672 regulator-always-on;
673 regulator-boot-on;
674 ams,ext-control = <1>;
675 };
676
677 ldo1 {
678 regulator-name = "+1.8V_RUN_CAM";
679 regulator-min-microvolt = <1800000>;
680 regulator-max-microvolt = <1800000>;
681 };
682
683 ldo2 {
684 regulator-name = "+1.2V_GEN_AVDD";
685 regulator-min-microvolt = <1200000>;
686 regulator-max-microvolt = <1200000>;
687 regulator-always-on;
688 regulator-boot-on;
689 };
690
691 ldo3 {
692 regulator-name = "+1.00V_LP0_VDD_RTC";
693 regulator-min-microvolt = <1000000>;
694 regulator-max-microvolt = <1000000>;
695 regulator-always-on;
696 regulator-boot-on;
697 ams,enable-tracking;
698 };
699
700 vdd_run_cam: ldo4 {
701 regulator-name = "+2.8V_RUN_CAM";
702 regulator-min-microvolt = <2800000>;
703 regulator-max-microvolt = <2800000>;
704 };
705
706 ldo5 {
707 regulator-name = "+1.2V_RUN_CAM_FRONT";
708 regulator-min-microvolt = <1200000>;
709 regulator-max-microvolt = <1200000>;
710 };
711
712 vddio_sdmmc3: ldo6 {
713 regulator-name = "+VDDIO_SDMMC3";
714 regulator-min-microvolt = <1800000>;
715 regulator-max-microvolt = <3300000>;
716 };
717
718 ldo7 {
719 regulator-name = "+1.05V_RUN_CAM_REAR";
720 regulator-min-microvolt = <1050000>;
721 regulator-max-microvolt = <1050000>;
722 };
723
724 ldo9 {
725 regulator-name = "+2.8V_RUN_TOUCH";
726 regulator-min-microvolt = <2800000>;
727 regulator-max-microvolt = <2800000>;
728 };
729
730 ldo10 {
731 regulator-name = "+2.8V_RUN_CAM_AF";
732 regulator-min-microvolt = <2800000>;
733 regulator-max-microvolt = <2800000>;
734 };
735
736 ldo11 {
737 regulator-name = "+1.8V_RUN_VPP_FUSE";
738 regulator-min-microvolt = <1800000>;
739 regulator-max-microvolt = <1800000>;
740 };
741 };
742 };
743 };
744
745 spi@0,7000d400 {
746 status = "okay";
747
748 ec: cros-ec@0 {
749 compatible = "google,cros-ec-spi";
750 spi-max-frequency = <3000000>;
751 interrupt-parent = <&gpio>;
752 interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
753 reg = <0>;
754
755 google,cros-ec-spi-msg-delay = <2000>;
756
757 i2c_20: i2c-tunnel {
758 compatible = "google,cros-ec-i2c-tunnel";
759 #address-cells = <1>;
760 #size-cells = <0>;
761
762 google,remote-bus = <0>;
763
764 charger: bq24735 {
765 compatible = "ti,bq24735";
766 reg = <0x9>;
767 interrupt-parent = <&gpio>;
768 interrupts = <TEGRA_GPIO(J, 0)
769 GPIO_ACTIVE_HIGH>;
770 ti,ac-detect-gpios = <&gpio
771 TEGRA_GPIO(J, 0)
772 GPIO_ACTIVE_HIGH>;
773 };
774
775 battery: smart-battery {
776 compatible = "sbs,sbs-battery";
777 reg = <0xb>;
778 battery-name = "battery";
779 sbs,i2c-retry-count = <2>;
780 sbs,poll-retry-count = <10>;
781 /* power-supplies = <&charger>; */
782 };
783 };
784
785 keyboard-controller {
786 compatible = "google,cros-ec-keyb";
787 keypad,num-rows = <8>;
788 keypad,num-columns = <13>;
789 google,needs-ghost-filter;
790 linux,keymap =
791 <MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
792 MATRIX_KEY(0x00, 0x02, KEY_F1)
793 MATRIX_KEY(0x00, 0x03, KEY_B)
794 MATRIX_KEY(0x00, 0x04, KEY_F10)
795 MATRIX_KEY(0x00, 0x06, KEY_N)
796 MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
797 MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
798
799 MATRIX_KEY(0x01, 0x01, KEY_ESC)
800 MATRIX_KEY(0x01, 0x02, KEY_F4)
801 MATRIX_KEY(0x01, 0x03, KEY_G)
802 MATRIX_KEY(0x01, 0x04, KEY_F7)
803 MATRIX_KEY(0x01, 0x06, KEY_H)
804 MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
805 MATRIX_KEY(0x01, 0x09, KEY_F9)
806 MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
807
808 MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
809 MATRIX_KEY(0x02, 0x01, KEY_TAB)
810 MATRIX_KEY(0x02, 0x02, KEY_F3)
811 MATRIX_KEY(0x02, 0x03, KEY_T)
812 MATRIX_KEY(0x02, 0x04, KEY_F6)
813 MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
814 MATRIX_KEY(0x02, 0x06, KEY_Y)
815 MATRIX_KEY(0x02, 0x07, KEY_102ND)
816 MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
817 MATRIX_KEY(0x02, 0x09, KEY_F8)
818
819 MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
820 MATRIX_KEY(0x03, 0x02, KEY_F2)
821 MATRIX_KEY(0x03, 0x03, KEY_5)
822 MATRIX_KEY(0x03, 0x04, KEY_F5)
823 MATRIX_KEY(0x03, 0x06, KEY_6)
824 MATRIX_KEY(0x03, 0x08, KEY_MINUS)
825 MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
826
827 MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
828 MATRIX_KEY(0x04, 0x01, KEY_A)
829 MATRIX_KEY(0x04, 0x02, KEY_D)
830 MATRIX_KEY(0x04, 0x03, KEY_F)
831 MATRIX_KEY(0x04, 0x04, KEY_S)
832 MATRIX_KEY(0x04, 0x05, KEY_K)
833 MATRIX_KEY(0x04, 0x06, KEY_J)
834 MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
835 MATRIX_KEY(0x04, 0x09, KEY_L)
836 MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
837 MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
838
839 MATRIX_KEY(0x05, 0x01, KEY_Z)
840 MATRIX_KEY(0x05, 0x02, KEY_C)
841 MATRIX_KEY(0x05, 0x03, KEY_V)
842 MATRIX_KEY(0x05, 0x04, KEY_X)
843 MATRIX_KEY(0x05, 0x05, KEY_COMMA)
844 MATRIX_KEY(0x05, 0x06, KEY_M)
845 MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
846 MATRIX_KEY(0x05, 0x08, KEY_SLASH)
847 MATRIX_KEY(0x05, 0x09, KEY_DOT)
848 MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
849
850 MATRIX_KEY(0x06, 0x01, KEY_1)
851 MATRIX_KEY(0x06, 0x02, KEY_3)
852 MATRIX_KEY(0x06, 0x03, KEY_4)
853 MATRIX_KEY(0x06, 0x04, KEY_2)
854 MATRIX_KEY(0x06, 0x05, KEY_8)
855 MATRIX_KEY(0x06, 0x06, KEY_7)
856 MATRIX_KEY(0x06, 0x08, KEY_0)
857 MATRIX_KEY(0x06, 0x09, KEY_9)
858 MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
859 MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
860 MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
861
862 MATRIX_KEY(0x07, 0x01, KEY_Q)
863 MATRIX_KEY(0x07, 0x02, KEY_E)
864 MATRIX_KEY(0x07, 0x03, KEY_R)
865 MATRIX_KEY(0x07, 0x04, KEY_W)
866 MATRIX_KEY(0x07, 0x05, KEY_I)
867 MATRIX_KEY(0x07, 0x06, KEY_U)
868 MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
869 MATRIX_KEY(0x07, 0x08, KEY_P)
870 MATRIX_KEY(0x07, 0x09, KEY_O)
871 MATRIX_KEY(0x07, 0x0b, KEY_UP)
872 MATRIX_KEY(0x07, 0x0c, KEY_LEFT)>;
873 };
874 };
875 };
876
877 pmc@0,7000e400 {
878 nvidia,invert-interrupt;
879 nvidia,suspend-mode = <0>;
880 #wake-cells = <3>;
881 nvidia,cpu-pwr-good-time = <500>;
882 nvidia,cpu-pwr-off-time = <300>;
883 nvidia,core-pwr-good-time = <641 3845>;
884 nvidia,core-pwr-off-time = <61036>;
885 nvidia,core-power-req-active-high;
886 nvidia,sys-clock-req-active-high;
887 nvidia,reset-gpio = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
888 };
889
890 /* WIFI/BT module */
891 sdhci@0,700b0000 {
892 status = "disabled";
893 };
894
895 /* external SD/MMC */
896 sdhci@0,700b0400 {
897 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
898 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
899 wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
900 status = "okay";
901 bus-width = <4>;
902 vqmmc-supply = <&vddio_sdmmc3>;
903 };
904
905 /* EMMC 4.51 */
906 sdhci@0,700b0600 {
907 status = "okay";
908 bus-width = <8>;
909 non-removable;
910 };
911
912 usb@0,7d000000 {
913 status = "okay";
914 };
915
916 usb-phy@0,7d000000 {
917 status = "okay";
918 vbus-supply = <&vdd_usb1_vbus>;
919 };
920
921 usb@0,7d004000 {
922 status = "okay";
923 };
924
925 usb-phy@0,7d004000 {
926 status = "okay";
927 vbus-supply = <&vdd_run_cam>;
928 };
929
930 usb@0,7d008000 {
931 status = "okay";
932 };
933
934 usb-phy@0,7d008000 {
935 status = "okay";
936 vbus-supply = <&vdd_usb3_vbus>;
937 };
938
939 backlight: backlight {
940 compatible = "pwm-backlight";
941
942 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
943 power-supply = <&vdd_led>;
944 pwms = <&pwm 1 1000000>;
945
946 brightness-levels = <0 4 8 16 32 64 128 255>;
947 default-brightness-level = <6>;
948
949 backlight-boot-off;
950 };
951
952 clocks {
953 compatible = "simple-bus";
954 #address-cells = <1>;
955 #size-cells = <0>;
956
957 clk32k_in: clock@0 {
958 compatible = "fixed-clock";
959 reg=<0>;
960 #clock-cells = <0>;
961 clock-frequency = <32768>;
962 };
963 };
964
965 gpio-keys {
966 compatible = "gpio-keys";
967
968 lid {
969 label = "Lid";
970 gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
971 linux,input-type = <5>;
972 linux,code = <0>;
973 debounce-interval = <1>;
974 gpio-key,wakeup;
975 };
976
977 power {
978 label = "Power";
979 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
980 linux,code = <KEY_POWER>;
981 debounce-interval = <10>;
982 gpio-key,wakeup;
983 };
984 };
985
986 panel: panel {
987 compatible = "innolux,n116bge", "simple-panel";
988 backlight = <&backlight>;
989 ddc-i2c-bus = <&dpaux>;
990 };
991
992 regulators {
993 compatible = "simple-bus";
994 #address-cells = <1>;
995 #size-cells = <0>;
996
997 vdd_mux: regulator@0 {
998 compatible = "regulator-fixed";
999 reg = <0>;
1000 regulator-name = "+VDD_MUX";
1001 regulator-min-microvolt = <19000000>;
1002 regulator-max-microvolt = <19000000>;
1003 regulator-always-on;
1004 regulator-boot-on;
1005 };
1006
1007 vdd_5v0_sys: regulator@1 {
1008 compatible = "regulator-fixed";
1009 reg = <1>;
1010 regulator-name = "+5V_SYS";
1011 regulator-min-microvolt = <5000000>;
1012 regulator-max-microvolt = <5000000>;
1013 regulator-always-on;
1014 regulator-boot-on;
1015 vin-supply = <&vdd_mux>;
1016 };
1017
1018 vdd_3v3_sys: regulator@2 {
1019 compatible = "regulator-fixed";
1020 reg = <2>;
1021 regulator-name = "+3.3V_SYS";
1022 regulator-min-microvolt = <3300000>;
1023 regulator-max-microvolt = <3300000>;
1024 regulator-always-on;
1025 regulator-boot-on;
1026 vin-supply = <&vdd_mux>;
1027 };
1028
1029 vdd_3v3_run: regulator@3 {
1030 compatible = "regulator-fixed";
1031 reg = <3>;
1032 regulator-name = "+3.3V_RUN";
1033 regulator-min-microvolt = <3300000>;
1034 regulator-max-microvolt = <3300000>;
1035 regulator-always-on;
1036 regulator-boot-on;
1037 gpio = <&as3722 1 GPIO_ACTIVE_HIGH>;
1038 enable-active-high;
1039 vin-supply = <&vdd_3v3_sys>;
1040 };
1041
1042 vdd_3v3_hdmi: regulator@4 {
1043 compatible = "regulator-fixed";
1044 reg = <4>;
1045 regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
1046 regulator-min-microvolt = <3300000>;
1047 regulator-max-microvolt = <3300000>;
1048 vin-supply = <&vdd_3v3_run>;
1049 };
1050
1051 vdd_led: regulator@5 {
1052 compatible = "regulator-fixed";
1053 reg = <5>;
1054 regulator-name = "+VDD_LED";
1055 regulator-min-microvolt = <3300000>;
1056 regulator-max-microvolt = <3300000>;
1057 gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
1058 enable-active-high;
1059 vin-supply = <&vdd_mux>;
1060 };
1061
1062 vdd_usb1_vbus: regulator@6 {
1063 compatible = "regulator-fixed";
1064 reg = <6>;
1065 regulator-name = "+5V_USB_HS";
1066 regulator-min-microvolt = <5000000>;
1067 regulator-max-microvolt = <5000000>;
1068 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
1069 enable-active-high;
1070 gpio-open-drain;
1071 vin-supply = <&vdd_5v0_sys>;
1072 };
1073
1074 vdd_usb3_vbus: regulator@7 {
1075 compatible = "regulator-fixed";
1076 reg = <7>;
1077 regulator-name = "+5V_USB_SS";
1078 regulator-min-microvolt = <5000000>;
1079 regulator-max-microvolt = <5000000>;
1080 gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
1081 enable-active-high;
1082 gpio-open-drain;
1083 vin-supply = <&vdd_5v0_sys>;
1084 };
1085
1086 vdd_3v3_panel: regulator@8 {
1087 compatible = "regulator-fixed";
1088 reg = <8>;
1089 regulator-name = "+3.3V_PANEL";
1090 regulator-min-microvolt = <3300000>;
1091 regulator-max-microvolt = <3300000>;
1092 gpio = <&as3722 4 GPIO_ACTIVE_HIGH>;
1093 enable-active-high;
1094 vin-supply = <&vdd_3v3_sys>;
1095 };
1096
1097 vdd_hdmi_pll: regulator@9 {
1098 compatible = "regulator-fixed";
1099 reg = <9>;
1100 regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE";
1101 regulator-min-microvolt = <1050000>;
1102 regulator-max-microvolt = <1050000>;
1103 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1104 vin-supply = <&vdd_1v05_run>;
1105 };
1106
1107 vdd_5v0_hdmi: regulator@10 {
1108 compatible = "regulator-fixed";
1109 reg = <10>;
1110 regulator-name = "+5V_HDMI_CON";
1111 regulator-min-microvolt = <5000000>;
1112 regulator-max-microvolt = <5000000>;
1113 gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
1114 enable-active-high;
1115 vin-supply = <&vdd_5v0_sys>;
1116 };
1117
1118 vdd_5v0_ts: regulator@11 {
1119 compatible = "regulator-fixed";
1120 reg = <11>;
1121 regulator-name = "+5V_VDD_TS";
1122 regulator-min-microvolt = <5000000>;
1123 regulator-max-microvolt = <5000000>;
1124 regulator-always-on;
1125 regulator-boot-on;
1126 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
1127 enable-active-high;
1128 };
1129 };
1130};
diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
new file mode 100644
index 000000000000..e8bb46027bed
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
@@ -0,0 +1,990 @@
1#include <dt-bindings/clock/tegra124-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/memory/tegra124-mc.h>
4#include <dt-bindings/pinctrl/pinctrl-tegra.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7
8/ {
9 compatible = "nvidia,tegra132", "nvidia,tegra124";
10 interrupt-parent = <&lic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 pcie-controller@0,01003000 {
15 compatible = "nvidia,tegra124-pcie";
16 device_type = "pci";
17 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
18 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
19 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
20 reg-names = "pads", "afi", "cs";
21 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
22 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
23 interrupt-names = "intr", "msi";
24
25 #interrupt-cells = <1>;
26 interrupt-map-mask = <0 0 0 0>;
27 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
28
29 bus-range = <0x00 0xff>;
30 #address-cells = <3>;
31 #size-cells = <2>;
32
33 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
34 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
35 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
36 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
37 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
38
39 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
40 <&tegra_car TEGRA124_CLK_AFI>,
41 <&tegra_car TEGRA124_CLK_PLL_E>,
42 <&tegra_car TEGRA124_CLK_CML0>;
43 clock-names = "pex", "afi", "pll_e", "cml";
44 resets = <&tegra_car 70>,
45 <&tegra_car 72>,
46 <&tegra_car 74>;
47 reset-names = "pex", "afi", "pcie_x";
48 status = "disabled";
49
50 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
51 phy-names = "pcie";
52
53 pci@1,0 {
54 device_type = "pci";
55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
56 reg = <0x000800 0 0 0 0>;
57 status = "disabled";
58
59 #address-cells = <3>;
60 #size-cells = <2>;
61 ranges;
62
63 nvidia,num-lanes = <2>;
64 };
65
66 pci@2,0 {
67 device_type = "pci";
68 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
69 reg = <0x001000 0 0 0 0>;
70 status = "disabled";
71
72 #address-cells = <3>;
73 #size-cells = <2>;
74 ranges;
75
76 nvidia,num-lanes = <1>;
77 };
78 };
79
80 host1x@0,50000000 {
81 compatible = "nvidia,tegra124-host1x", "simple-bus";
82 reg = <0x0 0x50000000 0x0 0x00034000>;
83 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
84 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
85 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
86 clock-names = "host1x";
87 resets = <&tegra_car 28>;
88 reset-names = "host1x";
89
90 #address-cells = <2>;
91 #size-cells = <2>;
92
93 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
94
95 dc@0,54200000 {
96 compatible = "nvidia,tegra124-dc";
97 reg = <0x0 0x54200000 0x0 0x00040000>;
98 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
100 <&tegra_car TEGRA124_CLK_PLL_P>;
101 clock-names = "dc", "parent";
102 resets = <&tegra_car 27>;
103 reset-names = "dc";
104
105 iommus = <&mc TEGRA_SWGROUP_DC>;
106
107 nvidia,head = <0>;
108 };
109
110 dc@0,54240000 {
111 compatible = "nvidia,tegra124-dc";
112 reg = <0x0 0x54240000 0x0 0x00040000>;
113 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
115 <&tegra_car TEGRA124_CLK_PLL_P>;
116 clock-names = "dc", "parent";
117 resets = <&tegra_car 26>;
118 reset-names = "dc";
119
120 iommus = <&mc TEGRA_SWGROUP_DCB>;
121
122 nvidia,head = <1>;
123 };
124
125 hdmi@0,54280000 {
126 compatible = "nvidia,tegra124-hdmi";
127 reg = <0x0 0x54280000 0x0 0x00040000>;
128 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
130 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
131 clock-names = "hdmi", "parent";
132 resets = <&tegra_car 51>;
133 reset-names = "hdmi";
134 status = "disabled";
135 };
136
137 sor@0,54540000 {
138 compatible = "nvidia,tegra124-sor";
139 reg = <0x0 0x54540000 0x0 0x00040000>;
140 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
142 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
143 <&tegra_car TEGRA124_CLK_PLL_DP>,
144 <&tegra_car TEGRA124_CLK_CLK_M>;
145 clock-names = "sor", "parent", "dp", "safe";
146 resets = <&tegra_car 182>;
147 reset-names = "sor";
148 status = "disabled";
149 };
150
151 dpaux: dpaux@0,545c0000 {
152 compatible = "nvidia,tegra124-dpaux";
153 reg = <0x0 0x545c0000 0x0 0x00040000>;
154 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
156 <&tegra_car TEGRA124_CLK_PLL_DP>;
157 clock-names = "dpaux", "parent";
158 resets = <&tegra_car 181>;
159 reset-names = "dpaux";
160 status = "disabled";
161 };
162 };
163
164 gic: interrupt-controller@0,50041000 {
165 compatible = "arm,cortex-a15-gic";
166 #interrupt-cells = <3>;
167 interrupt-controller;
168 reg = <0x0 0x50041000 0x0 0x1000>,
169 <0x0 0x50042000 0x0 0x2000>,
170 <0x0 0x50044000 0x0 0x2000>,
171 <0x0 0x50046000 0x0 0x2000>;
172 interrupts = <GIC_PPI 9
173 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
174 interrupt-parent = <&gic>;
175 };
176
177 gpu@0,57000000 {
178 compatible = "nvidia,gk20a";
179 reg = <0x0 0x57000000 0x0 0x01000000>,
180 <0x0 0x58000000 0x0 0x01000000>;
181 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
183 interrupt-names = "stall", "nonstall";
184 clocks = <&tegra_car TEGRA124_CLK_GPU>,
185 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
186 clock-names = "gpu", "pwr";
187 resets = <&tegra_car 184>;
188 reset-names = "gpu";
189 status = "disabled";
190 };
191
192 lic: interrupt-controller@60004000 {
193 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
194 reg = <0x0 0x60004000 0x0 0x100>,
195 <0x0 0x60004100 0x0 0x100>,
196 <0x0 0x60004200 0x0 0x100>,
197 <0x0 0x60004300 0x0 0x100>,
198 <0x0 0x60004400 0x0 0x100>;
199 interrupt-controller;
200 #interrupt-cells = <3>;
201 interrupt-parent = <&gic>;
202 };
203
204 timer@0,60005000 {
205 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
206 reg = <0x0 0x60005000 0x0 0x400>;
207 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
214 clock-names = "timer";
215 };
216
217 tegra_car: clock@0,60006000 {
218 compatible = "nvidia,tegra132-car";
219 reg = <0x0 0x60006000 0x0 0x1000>;
220 #clock-cells = <1>;
221 #reset-cells = <1>;
222 nvidia,external-memory-controller = <&emc>;
223 };
224
225 flow-controller@0,60007000 {
226 compatible = "nvidia,tegra124-flowctrl";
227 reg = <0x0 0x60007000 0x0 0x1000>;
228 };
229
230 actmon@0,6000c800 {
231 compatible = "nvidia,tegra124-actmon";
232 reg = <0x0 0x6000c800 0x0 0x400>;
233 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
235 <&tegra_car TEGRA124_CLK_EMC>;
236 clock-names = "actmon", "emc";
237 resets = <&tegra_car 119>;
238 reset-names = "actmon";
239 };
240
241 gpio: gpio@0,6000d000 {
242 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
243 reg = <0x0 0x6000d000 0x0 0x1000>;
244 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
252 #gpio-cells = <2>;
253 gpio-controller;
254 #interrupt-cells = <2>;
255 interrupt-controller;
256 };
257
258 apbdma: dma@0,60020000 {
259 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
260 reg = <0x0 0x60020000 0x0 0x1400>;
261 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
294 clock-names = "dma";
295 resets = <&tegra_car 34>;
296 reset-names = "dma";
297 #dma-cells = <1>;
298 };
299
300 apbmisc@0,70000800 {
301 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
302 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
303 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
304 };
305
306 pinmux: pinmux@0,70000868 {
307 compatible = "nvidia,tegra124-pinmux";
308 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
309 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
310 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
311 };
312
313 /*
314 * There are two serial driver i.e. 8250 based simple serial
315 * driver and APB DMA based serial driver for higher baudrate
316 * and performace. To enable the 8250 based driver, the compatible
317 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
318 * the APB DMA based serial driver, the comptible is
319 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
320 */
321 uarta: serial@0,70006000 {
322 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
323 reg = <0x0 0x70006000 0x0 0x40>;
324 reg-shift = <2>;
325 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
327 clock-names = "serial";
328 resets = <&tegra_car 6>;
329 reset-names = "serial";
330 dmas = <&apbdma 8>, <&apbdma 8>;
331 dma-names = "rx", "tx";
332 status = "disabled";
333 };
334
335 uartb: serial@0,70006040 {
336 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
337 reg = <0x0 0x70006040 0x0 0x40>;
338 reg-shift = <2>;
339 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
341 clock-names = "serial";
342 resets = <&tegra_car 7>;
343 reset-names = "serial";
344 dmas = <&apbdma 9>, <&apbdma 9>;
345 dma-names = "rx", "tx";
346 status = "disabled";
347 };
348
349 uartc: serial@0,70006200 {
350 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
351 reg = <0x0 0x70006200 0x0 0x40>;
352 reg-shift = <2>;
353 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
355 clock-names = "serial";
356 resets = <&tegra_car 55>;
357 reset-names = "serial";
358 dmas = <&apbdma 10>, <&apbdma 10>;
359 dma-names = "rx", "tx";
360 status = "disabled";
361 };
362
363 uartd: serial@0,70006300 {
364 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
365 reg = <0x0 0x70006300 0x0 0x40>;
366 reg-shift = <2>;
367 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
369 clock-names = "serial";
370 resets = <&tegra_car 65>;
371 reset-names = "serial";
372 dmas = <&apbdma 19>, <&apbdma 19>;
373 dma-names = "rx", "tx";
374 status = "disabled";
375 };
376
377 pwm: pwm@0,7000a000 {
378 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
379 reg = <0x0 0x7000a000 0x0 0x100>;
380 #pwm-cells = <2>;
381 clocks = <&tegra_car TEGRA124_CLK_PWM>;
382 clock-names = "pwm";
383 resets = <&tegra_car 17>;
384 reset-names = "pwm";
385 status = "disabled";
386 };
387
388 i2c@0,7000c000 {
389 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
390 reg = <0x0 0x7000c000 0x0 0x100>;
391 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
392 #address-cells = <1>;
393 #size-cells = <0>;
394 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
395 clock-names = "div-clk";
396 resets = <&tegra_car 12>;
397 reset-names = "i2c";
398 dmas = <&apbdma 21>, <&apbdma 21>;
399 dma-names = "rx", "tx";
400 status = "disabled";
401 };
402
403 i2c@0,7000c400 {
404 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
405 reg = <0x0 0x7000c400 0x0 0x100>;
406 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
407 #address-cells = <1>;
408 #size-cells = <0>;
409 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
410 clock-names = "div-clk";
411 resets = <&tegra_car 54>;
412 reset-names = "i2c";
413 dmas = <&apbdma 22>, <&apbdma 22>;
414 dma-names = "rx", "tx";
415 status = "disabled";
416 };
417
418 i2c@0,7000c500 {
419 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
420 reg = <0x0 0x7000c500 0x0 0x100>;
421 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
422 #address-cells = <1>;
423 #size-cells = <0>;
424 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
425 clock-names = "div-clk";
426 resets = <&tegra_car 67>;
427 reset-names = "i2c";
428 dmas = <&apbdma 23>, <&apbdma 23>;
429 dma-names = "rx", "tx";
430 status = "disabled";
431 };
432
433 i2c@0,7000c700 {
434 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
435 reg = <0x0 0x7000c700 0x0 0x100>;
436 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
437 #address-cells = <1>;
438 #size-cells = <0>;
439 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
440 clock-names = "div-clk";
441 resets = <&tegra_car 103>;
442 reset-names = "i2c";
443 dmas = <&apbdma 26>, <&apbdma 26>;
444 dma-names = "rx", "tx";
445 status = "disabled";
446 };
447
448 i2c@0,7000d000 {
449 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
450 reg = <0x0 0x7000d000 0x0 0x100>;
451 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
452 #address-cells = <1>;
453 #size-cells = <0>;
454 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
455 clock-names = "div-clk";
456 resets = <&tegra_car 47>;
457 reset-names = "i2c";
458 dmas = <&apbdma 24>, <&apbdma 24>;
459 dma-names = "rx", "tx";
460 status = "disabled";
461 };
462
463 i2c@0,7000d100 {
464 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
465 reg = <0x0 0x7000d100 0x0 0x100>;
466 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
470 clock-names = "div-clk";
471 resets = <&tegra_car 166>;
472 reset-names = "i2c";
473 dmas = <&apbdma 30>, <&apbdma 30>;
474 dma-names = "rx", "tx";
475 status = "disabled";
476 };
477
478 spi@0,7000d400 {
479 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
480 reg = <0x0 0x7000d400 0x0 0x200>;
481 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
482 #address-cells = <1>;
483 #size-cells = <0>;
484 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
485 clock-names = "spi";
486 resets = <&tegra_car 41>;
487 reset-names = "spi";
488 dmas = <&apbdma 15>, <&apbdma 15>;
489 dma-names = "rx", "tx";
490 status = "disabled";
491 };
492
493 spi@0,7000d600 {
494 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
495 reg = <0x0 0x7000d600 0x0 0x200>;
496 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
497 #address-cells = <1>;
498 #size-cells = <0>;
499 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
500 clock-names = "spi";
501 resets = <&tegra_car 44>;
502 reset-names = "spi";
503 dmas = <&apbdma 16>, <&apbdma 16>;
504 dma-names = "rx", "tx";
505 status = "disabled";
506 };
507
508 spi@0,7000d800 {
509 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
510 reg = <0x0 0x7000d800 0x0 0x200>;
511 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
512 #address-cells = <1>;
513 #size-cells = <0>;
514 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
515 clock-names = "spi";
516 resets = <&tegra_car 46>;
517 reset-names = "spi";
518 dmas = <&apbdma 17>, <&apbdma 17>;
519 dma-names = "rx", "tx";
520 status = "disabled";
521 };
522
523 spi@0,7000da00 {
524 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
525 reg = <0x0 0x7000da00 0x0 0x200>;
526 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
527 #address-cells = <1>;
528 #size-cells = <0>;
529 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
530 clock-names = "spi";
531 resets = <&tegra_car 68>;
532 reset-names = "spi";
533 dmas = <&apbdma 18>, <&apbdma 18>;
534 dma-names = "rx", "tx";
535 status = "disabled";
536 };
537
538 spi@0,7000dc00 {
539 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
540 reg = <0x0 0x7000dc00 0x0 0x200>;
541 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
542 #address-cells = <1>;
543 #size-cells = <0>;
544 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
545 clock-names = "spi";
546 resets = <&tegra_car 104>;
547 reset-names = "spi";
548 dmas = <&apbdma 27>, <&apbdma 27>;
549 dma-names = "rx", "tx";
550 status = "disabled";
551 };
552
553 spi@0,7000de00 {
554 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
555 reg = <0x0 0x7000de00 0x0 0x200>;
556 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
557 #address-cells = <1>;
558 #size-cells = <0>;
559 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
560 clock-names = "spi";
561 resets = <&tegra_car 105>;
562 reset-names = "spi";
563 dmas = <&apbdma 28>, <&apbdma 28>;
564 dma-names = "rx", "tx";
565 status = "disabled";
566 };
567
568 rtc@0,7000e000 {
569 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
570 reg = <0x0 0x7000e000 0x0 0x100>;
571 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&tegra_car TEGRA124_CLK_RTC>;
573 clock-names = "rtc";
574 };
575
576 pmc@0,7000e400 {
577 compatible = "nvidia,tegra124-pmc";
578 reg = <0x0 0x7000e400 0x0 0x400>;
579 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
580 clock-names = "pclk", "clk32k_in";
581 };
582
583 fuse@0,7000f800 {
584 compatible = "nvidia,tegra124-efuse";
585 reg = <0x0 0x7000f800 0x0 0x400>;
586 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
587 clock-names = "fuse";
588 resets = <&tegra_car 39>;
589 reset-names = "fuse";
590 };
591
592 mc: memory-controller@0,70019000 {
593 compatible = "nvidia,tegra132-mc";
594 reg = <0x0 0x70019000 0x0 0x1000>;
595 clocks = <&tegra_car TEGRA124_CLK_MC>;
596 clock-names = "mc";
597
598 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
599
600 #iommu-cells = <1>;
601 };
602
603 emc: emc@0,7001b000 {
604 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
605 reg = <0x0 0x7001b000 0x0 0x1000>;
606
607 nvidia,memory-controller = <&mc>;
608 };
609
610 sata@0,70020000 {
611 compatible = "nvidia,tegra124-ahci";
612 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
613 <0x0 0x70020000 0x0 0x7000>; /* SATA */
614 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&tegra_car TEGRA124_CLK_SATA>,
616 <&tegra_car TEGRA124_CLK_SATA_OOB>,
617 <&tegra_car TEGRA124_CLK_CML1>,
618 <&tegra_car TEGRA124_CLK_PLL_E>;
619 clock-names = "sata", "sata-oob", "cml1", "pll_e";
620 resets = <&tegra_car 124>,
621 <&tegra_car 123>,
622 <&tegra_car 129>;
623 reset-names = "sata", "sata-oob", "sata-cold";
624 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
625 phy-names = "sata-phy";
626 status = "disabled";
627 };
628
629 hda@0,70030000 {
630 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda",
631 "nvidia,tegra30-hda";
632 reg = <0x0 0x70030000 0x0 0x10000>;
633 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&tegra_car TEGRA124_CLK_HDA>,
635 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
636 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
637 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
638 resets = <&tegra_car 125>, /* hda */
639 <&tegra_car 128>, /* hda2hdmi */
640 <&tegra_car 111>; /* hda2codec_2x */
641 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
642 status = "disabled";
643 };
644
645 padctl: padctl@0,7009f000 {
646 compatible = "nvidia,tegra132-xusb-padctl",
647 "nvidia,tegra124-xusb-padctl";
648 reg = <0x0 0x7009f000 0x0 0x1000>;
649 resets = <&tegra_car 142>;
650 reset-names = "padctl";
651
652 #phy-cells = <1>;
653
654 phys {
655 pcie-0 {
656 status = "disabled";
657 };
658
659 sata-0 {
660 status = "disabled";
661 };
662
663 usb3-0 {
664 status = "disabled";
665 };
666
667 usb3-1 {
668 status = "disabled";
669 };
670
671 utmi-0 {
672 status = "disabled";
673 };
674
675 utmi-1 {
676 status = "disabled";
677 };
678
679 utmi-2 {
680 status = "disabled";
681 };
682 };
683 };
684
685 sdhci@0,700b0000 {
686 compatible = "nvidia,tegra124-sdhci";
687 reg = <0x0 0x700b0000 0x0 0x200>;
688 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
690 clock-names = "sdhci";
691 resets = <&tegra_car 14>;
692 reset-names = "sdhci";
693 status = "disabled";
694 };
695
696 sdhci@0,700b0200 {
697 compatible = "nvidia,tegra124-sdhci";
698 reg = <0x0 0x700b0200 0x0 0x200>;
699 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
701 clock-names = "sdhci";
702 resets = <&tegra_car 9>;
703 reset-names = "sdhci";
704 status = "disabled";
705 };
706
707 sdhci@0,700b0400 {
708 compatible = "nvidia,tegra124-sdhci";
709 reg = <0x0 0x700b0400 0x0 0x200>;
710 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
712 clock-names = "sdhci";
713 resets = <&tegra_car 69>;
714 reset-names = "sdhci";
715 status = "disabled";
716 };
717
718 sdhci@0,700b0600 {
719 compatible = "nvidia,tegra124-sdhci";
720 reg = <0x0 0x700b0600 0x0 0x200>;
721 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
723 clock-names = "sdhci";
724 resets = <&tegra_car 15>;
725 reset-names = "sdhci";
726 status = "disabled";
727 };
728
729 soctherm: thermal-sensor@0,700e2000 {
730 compatible = "nvidia,tegra124-soctherm";
731 reg = <0x0 0x700e2000 0x0 0x1000>;
732 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
734 <&tegra_car TEGRA124_CLK_SOC_THERM>;
735 clock-names = "tsensor", "soctherm";
736 resets = <&tegra_car 78>;
737 reset-names = "soctherm";
738 #thermal-sensor-cells = <1>;
739 };
740
741 ahub@0,70300000 {
742 compatible = "nvidia,tegra124-ahub";
743 reg = <0x0 0x70300000 0x0 0x200>,
744 <0x0 0x70300800 0x0 0x800>,
745 <0x0 0x70300200 0x0 0x600>;
746 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
748 <&tegra_car TEGRA124_CLK_APBIF>;
749 clock-names = "d_audio", "apbif";
750 resets = <&tegra_car 106>, /* d_audio */
751 <&tegra_car 107>, /* apbif */
752 <&tegra_car 30>, /* i2s0 */
753 <&tegra_car 11>, /* i2s1 */
754 <&tegra_car 18>, /* i2s2 */
755 <&tegra_car 101>, /* i2s3 */
756 <&tegra_car 102>, /* i2s4 */
757 <&tegra_car 108>, /* dam0 */
758 <&tegra_car 109>, /* dam1 */
759 <&tegra_car 110>, /* dam2 */
760 <&tegra_car 10>, /* spdif */
761 <&tegra_car 153>, /* amx */
762 <&tegra_car 185>, /* amx1 */
763 <&tegra_car 154>, /* adx */
764 <&tegra_car 180>, /* adx1 */
765 <&tegra_car 186>, /* afc0 */
766 <&tegra_car 187>, /* afc1 */
767 <&tegra_car 188>, /* afc2 */
768 <&tegra_car 189>, /* afc3 */
769 <&tegra_car 190>, /* afc4 */
770 <&tegra_car 191>; /* afc5 */
771 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
772 "i2s3", "i2s4", "dam0", "dam1", "dam2",
773 "spdif", "amx", "amx1", "adx", "adx1",
774 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
775 dmas = <&apbdma 1>, <&apbdma 1>,
776 <&apbdma 2>, <&apbdma 2>,
777 <&apbdma 3>, <&apbdma 3>,
778 <&apbdma 4>, <&apbdma 4>,
779 <&apbdma 6>, <&apbdma 6>,
780 <&apbdma 7>, <&apbdma 7>,
781 <&apbdma 12>, <&apbdma 12>,
782 <&apbdma 13>, <&apbdma 13>,
783 <&apbdma 14>, <&apbdma 14>,
784 <&apbdma 29>, <&apbdma 29>;
785 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
786 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
787 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
788 "rx9", "tx9";
789 ranges;
790 #address-cells = <2>;
791 #size-cells = <2>;
792
793 tegra_i2s0: i2s@0,70301000 {
794 compatible = "nvidia,tegra124-i2s";
795 reg = <0x0 0x70301000 0x0 0x100>;
796 nvidia,ahub-cif-ids = <4 4>;
797 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
798 clock-names = "i2s";
799 resets = <&tegra_car 30>;
800 reset-names = "i2s";
801 status = "disabled";
802 };
803
804 tegra_i2s1: i2s@0,70301100 {
805 compatible = "nvidia,tegra124-i2s";
806 reg = <0x0 0x70301100 0x0 0x100>;
807 nvidia,ahub-cif-ids = <5 5>;
808 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
809 clock-names = "i2s";
810 resets = <&tegra_car 11>;
811 reset-names = "i2s";
812 status = "disabled";
813 };
814
815 tegra_i2s2: i2s@0,70301200 {
816 compatible = "nvidia,tegra124-i2s";
817 reg = <0x0 0x70301200 0x0 0x100>;
818 nvidia,ahub-cif-ids = <6 6>;
819 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
820 clock-names = "i2s";
821 resets = <&tegra_car 18>;
822 reset-names = "i2s";
823 status = "disabled";
824 };
825
826 tegra_i2s3: i2s@0,70301300 {
827 compatible = "nvidia,tegra124-i2s";
828 reg = <0x0 0x70301300 0x0 0x100>;
829 nvidia,ahub-cif-ids = <7 7>;
830 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
831 clock-names = "i2s";
832 resets = <&tegra_car 101>;
833 reset-names = "i2s";
834 status = "disabled";
835 };
836
837 tegra_i2s4: i2s@0,70301400 {
838 compatible = "nvidia,tegra124-i2s";
839 reg = <0x0 0x70301400 0x0 0x100>;
840 nvidia,ahub-cif-ids = <8 8>;
841 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
842 clock-names = "i2s";
843 resets = <&tegra_car 102>;
844 reset-names = "i2s";
845 status = "disabled";
846 };
847 };
848
849 usb@0,7d000000 {
850 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
851 reg = <0x0 0x7d000000 0x0 0x4000>;
852 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
853 phy_type = "utmi";
854 clocks = <&tegra_car TEGRA124_CLK_USBD>;
855 clock-names = "usb";
856 resets = <&tegra_car 22>;
857 reset-names = "usb";
858 nvidia,phy = <&phy1>;
859 status = "disabled";
860 };
861
862 phy1: usb-phy@0,7d000000 {
863 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
864 reg = <0x0 0x7d000000 0x0 0x4000>,
865 <0x0 0x7d000000 0x0 0x4000>;
866 phy_type = "utmi";
867 clocks = <&tegra_car TEGRA124_CLK_USBD>,
868 <&tegra_car TEGRA124_CLK_PLL_U>,
869 <&tegra_car TEGRA124_CLK_USBD>;
870 clock-names = "reg", "pll_u", "utmi-pads";
871 resets = <&tegra_car 22>, <&tegra_car 22>;
872 reset-names = "usb", "utmi-pads";
873 nvidia,hssync-start-delay = <0>;
874 nvidia,idle-wait-delay = <17>;
875 nvidia,elastic-limit = <16>;
876 nvidia,term-range-adj = <6>;
877 nvidia,xcvr-setup = <9>;
878 nvidia,xcvr-lsfslew = <0>;
879 nvidia,xcvr-lsrslew = <3>;
880 nvidia,hssquelch-level = <2>;
881 nvidia,hsdiscon-level = <5>;
882 nvidia,xcvr-hsslew = <12>;
883 nvidia,has-utmi-pad-registers;
884 status = "disabled";
885 };
886
887 usb@0,7d004000 {
888 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
889 reg = <0x0 0x7d004000 0x0 0x4000>;
890 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
891 phy_type = "utmi";
892 clocks = <&tegra_car TEGRA124_CLK_USB2>;
893 clock-names = "usb";
894 resets = <&tegra_car 58>;
895 reset-names = "usb";
896 nvidia,phy = <&phy2>;
897 status = "disabled";
898 };
899
900 phy2: usb-phy@0,7d004000 {
901 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
902 reg = <0x0 0x7d004000 0x0 0x4000>,
903 <0x0 0x7d000000 0x0 0x4000>;
904 phy_type = "utmi";
905 clocks = <&tegra_car TEGRA124_CLK_USB2>,
906 <&tegra_car TEGRA124_CLK_PLL_U>,
907 <&tegra_car TEGRA124_CLK_USBD>;
908 clock-names = "reg", "pll_u", "utmi-pads";
909 resets = <&tegra_car 58>, <&tegra_car 22>;
910 reset-names = "usb", "utmi-pads";
911 nvidia,hssync-start-delay = <0>;
912 nvidia,idle-wait-delay = <17>;
913 nvidia,elastic-limit = <16>;
914 nvidia,term-range-adj = <6>;
915 nvidia,xcvr-setup = <9>;
916 nvidia,xcvr-lsfslew = <0>;
917 nvidia,xcvr-lsrslew = <3>;
918 nvidia,hssquelch-level = <2>;
919 nvidia,hsdiscon-level = <5>;
920 nvidia,xcvr-hsslew = <12>;
921 status = "disabled";
922 };
923
924 usb@0,7d008000 {
925 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
926 reg = <0x0 0x7d008000 0x0 0x4000>;
927 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
928 phy_type = "utmi";
929 clocks = <&tegra_car TEGRA124_CLK_USB3>;
930 clock-names = "usb";
931 resets = <&tegra_car 59>;
932 reset-names = "usb";
933 nvidia,phy = <&phy3>;
934 status = "disabled";
935 };
936
937 phy3: usb-phy@0,7d008000 {
938 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
939 reg = <0x0 0x7d008000 0x0 0x4000>,
940 <0x0 0x7d000000 0x0 0x4000>;
941 phy_type = "utmi";
942 clocks = <&tegra_car TEGRA124_CLK_USB3>,
943 <&tegra_car TEGRA124_CLK_PLL_U>,
944 <&tegra_car TEGRA124_CLK_USBD>;
945 clock-names = "reg", "pll_u", "utmi-pads";
946 resets = <&tegra_car 59>, <&tegra_car 22>;
947 reset-names = "usb", "utmi-pads";
948 nvidia,hssync-start-delay = <0>;
949 nvidia,idle-wait-delay = <17>;
950 nvidia,elastic-limit = <16>;
951 nvidia,term-range-adj = <6>;
952 nvidia,xcvr-setup = <9>;
953 nvidia,xcvr-lsfslew = <0>;
954 nvidia,xcvr-lsrslew = <3>;
955 nvidia,hssquelch-level = <2>;
956 nvidia,hsdiscon-level = <5>;
957 nvidia,xcvr-hsslew = <12>;
958 status = "disabled";
959 };
960
961 cpus {
962 #address-cells = <1>;
963 #size-cells = <0>;
964
965 cpu@0 {
966 device_type = "cpu";
967 compatible = "nvidia,denver", "arm,armv8";
968 reg = <0>;
969 };
970
971 cpu@1 {
972 device_type = "cpu";
973 compatible = "nvidia,denver", "arm,armv8";
974 reg = <1>;
975 };
976 };
977
978 timer {
979 compatible = "arm,armv7-timer";
980 interrupts = <GIC_PPI 13
981 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
982 <GIC_PPI 14
983 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
984 <GIC_PPI 11
985 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
986 <GIC_PPI 10
987 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
988 interrupt-parent = <&gic>;
989 };
990};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
new file mode 100644
index 000000000000..2b7f88950d1e
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
@@ -0,0 +1,45 @@
1#include "tegra210.dtsi"
2
3/ {
4 model = "NVIDIA Jetson TX1";
5 compatible = "nvidia,p2180", "nvidia,tegra210";
6
7 aliases {
8 rtc1 = "/rtc@0,7000e000";
9 serial0 = &uarta;
10 };
11
12 memory {
13 device_type = "memory";
14 reg = <0x0 0x80000000 0x1 0x0>;
15 };
16
17 /* debug port */
18 serial@0,70006000 {
19 status = "okay";
20 };
21
22 pmc@0,7000e400 {
23 nvidia,invert-interrupt;
24 };
25
26 /* eMMC */
27 sdhci@0,700b0600 {
28 status = "okay";
29 bus-width = <8>;
30 non-removable;
31 };
32
33 clocks {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 clk32k_in: clock@0 {
39 compatible = "fixed-clock";
40 reg = <0>;
41 #clock-cells = <0>;
42 clock-frequency = <32768>;
43 };
44 };
45};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-0000.dts
new file mode 100644
index 000000000000..1ddd8512e100
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-0000.dts
@@ -0,0 +1,9 @@
1/dts-v1/;
2
3#include "tegra210-p2530.dtsi"
4#include "tegra210-p2595.dtsi"
5
6/ {
7 model = "NVIDIA Tegra210 P2371 (P2530/P2595) reference design";
8 compatible = "nvidia,p2371-0000", "nvidia,tegra210";
9};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
new file mode 100644
index 000000000000..683b339a980c
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -0,0 +1,9 @@
1/dts-v1/;
2
3#include "tegra210-p2180.dtsi"
4#include "tegra210-p2597.dtsi"
5
6/ {
7 model = "NVIDIA Jetson TX1 Developer Kit";
8 compatible = "nvidia,p2371-2180", "nvidia,tegra210";
9};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi
new file mode 100644
index 000000000000..ece0dec61fae
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi
@@ -0,0 +1,50 @@
1#include "tegra210.dtsi"
2
3/ {
4 model = "NVIDIA Tegra210 P2530 main board";
5 compatible = "nvidia,p2530", "nvidia,tegra210";
6
7 aliases {
8 rtc1 = "/rtc@0,7000e000";
9 serial0 = &uarta;
10 };
11
12 memory {
13 device_type = "memory";
14 reg = <0x0 0x80000000 0x0 0xc0000000>;
15 };
16
17 /* debug port */
18 serial@0,70006000 {
19 status = "okay";
20 };
21
22 i2c@0,7000d000 {
23 status = "okay";
24 clock-frequency = <400000>;
25 };
26
27 pmc@0,7000e400 {
28 nvidia,invert-interrupt;
29 };
30
31 /* eMMC */
32 sdhci@0,700b0600 {
33 status = "okay";
34 bus-width = <8>;
35 non-removable;
36 };
37
38 clocks {
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 clk32k_in: clock@0 {
44 compatible = "fixed-clock";
45 reg = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <32768>;
48 };
49 };
50};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2571.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2571.dts
new file mode 100644
index 000000000000..58d27ddd57ff
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2571.dts
@@ -0,0 +1,1302 @@
1/dts-v1/;
2
3#include <dt-bindings/input/input.h>
4#include "tegra210-p2530.dtsi"
5
6/ {
7 model = "NVIDIA Tegra210 P2571 reference design";
8 compatible = "nvidia,p2571", "nvidia,tegra210";
9
10 pinmux: pinmux@0,700008d4 {
11 pinctrl-names = "boot";
12 pinctrl-0 = <&state_boot>;
13
14 state_boot: pinmux {
15 pex_l0_rst_n_pa0 {
16 nvidia,pins = "pex_l0_rst_n_pa0";
17 nvidia,pull = <TEGRA_PIN_PULL_UP>;
18 nvidia,tristate = <TEGRA_PIN_DISABLE>;
19 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
20 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
21 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
22 };
23 pex_l0_clkreq_n_pa1 {
24 nvidia,pins = "pex_l0_clkreq_n_pa1";
25 nvidia,function = "rsvd1";
26 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
27 nvidia,tristate = <TEGRA_PIN_ENABLE>;
28 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
29 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
30 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
31 };
32 pex_wake_n_pa2 {
33 nvidia,pins = "pex_wake_n_pa2";
34 nvidia,function = "rsvd1";
35 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
36 nvidia,tristate = <TEGRA_PIN_ENABLE>;
37 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
38 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
39 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
40 };
41 pex_l1_rst_n_pa3 {
42 nvidia,pins = "pex_l1_rst_n_pa3";
43 nvidia,function = "rsvd1";
44 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
45 nvidia,tristate = <TEGRA_PIN_ENABLE>;
46 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
47 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
48 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
49 };
50 pex_l1_clkreq_n_pa4 {
51 nvidia,pins = "pex_l1_clkreq_n_pa4";
52 nvidia,function = "rsvd1";
53 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
54 nvidia,tristate = <TEGRA_PIN_ENABLE>;
55 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
56 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
57 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
58 };
59 sata_led_active_pa5 {
60 nvidia,pins = "sata_led_active_pa5";
61 nvidia,pull = <TEGRA_PIN_PULL_UP>;
62 nvidia,tristate = <TEGRA_PIN_DISABLE>;
63 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
64 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
65 };
66 pa6 {
67 nvidia,pins = "pa6";
68 nvidia,function = "rsvd1";
69 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
70 nvidia,tristate = <TEGRA_PIN_ENABLE>;
71 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
72 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
73 };
74 dap1_fs_pb0 {
75 nvidia,pins = "dap1_fs_pb0";
76 nvidia,function = "rsvd1";
77 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
78 nvidia,tristate = <TEGRA_PIN_ENABLE>;
79 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
80 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
81 };
82 dap1_din_pb1 {
83 nvidia,pins = "dap1_din_pb1";
84 nvidia,function = "rsvd1";
85 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
86 nvidia,tristate = <TEGRA_PIN_ENABLE>;
87 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
88 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
89 };
90 dap1_dout_pb2 {
91 nvidia,pins = "dap1_dout_pb2";
92 nvidia,function = "rsvd1";
93 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
94 nvidia,tristate = <TEGRA_PIN_ENABLE>;
95 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
96 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
97 };
98 dap1_sclk_pb3 {
99 nvidia,pins = "dap1_sclk_pb3";
100 nvidia,function = "rsvd1";
101 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
102 nvidia,tristate = <TEGRA_PIN_ENABLE>;
103 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
104 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
105 };
106 spi2_mosi_pb4 {
107 nvidia,pins = "spi2_mosi_pb4";
108 nvidia,function = "rsvd2";
109 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
110 nvidia,tristate = <TEGRA_PIN_ENABLE>;
111 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
112 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
113 };
114 spi2_miso_pb5 {
115 nvidia,pins = "spi2_miso_pb5";
116 nvidia,function = "rsvd2";
117 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
118 nvidia,tristate = <TEGRA_PIN_ENABLE>;
119 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
120 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
121 };
122 spi2_sck_pb6 {
123 nvidia,pins = "spi2_sck_pb6";
124 nvidia,function = "rsvd2";
125 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
126 nvidia,tristate = <TEGRA_PIN_ENABLE>;
127 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
128 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
129 };
130 spi2_cs0_pb7 {
131 nvidia,pins = "spi2_cs0_pb7";
132 nvidia,function = "rsvd2";
133 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
134 nvidia,tristate = <TEGRA_PIN_ENABLE>;
135 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
136 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
137 };
138 spi1_mosi_pc0 {
139 nvidia,pins = "spi1_mosi_pc0";
140 nvidia,function = "rsvd1";
141 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
142 nvidia,tristate = <TEGRA_PIN_ENABLE>;
143 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
144 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
145 };
146 spi1_miso_pc1 {
147 nvidia,pins = "spi1_miso_pc1";
148 nvidia,function = "rsvd1";
149 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
150 nvidia,tristate = <TEGRA_PIN_ENABLE>;
151 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
152 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
153 };
154 spi1_sck_pc2 {
155 nvidia,pins = "spi1_sck_pc2";
156 nvidia,function = "rsvd1";
157 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
158 nvidia,tristate = <TEGRA_PIN_ENABLE>;
159 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
160 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
161 };
162 spi1_cs0_pc3 {
163 nvidia,pins = "spi1_cs0_pc3";
164 nvidia,function = "rsvd1";
165 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
166 nvidia,tristate = <TEGRA_PIN_ENABLE>;
167 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
168 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
169 };
170 spi1_cs1_pc4 {
171 nvidia,pins = "spi1_cs1_pc4";
172 nvidia,function = "rsvd1";
173 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
174 nvidia,tristate = <TEGRA_PIN_ENABLE>;
175 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
176 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
177 };
178 spi4_sck_pc5 {
179 nvidia,pins = "spi4_sck_pc5";
180 nvidia,function = "rsvd1";
181 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
182 nvidia,tristate = <TEGRA_PIN_ENABLE>;
183 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
184 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
185 };
186 spi4_cs0_pc6 {
187 nvidia,pins = "spi4_cs0_pc6";
188 nvidia,function = "rsvd1";
189 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
190 nvidia,tristate = <TEGRA_PIN_ENABLE>;
191 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
192 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
193 };
194 spi4_mosi_pc7 {
195 nvidia,pins = "spi4_mosi_pc7";
196 nvidia,function = "rsvd1";
197 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
198 nvidia,tristate = <TEGRA_PIN_ENABLE>;
199 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
200 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
201 };
202 spi4_miso_pd0 {
203 nvidia,pins = "spi4_miso_pd0";
204 nvidia,function = "rsvd1";
205 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
206 nvidia,tristate = <TEGRA_PIN_ENABLE>;
207 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
208 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
209 };
210 uart3_tx_pd1 {
211 nvidia,pins = "uart3_tx_pd1";
212 nvidia,function = "rsvd2";
213 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
214 nvidia,tristate = <TEGRA_PIN_ENABLE>;
215 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
216 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
217 };
218 uart3_rx_pd2 {
219 nvidia,pins = "uart3_rx_pd2";
220 nvidia,function = "rsvd2";
221 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
222 nvidia,tristate = <TEGRA_PIN_ENABLE>;
223 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
224 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
225 };
226 uart3_rts_pd3 {
227 nvidia,pins = "uart3_rts_pd3";
228 nvidia,function = "rsvd2";
229 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
230 nvidia,tristate = <TEGRA_PIN_ENABLE>;
231 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
232 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
233 };
234 uart3_cts_pd4 {
235 nvidia,pins = "uart3_cts_pd4";
236 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
237 nvidia,tristate = <TEGRA_PIN_DISABLE>;
238 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
239 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
240 };
241 dmic1_clk_pe0 {
242 nvidia,pins = "dmic1_clk_pe0";
243 nvidia,function = "i2s3";
244 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
245 nvidia,tristate = <TEGRA_PIN_DISABLE>;
246 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
247 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
248 };
249 dmic1_dat_pe1 {
250 nvidia,pins = "dmic1_dat_pe1";
251 nvidia,function = "i2s3";
252 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
253 nvidia,tristate = <TEGRA_PIN_DISABLE>;
254 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
255 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
256 };
257 dmic2_clk_pe2 {
258 nvidia,pins = "dmic2_clk_pe2";
259 nvidia,function = "i2s3";
260 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
261 nvidia,tristate = <TEGRA_PIN_DISABLE>;
262 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
263 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
264 };
265 dmic2_dat_pe3 {
266 nvidia,pins = "dmic2_dat_pe3";
267 nvidia,function = "i2s3";
268 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
269 nvidia,tristate = <TEGRA_PIN_DISABLE>;
270 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
271 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
272 };
273 dmic3_clk_pe4 {
274 nvidia,pins = "dmic3_clk_pe4";
275 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
276 nvidia,tristate = <TEGRA_PIN_DISABLE>;
277 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
278 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
279 };
280 dmic3_dat_pe5 {
281 nvidia,pins = "dmic3_dat_pe5";
282 nvidia,function = "rsvd2";
283 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
284 nvidia,tristate = <TEGRA_PIN_ENABLE>;
285 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
286 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
287 };
288 pe6 {
289 nvidia,pins = "pe6";
290 nvidia,function = "rsvd0";
291 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
292 nvidia,tristate = <TEGRA_PIN_ENABLE>;
293 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
294 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
295 };
296 pe7 {
297 nvidia,pins = "pe7";
298 nvidia,function = "pwm3";
299 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
300 nvidia,tristate = <TEGRA_PIN_DISABLE>;
301 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
302 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
303 };
304 gen3_i2c_scl_pf0 {
305 nvidia,pins = "gen3_i2c_scl_pf0";
306 nvidia,function = "i2c3";
307 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
308 nvidia,tristate = <TEGRA_PIN_DISABLE>;
309 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
310 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
311 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
312 };
313 gen3_i2c_sda_pf1 {
314 nvidia,pins = "gen3_i2c_sda_pf1";
315 nvidia,function = "i2c3";
316 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
317 nvidia,tristate = <TEGRA_PIN_DISABLE>;
318 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
319 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
320 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
321 };
322 uart2_tx_pg0 {
323 nvidia,pins = "uart2_tx_pg0";
324 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
325 nvidia,tristate = <TEGRA_PIN_DISABLE>;
326 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
327 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
328 };
329 uart2_rx_pg1 {
330 nvidia,pins = "uart2_rx_pg1";
331 nvidia,function = "uartb";
332 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
333 nvidia,tristate = <TEGRA_PIN_ENABLE>;
334 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
335 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
336 };
337 uart2_rts_pg2 {
338 nvidia,pins = "uart2_rts_pg2";
339 nvidia,function = "rsvd2";
340 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
341 nvidia,tristate = <TEGRA_PIN_ENABLE>;
342 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
343 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
344 };
345 uart2_cts_pg3 {
346 nvidia,pins = "uart2_cts_pg3";
347 nvidia,function = "rsvd2";
348 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
349 nvidia,tristate = <TEGRA_PIN_ENABLE>;
350 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
351 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
352 };
353 wifi_en_ph0 {
354 nvidia,pins = "wifi_en_ph0";
355 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
356 nvidia,tristate = <TEGRA_PIN_DISABLE>;
357 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
358 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
359 };
360 wifi_rst_ph1 {
361 nvidia,pins = "wifi_rst_ph1";
362 nvidia,function = "rsvd0";
363 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
364 nvidia,tristate = <TEGRA_PIN_ENABLE>;
365 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
366 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
367 };
368 wifi_wake_ap_ph2 {
369 nvidia,pins = "wifi_wake_ap_ph2";
370 nvidia,pull = <TEGRA_PIN_PULL_UP>;
371 nvidia,tristate = <TEGRA_PIN_DISABLE>;
372 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
373 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
374 };
375 ap_wake_bt_ph3 {
376 nvidia,pins = "ap_wake_bt_ph3";
377 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
378 nvidia,tristate = <TEGRA_PIN_DISABLE>;
379 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
380 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
381 };
382 bt_rst_ph4 {
383 nvidia,pins = "bt_rst_ph4";
384 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
385 nvidia,tristate = <TEGRA_PIN_DISABLE>;
386 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
387 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
388 };
389 bt_wake_ap_ph5 {
390 nvidia,pins = "bt_wake_ap_ph5";
391 nvidia,pull = <TEGRA_PIN_PULL_UP>;
392 nvidia,tristate = <TEGRA_PIN_DISABLE>;
393 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
394 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
395 };
396 ph6 {
397 nvidia,pins = "ph6";
398 nvidia,function = "rsvd0";
399 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
400 nvidia,tristate = <TEGRA_PIN_ENABLE>;
401 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
402 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
403 };
404 ap_wake_nfc_ph7 {
405 nvidia,pins = "ap_wake_nfc_ph7";
406 nvidia,function = "rsvd0";
407 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
408 nvidia,tristate = <TEGRA_PIN_ENABLE>;
409 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
410 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
411 };
412 nfc_en_pi0 {
413 nvidia,pins = "nfc_en_pi0";
414 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
415 nvidia,tristate = <TEGRA_PIN_DISABLE>;
416 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
417 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
418 };
419 nfc_int_pi1 {
420 nvidia,pins = "nfc_int_pi1";
421 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
422 nvidia,tristate = <TEGRA_PIN_DISABLE>;
423 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
424 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
425 };
426 gps_en_pi2 {
427 nvidia,pins = "gps_en_pi2";
428 nvidia,function = "rsvd0";
429 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
430 nvidia,tristate = <TEGRA_PIN_ENABLE>;
431 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
432 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
433 };
434 gps_rst_pi3 {
435 nvidia,pins = "gps_rst_pi3";
436 nvidia,function = "rsvd0";
437 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
438 nvidia,tristate = <TEGRA_PIN_ENABLE>;
439 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
440 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
441 };
442 uart4_tx_pi4 {
443 nvidia,pins = "uart4_tx_pi4";
444 nvidia,function = "uartd";
445 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
446 nvidia,tristate = <TEGRA_PIN_DISABLE>;
447 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
448 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
449 };
450 uart4_rx_pi5 {
451 nvidia,pins = "uart4_rx_pi5";
452 nvidia,function = "uartd";
453 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
454 nvidia,tristate = <TEGRA_PIN_DISABLE>;
455 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
456 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
457 };
458 uart4_rts_pi6 {
459 nvidia,pins = "uart4_rts_pi6";
460 nvidia,function = "uartd";
461 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
462 nvidia,tristate = <TEGRA_PIN_DISABLE>;
463 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
464 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
465 };
466 uart4_cts_pi7 {
467 nvidia,pins = "uart4_cts_pi7";
468 nvidia,function = "uartd";
469 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
470 nvidia,tristate = <TEGRA_PIN_DISABLE>;
471 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
472 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
473 };
474 gen1_i2c_sda_pj0 {
475 nvidia,pins = "gen1_i2c_sda_pj0";
476 nvidia,function = "i2c1";
477 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
478 nvidia,tristate = <TEGRA_PIN_DISABLE>;
479 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
480 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
481 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
482 };
483 gen1_i2c_scl_pj1 {
484 nvidia,pins = "gen1_i2c_scl_pj1";
485 nvidia,function = "i2c1";
486 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
487 nvidia,tristate = <TEGRA_PIN_DISABLE>;
488 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
489 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
490 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
491 };
492 gen2_i2c_scl_pj2 {
493 nvidia,pins = "gen2_i2c_scl_pj2";
494 nvidia,function = "i2c2";
495 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
496 nvidia,tristate = <TEGRA_PIN_DISABLE>;
497 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
498 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
499 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
500 };
501 gen2_i2c_sda_pj3 {
502 nvidia,pins = "gen2_i2c_sda_pj3";
503 nvidia,function = "i2c2";
504 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
505 nvidia,tristate = <TEGRA_PIN_DISABLE>;
506 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
507 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
508 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
509 };
510 dap4_fs_pj4 {
511 nvidia,pins = "dap4_fs_pj4";
512 nvidia,function = "rsvd1";
513 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
514 nvidia,tristate = <TEGRA_PIN_ENABLE>;
515 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
516 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
517 };
518 dap4_din_pj5 {
519 nvidia,pins = "dap4_din_pj5";
520 nvidia,function = "rsvd1";
521 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
522 nvidia,tristate = <TEGRA_PIN_ENABLE>;
523 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
524 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
525 };
526 dap4_dout_pj6 {
527 nvidia,pins = "dap4_dout_pj6";
528 nvidia,function = "rsvd1";
529 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
530 nvidia,tristate = <TEGRA_PIN_ENABLE>;
531 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
532 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
533 };
534 dap4_sclk_pj7 {
535 nvidia,pins = "dap4_sclk_pj7";
536 nvidia,function = "rsvd1";
537 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
538 nvidia,tristate = <TEGRA_PIN_ENABLE>;
539 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
540 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
541 };
542 pk0 {
543 nvidia,pins = "pk0";
544 nvidia,function = "rsvd2";
545 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
546 nvidia,tristate = <TEGRA_PIN_ENABLE>;
547 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
548 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
549 };
550 pk1 {
551 nvidia,pins = "pk1";
552 nvidia,function = "rsvd2";
553 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
554 nvidia,tristate = <TEGRA_PIN_ENABLE>;
555 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
556 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
557 };
558 pk2 {
559 nvidia,pins = "pk2";
560 nvidia,function = "rsvd2";
561 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
562 nvidia,tristate = <TEGRA_PIN_ENABLE>;
563 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
564 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
565 };
566 pk3 {
567 nvidia,pins = "pk3";
568 nvidia,function = "rsvd2";
569 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
570 nvidia,tristate = <TEGRA_PIN_ENABLE>;
571 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
572 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
573 };
574 pk4 {
575 nvidia,pins = "pk4";
576 nvidia,function = "rsvd1";
577 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
578 nvidia,tristate = <TEGRA_PIN_ENABLE>;
579 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
580 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
581 };
582 pk5 {
583 nvidia,pins = "pk5";
584 nvidia,function = "rsvd1";
585 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
586 nvidia,tristate = <TEGRA_PIN_ENABLE>;
587 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
588 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
589 };
590 pk6 {
591 nvidia,pins = "pk6";
592 nvidia,function = "rsvd1";
593 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
594 nvidia,tristate = <TEGRA_PIN_ENABLE>;
595 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
596 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
597 };
598 pk7 {
599 nvidia,pins = "pk7";
600 nvidia,function = "rsvd1";
601 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
602 nvidia,tristate = <TEGRA_PIN_ENABLE>;
603 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
604 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
605 };
606 pl0 {
607 nvidia,pins = "pl0";
608 nvidia,function = "rsvd0";
609 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
610 nvidia,tristate = <TEGRA_PIN_ENABLE>;
611 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
612 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
613 };
614 pl1 {
615 nvidia,pins = "pl1";
616 nvidia,function = "rsvd1";
617 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
618 nvidia,tristate = <TEGRA_PIN_ENABLE>;
619 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
620 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
621 };
622 sdmmc1_clk_pm0 {
623 nvidia,pins = "sdmmc1_clk_pm0";
624 nvidia,function = "sdmmc1";
625 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
626 nvidia,tristate = <TEGRA_PIN_DISABLE>;
627 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
628 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
629 };
630 sdmmc1_cmd_pm1 {
631 nvidia,pins = "sdmmc1_cmd_pm1";
632 nvidia,function = "sdmmc1";
633 nvidia,pull = <TEGRA_PIN_PULL_UP>;
634 nvidia,tristate = <TEGRA_PIN_DISABLE>;
635 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
636 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
637 };
638 sdmmc1_dat3_pm2 {
639 nvidia,pins = "sdmmc1_dat3_pm2";
640 nvidia,function = "sdmmc1";
641 nvidia,pull = <TEGRA_PIN_PULL_UP>;
642 nvidia,tristate = <TEGRA_PIN_DISABLE>;
643 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
644 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
645 };
646 sdmmc1_dat2_pm3 {
647 nvidia,pins = "sdmmc1_dat2_pm3";
648 nvidia,function = "sdmmc1";
649 nvidia,pull = <TEGRA_PIN_PULL_UP>;
650 nvidia,tristate = <TEGRA_PIN_DISABLE>;
651 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
652 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
653 };
654 sdmmc1_dat1_pm4 {
655 nvidia,pins = "sdmmc1_dat1_pm4";
656 nvidia,function = "sdmmc1";
657 nvidia,pull = <TEGRA_PIN_PULL_UP>;
658 nvidia,tristate = <TEGRA_PIN_DISABLE>;
659 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
660 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
661 };
662 sdmmc1_dat0_pm5 {
663 nvidia,pins = "sdmmc1_dat0_pm5";
664 nvidia,function = "sdmmc1";
665 nvidia,pull = <TEGRA_PIN_PULL_UP>;
666 nvidia,tristate = <TEGRA_PIN_DISABLE>;
667 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
668 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
669 };
670 sdmmc3_clk_pp0 {
671 nvidia,pins = "sdmmc3_clk_pp0";
672 nvidia,function = "sdmmc3";
673 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
674 nvidia,tristate = <TEGRA_PIN_DISABLE>;
675 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
676 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
677 };
678 sdmmc3_cmd_pp1 {
679 nvidia,pins = "sdmmc3_cmd_pp1";
680 nvidia,function = "sdmmc3";
681 nvidia,pull = <TEGRA_PIN_PULL_UP>;
682 nvidia,tristate = <TEGRA_PIN_DISABLE>;
683 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
684 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
685 };
686 sdmmc3_dat3_pp2 {
687 nvidia,pins = "sdmmc3_dat3_pp2";
688 nvidia,function = "sdmmc3";
689 nvidia,pull = <TEGRA_PIN_PULL_UP>;
690 nvidia,tristate = <TEGRA_PIN_DISABLE>;
691 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
692 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
693 };
694 sdmmc3_dat2_pp3 {
695 nvidia,pins = "sdmmc3_dat2_pp3";
696 nvidia,function = "sdmmc3";
697 nvidia,pull = <TEGRA_PIN_PULL_UP>;
698 nvidia,tristate = <TEGRA_PIN_DISABLE>;
699 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
700 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
701 };
702 sdmmc3_dat1_pp4 {
703 nvidia,pins = "sdmmc3_dat1_pp4";
704 nvidia,function = "sdmmc3";
705 nvidia,pull = <TEGRA_PIN_PULL_UP>;
706 nvidia,tristate = <TEGRA_PIN_DISABLE>;
707 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
708 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
709 };
710 sdmmc3_dat0_pp5 {
711 nvidia,pins = "sdmmc3_dat0_pp5";
712 nvidia,function = "sdmmc3";
713 nvidia,pull = <TEGRA_PIN_PULL_UP>;
714 nvidia,tristate = <TEGRA_PIN_DISABLE>;
715 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
716 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
717 };
718 cam1_mclk_ps0 {
719 nvidia,pins = "cam1_mclk_ps0";
720 nvidia,function = "rsvd1";
721 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
722 nvidia,tristate = <TEGRA_PIN_ENABLE>;
723 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
724 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
725 };
726 cam2_mclk_ps1 {
727 nvidia,pins = "cam2_mclk_ps1";
728 nvidia,function = "rsvd1";
729 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
730 nvidia,tristate = <TEGRA_PIN_ENABLE>;
731 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
732 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
733 };
734 cam_i2c_scl_ps2 {
735 nvidia,pins = "cam_i2c_scl_ps2";
736 nvidia,function = "i2cvi";
737 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
738 nvidia,tristate = <TEGRA_PIN_DISABLE>;
739 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
740 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
741 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
742 };
743 cam_i2c_sda_ps3 {
744 nvidia,pins = "cam_i2c_sda_ps3";
745 nvidia,function = "i2cvi";
746 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
747 nvidia,tristate = <TEGRA_PIN_DISABLE>;
748 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
749 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
750 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
751 };
752 cam_rst_ps4 {
753 nvidia,pins = "cam_rst_ps4";
754 nvidia,function = "rsvd1";
755 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
756 nvidia,tristate = <TEGRA_PIN_ENABLE>;
757 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
758 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
759 };
760 cam_af_en_ps5 {
761 nvidia,pins = "cam_af_en_ps5";
762 nvidia,function = "rsvd2";
763 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
764 nvidia,tristate = <TEGRA_PIN_ENABLE>;
765 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
766 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
767 };
768 cam_flash_en_ps6 {
769 nvidia,pins = "cam_flash_en_ps6";
770 nvidia,function = "rsvd2";
771 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
772 nvidia,tristate = <TEGRA_PIN_ENABLE>;
773 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
774 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
775 };
776 cam1_pwdn_ps7 {
777 nvidia,pins = "cam1_pwdn_ps7";
778 nvidia,function = "rsvd1";
779 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
780 nvidia,tristate = <TEGRA_PIN_ENABLE>;
781 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
782 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
783 };
784 cam2_pwdn_pt0 {
785 nvidia,pins = "cam2_pwdn_pt0";
786 nvidia,function = "rsvd1";
787 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
788 nvidia,tristate = <TEGRA_PIN_ENABLE>;
789 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
790 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
791 };
792 cam1_strobe_pt1 {
793 nvidia,pins = "cam1_strobe_pt1";
794 nvidia,function = "rsvd1";
795 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
796 nvidia,tristate = <TEGRA_PIN_ENABLE>;
797 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
798 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
799 };
800 uart1_tx_pu0 {
801 nvidia,pins = "uart1_tx_pu0";
802 nvidia,function = "uarta";
803 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
804 nvidia,tristate = <TEGRA_PIN_DISABLE>;
805 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
806 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
807 };
808 uart1_rx_pu1 {
809 nvidia,pins = "uart1_rx_pu1";
810 nvidia,function = "uarta";
811 nvidia,pull = <TEGRA_PIN_PULL_UP>;
812 nvidia,tristate = <TEGRA_PIN_DISABLE>;
813 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
814 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
815 };
816 uart1_rts_pu2 {
817 nvidia,pins = "uart1_rts_pu2";
818 nvidia,function = "uarta";
819 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
820 nvidia,tristate = <TEGRA_PIN_DISABLE>;
821 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
822 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
823 };
824 uart1_cts_pu3 {
825 nvidia,pins = "uart1_cts_pu3";
826 nvidia,function = "uarta";
827 nvidia,pull = <TEGRA_PIN_PULL_UP>;
828 nvidia,tristate = <TEGRA_PIN_DISABLE>;
829 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
830 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
831 };
832 lcd_bl_pwm_pv0 {
833 nvidia,pins = "lcd_bl_pwm_pv0";
834 nvidia,function = "pwm0";
835 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
836 nvidia,tristate = <TEGRA_PIN_DISABLE>;
837 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
838 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
839 };
840 lcd_bl_en_pv1 {
841 nvidia,pins = "lcd_bl_en_pv1";
842 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
843 nvidia,tristate = <TEGRA_PIN_DISABLE>;
844 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
845 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
846 };
847 lcd_rst_pv2 {
848 nvidia,pins = "lcd_rst_pv2";
849 nvidia,function = "rsvd0";
850 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
851 nvidia,tristate = <TEGRA_PIN_ENABLE>;
852 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
853 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
854 };
855 lcd_gpio1_pv3 {
856 nvidia,pins = "lcd_gpio1_pv3";
857 nvidia,function = "rsvd1";
858 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
859 nvidia,tristate = <TEGRA_PIN_ENABLE>;
860 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
861 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
862 };
863 lcd_gpio2_pv4 {
864 nvidia,pins = "lcd_gpio2_pv4";
865 nvidia,function = "pwm1";
866 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
867 nvidia,tristate = <TEGRA_PIN_DISABLE>;
868 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
869 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
870 };
871 ap_ready_pv5 {
872 nvidia,pins = "ap_ready_pv5";
873 nvidia,function = "rsvd0";
874 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
875 nvidia,tristate = <TEGRA_PIN_ENABLE>;
876 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
877 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
878 };
879 touch_rst_pv6 {
880 nvidia,pins = "touch_rst_pv6";
881 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
882 nvidia,tristate = <TEGRA_PIN_DISABLE>;
883 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
884 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
885 };
886 touch_clk_pv7 {
887 nvidia,pins = "touch_clk_pv7";
888 nvidia,function = "rsvd1";
889 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
890 nvidia,tristate = <TEGRA_PIN_ENABLE>;
891 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
892 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
893 };
894 modem_wake_ap_px0 {
895 nvidia,pins = "modem_wake_ap_px0";
896 nvidia,function = "rsvd0";
897 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
898 nvidia,tristate = <TEGRA_PIN_ENABLE>;
899 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
900 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
901 };
902 touch_int_px1 {
903 nvidia,pins = "touch_int_px1";
904 nvidia,function = "rsvd0";
905 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
906 nvidia,tristate = <TEGRA_PIN_ENABLE>;
907 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
908 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
909 };
910 motion_int_px2 {
911 nvidia,pins = "motion_int_px2";
912 nvidia,function = "rsvd0";
913 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
914 nvidia,tristate = <TEGRA_PIN_ENABLE>;
915 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
916 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
917 };
918 als_prox_int_px3 {
919 nvidia,pins = "als_prox_int_px3";
920 nvidia,function = "rsvd0";
921 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
922 nvidia,tristate = <TEGRA_PIN_ENABLE>;
923 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
924 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
925 };
926 temp_alert_px4 {
927 nvidia,pins = "temp_alert_px4";
928 nvidia,pull = <TEGRA_PIN_PULL_UP>;
929 nvidia,tristate = <TEGRA_PIN_DISABLE>;
930 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
931 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
932 };
933 button_power_on_px5 {
934 nvidia,pins = "button_power_on_px5";
935 nvidia,function = "rsvd0";
936 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
937 nvidia,tristate = <TEGRA_PIN_ENABLE>;
938 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
939 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
940 };
941 button_vol_up_px6 {
942 nvidia,pins = "button_vol_up_px6";
943 nvidia,pull = <TEGRA_PIN_PULL_UP>;
944 nvidia,tristate = <TEGRA_PIN_DISABLE>;
945 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
946 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
947 };
948 button_vol_down_px7 {
949 nvidia,pins = "button_vol_down_px7";
950 nvidia,pull = <TEGRA_PIN_PULL_UP>;
951 nvidia,tristate = <TEGRA_PIN_DISABLE>;
952 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
953 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
954 };
955 button_slide_sw_py0 {
956 nvidia,pins = "button_slide_sw_py0";
957 nvidia,function = "rsvd0";
958 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
959 nvidia,tristate = <TEGRA_PIN_ENABLE>;
960 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
961 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
962 };
963 button_home_py1 {
964 nvidia,pins = "button_home_py1";
965 nvidia,pull = <TEGRA_PIN_PULL_UP>;
966 nvidia,tristate = <TEGRA_PIN_DISABLE>;
967 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
968 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
969 };
970 lcd_te_py2 {
971 nvidia,pins = "lcd_te_py2";
972 nvidia,function = "rsvd1";
973 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
974 nvidia,tristate = <TEGRA_PIN_ENABLE>;
975 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
976 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
977 };
978 pwr_i2c_scl_py3 {
979 nvidia,pins = "pwr_i2c_scl_py3";
980 nvidia,function = "i2cpmu";
981 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
982 nvidia,tristate = <TEGRA_PIN_DISABLE>;
983 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
984 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
985 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
986 };
987 pwr_i2c_sda_py4 {
988 nvidia,pins = "pwr_i2c_sda_py4";
989 nvidia,function = "i2cpmu";
990 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
991 nvidia,tristate = <TEGRA_PIN_DISABLE>;
992 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
993 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
994 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
995 };
996 clk_32k_out_py5 {
997 nvidia,pins = "clk_32k_out_py5";
998 nvidia,function = "soc";
999 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1000 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1001 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1002 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1003 };
1004 pz0 {
1005 nvidia,pins = "pz0";
1006 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1007 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1008 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1009 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1010 };
1011 pz1 {
1012 nvidia,pins = "pz1";
1013 nvidia,function = "sdmmc1";
1014 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1015 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1016 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1017 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1018 };
1019 pz2 {
1020 nvidia,pins = "pz2";
1021 nvidia,function = "rsvd2";
1022 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1023 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1024 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1025 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1026 };
1027 pz3 {
1028 nvidia,pins = "pz3";
1029 nvidia,function = "rsvd1";
1030 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1031 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1032 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1033 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1034 };
1035 pz4 {
1036 nvidia,pins = "pz4";
1037 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1038 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1039 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1040 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1041 };
1042 pz5 {
1043 nvidia,pins = "pz5";
1044 nvidia,function = "soc";
1045 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1046 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1047 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1048 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1049 };
1050 dap2_fs_paa0 {
1051 nvidia,pins = "dap2_fs_paa0";
1052 nvidia,function = "i2s2";
1053 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1054 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1055 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1056 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1057 };
1058 dap2_sclk_paa1 {
1059 nvidia,pins = "dap2_sclk_paa1";
1060 nvidia,function = "i2s2";
1061 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1062 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1063 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1064 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1065 };
1066 dap2_din_paa2 {
1067 nvidia,pins = "dap2_din_paa2";
1068 nvidia,function = "i2s2";
1069 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1070 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1071 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1072 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1073 };
1074 dap2_dout_paa3 {
1075 nvidia,pins = "dap2_dout_paa3";
1076 nvidia,function = "i2s2";
1077 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1078 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1079 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1080 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1081 };
1082 aud_mclk_pbb0 {
1083 nvidia,pins = "aud_mclk_pbb0";
1084 nvidia,function = "aud";
1085 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1086 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1087 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1088 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1089 };
1090 dvfs_pwm_pbb1 {
1091 nvidia,pins = "dvfs_pwm_pbb1";
1092 nvidia,function = "cldvfs";
1093 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1094 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1095 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1096 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1097 };
1098 dvfs_clk_pbb2 {
1099 nvidia,pins = "dvfs_clk_pbb2";
1100 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1101 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1102 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1103 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1104 };
1105 gpio_x1_aud_pbb3 {
1106 nvidia,pins = "gpio_x1_aud_pbb3";
1107 nvidia,function = "rsvd0";
1108 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1109 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1110 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1111 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1112 };
1113 gpio_x3_aud_pbb4 {
1114 nvidia,pins = "gpio_x3_aud_pbb4";
1115 nvidia,function = "rsvd0";
1116 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1117 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1118 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1119 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1120 };
1121 hdmi_cec_pcc0 {
1122 nvidia,pins = "hdmi_cec_pcc0";
1123 nvidia,function = "cec";
1124 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1125 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1126 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1127 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1128 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
1129 };
1130 hdmi_int_dp_hpd_pcc1 {
1131 nvidia,pins = "hdmi_int_dp_hpd_pcc1";
1132 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1133 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1134 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1135 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1136 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
1137 };
1138 spdif_out_pcc2 {
1139 nvidia,pins = "spdif_out_pcc2";
1140 nvidia,function = "rsvd1";
1141 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1142 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1143 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1144 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1145 };
1146 spdif_in_pcc3 {
1147 nvidia,pins = "spdif_in_pcc3";
1148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1150 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1151 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1152 };
1153 usb_vbus_en0_pcc4 {
1154 nvidia,pins = "usb_vbus_en0_pcc4";
1155 nvidia,function = "usb";
1156 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1157 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1158 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1159 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1160 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
1161 };
1162 usb_vbus_en1_pcc5 {
1163 nvidia,pins = "usb_vbus_en1_pcc5";
1164 nvidia,function = "usb";
1165 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1166 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1167 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1168 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1169 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
1170 };
1171 dp_hpd0_pcc6 {
1172 nvidia,pins = "dp_hpd0_pcc6";
1173 nvidia,function = "rsvd1";
1174 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1175 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1176 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1177 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1178 };
1179 pcc7 {
1180 nvidia,pins = "pcc7";
1181 nvidia,function = "rsvd0";
1182 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1183 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1184 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1185 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1186 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
1187 };
1188 spi2_cs1_pdd0 {
1189 nvidia,pins = "spi2_cs1_pdd0";
1190 nvidia,function = "rsvd1";
1191 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1192 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1193 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1194 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1195 };
1196 qspi_sck_pee0 {
1197 nvidia,pins = "qspi_sck_pee0";
1198 nvidia,function = "rsvd1";
1199 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1200 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1201 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1202 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1203 };
1204 qspi_cs_n_pee1 {
1205 nvidia,pins = "qspi_cs_n_pee1";
1206 nvidia,function = "rsvd1";
1207 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1208 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1209 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1210 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1211 };
1212 qspi_io0_pee2 {
1213 nvidia,pins = "qspi_io0_pee2";
1214 nvidia,function = "rsvd1";
1215 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1216 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1217 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1218 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1219 };
1220 qspi_io1_pee3 {
1221 nvidia,pins = "qspi_io1_pee3";
1222 nvidia,function = "rsvd1";
1223 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1224 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1225 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1226 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1227 };
1228 qspi_io2_pee4 {
1229 nvidia,pins = "qspi_io2_pee4";
1230 nvidia,function = "rsvd1";
1231 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1232 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1233 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1234 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1235 };
1236 qspi_io3_pee5 {
1237 nvidia,pins = "qspi_io3_pee5";
1238 nvidia,function = "rsvd1";
1239 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1240 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1241 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1242 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1243 };
1244 core_pwr_req {
1245 nvidia,pins = "core_pwr_req";
1246 nvidia,function = "core";
1247 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1248 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1249 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1250 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1251 };
1252 cpu_pwr_req {
1253 nvidia,pins = "cpu_pwr_req";
1254 nvidia,function = "cpu";
1255 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1256 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1257 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1258 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1259 };
1260 pwr_int_n {
1261 nvidia,pins = "pwr_int_n";
1262 nvidia,function = "pmi";
1263 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1264 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1265 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1266 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1267 };
1268 clk_32k_in {
1269 nvidia,pins = "clk_32k_in";
1270 nvidia,function = "clk";
1271 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1272 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1273 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1274 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1275 };
1276 jtag_rtck {
1277 nvidia,pins = "jtag_rtck";
1278 nvidia,function = "jtag";
1279 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1280 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1281 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1282 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1283 };
1284 clk_req {
1285 nvidia,pins = "clk_req";
1286 nvidia,function = "sys";
1287 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1288 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1289 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1290 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1291 };
1292 shutdown {
1293 nvidia,pins = "shutdown";
1294 nvidia,function = "shutdown";
1295 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1296 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1297 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1298 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1299 };
1300 };
1301 };
1302};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi
new file mode 100644
index 000000000000..f3f91392214e
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi
@@ -0,0 +1,1272 @@
1/ {
2 model = "NVIDIA Tegra210 P2595 I/O board";
3 compatible = "nvidia,p2595", "nvidia,tegra210";
4
5 pinmux: pinmux@0,700008d4 {
6 pinctrl-names = "boot";
7 pinctrl-0 = <&state_boot>;
8
9 state_boot: pinmux {
10 pex_l0_rst_n_pa0 {
11 nvidia,pins = "pex_l0_rst_n_pa0";
12 nvidia,function = "pe0";
13 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
14 nvidia,tristate = <TEGRA_PIN_DISABLE>;
15 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
16 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
17 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
18 };
19 pex_l0_clkreq_n_pa1 {
20 nvidia,pins = "pex_l0_clkreq_n_pa1";
21 nvidia,function = "pe0";
22 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
23 nvidia,tristate = <TEGRA_PIN_DISABLE>;
24 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
25 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
26 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
27 };
28 pex_wake_n_pa2 {
29 nvidia,pins = "pex_wake_n_pa2";
30 nvidia,function = "pe";
31 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
32 nvidia,tristate = <TEGRA_PIN_DISABLE>;
33 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
34 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
35 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
36 };
37 pex_l1_rst_n_pa3 {
38 nvidia,pins = "pex_l1_rst_n_pa3";
39 nvidia,function = "pe1";
40 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
41 nvidia,tristate = <TEGRA_PIN_DISABLE>;
42 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
43 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
44 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
45 };
46 pex_l1_clkreq_n_pa4 {
47 nvidia,pins = "pex_l1_clkreq_n_pa4";
48 nvidia,function = "pe1";
49 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
50 nvidia,tristate = <TEGRA_PIN_DISABLE>;
51 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
52 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
53 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
54 };
55 sata_led_active_pa5 {
56 nvidia,pins = "sata_led_active_pa5";
57 nvidia,pull = <TEGRA_PIN_PULL_UP>;
58 nvidia,tristate = <TEGRA_PIN_DISABLE>;
59 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
60 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
61 };
62 pa6 {
63 nvidia,pins = "pa6";
64 nvidia,function = "rsvd1";
65 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
66 nvidia,tristate = <TEGRA_PIN_ENABLE>;
67 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
69 };
70 dap1_fs_pb0 {
71 nvidia,pins = "dap1_fs_pb0";
72 nvidia,function = "i2s1";
73 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
74 nvidia,tristate = <TEGRA_PIN_DISABLE>;
75 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
76 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
77 };
78 dap1_din_pb1 {
79 nvidia,pins = "dap1_din_pb1";
80 nvidia,function = "i2s1";
81 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
82 nvidia,tristate = <TEGRA_PIN_DISABLE>;
83 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
84 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
85 };
86 dap1_dout_pb2 {
87 nvidia,pins = "dap1_dout_pb2";
88 nvidia,function = "i2s1";
89 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
90 nvidia,tristate = <TEGRA_PIN_DISABLE>;
91 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
92 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
93 };
94 dap1_sclk_pb3 {
95 nvidia,pins = "dap1_sclk_pb3";
96 nvidia,function = "i2s1";
97 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
98 nvidia,tristate = <TEGRA_PIN_DISABLE>;
99 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
100 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
101 };
102 spi2_mosi_pb4 {
103 nvidia,pins = "spi2_mosi_pb4";
104 nvidia,function = "rsvd2";
105 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
106 nvidia,tristate = <TEGRA_PIN_ENABLE>;
107 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
108 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
109 };
110 spi2_miso_pb5 {
111 nvidia,pins = "spi2_miso_pb5";
112 nvidia,function = "rsvd2";
113 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
114 nvidia,tristate = <TEGRA_PIN_ENABLE>;
115 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
116 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
117 };
118 spi2_sck_pb6 {
119 nvidia,pins = "spi2_sck_pb6";
120 nvidia,function = "rsvd2";
121 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
122 nvidia,tristate = <TEGRA_PIN_ENABLE>;
123 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
124 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
125 };
126 spi2_cs0_pb7 {
127 nvidia,pins = "spi2_cs0_pb7";
128 nvidia,function = "rsvd2";
129 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
130 nvidia,tristate = <TEGRA_PIN_ENABLE>;
131 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
132 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
133 };
134 spi1_mosi_pc0 {
135 nvidia,pins = "spi1_mosi_pc0";
136 nvidia,function = "spi1";
137 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
138 nvidia,tristate = <TEGRA_PIN_DISABLE>;
139 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
140 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
141 };
142 spi1_miso_pc1 {
143 nvidia,pins = "spi1_miso_pc1";
144 nvidia,function = "spi1";
145 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
146 nvidia,tristate = <TEGRA_PIN_DISABLE>;
147 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
148 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
149 };
150 spi1_sck_pc2 {
151 nvidia,pins = "spi1_sck_pc2";
152 nvidia,function = "spi1";
153 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
154 nvidia,tristate = <TEGRA_PIN_DISABLE>;
155 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
156 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
157 };
158 spi1_cs0_pc3 {
159 nvidia,pins = "spi1_cs0_pc3";
160 nvidia,function = "spi1";
161 nvidia,pull = <TEGRA_PIN_PULL_UP>;
162 nvidia,tristate = <TEGRA_PIN_DISABLE>;
163 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
164 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
165 };
166 spi1_cs1_pc4 {
167 nvidia,pins = "spi1_cs1_pc4";
168 nvidia,function = "spi1";
169 nvidia,pull = <TEGRA_PIN_PULL_UP>;
170 nvidia,tristate = <TEGRA_PIN_DISABLE>;
171 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
172 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
173 };
174 spi4_sck_pc5 {
175 nvidia,pins = "spi4_sck_pc5";
176 nvidia,function = "spi4";
177 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
178 nvidia,tristate = <TEGRA_PIN_DISABLE>;
179 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
180 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
181 };
182 spi4_cs0_pc6 {
183 nvidia,pins = "spi4_cs0_pc6";
184 nvidia,function = "spi4";
185 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
186 nvidia,tristate = <TEGRA_PIN_DISABLE>;
187 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
188 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
189 };
190 spi4_mosi_pc7 {
191 nvidia,pins = "spi4_mosi_pc7";
192 nvidia,function = "spi4";
193 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
194 nvidia,tristate = <TEGRA_PIN_DISABLE>;
195 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
196 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
197 };
198 spi4_miso_pd0 {
199 nvidia,pins = "spi4_miso_pd0";
200 nvidia,function = "spi4";
201 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202 nvidia,tristate = <TEGRA_PIN_DISABLE>;
203 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
204 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
205 };
206 uart3_tx_pd1 {
207 nvidia,pins = "uart3_tx_pd1";
208 nvidia,function = "uartc";
209 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
210 nvidia,tristate = <TEGRA_PIN_DISABLE>;
211 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
212 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
213 };
214 uart3_rx_pd2 {
215 nvidia,pins = "uart3_rx_pd2";
216 nvidia,function = "uartc";
217 nvidia,pull = <TEGRA_PIN_PULL_UP>;
218 nvidia,tristate = <TEGRA_PIN_DISABLE>;
219 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
220 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
221 };
222 uart3_rts_pd3 {
223 nvidia,pins = "uart3_rts_pd3";
224 nvidia,function = "uartc";
225 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
226 nvidia,tristate = <TEGRA_PIN_DISABLE>;
227 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
228 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
229 };
230 uart3_cts_pd4 {
231 nvidia,pins = "uart3_cts_pd4";
232 nvidia,function = "uartc";
233 nvidia,pull = <TEGRA_PIN_PULL_UP>;
234 nvidia,tristate = <TEGRA_PIN_DISABLE>;
235 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
236 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
237 };
238 dmic1_clk_pe0 {
239 nvidia,pins = "dmic1_clk_pe0";
240 nvidia,function = "dmic1";
241 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
242 nvidia,tristate = <TEGRA_PIN_DISABLE>;
243 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
244 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
245 };
246 dmic1_dat_pe1 {
247 nvidia,pins = "dmic1_dat_pe1";
248 nvidia,function = "dmic1";
249 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
250 nvidia,tristate = <TEGRA_PIN_DISABLE>;
251 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
252 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
253 };
254 dmic2_clk_pe2 {
255 nvidia,pins = "dmic2_clk_pe2";
256 nvidia,function = "dmic2";
257 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
258 nvidia,tristate = <TEGRA_PIN_DISABLE>;
259 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
260 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
261 };
262 dmic2_dat_pe3 {
263 nvidia,pins = "dmic2_dat_pe3";
264 nvidia,function = "dmic2";
265 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
266 nvidia,tristate = <TEGRA_PIN_DISABLE>;
267 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
268 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
269 };
270 dmic3_clk_pe4 {
271 nvidia,pins = "dmic3_clk_pe4";
272 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
273 nvidia,tristate = <TEGRA_PIN_DISABLE>;
274 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
275 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
276 };
277 dmic3_dat_pe5 {
278 nvidia,pins = "dmic3_dat_pe5";
279 nvidia,function = "rsvd2";
280 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
281 nvidia,tristate = <TEGRA_PIN_ENABLE>;
282 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
283 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
284 };
285 pe6 {
286 nvidia,pins = "pe6";
287 nvidia,pull = <TEGRA_PIN_PULL_UP>;
288 nvidia,tristate = <TEGRA_PIN_DISABLE>;
289 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
290 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
291 };
292 pe7 {
293 nvidia,pins = "pe7";
294 nvidia,function = "pwm3";
295 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
296 nvidia,tristate = <TEGRA_PIN_DISABLE>;
297 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
298 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
299 };
300 gen3_i2c_scl_pf0 {
301 nvidia,pins = "gen3_i2c_scl_pf0";
302 nvidia,function = "i2c3";
303 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
304 nvidia,tristate = <TEGRA_PIN_DISABLE>;
305 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
306 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
307 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
308 };
309 gen3_i2c_sda_pf1 {
310 nvidia,pins = "gen3_i2c_sda_pf1";
311 nvidia,function = "i2c3";
312 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
313 nvidia,tristate = <TEGRA_PIN_DISABLE>;
314 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
315 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
316 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
317 };
318 uart2_tx_pg0 {
319 nvidia,pins = "uart2_tx_pg0";
320 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
321 nvidia,tristate = <TEGRA_PIN_DISABLE>;
322 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
323 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
324 };
325 uart2_rx_pg1 {
326 nvidia,pins = "uart2_rx_pg1";
327 nvidia,function = "uartb";
328 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
329 nvidia,tristate = <TEGRA_PIN_ENABLE>;
330 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
331 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
332 };
333 uart2_rts_pg2 {
334 nvidia,pins = "uart2_rts_pg2";
335 nvidia,function = "rsvd2";
336 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
337 nvidia,tristate = <TEGRA_PIN_ENABLE>;
338 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
339 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
340 };
341 uart2_cts_pg3 {
342 nvidia,pins = "uart2_cts_pg3";
343 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
344 nvidia,tristate = <TEGRA_PIN_DISABLE>;
345 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
346 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
347 };
348 wifi_en_ph0 {
349 nvidia,pins = "wifi_en_ph0";
350 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
351 nvidia,tristate = <TEGRA_PIN_DISABLE>;
352 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
353 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
354 };
355 wifi_rst_ph1 {
356 nvidia,pins = "wifi_rst_ph1";
357 nvidia,function = "rsvd0";
358 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
359 nvidia,tristate = <TEGRA_PIN_ENABLE>;
360 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
361 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
362 };
363 wifi_wake_ap_ph2 {
364 nvidia,pins = "wifi_wake_ap_ph2";
365 nvidia,pull = <TEGRA_PIN_PULL_UP>;
366 nvidia,tristate = <TEGRA_PIN_DISABLE>;
367 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
368 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
369 };
370 ap_wake_bt_ph3 {
371 nvidia,pins = "ap_wake_bt_ph3";
372 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
373 nvidia,tristate = <TEGRA_PIN_DISABLE>;
374 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
375 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
376 };
377 bt_rst_ph4 {
378 nvidia,pins = "bt_rst_ph4";
379 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
380 nvidia,tristate = <TEGRA_PIN_DISABLE>;
381 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
382 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
383 };
384 bt_wake_ap_ph5 {
385 nvidia,pins = "bt_wake_ap_ph5";
386 nvidia,pull = <TEGRA_PIN_PULL_UP>;
387 nvidia,tristate = <TEGRA_PIN_DISABLE>;
388 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
389 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
390 };
391 ph6 {
392 nvidia,pins = "ph6";
393 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
394 nvidia,tristate = <TEGRA_PIN_DISABLE>;
395 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
396 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
397 };
398 ap_wake_nfc_ph7 {
399 nvidia,pins = "ap_wake_nfc_ph7";
400 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
401 nvidia,tristate = <TEGRA_PIN_DISABLE>;
402 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
403 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
404 };
405 nfc_en_pi0 {
406 nvidia,pins = "nfc_en_pi0";
407 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
408 nvidia,tristate = <TEGRA_PIN_DISABLE>;
409 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
410 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
411 };
412 nfc_int_pi1 {
413 nvidia,pins = "nfc_int_pi1";
414 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
415 nvidia,tristate = <TEGRA_PIN_DISABLE>;
416 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
417 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
418 };
419 gps_en_pi2 {
420 nvidia,pins = "gps_en_pi2";
421 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
422 nvidia,tristate = <TEGRA_PIN_DISABLE>;
423 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
424 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
425 };
426 gps_rst_pi3 {
427 nvidia,pins = "gps_rst_pi3";
428 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
429 nvidia,tristate = <TEGRA_PIN_DISABLE>;
430 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
431 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
432 };
433 uart4_tx_pi4 {
434 nvidia,pins = "uart4_tx_pi4";
435 nvidia,function = "uartd";
436 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
437 nvidia,tristate = <TEGRA_PIN_DISABLE>;
438 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
439 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
440 };
441 uart4_rx_pi5 {
442 nvidia,pins = "uart4_rx_pi5";
443 nvidia,function = "uartd";
444 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
445 nvidia,tristate = <TEGRA_PIN_DISABLE>;
446 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
447 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
448 };
449 uart4_rts_pi6 {
450 nvidia,pins = "uart4_rts_pi6";
451 nvidia,function = "uartd";
452 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
453 nvidia,tristate = <TEGRA_PIN_DISABLE>;
454 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
455 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
456 };
457 uart4_cts_pi7 {
458 nvidia,pins = "uart4_cts_pi7";
459 nvidia,function = "uartd";
460 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
461 nvidia,tristate = <TEGRA_PIN_DISABLE>;
462 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
463 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
464 };
465 gen1_i2c_sda_pj0 {
466 nvidia,pins = "gen1_i2c_sda_pj0";
467 nvidia,function = "i2c1";
468 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
469 nvidia,tristate = <TEGRA_PIN_DISABLE>;
470 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
471 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
472 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
473 };
474 gen1_i2c_scl_pj1 {
475 nvidia,pins = "gen1_i2c_scl_pj1";
476 nvidia,function = "i2c1";
477 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
478 nvidia,tristate = <TEGRA_PIN_DISABLE>;
479 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
480 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
481 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
482 };
483 gen2_i2c_scl_pj2 {
484 nvidia,pins = "gen2_i2c_scl_pj2";
485 nvidia,function = "i2c2";
486 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
487 nvidia,tristate = <TEGRA_PIN_DISABLE>;
488 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
489 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
490 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
491 };
492 gen2_i2c_sda_pj3 {
493 nvidia,pins = "gen2_i2c_sda_pj3";
494 nvidia,function = "i2c2";
495 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
496 nvidia,tristate = <TEGRA_PIN_DISABLE>;
497 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
498 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
499 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
500 };
501 dap4_fs_pj4 {
502 nvidia,pins = "dap4_fs_pj4";
503 nvidia,function = "i2s4b";
504 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
505 nvidia,tristate = <TEGRA_PIN_DISABLE>;
506 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
507 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
508 };
509 dap4_din_pj5 {
510 nvidia,pins = "dap4_din_pj5";
511 nvidia,function = "i2s4b";
512 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
513 nvidia,tristate = <TEGRA_PIN_DISABLE>;
514 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
515 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
516 };
517 dap4_dout_pj6 {
518 nvidia,pins = "dap4_dout_pj6";
519 nvidia,function = "i2s4b";
520 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
521 nvidia,tristate = <TEGRA_PIN_DISABLE>;
522 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
523 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
524 };
525 dap4_sclk_pj7 {
526 nvidia,pins = "dap4_sclk_pj7";
527 nvidia,function = "i2s4b";
528 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
529 nvidia,tristate = <TEGRA_PIN_DISABLE>;
530 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
531 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
532 };
533 pk0 {
534 nvidia,pins = "pk0";
535 nvidia,function = "i2s5b";
536 nvidia,pull = <TEGRA_PIN_PULL_UP>;
537 nvidia,tristate = <TEGRA_PIN_DISABLE>;
538 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
539 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
540 };
541 pk1 {
542 nvidia,pins = "pk1";
543 nvidia,function = "i2s5b";
544 nvidia,pull = <TEGRA_PIN_PULL_UP>;
545 nvidia,tristate = <TEGRA_PIN_DISABLE>;
546 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
547 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
548 };
549 pk2 {
550 nvidia,pins = "pk2";
551 nvidia,function = "i2s5b";
552 nvidia,pull = <TEGRA_PIN_PULL_UP>;
553 nvidia,tristate = <TEGRA_PIN_DISABLE>;
554 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
555 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
556 };
557 pk3 {
558 nvidia,pins = "pk3";
559 nvidia,function = "i2s5b";
560 nvidia,pull = <TEGRA_PIN_PULL_UP>;
561 nvidia,tristate = <TEGRA_PIN_DISABLE>;
562 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
563 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
564 };
565 pk4 {
566 nvidia,pins = "pk4";
567 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
568 nvidia,tristate = <TEGRA_PIN_DISABLE>;
569 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
570 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
571 };
572 pk5 {
573 nvidia,pins = "pk5";
574 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
575 nvidia,tristate = <TEGRA_PIN_DISABLE>;
576 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
577 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
578 };
579 pk6 {
580 nvidia,pins = "pk6";
581 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
582 nvidia,tristate = <TEGRA_PIN_DISABLE>;
583 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
584 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
585 };
586 pk7 {
587 nvidia,pins = "pk7";
588 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
589 nvidia,tristate = <TEGRA_PIN_DISABLE>;
590 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
591 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
592 };
593 pl0 {
594 nvidia,pins = "pl0";
595 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
596 nvidia,tristate = <TEGRA_PIN_DISABLE>;
597 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
598 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
599 };
600 pl1 {
601 nvidia,pins = "pl1";
602 nvidia,function = "soc";
603 nvidia,pull = <TEGRA_PIN_PULL_UP>;
604 nvidia,tristate = <TEGRA_PIN_DISABLE>;
605 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
606 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
607 };
608 sdmmc1_clk_pm0 {
609 nvidia,pins = "sdmmc1_clk_pm0";
610 nvidia,function = "sdmmc1";
611 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
612 nvidia,tristate = <TEGRA_PIN_DISABLE>;
613 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
614 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
615 };
616 sdmmc1_cmd_pm1 {
617 nvidia,pins = "sdmmc1_cmd_pm1";
618 nvidia,function = "sdmmc1";
619 nvidia,pull = <TEGRA_PIN_PULL_UP>;
620 nvidia,tristate = <TEGRA_PIN_DISABLE>;
621 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
622 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
623 };
624 sdmmc1_dat3_pm2 {
625 nvidia,pins = "sdmmc1_dat3_pm2";
626 nvidia,function = "sdmmc1";
627 nvidia,pull = <TEGRA_PIN_PULL_UP>;
628 nvidia,tristate = <TEGRA_PIN_DISABLE>;
629 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
630 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
631 };
632 sdmmc1_dat2_pm3 {
633 nvidia,pins = "sdmmc1_dat2_pm3";
634 nvidia,function = "sdmmc1";
635 nvidia,pull = <TEGRA_PIN_PULL_UP>;
636 nvidia,tristate = <TEGRA_PIN_DISABLE>;
637 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
638 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
639 };
640 sdmmc1_dat1_pm4 {
641 nvidia,pins = "sdmmc1_dat1_pm4";
642 nvidia,function = "sdmmc1";
643 nvidia,pull = <TEGRA_PIN_PULL_UP>;
644 nvidia,tristate = <TEGRA_PIN_DISABLE>;
645 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
646 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
647 };
648 sdmmc1_dat0_pm5 {
649 nvidia,pins = "sdmmc1_dat0_pm5";
650 nvidia,function = "sdmmc1";
651 nvidia,pull = <TEGRA_PIN_PULL_UP>;
652 nvidia,tristate = <TEGRA_PIN_DISABLE>;
653 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
654 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
655 };
656 sdmmc3_clk_pp0 {
657 nvidia,pins = "sdmmc3_clk_pp0";
658 nvidia,function = "sdmmc3";
659 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
660 nvidia,tristate = <TEGRA_PIN_DISABLE>;
661 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
662 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
663 };
664 sdmmc3_cmd_pp1 {
665 nvidia,pins = "sdmmc3_cmd_pp1";
666 nvidia,function = "sdmmc3";
667 nvidia,pull = <TEGRA_PIN_PULL_UP>;
668 nvidia,tristate = <TEGRA_PIN_DISABLE>;
669 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
670 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
671 };
672 sdmmc3_dat3_pp2 {
673 nvidia,pins = "sdmmc3_dat3_pp2";
674 nvidia,function = "sdmmc3";
675 nvidia,pull = <TEGRA_PIN_PULL_UP>;
676 nvidia,tristate = <TEGRA_PIN_DISABLE>;
677 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
678 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
679 };
680 sdmmc3_dat2_pp3 {
681 nvidia,pins = "sdmmc3_dat2_pp3";
682 nvidia,function = "sdmmc3";
683 nvidia,pull = <TEGRA_PIN_PULL_UP>;
684 nvidia,tristate = <TEGRA_PIN_DISABLE>;
685 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
686 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
687 };
688 sdmmc3_dat1_pp4 {
689 nvidia,pins = "sdmmc3_dat1_pp4";
690 nvidia,function = "sdmmc3";
691 nvidia,pull = <TEGRA_PIN_PULL_UP>;
692 nvidia,tristate = <TEGRA_PIN_DISABLE>;
693 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
694 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
695 };
696 sdmmc3_dat0_pp5 {
697 nvidia,pins = "sdmmc3_dat0_pp5";
698 nvidia,function = "sdmmc3";
699 nvidia,pull = <TEGRA_PIN_PULL_UP>;
700 nvidia,tristate = <TEGRA_PIN_DISABLE>;
701 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
702 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
703 };
704 cam1_mclk_ps0 {
705 nvidia,pins = "cam1_mclk_ps0";
706 nvidia,function = "extperiph3";
707 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
708 nvidia,tristate = <TEGRA_PIN_DISABLE>;
709 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
710 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
711 };
712 cam2_mclk_ps1 {
713 nvidia,pins = "cam2_mclk_ps1";
714 nvidia,function = "extperiph3";
715 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
716 nvidia,tristate = <TEGRA_PIN_DISABLE>;
717 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
718 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
719 };
720 cam_i2c_scl_ps2 {
721 nvidia,pins = "cam_i2c_scl_ps2";
722 nvidia,function = "i2cvi";
723 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
724 nvidia,tristate = <TEGRA_PIN_DISABLE>;
725 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
726 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
727 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
728 };
729 cam_i2c_sda_ps3 {
730 nvidia,pins = "cam_i2c_sda_ps3";
731 nvidia,function = "i2cvi";
732 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
733 nvidia,tristate = <TEGRA_PIN_DISABLE>;
734 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
735 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
736 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
737 };
738 cam_rst_ps4 {
739 nvidia,pins = "cam_rst_ps4";
740 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
741 nvidia,tristate = <TEGRA_PIN_DISABLE>;
742 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
743 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
744 };
745 cam_af_en_ps5 {
746 nvidia,pins = "cam_af_en_ps5";
747 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
748 nvidia,tristate = <TEGRA_PIN_DISABLE>;
749 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
750 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
751 };
752 cam_flash_en_ps6 {
753 nvidia,pins = "cam_flash_en_ps6";
754 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
755 nvidia,tristate = <TEGRA_PIN_DISABLE>;
756 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
757 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
758 };
759 cam1_pwdn_ps7 {
760 nvidia,pins = "cam1_pwdn_ps7";
761 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
762 nvidia,tristate = <TEGRA_PIN_DISABLE>;
763 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
764 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
765 };
766 cam2_pwdn_pt0 {
767 nvidia,pins = "cam2_pwdn_pt0";
768 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
769 nvidia,tristate = <TEGRA_PIN_DISABLE>;
770 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
771 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
772 };
773 cam1_strobe_pt1 {
774 nvidia,pins = "cam1_strobe_pt1";
775 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
776 nvidia,tristate = <TEGRA_PIN_DISABLE>;
777 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
778 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
779 };
780 uart1_tx_pu0 {
781 nvidia,pins = "uart1_tx_pu0";
782 nvidia,function = "uarta";
783 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
784 nvidia,tristate = <TEGRA_PIN_DISABLE>;
785 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
786 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
787 };
788 uart1_rx_pu1 {
789 nvidia,pins = "uart1_rx_pu1";
790 nvidia,function = "uarta";
791 nvidia,pull = <TEGRA_PIN_PULL_UP>;
792 nvidia,tristate = <TEGRA_PIN_DISABLE>;
793 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
794 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
795 };
796 uart1_rts_pu2 {
797 nvidia,pins = "uart1_rts_pu2";
798 nvidia,function = "uarta";
799 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
800 nvidia,tristate = <TEGRA_PIN_DISABLE>;
801 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
802 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
803 };
804 uart1_cts_pu3 {
805 nvidia,pins = "uart1_cts_pu3";
806 nvidia,function = "uarta";
807 nvidia,pull = <TEGRA_PIN_PULL_UP>;
808 nvidia,tristate = <TEGRA_PIN_DISABLE>;
809 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
810 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
811 };
812 lcd_bl_pwm_pv0 {
813 nvidia,pins = "lcd_bl_pwm_pv0";
814 nvidia,function = "pwm0";
815 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
816 nvidia,tristate = <TEGRA_PIN_DISABLE>;
817 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
818 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
819 };
820 lcd_bl_en_pv1 {
821 nvidia,pins = "lcd_bl_en_pv1";
822 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
823 nvidia,tristate = <TEGRA_PIN_DISABLE>;
824 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
825 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
826 };
827 lcd_rst_pv2 {
828 nvidia,pins = "lcd_rst_pv2";
829 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
830 nvidia,tristate = <TEGRA_PIN_DISABLE>;
831 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
832 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
833 };
834 lcd_gpio1_pv3 {
835 nvidia,pins = "lcd_gpio1_pv3";
836 nvidia,function = "rsvd1";
837 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
838 nvidia,tristate = <TEGRA_PIN_ENABLE>;
839 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
840 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
841 };
842 lcd_gpio2_pv4 {
843 nvidia,pins = "lcd_gpio2_pv4";
844 nvidia,function = "pwm1";
845 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
846 nvidia,tristate = <TEGRA_PIN_DISABLE>;
847 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
848 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
849 };
850 ap_ready_pv5 {
851 nvidia,pins = "ap_ready_pv5";
852 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
853 nvidia,tristate = <TEGRA_PIN_DISABLE>;
854 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
855 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
856 };
857 touch_rst_pv6 {
858 nvidia,pins = "touch_rst_pv6";
859 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
860 nvidia,tristate = <TEGRA_PIN_DISABLE>;
861 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
862 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
863 };
864 touch_clk_pv7 {
865 nvidia,pins = "touch_clk_pv7";
866 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
867 nvidia,tristate = <TEGRA_PIN_DISABLE>;
868 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
869 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
870 };
871 modem_wake_ap_px0 {
872 nvidia,pins = "modem_wake_ap_px0";
873 nvidia,pull = <TEGRA_PIN_PULL_UP>;
874 nvidia,tristate = <TEGRA_PIN_DISABLE>;
875 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
876 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
877 };
878 touch_int_px1 {
879 nvidia,pins = "touch_int_px1";
880 nvidia,pull = <TEGRA_PIN_PULL_UP>;
881 nvidia,tristate = <TEGRA_PIN_DISABLE>;
882 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
883 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
884 };
885 motion_int_px2 {
886 nvidia,pins = "motion_int_px2";
887 nvidia,pull = <TEGRA_PIN_PULL_UP>;
888 nvidia,tristate = <TEGRA_PIN_DISABLE>;
889 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
890 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
891 };
892 als_prox_int_px3 {
893 nvidia,pins = "als_prox_int_px3";
894 nvidia,pull = <TEGRA_PIN_PULL_UP>;
895 nvidia,tristate = <TEGRA_PIN_DISABLE>;
896 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
897 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
898 };
899 temp_alert_px4 {
900 nvidia,pins = "temp_alert_px4";
901 nvidia,pull = <TEGRA_PIN_PULL_UP>;
902 nvidia,tristate = <TEGRA_PIN_DISABLE>;
903 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
904 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
905 };
906 button_power_on_px5 {
907 nvidia,pins = "button_power_on_px5";
908 nvidia,pull = <TEGRA_PIN_PULL_UP>;
909 nvidia,tristate = <TEGRA_PIN_DISABLE>;
910 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
911 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
912 };
913 button_vol_up_px6 {
914 nvidia,pins = "button_vol_up_px6";
915 nvidia,pull = <TEGRA_PIN_PULL_UP>;
916 nvidia,tristate = <TEGRA_PIN_DISABLE>;
917 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
918 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
919 };
920 button_vol_down_px7 {
921 nvidia,pins = "button_vol_down_px7";
922 nvidia,pull = <TEGRA_PIN_PULL_UP>;
923 nvidia,tristate = <TEGRA_PIN_DISABLE>;
924 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
925 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
926 };
927 button_slide_sw_py0 {
928 nvidia,pins = "button_slide_sw_py0";
929 nvidia,function = "rsvd0";
930 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
931 nvidia,tristate = <TEGRA_PIN_ENABLE>;
932 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
933 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
934 };
935 button_home_py1 {
936 nvidia,pins = "button_home_py1";
937 nvidia,pull = <TEGRA_PIN_PULL_UP>;
938 nvidia,tristate = <TEGRA_PIN_DISABLE>;
939 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
940 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
941 };
942 lcd_te_py2 {
943 nvidia,pins = "lcd_te_py2";
944 nvidia,function = "displaya";
945 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
946 nvidia,tristate = <TEGRA_PIN_DISABLE>;
947 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
948 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
949 };
950 pwr_i2c_scl_py3 {
951 nvidia,pins = "pwr_i2c_scl_py3";
952 nvidia,function = "i2cpmu";
953 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
954 nvidia,tristate = <TEGRA_PIN_DISABLE>;
955 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
956 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
957 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
958 };
959 pwr_i2c_sda_py4 {
960 nvidia,pins = "pwr_i2c_sda_py4";
961 nvidia,function = "i2cpmu";
962 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
963 nvidia,tristate = <TEGRA_PIN_DISABLE>;
964 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
965 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
966 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
967 };
968 clk_32k_out_py5 {
969 nvidia,pins = "clk_32k_out_py5";
970 nvidia,function = "soc";
971 nvidia,pull = <TEGRA_PIN_PULL_UP>;
972 nvidia,tristate = <TEGRA_PIN_DISABLE>;
973 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
974 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
975 };
976 pz0 {
977 nvidia,pins = "pz0";
978 nvidia,pull = <TEGRA_PIN_PULL_UP>;
979 nvidia,tristate = <TEGRA_PIN_DISABLE>;
980 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
981 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
982 };
983 pz1 {
984 nvidia,pins = "pz1";
985 nvidia,function = "sdmmc1";
986 nvidia,pull = <TEGRA_PIN_PULL_UP>;
987 nvidia,tristate = <TEGRA_PIN_DISABLE>;
988 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
989 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
990 };
991 pz2 {
992 nvidia,pins = "pz2";
993 nvidia,function = "rsvd2";
994 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
995 nvidia,tristate = <TEGRA_PIN_ENABLE>;
996 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
997 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
998 };
999 pz3 {
1000 nvidia,pins = "pz3";
1001 nvidia,function = "rsvd1";
1002 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1003 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1004 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1005 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1006 };
1007 pz4 {
1008 nvidia,pins = "pz4";
1009 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1010 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1011 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1012 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1013 };
1014 pz5 {
1015 nvidia,pins = "pz5";
1016 nvidia,function = "soc";
1017 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1018 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1019 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1020 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1021 };
1022 dap2_fs_paa0 {
1023 nvidia,pins = "dap2_fs_paa0";
1024 nvidia,function = "i2s2";
1025 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1026 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1027 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1028 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1029 };
1030 dap2_sclk_paa1 {
1031 nvidia,pins = "dap2_sclk_paa1";
1032 nvidia,function = "i2s2";
1033 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1034 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1035 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1036 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1037 };
1038 dap2_din_paa2 {
1039 nvidia,pins = "dap2_din_paa2";
1040 nvidia,function = "i2s2";
1041 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1042 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1043 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1044 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1045 };
1046 dap2_dout_paa3 {
1047 nvidia,pins = "dap2_dout_paa3";
1048 nvidia,function = "i2s2";
1049 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1050 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1051 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1052 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1053 };
1054 aud_mclk_pbb0 {
1055 nvidia,pins = "aud_mclk_pbb0";
1056 nvidia,function = "aud";
1057 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1058 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1059 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1060 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1061 };
1062 dvfs_pwm_pbb1 {
1063 nvidia,pins = "dvfs_pwm_pbb1";
1064 nvidia,function = "cldvfs";
1065 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1066 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1067 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1068 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1069 };
1070 dvfs_clk_pbb2 {
1071 nvidia,pins = "dvfs_clk_pbb2";
1072 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1073 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1074 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1075 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1076 };
1077 gpio_x1_aud_pbb3 {
1078 nvidia,pins = "gpio_x1_aud_pbb3";
1079 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1080 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1081 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1082 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1083 };
1084 gpio_x3_aud_pbb4 {
1085 nvidia,pins = "gpio_x3_aud_pbb4";
1086 nvidia,function = "rsvd0";
1087 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1088 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1089 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1090 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1091 };
1092 hdmi_cec_pcc0 {
1093 nvidia,pins = "hdmi_cec_pcc0";
1094 nvidia,function = "cec";
1095 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1096 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1097 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1098 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1099 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
1100 };
1101 hdmi_int_dp_hpd_pcc1 {
1102 nvidia,pins = "hdmi_int_dp_hpd_pcc1";
1103 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1104 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1105 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1106 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1107 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
1108 };
1109 spdif_out_pcc2 {
1110 nvidia,pins = "spdif_out_pcc2";
1111 nvidia,function = "rsvd1";
1112 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1113 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1114 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1115 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1116 };
1117 spdif_in_pcc3 {
1118 nvidia,pins = "spdif_in_pcc3";
1119 nvidia,function = "rsvd1";
1120 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1121 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1122 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1123 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1124 };
1125 usb_vbus_en0_pcc4 {
1126 nvidia,pins = "usb_vbus_en0_pcc4";
1127 nvidia,function = "usb";
1128 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1129 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1130 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1131 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1132 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
1133 };
1134 usb_vbus_en1_pcc5 {
1135 nvidia,pins = "usb_vbus_en1_pcc5";
1136 nvidia,function = "rsvd1";
1137 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1138 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1139 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1140 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1141 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
1142 };
1143 dp_hpd0_pcc6 {
1144 nvidia,pins = "dp_hpd0_pcc6";
1145 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1146 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1147 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1148 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1149 };
1150 pcc7 {
1151 nvidia,pins = "pcc7";
1152 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1153 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1154 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1155 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1156 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
1157 };
1158 spi2_cs1_pdd0 {
1159 nvidia,pins = "spi2_cs1_pdd0";
1160 nvidia,function = "rsvd1";
1161 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1162 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1163 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1164 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1165 };
1166 qspi_sck_pee0 {
1167 nvidia,pins = "qspi_sck_pee0";
1168 nvidia,function = "rsvd1";
1169 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1170 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1171 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1172 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1173 };
1174 qspi_cs_n_pee1 {
1175 nvidia,pins = "qspi_cs_n_pee1";
1176 nvidia,function = "rsvd1";
1177 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1178 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1179 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1180 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1181 };
1182 qspi_io0_pee2 {
1183 nvidia,pins = "qspi_io0_pee2";
1184 nvidia,function = "rsvd1";
1185 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1186 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1187 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1188 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1189 };
1190 qspi_io1_pee3 {
1191 nvidia,pins = "qspi_io1_pee3";
1192 nvidia,function = "rsvd1";
1193 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1194 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1195 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1196 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1197 };
1198 qspi_io2_pee4 {
1199 nvidia,pins = "qspi_io2_pee4";
1200 nvidia,function = "rsvd1";
1201 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1202 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1203 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1204 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1205 };
1206 qspi_io3_pee5 {
1207 nvidia,pins = "qspi_io3_pee5";
1208 nvidia,function = "rsvd1";
1209 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1210 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1211 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1212 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1213 };
1214 core_pwr_req {
1215 nvidia,pins = "core_pwr_req";
1216 nvidia,function = "core";
1217 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1218 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1219 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1220 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1221 };
1222 cpu_pwr_req {
1223 nvidia,pins = "cpu_pwr_req";
1224 nvidia,function = "cpu";
1225 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1226 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1227 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1228 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1229 };
1230 pwr_int_n {
1231 nvidia,pins = "pwr_int_n";
1232 nvidia,function = "pmi";
1233 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1234 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1235 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1236 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1237 };
1238 clk_32k_in {
1239 nvidia,pins = "clk_32k_in";
1240 nvidia,function = "clk";
1241 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1242 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1243 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1244 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1245 };
1246 jtag_rtck {
1247 nvidia,pins = "jtag_rtck";
1248 nvidia,function = "jtag";
1249 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1250 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1251 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1252 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1253 };
1254 clk_req {
1255 nvidia,pins = "clk_req";
1256 nvidia,function = "sys";
1257 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1258 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1259 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1260 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1261 };
1262 shutdown {
1263 nvidia,pins = "shutdown";
1264 nvidia,function = "shutdown";
1265 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1266 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1267 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1268 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1269 };
1270 };
1271 };
1272};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
new file mode 100644
index 000000000000..be3eccbe8013
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
@@ -0,0 +1,1270 @@
1/ {
2 model = "NVIDIA Tegra210 P2597 I/O board";
3 compatible = "nvidia,p2597", "nvidia,tegra210";
4
5 pinmux: pinmux@0,700008d4 {
6 pinctrl-names = "boot";
7 pinctrl-0 = <&state_boot>;
8
9 state_boot: pinmux {
10 pex_l0_rst_n_pa0 {
11 nvidia,pins = "pex_l0_rst_n_pa0";
12 nvidia,function = "pe0";
13 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
14 nvidia,tristate = <TEGRA_PIN_DISABLE>;
15 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
16 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
17 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
18 };
19 pex_l0_clkreq_n_pa1 {
20 nvidia,pins = "pex_l0_clkreq_n_pa1";
21 nvidia,function = "pe0";
22 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
23 nvidia,tristate = <TEGRA_PIN_DISABLE>;
24 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
25 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
26 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
27 };
28 pex_wake_n_pa2 {
29 nvidia,pins = "pex_wake_n_pa2";
30 nvidia,function = "pe";
31 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
32 nvidia,tristate = <TEGRA_PIN_DISABLE>;
33 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
34 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
35 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
36 };
37 pex_l1_rst_n_pa3 {
38 nvidia,pins = "pex_l1_rst_n_pa3";
39 nvidia,function = "pe1";
40 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
41 nvidia,tristate = <TEGRA_PIN_DISABLE>;
42 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
43 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
44 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
45 };
46 pex_l1_clkreq_n_pa4 {
47 nvidia,pins = "pex_l1_clkreq_n_pa4";
48 nvidia,function = "pe1";
49 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
50 nvidia,tristate = <TEGRA_PIN_DISABLE>;
51 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
52 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
53 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
54 };
55 sata_led_active_pa5 {
56 nvidia,pins = "sata_led_active_pa5";
57 nvidia,pull = <TEGRA_PIN_PULL_UP>;
58 nvidia,tristate = <TEGRA_PIN_DISABLE>;
59 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
60 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
61 };
62 pa6 {
63 nvidia,pins = "pa6";
64 nvidia,function = "sata";
65 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
66 nvidia,tristate = <TEGRA_PIN_DISABLE>;
67 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
69 };
70 dap1_fs_pb0 {
71 nvidia,pins = "dap1_fs_pb0";
72 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
73 nvidia,tristate = <TEGRA_PIN_DISABLE>;
74 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
75 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
76 };
77 dap1_din_pb1 {
78 nvidia,pins = "dap1_din_pb1";
79 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
80 nvidia,tristate = <TEGRA_PIN_DISABLE>;
81 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
82 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
83 };
84 dap1_dout_pb2 {
85 nvidia,pins = "dap1_dout_pb2";
86 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
87 nvidia,tristate = <TEGRA_PIN_DISABLE>;
88 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
89 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
90 };
91 dap1_sclk_pb3 {
92 nvidia,pins = "dap1_sclk_pb3";
93 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
94 nvidia,tristate = <TEGRA_PIN_DISABLE>;
95 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
96 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
97 };
98 spi2_mosi_pb4 {
99 nvidia,pins = "spi2_mosi_pb4";
100 nvidia,function = "spi2";
101 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
102 nvidia,tristate = <TEGRA_PIN_DISABLE>;
103 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
104 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
105 };
106 spi2_miso_pb5 {
107 nvidia,pins = "spi2_miso_pb5";
108 nvidia,function = "spi2";
109 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
110 nvidia,tristate = <TEGRA_PIN_DISABLE>;
111 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
112 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
113 };
114 spi2_sck_pb6 {
115 nvidia,pins = "spi2_sck_pb6";
116 nvidia,function = "spi2";
117 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
118 nvidia,tristate = <TEGRA_PIN_DISABLE>;
119 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
120 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
121 };
122 spi2_cs0_pb7 {
123 nvidia,pins = "spi2_cs0_pb7";
124 nvidia,function = "spi2";
125 nvidia,pull = <TEGRA_PIN_PULL_UP>;
126 nvidia,tristate = <TEGRA_PIN_DISABLE>;
127 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
128 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
129 };
130 spi1_mosi_pc0 {
131 nvidia,pins = "spi1_mosi_pc0";
132 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
133 nvidia,tristate = <TEGRA_PIN_DISABLE>;
134 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
135 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
136 };
137 spi1_miso_pc1 {
138 nvidia,pins = "spi1_miso_pc1";
139 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
140 nvidia,tristate = <TEGRA_PIN_DISABLE>;
141 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
142 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
143 };
144 spi1_sck_pc2 {
145 nvidia,pins = "spi1_sck_pc2";
146 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
147 nvidia,tristate = <TEGRA_PIN_DISABLE>;
148 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
149 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
150 };
151 spi1_cs0_pc3 {
152 nvidia,pins = "spi1_cs0_pc3";
153 nvidia,pull = <TEGRA_PIN_PULL_UP>;
154 nvidia,tristate = <TEGRA_PIN_DISABLE>;
155 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
156 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
157 };
158 spi1_cs1_pc4 {
159 nvidia,pins = "spi1_cs1_pc4";
160 nvidia,pull = <TEGRA_PIN_PULL_UP>;
161 nvidia,tristate = <TEGRA_PIN_DISABLE>;
162 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
163 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
164 };
165 spi4_sck_pc5 {
166 nvidia,pins = "spi4_sck_pc5";
167 nvidia,function = "spi4";
168 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
169 nvidia,tristate = <TEGRA_PIN_DISABLE>;
170 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
171 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
172 };
173 spi4_cs0_pc6 {
174 nvidia,pins = "spi4_cs0_pc6";
175 nvidia,function = "spi4";
176 nvidia,pull = <TEGRA_PIN_PULL_UP>;
177 nvidia,tristate = <TEGRA_PIN_DISABLE>;
178 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
179 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
180 };
181 spi4_mosi_pc7 {
182 nvidia,pins = "spi4_mosi_pc7";
183 nvidia,function = "spi4";
184 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
185 nvidia,tristate = <TEGRA_PIN_DISABLE>;
186 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
187 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
188 };
189 spi4_miso_pd0 {
190 nvidia,pins = "spi4_miso_pd0";
191 nvidia,function = "spi4";
192 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
193 nvidia,tristate = <TEGRA_PIN_DISABLE>;
194 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
195 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
196 };
197 uart3_tx_pd1 {
198 nvidia,pins = "uart3_tx_pd1";
199 nvidia,function = "uartc";
200 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
201 nvidia,tristate = <TEGRA_PIN_DISABLE>;
202 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
203 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
204 };
205 uart3_rx_pd2 {
206 nvidia,pins = "uart3_rx_pd2";
207 nvidia,function = "uartc";
208 nvidia,pull = <TEGRA_PIN_PULL_UP>;
209 nvidia,tristate = <TEGRA_PIN_DISABLE>;
210 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
211 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
212 };
213 uart3_rts_pd3 {
214 nvidia,pins = "uart3_rts_pd3";
215 nvidia,function = "uartc";
216 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
217 nvidia,tristate = <TEGRA_PIN_DISABLE>;
218 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
219 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
220 };
221 uart3_cts_pd4 {
222 nvidia,pins = "uart3_cts_pd4";
223 nvidia,function = "uartc";
224 nvidia,pull = <TEGRA_PIN_PULL_UP>;
225 nvidia,tristate = <TEGRA_PIN_DISABLE>;
226 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
227 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
228 };
229 dmic1_clk_pe0 {
230 nvidia,pins = "dmic1_clk_pe0";
231 nvidia,function = "i2s3";
232 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
233 nvidia,tristate = <TEGRA_PIN_DISABLE>;
234 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
235 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
236 };
237 dmic1_dat_pe1 {
238 nvidia,pins = "dmic1_dat_pe1";
239 nvidia,function = "i2s3";
240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 nvidia,tristate = <TEGRA_PIN_DISABLE>;
242 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
243 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
244 };
245 dmic2_clk_pe2 {
246 nvidia,pins = "dmic2_clk_pe2";
247 nvidia,function = "i2s3";
248 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
249 nvidia,tristate = <TEGRA_PIN_DISABLE>;
250 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
251 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
252 };
253 dmic2_dat_pe3 {
254 nvidia,pins = "dmic2_dat_pe3";
255 nvidia,function = "i2s3";
256 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
257 nvidia,tristate = <TEGRA_PIN_DISABLE>;
258 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
259 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
260 };
261 dmic3_clk_pe4 {
262 nvidia,pins = "dmic3_clk_pe4";
263 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
264 nvidia,tristate = <TEGRA_PIN_DISABLE>;
265 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
266 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
267 };
268 dmic3_dat_pe5 {
269 nvidia,pins = "dmic3_dat_pe5";
270 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
271 nvidia,tristate = <TEGRA_PIN_DISABLE>;
272 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
273 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
274 };
275 pe6 {
276 nvidia,pins = "pe6";
277 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
278 nvidia,tristate = <TEGRA_PIN_DISABLE>;
279 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
280 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
281 };
282 pe7 {
283 nvidia,pins = "pe7";
284 nvidia,function = "pwm3";
285 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
286 nvidia,tristate = <TEGRA_PIN_DISABLE>;
287 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
288 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
289 };
290 gen3_i2c_scl_pf0 {
291 nvidia,pins = "gen3_i2c_scl_pf0";
292 nvidia,function = "i2c3";
293 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
294 nvidia,tristate = <TEGRA_PIN_DISABLE>;
295 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
296 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
297 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
298 };
299 gen3_i2c_sda_pf1 {
300 nvidia,pins = "gen3_i2c_sda_pf1";
301 nvidia,function = "i2c3";
302 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
303 nvidia,tristate = <TEGRA_PIN_DISABLE>;
304 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
305 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
306 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
307 };
308 uart2_tx_pg0 {
309 nvidia,pins = "uart2_tx_pg0";
310 nvidia,function = "uartb";
311 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
312 nvidia,tristate = <TEGRA_PIN_DISABLE>;
313 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
314 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
315 };
316 uart2_rx_pg1 {
317 nvidia,pins = "uart2_rx_pg1";
318 nvidia,function = "uartb";
319 nvidia,pull = <TEGRA_PIN_PULL_UP>;
320 nvidia,tristate = <TEGRA_PIN_DISABLE>;
321 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
322 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
323 };
324 uart2_rts_pg2 {
325 nvidia,pins = "uart2_rts_pg2";
326 nvidia,function = "uartb";
327 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
328 nvidia,tristate = <TEGRA_PIN_DISABLE>;
329 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
330 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
331 };
332 uart2_cts_pg3 {
333 nvidia,pins = "uart2_cts_pg3";
334 nvidia,function = "uartb";
335 nvidia,pull = <TEGRA_PIN_PULL_UP>;
336 nvidia,tristate = <TEGRA_PIN_DISABLE>;
337 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
338 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
339 };
340 wifi_en_ph0 {
341 nvidia,pins = "wifi_en_ph0";
342 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
343 nvidia,tristate = <TEGRA_PIN_DISABLE>;
344 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
345 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
346 };
347 wifi_rst_ph1 {
348 nvidia,pins = "wifi_rst_ph1";
349 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
350 nvidia,tristate = <TEGRA_PIN_DISABLE>;
351 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
352 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
353 };
354 wifi_wake_ap_ph2 {
355 nvidia,pins = "wifi_wake_ap_ph2";
356 nvidia,pull = <TEGRA_PIN_PULL_UP>;
357 nvidia,tristate = <TEGRA_PIN_DISABLE>;
358 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
359 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
360 };
361 ap_wake_bt_ph3 {
362 nvidia,pins = "ap_wake_bt_ph3";
363 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
364 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
366 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
367 };
368 bt_rst_ph4 {
369 nvidia,pins = "bt_rst_ph4";
370 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
371 nvidia,tristate = <TEGRA_PIN_DISABLE>;
372 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
373 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
374 };
375 bt_wake_ap_ph5 {
376 nvidia,pins = "bt_wake_ap_ph5";
377 nvidia,pull = <TEGRA_PIN_PULL_UP>;
378 nvidia,tristate = <TEGRA_PIN_DISABLE>;
379 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
380 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
381 };
382 ph6 {
383 nvidia,pins = "ph6";
384 nvidia,pull = <TEGRA_PIN_PULL_UP>;
385 nvidia,tristate = <TEGRA_PIN_DISABLE>;
386 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
387 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
388 };
389 ap_wake_nfc_ph7 {
390 nvidia,pins = "ap_wake_nfc_ph7";
391 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
392 nvidia,tristate = <TEGRA_PIN_DISABLE>;
393 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
394 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
395 };
396 nfc_en_pi0 {
397 nvidia,pins = "nfc_en_pi0";
398 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
399 nvidia,tristate = <TEGRA_PIN_DISABLE>;
400 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
401 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
402 };
403 nfc_int_pi1 {
404 nvidia,pins = "nfc_int_pi1";
405 nvidia,pull = <TEGRA_PIN_PULL_UP>;
406 nvidia,tristate = <TEGRA_PIN_DISABLE>;
407 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
408 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
409 };
410 gps_en_pi2 {
411 nvidia,pins = "gps_en_pi2";
412 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
413 nvidia,tristate = <TEGRA_PIN_DISABLE>;
414 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
415 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
416 };
417 gps_rst_pi3 {
418 nvidia,pins = "gps_rst_pi3";
419 nvidia,function = "rsvd0";
420 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
421 nvidia,tristate = <TEGRA_PIN_ENABLE>;
422 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
423 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
424 };
425 uart4_tx_pi4 {
426 nvidia,pins = "uart4_tx_pi4";
427 nvidia,function = "uartd";
428 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
429 nvidia,tristate = <TEGRA_PIN_DISABLE>;
430 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
431 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
432 };
433 uart4_rx_pi5 {
434 nvidia,pins = "uart4_rx_pi5";
435 nvidia,function = "uartd";
436 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
437 nvidia,tristate = <TEGRA_PIN_DISABLE>;
438 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
439 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
440 };
441 uart4_rts_pi6 {
442 nvidia,pins = "uart4_rts_pi6";
443 nvidia,function = "uartd";
444 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
445 nvidia,tristate = <TEGRA_PIN_DISABLE>;
446 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
447 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
448 };
449 uart4_cts_pi7 {
450 nvidia,pins = "uart4_cts_pi7";
451 nvidia,function = "uartd";
452 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
453 nvidia,tristate = <TEGRA_PIN_DISABLE>;
454 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
455 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
456 };
457 gen1_i2c_sda_pj0 {
458 nvidia,pins = "gen1_i2c_sda_pj0";
459 nvidia,function = "i2c1";
460 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
461 nvidia,tristate = <TEGRA_PIN_DISABLE>;
462 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
463 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
464 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
465 };
466 gen1_i2c_scl_pj1 {
467 nvidia,pins = "gen1_i2c_scl_pj1";
468 nvidia,function = "i2c1";
469 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
470 nvidia,tristate = <TEGRA_PIN_DISABLE>;
471 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
472 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
473 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
474 };
475 gen2_i2c_scl_pj2 {
476 nvidia,pins = "gen2_i2c_scl_pj2";
477 nvidia,function = "i2c2";
478 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
479 nvidia,tristate = <TEGRA_PIN_DISABLE>;
480 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
481 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
482 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
483 };
484 gen2_i2c_sda_pj3 {
485 nvidia,pins = "gen2_i2c_sda_pj3";
486 nvidia,function = "i2c2";
487 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
488 nvidia,tristate = <TEGRA_PIN_DISABLE>;
489 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
490 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
491 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
492 };
493 dap4_fs_pj4 {
494 nvidia,pins = "dap4_fs_pj4";
495 nvidia,function = "i2s4b";
496 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
497 nvidia,tristate = <TEGRA_PIN_DISABLE>;
498 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
499 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
500 };
501 dap4_din_pj5 {
502 nvidia,pins = "dap4_din_pj5";
503 nvidia,function = "i2s4b";
504 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
505 nvidia,tristate = <TEGRA_PIN_DISABLE>;
506 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
507 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
508 };
509 dap4_dout_pj6 {
510 nvidia,pins = "dap4_dout_pj6";
511 nvidia,function = "i2s4b";
512 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
513 nvidia,tristate = <TEGRA_PIN_DISABLE>;
514 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
515 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
516 };
517 dap4_sclk_pj7 {
518 nvidia,pins = "dap4_sclk_pj7";
519 nvidia,function = "i2s4b";
520 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
521 nvidia,tristate = <TEGRA_PIN_DISABLE>;
522 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
523 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
524 };
525 pk0 {
526 nvidia,pins = "pk0";
527 nvidia,function = "i2s5b";
528 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
529 nvidia,tristate = <TEGRA_PIN_DISABLE>;
530 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
531 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
532 };
533 pk1 {
534 nvidia,pins = "pk1";
535 nvidia,function = "i2s5b";
536 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
537 nvidia,tristate = <TEGRA_PIN_DISABLE>;
538 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
539 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
540 };
541 pk2 {
542 nvidia,pins = "pk2";
543 nvidia,function = "i2s5b";
544 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
545 nvidia,tristate = <TEGRA_PIN_DISABLE>;
546 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
547 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
548 };
549 pk3 {
550 nvidia,pins = "pk3";
551 nvidia,function = "i2s5b";
552 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
553 nvidia,tristate = <TEGRA_PIN_DISABLE>;
554 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
555 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
556 };
557 pk4 {
558 nvidia,pins = "pk4";
559 nvidia,pull = <TEGRA_PIN_PULL_UP>;
560 nvidia,tristate = <TEGRA_PIN_DISABLE>;
561 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
562 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
563 };
564 pk5 {
565 nvidia,pins = "pk5";
566 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
567 nvidia,tristate = <TEGRA_PIN_DISABLE>;
568 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
569 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
570 };
571 pk6 {
572 nvidia,pins = "pk6";
573 nvidia,pull = <TEGRA_PIN_PULL_UP>;
574 nvidia,tristate = <TEGRA_PIN_DISABLE>;
575 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
576 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
577 };
578 pk7 {
579 nvidia,pins = "pk7";
580 nvidia,pull = <TEGRA_PIN_PULL_UP>;
581 nvidia,tristate = <TEGRA_PIN_DISABLE>;
582 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
583 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
584 };
585 pl0 {
586 nvidia,pins = "pl0";
587 nvidia,function = "rsvd0";
588 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
589 nvidia,tristate = <TEGRA_PIN_ENABLE>;
590 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
591 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
592 };
593 pl1 {
594 nvidia,pins = "pl1";
595 nvidia,pull = <TEGRA_PIN_PULL_UP>;
596 nvidia,tristate = <TEGRA_PIN_DISABLE>;
597 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
598 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
599 };
600 sdmmc1_clk_pm0 {
601 nvidia,pins = "sdmmc1_clk_pm0";
602 nvidia,function = "sdmmc1";
603 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
604 nvidia,tristate = <TEGRA_PIN_DISABLE>;
605 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
606 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
607 };
608 sdmmc1_cmd_pm1 {
609 nvidia,pins = "sdmmc1_cmd_pm1";
610 nvidia,function = "sdmmc1";
611 nvidia,pull = <TEGRA_PIN_PULL_UP>;
612 nvidia,tristate = <TEGRA_PIN_DISABLE>;
613 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
614 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
615 };
616 sdmmc1_dat3_pm2 {
617 nvidia,pins = "sdmmc1_dat3_pm2";
618 nvidia,function = "sdmmc1";
619 nvidia,pull = <TEGRA_PIN_PULL_UP>;
620 nvidia,tristate = <TEGRA_PIN_DISABLE>;
621 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
622 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
623 };
624 sdmmc1_dat2_pm3 {
625 nvidia,pins = "sdmmc1_dat2_pm3";
626 nvidia,function = "sdmmc1";
627 nvidia,pull = <TEGRA_PIN_PULL_UP>;
628 nvidia,tristate = <TEGRA_PIN_DISABLE>;
629 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
630 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
631 };
632 sdmmc1_dat1_pm4 {
633 nvidia,pins = "sdmmc1_dat1_pm4";
634 nvidia,function = "sdmmc1";
635 nvidia,pull = <TEGRA_PIN_PULL_UP>;
636 nvidia,tristate = <TEGRA_PIN_DISABLE>;
637 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
638 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
639 };
640 sdmmc1_dat0_pm5 {
641 nvidia,pins = "sdmmc1_dat0_pm5";
642 nvidia,function = "sdmmc1";
643 nvidia,pull = <TEGRA_PIN_PULL_UP>;
644 nvidia,tristate = <TEGRA_PIN_DISABLE>;
645 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
646 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
647 };
648 sdmmc3_clk_pp0 {
649 nvidia,pins = "sdmmc3_clk_pp0";
650 nvidia,function = "sdmmc3";
651 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
652 nvidia,tristate = <TEGRA_PIN_DISABLE>;
653 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
654 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
655 };
656 sdmmc3_cmd_pp1 {
657 nvidia,pins = "sdmmc3_cmd_pp1";
658 nvidia,function = "sdmmc3";
659 nvidia,pull = <TEGRA_PIN_PULL_UP>;
660 nvidia,tristate = <TEGRA_PIN_DISABLE>;
661 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
662 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
663 };
664 sdmmc3_dat3_pp2 {
665 nvidia,pins = "sdmmc3_dat3_pp2";
666 nvidia,function = "sdmmc3";
667 nvidia,pull = <TEGRA_PIN_PULL_UP>;
668 nvidia,tristate = <TEGRA_PIN_DISABLE>;
669 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
670 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
671 };
672 sdmmc3_dat2_pp3 {
673 nvidia,pins = "sdmmc3_dat2_pp3";
674 nvidia,function = "sdmmc3";
675 nvidia,pull = <TEGRA_PIN_PULL_UP>;
676 nvidia,tristate = <TEGRA_PIN_DISABLE>;
677 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
678 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
679 };
680 sdmmc3_dat1_pp4 {
681 nvidia,pins = "sdmmc3_dat1_pp4";
682 nvidia,function = "sdmmc3";
683 nvidia,pull = <TEGRA_PIN_PULL_UP>;
684 nvidia,tristate = <TEGRA_PIN_DISABLE>;
685 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
686 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
687 };
688 sdmmc3_dat0_pp5 {
689 nvidia,pins = "sdmmc3_dat0_pp5";
690 nvidia,function = "sdmmc3";
691 nvidia,pull = <TEGRA_PIN_PULL_UP>;
692 nvidia,tristate = <TEGRA_PIN_DISABLE>;
693 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
694 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
695 };
696 cam1_mclk_ps0 {
697 nvidia,pins = "cam1_mclk_ps0";
698 nvidia,function = "extperiph3";
699 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
700 nvidia,tristate = <TEGRA_PIN_DISABLE>;
701 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
702 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
703 };
704 cam2_mclk_ps1 {
705 nvidia,pins = "cam2_mclk_ps1";
706 nvidia,function = "extperiph3";
707 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
708 nvidia,tristate = <TEGRA_PIN_DISABLE>;
709 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
710 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
711 };
712 cam_i2c_scl_ps2 {
713 nvidia,pins = "cam_i2c_scl_ps2";
714 nvidia,function = "i2cvi";
715 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
716 nvidia,tristate = <TEGRA_PIN_DISABLE>;
717 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
718 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
719 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
720 };
721 cam_i2c_sda_ps3 {
722 nvidia,pins = "cam_i2c_sda_ps3";
723 nvidia,function = "i2cvi";
724 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
725 nvidia,tristate = <TEGRA_PIN_DISABLE>;
726 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
727 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
728 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
729 };
730 cam_rst_ps4 {
731 nvidia,pins = "cam_rst_ps4";
732 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
733 nvidia,tristate = <TEGRA_PIN_DISABLE>;
734 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
735 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
736 };
737 cam_af_en_ps5 {
738 nvidia,pins = "cam_af_en_ps5";
739 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
740 nvidia,tristate = <TEGRA_PIN_DISABLE>;
741 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
742 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
743 };
744 cam_flash_en_ps6 {
745 nvidia,pins = "cam_flash_en_ps6";
746 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
747 nvidia,tristate = <TEGRA_PIN_DISABLE>;
748 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
749 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
750 };
751 cam1_pwdn_ps7 {
752 nvidia,pins = "cam1_pwdn_ps7";
753 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
754 nvidia,tristate = <TEGRA_PIN_DISABLE>;
755 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
756 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
757 };
758 cam2_pwdn_pt0 {
759 nvidia,pins = "cam2_pwdn_pt0";
760 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
761 nvidia,tristate = <TEGRA_PIN_DISABLE>;
762 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
763 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
764 };
765 cam1_strobe_pt1 {
766 nvidia,pins = "cam1_strobe_pt1";
767 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
768 nvidia,tristate = <TEGRA_PIN_DISABLE>;
769 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
770 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
771 };
772 uart1_tx_pu0 {
773 nvidia,pins = "uart1_tx_pu0";
774 nvidia,function = "uarta";
775 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
776 nvidia,tristate = <TEGRA_PIN_DISABLE>;
777 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
778 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
779 };
780 uart1_rx_pu1 {
781 nvidia,pins = "uart1_rx_pu1";
782 nvidia,function = "uarta";
783 nvidia,pull = <TEGRA_PIN_PULL_UP>;
784 nvidia,tristate = <TEGRA_PIN_DISABLE>;
785 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
786 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
787 };
788 uart1_rts_pu2 {
789 nvidia,pins = "uart1_rts_pu2";
790 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
791 nvidia,tristate = <TEGRA_PIN_DISABLE>;
792 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
793 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
794 };
795 uart1_cts_pu3 {
796 nvidia,pins = "uart1_cts_pu3";
797 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
798 nvidia,tristate = <TEGRA_PIN_DISABLE>;
799 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
800 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
801 };
802 lcd_bl_pwm_pv0 {
803 nvidia,pins = "lcd_bl_pwm_pv0";
804 nvidia,function = "pwm0";
805 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
806 nvidia,tristate = <TEGRA_PIN_DISABLE>;
807 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
808 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
809 };
810 lcd_bl_en_pv1 {
811 nvidia,pins = "lcd_bl_en_pv1";
812 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
813 nvidia,tristate = <TEGRA_PIN_DISABLE>;
814 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
815 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
816 };
817 lcd_rst_pv2 {
818 nvidia,pins = "lcd_rst_pv2";
819 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
820 nvidia,tristate = <TEGRA_PIN_DISABLE>;
821 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
822 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
823 };
824 lcd_gpio1_pv3 {
825 nvidia,pins = "lcd_gpio1_pv3";
826 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
827 nvidia,tristate = <TEGRA_PIN_DISABLE>;
828 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
829 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
830 };
831 lcd_gpio2_pv4 {
832 nvidia,pins = "lcd_gpio2_pv4";
833 nvidia,function = "pwm1";
834 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
835 nvidia,tristate = <TEGRA_PIN_DISABLE>;
836 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
837 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
838 };
839 ap_ready_pv5 {
840 nvidia,pins = "ap_ready_pv5";
841 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
842 nvidia,tristate = <TEGRA_PIN_DISABLE>;
843 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
844 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
845 };
846 touch_rst_pv6 {
847 nvidia,pins = "touch_rst_pv6";
848 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
849 nvidia,tristate = <TEGRA_PIN_DISABLE>;
850 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
851 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
852 };
853 touch_clk_pv7 {
854 nvidia,pins = "touch_clk_pv7";
855 nvidia,function = "touch";
856 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
857 nvidia,tristate = <TEGRA_PIN_DISABLE>;
858 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
859 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
860 };
861 modem_wake_ap_px0 {
862 nvidia,pins = "modem_wake_ap_px0";
863 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
864 nvidia,tristate = <TEGRA_PIN_DISABLE>;
865 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
866 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
867 };
868 touch_int_px1 {
869 nvidia,pins = "touch_int_px1";
870 nvidia,pull = <TEGRA_PIN_PULL_UP>;
871 nvidia,tristate = <TEGRA_PIN_DISABLE>;
872 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
873 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
874 };
875 motion_int_px2 {
876 nvidia,pins = "motion_int_px2";
877 nvidia,pull = <TEGRA_PIN_PULL_UP>;
878 nvidia,tristate = <TEGRA_PIN_DISABLE>;
879 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
880 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
881 };
882 als_prox_int_px3 {
883 nvidia,pins = "als_prox_int_px3";
884 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
885 nvidia,tristate = <TEGRA_PIN_DISABLE>;
886 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
887 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
888 };
889 temp_alert_px4 {
890 nvidia,pins = "temp_alert_px4";
891 nvidia,pull = <TEGRA_PIN_PULL_UP>;
892 nvidia,tristate = <TEGRA_PIN_DISABLE>;
893 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
894 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
895 };
896 button_power_on_px5 {
897 nvidia,pins = "button_power_on_px5";
898 nvidia,pull = <TEGRA_PIN_PULL_UP>;
899 nvidia,tristate = <TEGRA_PIN_DISABLE>;
900 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
901 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
902 };
903 button_vol_up_px6 {
904 nvidia,pins = "button_vol_up_px6";
905 nvidia,pull = <TEGRA_PIN_PULL_UP>;
906 nvidia,tristate = <TEGRA_PIN_DISABLE>;
907 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
908 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
909 };
910 button_vol_down_px7 {
911 nvidia,pins = "button_vol_down_px7";
912 nvidia,pull = <TEGRA_PIN_PULL_UP>;
913 nvidia,tristate = <TEGRA_PIN_DISABLE>;
914 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
915 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
916 };
917 button_slide_sw_py0 {
918 nvidia,pins = "button_slide_sw_py0";
919 nvidia,pull = <TEGRA_PIN_PULL_UP>;
920 nvidia,tristate = <TEGRA_PIN_DISABLE>;
921 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
922 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
923 };
924 button_home_py1 {
925 nvidia,pins = "button_home_py1";
926 nvidia,pull = <TEGRA_PIN_PULL_UP>;
927 nvidia,tristate = <TEGRA_PIN_DISABLE>;
928 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
929 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
930 };
931 lcd_te_py2 {
932 nvidia,pins = "lcd_te_py2";
933 nvidia,function = "displaya";
934 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
935 nvidia,tristate = <TEGRA_PIN_DISABLE>;
936 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
937 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
938 };
939 pwr_i2c_scl_py3 {
940 nvidia,pins = "pwr_i2c_scl_py3";
941 nvidia,function = "i2cpmu";
942 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
943 nvidia,tristate = <TEGRA_PIN_DISABLE>;
944 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
945 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
946 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
947 };
948 pwr_i2c_sda_py4 {
949 nvidia,pins = "pwr_i2c_sda_py4";
950 nvidia,function = "i2cpmu";
951 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
952 nvidia,tristate = <TEGRA_PIN_DISABLE>;
953 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
954 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
955 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
956 };
957 clk_32k_out_py5 {
958 nvidia,pins = "clk_32k_out_py5";
959 nvidia,function = "soc";
960 nvidia,pull = <TEGRA_PIN_PULL_UP>;
961 nvidia,tristate = <TEGRA_PIN_DISABLE>;
962 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
963 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
964 };
965 pz0 {
966 nvidia,pins = "pz0";
967 nvidia,pull = <TEGRA_PIN_PULL_UP>;
968 nvidia,tristate = <TEGRA_PIN_DISABLE>;
969 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
970 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
971 };
972 pz1 {
973 nvidia,pins = "pz1";
974 nvidia,function = "sdmmc1";
975 nvidia,pull = <TEGRA_PIN_PULL_UP>;
976 nvidia,tristate = <TEGRA_PIN_DISABLE>;
977 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
978 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
979 };
980 pz2 {
981 nvidia,pins = "pz2";
982 nvidia,pull = <TEGRA_PIN_PULL_UP>;
983 nvidia,tristate = <TEGRA_PIN_DISABLE>;
984 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
985 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
986 };
987 pz3 {
988 nvidia,pins = "pz3";
989 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
990 nvidia,tristate = <TEGRA_PIN_DISABLE>;
991 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
992 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
993 };
994 pz4 {
995 nvidia,pins = "pz4";
996 nvidia,function = "sdmmc1";
997 nvidia,pull = <TEGRA_PIN_PULL_UP>;
998 nvidia,tristate = <TEGRA_PIN_DISABLE>;
999 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1000 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1001 };
1002 pz5 {
1003 nvidia,pins = "pz5";
1004 nvidia,function = "soc";
1005 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1006 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1007 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1008 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1009 };
1010 dap2_fs_paa0 {
1011 nvidia,pins = "dap2_fs_paa0";
1012 nvidia,function = "i2s2";
1013 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1014 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1015 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1016 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1017 };
1018 dap2_sclk_paa1 {
1019 nvidia,pins = "dap2_sclk_paa1";
1020 nvidia,function = "i2s2";
1021 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1022 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1023 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1024 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1025 };
1026 dap2_din_paa2 {
1027 nvidia,pins = "dap2_din_paa2";
1028 nvidia,function = "i2s2";
1029 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1030 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1031 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1032 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1033 };
1034 dap2_dout_paa3 {
1035 nvidia,pins = "dap2_dout_paa3";
1036 nvidia,function = "i2s2";
1037 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1038 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1039 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1040 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1041 };
1042 aud_mclk_pbb0 {
1043 nvidia,pins = "aud_mclk_pbb0";
1044 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1045 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1046 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1047 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1048 };
1049 dvfs_pwm_pbb1 {
1050 nvidia,pins = "dvfs_pwm_pbb1";
1051 nvidia,function = "cldvfs";
1052 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1053 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1054 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1055 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1056 };
1057 dvfs_clk_pbb2 {
1058 nvidia,pins = "dvfs_clk_pbb2";
1059 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1060 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1061 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1062 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1063 };
1064 gpio_x1_aud_pbb3 {
1065 nvidia,pins = "gpio_x1_aud_pbb3";
1066 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1067 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1068 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1069 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1070 };
1071 gpio_x3_aud_pbb4 {
1072 nvidia,pins = "gpio_x3_aud_pbb4";
1073 nvidia,function = "rsvd0";
1074 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1075 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1076 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1077 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1078 };
1079 hdmi_cec_pcc0 {
1080 nvidia,pins = "hdmi_cec_pcc0";
1081 nvidia,function = "cec";
1082 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1083 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1084 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1085 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1086 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
1087 };
1088 hdmi_int_dp_hpd_pcc1 {
1089 nvidia,pins = "hdmi_int_dp_hpd_pcc1";
1090 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1091 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1092 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1093 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1094 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
1095 };
1096 spdif_out_pcc2 {
1097 nvidia,pins = "spdif_out_pcc2";
1098 nvidia,function = "rsvd1";
1099 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1100 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1101 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1102 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1103 };
1104 spdif_in_pcc3 {
1105 nvidia,pins = "spdif_in_pcc3";
1106 nvidia,function = "rsvd1";
1107 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1108 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1109 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1110 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1111 };
1112 usb_vbus_en0_pcc4 {
1113 nvidia,pins = "usb_vbus_en0_pcc4";
1114 nvidia,function = "usb";
1115 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1116 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1117 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1118 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1119 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
1120 };
1121 usb_vbus_en1_pcc5 {
1122 nvidia,pins = "usb_vbus_en1_pcc5";
1123 nvidia,function = "usb";
1124 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1125 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1126 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1127 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1128 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
1129 };
1130 dp_hpd0_pcc6 {
1131 nvidia,pins = "dp_hpd0_pcc6";
1132 nvidia,function = "dp";
1133 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1134 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1135 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1136 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1137 };
1138 pcc7 {
1139 nvidia,pins = "pcc7";
1140 nvidia,function = "rsvd0";
1141 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1142 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1143 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1144 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1145 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
1146 };
1147 spi2_cs1_pdd0 {
1148 nvidia,pins = "spi2_cs1_pdd0";
1149 nvidia,function = "spi2";
1150 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1151 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1152 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1153 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1154 };
1155 qspi_sck_pee0 {
1156 nvidia,pins = "qspi_sck_pee0";
1157 nvidia,function = "rsvd1";
1158 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1159 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1160 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1161 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1162 };
1163 qspi_cs_n_pee1 {
1164 nvidia,pins = "qspi_cs_n_pee1";
1165 nvidia,function = "rsvd1";
1166 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1167 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1168 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1169 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1170 };
1171 qspi_io0_pee2 {
1172 nvidia,pins = "qspi_io0_pee2";
1173 nvidia,function = "rsvd1";
1174 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1175 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1176 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1177 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1178 };
1179 qspi_io1_pee3 {
1180 nvidia,pins = "qspi_io1_pee3";
1181 nvidia,function = "rsvd1";
1182 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1183 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1184 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1185 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1186 };
1187 qspi_io2_pee4 {
1188 nvidia,pins = "qspi_io2_pee4";
1189 nvidia,function = "rsvd1";
1190 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1191 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1192 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1193 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1194 };
1195 qspi_io3_pee5 {
1196 nvidia,pins = "qspi_io3_pee5";
1197 nvidia,function = "rsvd1";
1198 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1199 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1200 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1201 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1202 };
1203 core_pwr_req {
1204 nvidia,pins = "core_pwr_req";
1205 nvidia,function = "core";
1206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1207 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1208 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1209 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1210 };
1211 cpu_pwr_req {
1212 nvidia,pins = "cpu_pwr_req";
1213 nvidia,function = "cpu";
1214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1215 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1216 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1217 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1218 };
1219 pwr_int_n {
1220 nvidia,pins = "pwr_int_n";
1221 nvidia,function = "pmi";
1222 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1223 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1224 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1225 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1226 };
1227 clk_32k_in {
1228 nvidia,pins = "clk_32k_in";
1229 nvidia,function = "clk";
1230 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1231 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1232 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1233 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1234 };
1235 jtag_rtck {
1236 nvidia,pins = "jtag_rtck";
1237 nvidia,function = "jtag";
1238 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1239 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1240 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1241 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1242 };
1243 clk_req {
1244 nvidia,pins = "clk_req";
1245 nvidia,function = "rsvd1";
1246 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1247 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1248 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1249 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1250 };
1251 shutdown {
1252 nvidia,pins = "shutdown";
1253 nvidia,function = "shutdown";
1254 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1255 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1256 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1257 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1258 };
1259 };
1260 };
1261
1262 /* MMC/SD */
1263 sdhci@0,700b0000 {
1264 status = "okay";
1265 bus-width = <4>;
1266 no-1-8-v;
1267
1268 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
1269 };
1270};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
new file mode 100644
index 000000000000..bc23f4dea002
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -0,0 +1,805 @@
1#include <dt-bindings/clock/tegra210-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/memory/tegra210-mc.h>
4#include <dt-bindings/pinctrl/pinctrl-tegra.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6
7/ {
8 compatible = "nvidia,tegra210";
9 interrupt-parent = <&lic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
12
13 host1x@0,50000000 {
14 compatible = "nvidia,tegra210-host1x", "simple-bus";
15 reg = <0x0 0x50000000 0x0 0x00034000>;
16 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
17 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
18 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
19 clock-names = "host1x";
20 resets = <&tegra_car 28>;
21 reset-names = "host1x";
22
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
27
28 dpaux1: dpaux@0,54040000 {
29 compatible = "nvidia,tegra210-dpaux";
30 reg = <0x0 0x54040000 0x0 0x00040000>;
31 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
32 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
33 <&tegra_car TEGRA210_CLK_PLL_DP>;
34 clock-names = "dpaux", "parent";
35 resets = <&tegra_car 207>;
36 reset-names = "dpaux";
37 status = "disabled";
38 };
39
40 vi@0,54080000 {
41 compatible = "nvidia,tegra210-vi";
42 reg = <0x0 0x54080000 0x0 0x00040000>;
43 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
44 status = "disabled";
45 };
46
47 tsec@0,54100000 {
48 compatible = "nvidia,tegra210-tsec";
49 reg = <0x0 0x54100000 0x0 0x00040000>;
50 };
51
52 dc@0,54200000 {
53 compatible = "nvidia,tegra210-dc";
54 reg = <0x0 0x54200000 0x0 0x00040000>;
55 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&tegra_car TEGRA210_CLK_DISP1>,
57 <&tegra_car TEGRA210_CLK_PLL_P>;
58 clock-names = "dc", "parent";
59 resets = <&tegra_car 27>;
60 reset-names = "dc";
61
62 iommus = <&mc TEGRA_SWGROUP_DC>;
63
64 nvidia,head = <0>;
65 };
66
67 dc@0,54240000 {
68 compatible = "nvidia,tegra210-dc";
69 reg = <0x0 0x54240000 0x0 0x00040000>;
70 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
71 clocks = <&tegra_car TEGRA210_CLK_DISP2>,
72 <&tegra_car TEGRA210_CLK_PLL_P>;
73 clock-names = "dc", "parent";
74 resets = <&tegra_car 26>;
75 reset-names = "dc";
76
77 iommus = <&mc TEGRA_SWGROUP_DCB>;
78
79 nvidia,head = <1>;
80 };
81
82 dsi@0,54300000 {
83 compatible = "nvidia,tegra210-dsi";
84 reg = <0x0 0x54300000 0x0 0x00040000>;
85 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
86 <&tegra_car TEGRA210_CLK_DSIALP>,
87 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
88 clock-names = "dsi", "lp", "parent";
89 resets = <&tegra_car 48>;
90 reset-names = "dsi";
91 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
92
93 status = "disabled";
94
95 #address-cells = <1>;
96 #size-cells = <0>;
97 };
98
99 vic@0,54340000 {
100 compatible = "nvidia,tegra210-vic";
101 reg = <0x0 0x54340000 0x0 0x00040000>;
102 status = "disabled";
103 };
104
105 nvjpg@0,54380000 {
106 compatible = "nvidia,tegra210-nvjpg";
107 reg = <0x0 0x54380000 0x0 0x00040000>;
108 status = "disabled";
109 };
110
111 dsi@0,54400000 {
112 compatible = "nvidia,tegra210-dsi";
113 reg = <0x0 0x54400000 0x0 0x00040000>;
114 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
115 <&tegra_car TEGRA210_CLK_DSIBLP>,
116 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
117 clock-names = "dsi", "lp", "parent";
118 resets = <&tegra_car 82>;
119 reset-names = "dsi";
120 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
121
122 status = "disabled";
123
124 #address-cells = <1>;
125 #size-cells = <0>;
126 };
127
128 nvdec@0,54480000 {
129 compatible = "nvidia,tegra210-nvdec";
130 reg = <0x0 0x54480000 0x0 0x00040000>;
131 status = "disabled";
132 };
133
134 nvenc@0,544c0000 {
135 compatible = "nvidia,tegra210-nvenc";
136 reg = <0x0 0x544c0000 0x0 0x00040000>;
137 status = "disabled";
138 };
139
140 tsec@0,54500000 {
141 compatible = "nvidia,tegra210-tsec";
142 reg = <0x0 0x54500000 0x0 0x00040000>;
143 status = "disabled";
144 };
145
146 sor@0,54540000 {
147 compatible = "nvidia,tegra210-sor";
148 reg = <0x0 0x54540000 0x0 0x00040000>;
149 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
151 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
152 <&tegra_car TEGRA210_CLK_PLL_DP>,
153 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
154 clock-names = "sor", "parent", "dp", "safe";
155 resets = <&tegra_car 182>;
156 reset-names = "sor";
157 status = "disabled";
158 };
159
160 sor@0,54580000 {
161 compatible = "nvidia,tegra210-sor1";
162 reg = <0x0 0x54580000 0x0 0x00040000>;
163 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
165 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
166 <&tegra_car TEGRA210_CLK_PLL_DP>,
167 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
168 clock-names = "sor", "parent", "dp", "safe";
169 resets = <&tegra_car 183>;
170 reset-names = "sor";
171 status = "disabled";
172 };
173
174 dpaux: dpaux@0,545c0000 {
175 compatible = "nvidia,tegra124-dpaux";
176 reg = <0x0 0x545c0000 0x0 0x00040000>;
177 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
179 <&tegra_car TEGRA210_CLK_PLL_DP>;
180 clock-names = "dpaux", "parent";
181 resets = <&tegra_car 181>;
182 reset-names = "dpaux";
183 status = "disabled";
184 };
185
186 isp@0,54600000 {
187 compatible = "nvidia,tegra210-isp";
188 reg = <0x0 0x54600000 0x0 0x00040000>;
189 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
190 status = "disabled";
191 };
192
193 isp@0,54680000 {
194 compatible = "nvidia,tegra210-isp";
195 reg = <0x0 0x54680000 0x0 0x00040000>;
196 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
197 status = "disabled";
198 };
199
200 i2c@0,546c0000 {
201 compatible = "nvidia,tegra210-i2c-vi";
202 reg = <0x0 0x546c0000 0x0 0x00040000>;
203 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
204 status = "disabled";
205 };
206 };
207
208 gic: interrupt-controller@0,50041000 {
209 compatible = "arm,gic-400";
210 #interrupt-cells = <3>;
211 interrupt-controller;
212 reg = <0x0 0x50041000 0x0 0x1000>,
213 <0x0 0x50042000 0x0 0x2000>,
214 <0x0 0x50044000 0x0 0x2000>,
215 <0x0 0x50046000 0x0 0x2000>;
216 interrupts = <GIC_PPI 9
217 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
218 interrupt-parent = <&gic>;
219 };
220
221 gpu@0,57000000 {
222 compatible = "nvidia,gm20b";
223 reg = <0x0 0x57000000 0x0 0x01000000>,
224 <0x0 0x58000000 0x0 0x01000000>;
225 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
227 interrupt-names = "stall", "nonstall";
228 clocks = <&tegra_car TEGRA210_CLK_GPU>,
229 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>;
230 clock-names = "gpu", "pwr";
231 resets = <&tegra_car 184>;
232 reset-names = "gpu";
233 status = "disabled";
234 };
235
236 lic: interrupt-controller@0,60004000 {
237 compatible = "nvidia,tegra210-ictlr";
238 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
239 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
240 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
241 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
242 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
243 <0x0 0x60004500 0x0 0x40>; /* senary controller */
244 interrupt-controller;
245 #interrupt-cells = <3>;
246 interrupt-parent = <&gic>;
247 };
248
249 timer@0,60005000 {
250 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
251 reg = <0x0 0x60005000 0x0 0x400>;
252 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
259 clock-names = "timer";
260 };
261
262 tegra_car: clock@0,60006000 {
263 compatible = "nvidia,tegra210-car";
264 reg = <0x0 0x60006000 0x0 0x1000>;
265 #clock-cells = <1>;
266 #reset-cells = <1>;
267 };
268
269 flow-controller@0,60007000 {
270 compatible = "nvidia,tegra210-flowctrl";
271 reg = <0x0 0x60007000 0x0 0x1000>;
272 };
273
274 gpio: gpio@0,6000d000 {
275 compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
276 reg = <0x0 0x6000d000 0x0 0x1000>;
277 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
285 #gpio-cells = <2>;
286 gpio-controller;
287 #interrupt-cells = <2>;
288 interrupt-controller;
289 };
290
291 apbdma: dma@0,60020000 {
292 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
293 reg = <0x0 0x60020000 0x0 0x1400>;
294 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
327 clock-names = "dma";
328 resets = <&tegra_car 34>;
329 reset-names = "dma";
330 #dma-cells = <1>;
331 };
332
333 apbmisc@0,70000800 {
334 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
335 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
336 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
337 };
338
339 pinmux: pinmux@0,700008d4 {
340 compatible = "nvidia,tegra210-pinmux";
341 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
342 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
343 };
344
345 /*
346 * There are two serial driver i.e. 8250 based simple serial
347 * driver and APB DMA based serial driver for higher baudrate
348 * and performace. To enable the 8250 based driver, the compatible
349 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
350 * the APB DMA based serial driver, the comptible is
351 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
352 */
353 uarta: serial@0,70006000 {
354 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
355 reg = <0x0 0x70006000 0x0 0x40>;
356 reg-shift = <2>;
357 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
359 clock-names = "serial";
360 resets = <&tegra_car 6>;
361 reset-names = "serial";
362 dmas = <&apbdma 8>, <&apbdma 8>;
363 dma-names = "rx", "tx";
364 status = "disabled";
365 };
366
367 uartb: serial@0,70006040 {
368 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
369 reg = <0x0 0x70006040 0x0 0x40>;
370 reg-shift = <2>;
371 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
373 clock-names = "serial";
374 resets = <&tegra_car 7>;
375 reset-names = "serial";
376 dmas = <&apbdma 9>, <&apbdma 9>;
377 dma-names = "rx", "tx";
378 status = "disabled";
379 };
380
381 uartc: serial@0,70006200 {
382 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
383 reg = <0x0 0x70006200 0x0 0x40>;
384 reg-shift = <2>;
385 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
387 clock-names = "serial";
388 resets = <&tegra_car 55>;
389 reset-names = "serial";
390 dmas = <&apbdma 10>, <&apbdma 10>;
391 dma-names = "rx", "tx";
392 status = "disabled";
393 };
394
395 uartd: serial@0,70006300 {
396 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
397 reg = <0x0 0x70006300 0x0 0x40>;
398 reg-shift = <2>;
399 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
401 clock-names = "serial";
402 resets = <&tegra_car 65>;
403 reset-names = "serial";
404 dmas = <&apbdma 19>, <&apbdma 19>;
405 dma-names = "rx", "tx";
406 status = "disabled";
407 };
408
409 pwm: pwm@0,7000a000 {
410 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
411 reg = <0x0 0x7000a000 0x0 0x100>;
412 #pwm-cells = <2>;
413 clocks = <&tegra_car TEGRA210_CLK_PWM>;
414 clock-names = "pwm";
415 resets = <&tegra_car 17>;
416 reset-names = "pwm";
417 status = "disabled";
418 };
419
420 i2c@0,7000c000 {
421 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
422 reg = <0x0 0x7000c000 0x0 0x100>;
423 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
424 #address-cells = <1>;
425 #size-cells = <0>;
426 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
427 clock-names = "div-clk";
428 resets = <&tegra_car 12>;
429 reset-names = "i2c";
430 dmas = <&apbdma 21>, <&apbdma 21>;
431 dma-names = "rx", "tx";
432 status = "disabled";
433 };
434
435 i2c@0,7000c400 {
436 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
437 reg = <0x0 0x7000c400 0x0 0x100>;
438 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
439 #address-cells = <1>;
440 #size-cells = <0>;
441 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
442 clock-names = "div-clk";
443 resets = <&tegra_car 54>;
444 reset-names = "i2c";
445 dmas = <&apbdma 22>, <&apbdma 22>;
446 dma-names = "rx", "tx";
447 status = "disabled";
448 };
449
450 i2c@0,7000c500 {
451 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
452 reg = <0x0 0x7000c500 0x0 0x100>;
453 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
455 #size-cells = <0>;
456 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
457 clock-names = "div-clk";
458 resets = <&tegra_car 67>;
459 reset-names = "i2c";
460 dmas = <&apbdma 23>, <&apbdma 23>;
461 dma-names = "rx", "tx";
462 status = "disabled";
463 };
464
465 i2c@0,7000c700 {
466 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
467 reg = <0x0 0x7000c700 0x0 0x100>;
468 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
469 #address-cells = <1>;
470 #size-cells = <0>;
471 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
472 clock-names = "div-clk";
473 resets = <&tegra_car 103>;
474 reset-names = "i2c";
475 dmas = <&apbdma 26>, <&apbdma 26>;
476 dma-names = "rx", "tx";
477 status = "disabled";
478 };
479
480 i2c@0,7000d000 {
481 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
482 reg = <0x0 0x7000d000 0x0 0x100>;
483 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
484 #address-cells = <1>;
485 #size-cells = <0>;
486 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
487 clock-names = "div-clk";
488 resets = <&tegra_car 47>;
489 reset-names = "i2c";
490 dmas = <&apbdma 24>, <&apbdma 24>;
491 dma-names = "rx", "tx";
492 status = "disabled";
493 };
494
495 i2c@0,7000d100 {
496 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
497 reg = <0x0 0x7000d100 0x0 0x100>;
498 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
499 #address-cells = <1>;
500 #size-cells = <0>;
501 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
502 clock-names = "div-clk";
503 resets = <&tegra_car 166>;
504 reset-names = "i2c";
505 dmas = <&apbdma 30>, <&apbdma 30>;
506 dma-names = "rx", "tx";
507 status = "disabled";
508 };
509
510 spi@0,7000d400 {
511 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
512 reg = <0x0 0x7000d400 0x0 0x200>;
513 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
514 #address-cells = <1>;
515 #size-cells = <0>;
516 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
517 clock-names = "spi";
518 resets = <&tegra_car 41>;
519 reset-names = "spi";
520 dmas = <&apbdma 15>, <&apbdma 15>;
521 dma-names = "rx", "tx";
522 status = "disabled";
523 };
524
525 spi@0,7000d600 {
526 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
527 reg = <0x0 0x7000d600 0x0 0x200>;
528 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
529 #address-cells = <1>;
530 #size-cells = <0>;
531 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
532 clock-names = "spi";
533 resets = <&tegra_car 44>;
534 reset-names = "spi";
535 dmas = <&apbdma 16>, <&apbdma 16>;
536 dma-names = "rx", "tx";
537 status = "disabled";
538 };
539
540 spi@0,7000d800 {
541 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
542 reg = <0x0 0x7000d800 0x0 0x200>;
543 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
544 #address-cells = <1>;
545 #size-cells = <0>;
546 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
547 clock-names = "spi";
548 resets = <&tegra_car 46>;
549 reset-names = "spi";
550 dmas = <&apbdma 17>, <&apbdma 17>;
551 dma-names = "rx", "tx";
552 status = "disabled";
553 };
554
555 spi@0,7000da00 {
556 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
557 reg = <0x0 0x7000da00 0x0 0x200>;
558 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
559 #address-cells = <1>;
560 #size-cells = <0>;
561 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
562 clock-names = "spi";
563 resets = <&tegra_car 68>;
564 reset-names = "spi";
565 dmas = <&apbdma 18>, <&apbdma 18>;
566 dma-names = "rx", "tx";
567 status = "disabled";
568 };
569
570 rtc@0,7000e000 {
571 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
572 reg = <0x0 0x7000e000 0x0 0x100>;
573 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&tegra_car TEGRA210_CLK_RTC>;
575 clock-names = "rtc";
576 };
577
578 pmc: pmc@0,7000e400 {
579 compatible = "nvidia,tegra210-pmc";
580 reg = <0x0 0x7000e400 0x0 0x400>;
581 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
582 clock-names = "pclk", "clk32k_in";
583
584 #power-domain-cells = <1>;
585 };
586
587 fuse@0,7000f800 {
588 compatible = "nvidia,tegra210-efuse";
589 reg = <0x0 0x7000f800 0x0 0x400>;
590 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
591 clock-names = "fuse";
592 resets = <&tegra_car 39>;
593 reset-names = "fuse";
594 };
595
596 mc: memory-controller@0,70019000 {
597 compatible = "nvidia,tegra210-mc";
598 reg = <0x0 0x70019000 0x0 0x1000>;
599 clocks = <&tegra_car TEGRA210_CLK_MC>;
600 clock-names = "mc";
601
602 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
603
604 #iommu-cells = <1>;
605 };
606
607 hda@0,70030000 {
608 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
609 reg = <0x0 0x70030000 0x0 0x10000>;
610 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&tegra_car TEGRA210_CLK_HDA>,
612 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
613 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
614 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
615 resets = <&tegra_car 125>, /* hda */
616 <&tegra_car 128>, /* hda2hdmi */
617 <&tegra_car 111>; /* hda2codec_2x */
618 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
619 status = "disabled";
620 };
621
622 sdhci@0,700b0000 {
623 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
624 reg = <0x0 0x700b0000 0x0 0x200>;
625 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
627 clock-names = "sdhci";
628 resets = <&tegra_car 14>;
629 reset-names = "sdhci";
630 status = "disabled";
631 };
632
633 sdhci@0,700b0200 {
634 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
635 reg = <0x0 0x700b0200 0x0 0x200>;
636 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
638 clock-names = "sdhci";
639 resets = <&tegra_car 9>;
640 reset-names = "sdhci";
641 status = "disabled";
642 };
643
644 sdhci@0,700b0400 {
645 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
646 reg = <0x0 0x700b0400 0x0 0x200>;
647 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
649 clock-names = "sdhci";
650 resets = <&tegra_car 69>;
651 reset-names = "sdhci";
652 status = "disabled";
653 };
654
655 sdhci@0,700b0600 {
656 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
657 reg = <0x0 0x700b0600 0x0 0x200>;
658 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
660 clock-names = "sdhci";
661 resets = <&tegra_car 15>;
662 reset-names = "sdhci";
663 status = "disabled";
664 };
665
666 mipi: mipi@0,700e3000 {
667 compatible = "nvidia,tegra210-mipi";
668 reg = <0x0 0x700e3000 0x0 0x100>;
669 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
670 clock-names = "mipi-cal";
671 #nvidia,mipi-calibrate-cells = <1>;
672 };
673
674 spi@0,70410000 {
675 compatible = "nvidia,tegra210-qspi";
676 reg = <0x0 0x70410000 0x0 0x1000>;
677 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
678 #address-cells = <1>;
679 #size-cells = <0>;
680 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
681 clock-names = "qspi";
682 resets = <&tegra_car 211>;
683 reset-names = "qspi";
684 dmas = <&apbdma 5>, <&apbdma 5>;
685 dma-names = "rx", "tx";
686 status = "disabled";
687 };
688
689 usb@0,7d000000 {
690 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
691 reg = <0x0 0x7d000000 0x0 0x4000>;
692 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
693 phy_type = "utmi";
694 clocks = <&tegra_car TEGRA210_CLK_USBD>;
695 clock-names = "usb";
696 resets = <&tegra_car 22>;
697 reset-names = "usb";
698 nvidia,phy = <&phy1>;
699 status = "disabled";
700 };
701
702 phy1: usb-phy@0,7d000000 {
703 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
704 reg = <0x0 0x7d000000 0x0 0x4000>,
705 <0x0 0x7d000000 0x0 0x4000>;
706 phy_type = "utmi";
707 clocks = <&tegra_car TEGRA210_CLK_USBD>,
708 <&tegra_car TEGRA210_CLK_PLL_U>,
709 <&tegra_car TEGRA210_CLK_USBD>;
710 clock-names = "reg", "pll_u", "utmi-pads";
711 resets = <&tegra_car 22>, <&tegra_car 22>;
712 reset-names = "usb", "utmi-pads";
713 nvidia,hssync-start-delay = <0>;
714 nvidia,idle-wait-delay = <17>;
715 nvidia,elastic-limit = <16>;
716 nvidia,term-range-adj = <6>;
717 nvidia,xcvr-setup = <9>;
718 nvidia,xcvr-lsfslew = <0>;
719 nvidia,xcvr-lsrslew = <3>;
720 nvidia,hssquelch-level = <2>;
721 nvidia,hsdiscon-level = <5>;
722 nvidia,xcvr-hsslew = <12>;
723 nvidia,has-utmi-pad-registers;
724 status = "disabled";
725 };
726
727 usb@0,7d004000 {
728 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
729 reg = <0x0 0x7d004000 0x0 0x4000>;
730 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
731 phy_type = "utmi";
732 clocks = <&tegra_car TEGRA210_CLK_USB2>;
733 clock-names = "usb";
734 resets = <&tegra_car 58>;
735 reset-names = "usb";
736 nvidia,phy = <&phy2>;
737 status = "disabled";
738 };
739
740 phy2: usb-phy@0,7d004000 {
741 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
742 reg = <0x0 0x7d004000 0x0 0x4000>,
743 <0x0 0x7d000000 0x0 0x4000>;
744 phy_type = "utmi";
745 clocks = <&tegra_car TEGRA210_CLK_USB2>,
746 <&tegra_car TEGRA210_CLK_PLL_U>,
747 <&tegra_car TEGRA210_CLK_USBD>;
748 clock-names = "reg", "pll_u", "utmi-pads";
749 resets = <&tegra_car 58>, <&tegra_car 22>;
750 reset-names = "usb", "utmi-pads";
751 nvidia,hssync-start-delay = <0>;
752 nvidia,idle-wait-delay = <17>;
753 nvidia,elastic-limit = <16>;
754 nvidia,term-range-adj = <6>;
755 nvidia,xcvr-setup = <9>;
756 nvidia,xcvr-lsfslew = <0>;
757 nvidia,xcvr-lsrslew = <3>;
758 nvidia,hssquelch-level = <2>;
759 nvidia,hsdiscon-level = <5>;
760 nvidia,xcvr-hsslew = <12>;
761 status = "disabled";
762 };
763
764 cpus {
765 #address-cells = <1>;
766 #size-cells = <0>;
767
768 cpu@0 {
769 device_type = "cpu";
770 compatible = "arm,cortex-a57";
771 reg = <0>;
772 };
773
774 cpu@1 {
775 device_type = "cpu";
776 compatible = "arm,cortex-a57";
777 reg = <1>;
778 };
779
780 cpu@2 {
781 device_type = "cpu";
782 compatible = "arm,cortex-a57";
783 reg = <2>;
784 };
785
786 cpu@3 {
787 device_type = "cpu";
788 compatible = "arm,cortex-a57";
789 reg = <3>;
790 };
791 };
792
793 timer {
794 compatible = "arm,armv8-timer";
795 interrupts = <GIC_PPI 13
796 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
797 <GIC_PPI 14
798 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
799 <GIC_PPI 11
800 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
801 <GIC_PPI 10
802 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
803 interrupt-parent = <&gic>;
804 };
805};
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
new file mode 100644
index 000000000000..6f45aea49e4f
--- /dev/null
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -0,0 +1,401 @@
1/*
2 * This header provides constants for binding nvidia,tegra210-car.
3 *
4 * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
5 * registers. These IDs often match those in the CAR's RST_DEVICES registers,
6 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
7 * this case, those clocks are assigned IDs above 224 in order to highlight
8 * this issue. Implementations that interpret these clock IDs as bit values
9 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
10 * explicitly handle these special cases.
11 *
12 * The balance of the clocks controlled by the CAR are assigned IDs of 224 and
13 * above.
14 */
15
16#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
17#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
18
19/* 0 */
20/* 1 */
21/* 2 */
22#define TEGRA210_CLK_ISPB 3
23#define TEGRA210_CLK_RTC 4
24#define TEGRA210_CLK_TIMER 5
25#define TEGRA210_CLK_UARTA 6
26/* 7 (register bit affects uartb and vfir) */
27#define TEGRA210_CLK_GPIO 8
28#define TEGRA210_CLK_SDMMC2 9
29/* 10 (register bit affects spdif_in and spdif_out) */
30#define TEGRA210_CLK_I2S1 11
31#define TEGRA210_CLK_I2C1 12
32/* 13 */
33#define TEGRA210_CLK_SDMMC1 14
34#define TEGRA210_CLK_SDMMC4 15
35/* 16 */
36#define TEGRA210_CLK_PWM 17
37#define TEGRA210_CLK_I2S2 18
38/* 19 */
39/* 20 (register bit affects vi and vi_sensor) */
40/* 21 */
41#define TEGRA210_CLK_USBD 22
42#define TEGRA210_CLK_ISP 23
43/* 24 */
44/* 25 */
45#define TEGRA210_CLK_DISP2 26
46#define TEGRA210_CLK_DISP1 27
47#define TEGRA210_CLK_HOST1X 28
48/* 29 */
49#define TEGRA210_CLK_I2S0 30
50/* 31 */
51
52#define TEGRA210_CLK_MC 32
53#define TEGRA210_CLK_AHBDMA 33
54#define TEGRA210_CLK_APBDMA 34
55/* 35 */
56/* 36 */
57/* 37 */
58#define TEGRA210_CLK_PMC 38
59/* 39 (register bit affects fuse and fuse_burn) */
60#define TEGRA210_CLK_KFUSE 40
61#define TEGRA210_CLK_SBC1 41
62/* 42 */
63/* 43 */
64#define TEGRA210_CLK_SBC2 44
65/* 45 */
66#define TEGRA210_CLK_SBC3 46
67#define TEGRA210_CLK_I2C5 47
68#define TEGRA210_CLK_DSIA 48
69/* 49 */
70/* 50 */
71/* 51 */
72#define TEGRA210_CLK_CSI 52
73/* 53 */
74#define TEGRA210_CLK_I2C2 54
75#define TEGRA210_CLK_UARTC 55
76#define TEGRA210_CLK_MIPI_CAL 56
77#define TEGRA210_CLK_EMC 57
78#define TEGRA210_CLK_USB2 58
79/* 59 */
80/* 60 */
81/* 61 */
82/* 62 */
83#define TEGRA210_CLK_BSEV 63
84
85/* 64 */
86#define TEGRA210_CLK_UARTD 65
87/* 66 */
88#define TEGRA210_CLK_I2C3 67
89#define TEGRA210_CLK_SBC4 68
90#define TEGRA210_CLK_SDMMC3 69
91#define TEGRA210_CLK_PCIE 70
92#define TEGRA210_CLK_OWR 71
93#define TEGRA210_CLK_AFI 72
94#define TEGRA210_CLK_CSITE 73
95/* 74 */
96/* 75 */
97/* 76 */
98/* 77 */
99#define TEGRA210_CLK_SOC_THERM 78
100#define TEGRA210_CLK_DTV 79
101/* 80 */
102#define TEGRA210_CLK_I2CSLOW 81
103#define TEGRA210_CLK_DSIB 82
104#define TEGRA210_CLK_TSEC 83
105/* 84 */
106/* 85 */
107/* 86 */
108/* 87 */
109/* 88 */
110#define TEGRA210_CLK_XUSB_HOST 89
111/* 90 */
112/* 91 */
113#define TEGRA210_CLK_CSUS 92
114/* 93 */
115/* 94 */
116/* 95 (bit affects xusb_dev and xusb_dev_src) */
117
118/* 96 */
119/* 97 */
120/* 98 */
121#define TEGRA210_CLK_MSELECT 99
122#define TEGRA210_CLK_TSENSOR 100
123#define TEGRA210_CLK_I2S3 101
124#define TEGRA210_CLK_I2S4 102
125#define TEGRA210_CLK_I2C4 103
126/* 104 */
127/* 105 */
128#define TEGRA210_CLK_D_AUDIO 106
129/* 107 ( affects abp -> ape) */
130/* 108 */
131/* 109 */
132/* 110 */
133#define TEGRA210_CLK_HDA2CODEC_2X 111
134/* 112 */
135/* 113 */
136/* 114 */
137/* 115 */
138/* 116 */
139/* 117 */
140#define TEGRA210_CLK_SPDIF_2X 118
141#define TEGRA210_CLK_ACTMON 119
142#define TEGRA210_CLK_EXTERN1 120
143#define TEGRA210_CLK_EXTERN2 121
144#define TEGRA210_CLK_EXTERN3 122
145#define TEGRA210_CLK_SATA_OOB 123
146#define TEGRA210_CLK_SATA 124
147#define TEGRA210_CLK_HDA 125
148/* 126 */
149/* 127 */
150
151#define TEGRA210_CLK_HDA2HDMI 128
152/* 129 */
153/* 130 */
154/* 131 */
155/* 132 */
156/* 133 */
157/* 134 */
158/* 135 */
159/* 136 */
160/* 137 */
161/* 138 */
162/* 139 */
163/* 140 */
164/* 141 */
165/* 142 */
166/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */
167#define TEGRA210_CLK_XUSB_GATE 143
168#define TEGRA210_CLK_CILAB 144
169#define TEGRA210_CLK_CILCD 145
170#define TEGRA210_CLK_CILE 146
171#define TEGRA210_CLK_DSIALP 147
172#define TEGRA210_CLK_DSIBLP 148
173#define TEGRA210_CLK_ENTROPY 149
174/* 150 */
175/* 151 */
176/* 152 */
177/* 153 */
178/* 154 */
179/* 155 (bit affects dfll_ref and dfll_soc) */
180#define TEGRA210_CLK_XUSB_SS 156
181/* 157 */
182/* 158 */
183/* 159 */
184
185/* 160 */
186#define TEGRA210_CLK_DMIC1 161
187#define TEGRA210_CLK_DMIC2 162
188/* 163 */
189/* 164 */
190/* 165 */
191#define TEGRA210_CLK_I2C6 166
192/* 167 */
193/* 168 */
194/* 169 */
195/* 170 */
196#define TEGRA210_CLK_VIM2_CLK 171
197/* 172 */
198#define TEGRA210_CLK_MIPIBIF 173
199/* 174 */
200/* 175 */
201/* 176 */
202#define TEGRA210_CLK_CLK72MHZ 177
203#define TEGRA210_CLK_VIC03 178
204/* 179 */
205/* 180 */
206#define TEGRA210_CLK_DPAUX 181
207#define TEGRA210_CLK_SOR0 182
208#define TEGRA210_CLK_SOR1 183
209#define TEGRA210_CLK_GPU 184
210#define TEGRA210_CLK_DBGAPB 185
211/* 186 */
212#define TEGRA210_CLK_PLL_P_OUT_ADSP 187
213/* 188 */
214#define TEGRA210_CLK_PLL_G_REF 189
215/* 190 */
216/* 191 */
217
218/* 192 */
219#define TEGRA210_CLK_SDMMC_LEGACY 193
220#define TEGRA210_CLK_NVDEC 194
221#define TEGRA210_CLK_NVJPG 195
222/* 196 */
223#define TEGRA210_CLK_DMIC3 197
224#define TEGRA210_CLK_APE 198
225/* 199 */
226/* 200 */
227/* 201 */
228#define TEGRA210_CLK_MAUD 202
229/* 203 */
230/* 204 */
231/* 205 */
232#define TEGRA210_CLK_TSECB 206
233#define TEGRA210_CLK_DPAUX1 207
234#define TEGRA210_CLK_VI_I2C 208
235#define TEGRA210_CLK_HSIC_TRK 209
236#define TEGRA210_CLK_USB2_TRK 210
237#define TEGRA210_CLK_QSPI 211
238#define TEGRA210_CLK_UARTAPE 212
239/* 213 */
240/* 214 */
241/* 215 */
242/* 216 */
243/* 217 */
244/* 218 */
245#define TEGRA210_CLK_NVENC 219
246/* 220 */
247/* 221 */
248#define TEGRA210_CLK_SOR_SAFE 222
249#define TEGRA210_CLK_PLL_P_OUT_CPU 223
250
251
252#define TEGRA210_CLK_UARTB 224
253#define TEGRA210_CLK_VFIR 225
254#define TEGRA210_CLK_SPDIF_IN 226
255#define TEGRA210_CLK_SPDIF_OUT 227
256#define TEGRA210_CLK_VI 228
257#define TEGRA210_CLK_VI_SENSOR 229
258#define TEGRA210_CLK_FUSE 230
259#define TEGRA210_CLK_FUSE_BURN 231
260#define TEGRA210_CLK_CLK_32K 232
261#define TEGRA210_CLK_CLK_M 233
262#define TEGRA210_CLK_CLK_M_DIV2 234
263#define TEGRA210_CLK_CLK_M_DIV4 235
264#define TEGRA210_CLK_PLL_REF 236
265#define TEGRA210_CLK_PLL_C 237
266#define TEGRA210_CLK_PLL_C_OUT1 238
267#define TEGRA210_CLK_PLL_C2 239
268#define TEGRA210_CLK_PLL_C3 240
269#define TEGRA210_CLK_PLL_M 241
270#define TEGRA210_CLK_PLL_M_OUT1 242
271#define TEGRA210_CLK_PLL_P 243
272#define TEGRA210_CLK_PLL_P_OUT1 244
273#define TEGRA210_CLK_PLL_P_OUT2 245
274#define TEGRA210_CLK_PLL_P_OUT3 246
275#define TEGRA210_CLK_PLL_P_OUT4 247
276#define TEGRA210_CLK_PLL_A 248
277#define TEGRA210_CLK_PLL_A_OUT0 249
278#define TEGRA210_CLK_PLL_D 250
279#define TEGRA210_CLK_PLL_D_OUT0 251
280#define TEGRA210_CLK_PLL_D2 252
281#define TEGRA210_CLK_PLL_D2_OUT0 253
282#define TEGRA210_CLK_PLL_U 254
283#define TEGRA210_CLK_PLL_U_480M 255
284
285#define TEGRA210_CLK_PLL_U_60M 256
286#define TEGRA210_CLK_PLL_U_48M 257
287/* 258 */
288#define TEGRA210_CLK_PLL_X 259
289#define TEGRA210_CLK_PLL_X_OUT0 260
290#define TEGRA210_CLK_PLL_RE_VCO 261
291#define TEGRA210_CLK_PLL_RE_OUT 262
292#define TEGRA210_CLK_PLL_E 263
293#define TEGRA210_CLK_SPDIF_IN_SYNC 264
294#define TEGRA210_CLK_I2S0_SYNC 265
295#define TEGRA210_CLK_I2S1_SYNC 266
296#define TEGRA210_CLK_I2S2_SYNC 267
297#define TEGRA210_CLK_I2S3_SYNC 268
298#define TEGRA210_CLK_I2S4_SYNC 269
299#define TEGRA210_CLK_VIMCLK_SYNC 270
300#define TEGRA210_CLK_AUDIO0 271
301#define TEGRA210_CLK_AUDIO1 272
302#define TEGRA210_CLK_AUDIO2 273
303#define TEGRA210_CLK_AUDIO3 274
304#define TEGRA210_CLK_AUDIO4 275
305#define TEGRA210_CLK_SPDIF 276
306#define TEGRA210_CLK_CLK_OUT_1 277
307#define TEGRA210_CLK_CLK_OUT_2 278
308#define TEGRA210_CLK_CLK_OUT_3 279
309#define TEGRA210_CLK_BLINK 280
310/* 281 */
311/* 282 */
312/* 283 */
313#define TEGRA210_CLK_XUSB_HOST_SRC 284
314#define TEGRA210_CLK_XUSB_FALCON_SRC 285
315#define TEGRA210_CLK_XUSB_FS_SRC 286
316#define TEGRA210_CLK_XUSB_SS_SRC 287
317
318#define TEGRA210_CLK_XUSB_DEV_SRC 288
319#define TEGRA210_CLK_XUSB_DEV 289
320#define TEGRA210_CLK_XUSB_HS_SRC 290
321#define TEGRA210_CLK_SCLK 291
322#define TEGRA210_CLK_HCLK 292
323#define TEGRA210_CLK_PCLK 293
324#define TEGRA210_CLK_CCLK_G 294
325#define TEGRA210_CLK_CCLK_LP 295
326#define TEGRA210_CLK_DFLL_REF 296
327#define TEGRA210_CLK_DFLL_SOC 297
328#define TEGRA210_CLK_VI_SENSOR2 298
329#define TEGRA210_CLK_PLL_P_OUT5 299
330#define TEGRA210_CLK_CML0 300
331#define TEGRA210_CLK_CML1 301
332#define TEGRA210_CLK_PLL_C4 302
333#define TEGRA210_CLK_PLL_DP 303
334#define TEGRA210_CLK_PLL_E_MUX 304
335#define TEGRA210_CLK_PLL_MB 305
336#define TEGRA210_CLK_PLL_A1 306
337#define TEGRA210_CLK_PLL_D_DSI_OUT 307
338#define TEGRA210_CLK_PLL_C4_OUT0 308
339#define TEGRA210_CLK_PLL_C4_OUT1 309
340#define TEGRA210_CLK_PLL_C4_OUT2 310
341#define TEGRA210_CLK_PLL_C4_OUT3 311
342#define TEGRA210_CLK_PLL_U_OUT 312
343#define TEGRA210_CLK_PLL_U_OUT1 313
344#define TEGRA210_CLK_PLL_U_OUT2 314
345#define TEGRA210_CLK_USB2_HSIC_TRK 315
346#define TEGRA210_CLK_PLL_P_OUT_HSIO 316
347#define TEGRA210_CLK_PLL_P_OUT_XUSB 317
348#define TEGRA210_CLK_XUSB_SSP_SRC 318
349/* 319 */
350/* 320 */
351/* 321 */
352/* 322 */
353/* 323 */
354/* 324 */
355/* 325 */
356/* 326 */
357/* 327 */
358/* 328 */
359/* 329 */
360/* 330 */
361/* 331 */
362/* 332 */
363/* 333 */
364/* 334 */
365/* 335 */
366/* 336 */
367/* 337 */
368/* 338 */
369/* 339 */
370/* 340 */
371/* 341 */
372/* 342 */
373/* 343 */
374/* 344 */
375/* 345 */
376/* 346 */
377/* 347 */
378/* 348 */
379/* 349 */
380
381#define TEGRA210_CLK_AUDIO0_MUX 350
382#define TEGRA210_CLK_AUDIO1_MUX 351
383#define TEGRA210_CLK_AUDIO2_MUX 352
384#define TEGRA210_CLK_AUDIO3_MUX 353
385#define TEGRA210_CLK_AUDIO4_MUX 354
386#define TEGRA210_CLK_SPDIF_MUX 355
387#define TEGRA210_CLK_CLK_OUT_1_MUX 356
388#define TEGRA210_CLK_CLK_OUT_2_MUX 357
389#define TEGRA210_CLK_CLK_OUT_3_MUX 358
390#define TEGRA210_CLK_DSIA_MUX 359
391#define TEGRA210_CLK_DSIB_MUX 360
392#define TEGRA210_CLK_SOR0_LVDS 361
393#define TEGRA210_CLK_XUSB_SS_DIV2 362
394
395#define TEGRA210_CLK_PLL_M_UD 363
396#define TEGRA210_CLK_PLL_C_UD 364
397#define TEGRA210_CLK_SCLK_MUX 365
398
399#define TEGRA210_CLK_CLK_MAX 366
400
401#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
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