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-rw-r--r--arch/arm/boot/dts/sun5i-r8.dtsi137
1 files changed, 137 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index 691d3de75b35..c04cf690b858 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -57,4 +57,141 @@
57 status = "disabled"; 57 status = "disabled";
58 }; 58 };
59 }; 59 };
60
61 soc@01c00000 {
62 tve0: tv-encoder@01c0a000 {
63 compatible = "allwinner,sun4i-a10-tv-encoder";
64 reg = <0x01c0a000 0x1000>;
65 clocks = <&ahb_gates 34>;
66 resets = <&tcon_ch0_clk 0>;
67 status = "disabled";
68
69 port {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 tve0_in_tcon0: endpoint@0 {
74 reg = <0>;
75 remote-endpoint = <&tcon0_out_tve0>;
76 };
77 };
78 };
79
80 tcon0: lcd-controller@01c0c000 {
81 compatible = "allwinner,sun5i-a13-tcon";
82 reg = <0x01c0c000 0x1000>;
83 interrupts = <44>;
84 resets = <&tcon_ch0_clk 1>;
85 reset-names = "lcd";
86 clocks = <&ahb_gates 36>,
87 <&tcon_ch0_clk>,
88 <&tcon_ch1_clk>;
89 clock-names = "ahb",
90 "tcon-ch0",
91 "tcon-ch1";
92 clock-output-names = "tcon-pixel-clock";
93 status = "disabled";
94
95 ports {
96 #address-cells = <1>;
97 #size-cells = <0>;
98
99 tcon0_in: port@0 {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 reg = <0>;
103
104 tcon0_in_be0: endpoint@0 {
105 reg = <0>;
106 remote-endpoint = <&be0_out_tcon0>;
107 };
108 };
109
110 tcon0_out: port@1 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 reg = <1>;
114
115 tcon0_out_tve0: endpoint@1 {
116 reg = <1>;
117 remote-endpoint = <&tve0_in_tcon0>;
118 };
119 };
120 };
121 };
122
123 fe0: display-frontend@01e00000 {
124 compatible = "allwinner,sun5i-a13-display-frontend";
125 reg = <0x01e00000 0x20000>;
126 interrupts = <47>;
127 clocks = <&ahb_gates 46>, <&de_fe_clk>,
128 <&dram_gates 25>;
129 clock-names = "ahb", "mod",
130 "ram";
131 resets = <&de_fe_clk>;
132 status = "disabled";
133
134 ports {
135 #address-cells = <1>;
136 #size-cells = <0>;
137
138 fe0_out: port@1 {
139 #address-cells = <1>;
140 #size-cells = <0>;
141 reg = <1>;
142
143 fe0_out_be0: endpoint@0 {
144 reg = <0>;
145 remote-endpoint = <&be0_in_fe0>;
146 };
147 };
148 };
149 };
150
151 be0: display-backend@01e60000 {
152 compatible = "allwinner,sun5i-a13-display-backend";
153 reg = <0x01e60000 0x10000>;
154 clocks = <&ahb_gates 44>, <&de_be_clk>,
155 <&dram_gates 26>;
156 clock-names = "ahb", "mod",
157 "ram";
158 resets = <&de_be_clk>;
159 status = "disabled";
160
161 assigned-clocks = <&de_be_clk>;
162 assigned-clock-rates = <300000000>;
163
164 ports {
165 #address-cells = <1>;
166 #size-cells = <0>;
167
168 be0_in: port@0 {
169 #address-cells = <1>;
170 #size-cells = <0>;
171 reg = <0>;
172
173 be0_in_fe0: endpoint@0 {
174 reg = <0>;
175 remote-endpoint = <&fe0_out_be0>;
176 };
177 };
178
179 be0_out: port@1 {
180 #address-cells = <1>;
181 #size-cells = <0>;
182 reg = <1>;
183
184 be0_out_tcon0: endpoint@0 {
185 reg = <0>;
186 remote-endpoint = <&tcon0_in_be0>;
187 };
188 };
189 };
190 };
191 };
192
193 display-engine {
194 compatible = "allwinner,sun5i-a13-display-engine";
195 allwinner,pipelines = <&fe0>;
196 };
60}; 197};