ALSA: hda - Add the controller helper codes to hda-core module

This patch adds the controller helper codes to hda-core library.
The I/O access ops are added to the bus ops.  The CORB/RIRB, the basic
attributes like irq# and iomap address, some locks and the list of
streams are added to the bus object, together with the stream object
and its helpers.

Currently the codes are just copied from the legacy driver, so you can
find duplicated codes in both directories.  Only constants are removed
from the original hda_controller.h.  More integration work will follow
in the later patches.

Signed-off-by: Takashi Iwai <tiwai@suse.de>

6 files changed, 1007 insertions, 134 deletions

diff --git a/sound/hda/Makefile b/sound/hda/Makefile
index 7a359f5b7e25..5b4bb47c16fd 100644
--- a/sound/hda/Makefile
+++ b/sound/hda/Makefile
@@ -1,5 +1,5 @@
 snd-hda-core-objs := hda_bus_type.o hdac_bus.o hdac_device.o hdac_sysfs.o \
-        hdac_regmap.o array.o
+        hdac_regmap.o hdac_controller.o hdac_stream.o array.o
 
 snd-hda-core-objs += trace.o
 CFLAGS_trace.o := -I$(src)
diff --git a/sound/hda/hdac_bus.c b/sound/hda/hdac_bus.c
index 8e262da74f6a..27c447e4fe5c 100644
--- a/sound/hda/hdac_bus.c
+++ b/sound/hda/hdac_bus.c
@@ -11,21 +11,36 @@
 
 static void process_unsol_events(struct work_struct *work);
 
+static const struct hdac_bus_ops default_ops = {
+        .command = snd_hdac_bus_send_cmd,
+        .get_response = snd_hdac_bus_get_response,
+};
+
 /**
  * snd_hdac_bus_init - initialize a HD-audio bas bus
  * @bus: the pointer to bus object
+ * @ops: bus verb operators
+ * @io_ops: lowlevel I/O operators
  *
  * Returns 0 if successful, or a negative error code.
  */
 int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,
-                      const struct hdac_bus_ops *ops)
+                      const struct hdac_bus_ops *ops,
+                      const struct hdac_io_ops *io_ops)
 {
         memset(bus, 0, sizeof(*bus));
         bus->dev = dev;
-        bus->ops = ops;
+        if (ops)
+                bus->ops = ops;
+        else
+                bus->ops = &default_ops;
+        bus->io_ops = io_ops;
+        INIT_LIST_HEAD(&bus->stream_list);
         INIT_LIST_HEAD(&bus->codec_list);
         INIT_WORK(&bus->unsol_work, process_unsol_events);
+        spin_lock_init(&bus->reg_lock);
         mutex_init(&bus->cmd_mutex);
+        bus->irq = -1;
         return 0;
 }
 EXPORT_SYMBOL_GPL(snd_hdac_bus_init);
@@ -36,6 +51,7 @@ EXPORT_SYMBOL_GPL(snd_hdac_bus_init);
  */
 void snd_hdac_bus_exit(struct hdac_bus *bus)
 {
+        WARN_ON(!list_empty(&bus->stream_list));
         WARN_ON(!list_empty(&bus->codec_list));
         cancel_work_sync(&bus->unsol_work);
 }
diff --git a/sound/hda/hdac_controller.c b/sound/hda/hdac_controller.c
new file mode 100644
index 000000000000..c0069d0b7875
--- /dev/null
+++ b/sound/hda/hdac_controller.c
@@ -0,0 +1,449 @@
+/*
+ * HD-audio controller helpers
+ */
+
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/export.h>
+#include <sound/core.h>
+#include <sound/hdaudio.h>
+#include <sound/hda_register.h>
+
+/* clear CORB read pointer properly */
+static void azx_clear_corbrp(struct hdac_bus *bus)
+{
+        int timeout;
+
+        for (timeout = 1000; timeout > 0; timeout--) {
+                if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
+                        break;
+                udelay(1);
+        }
+        if (timeout <= 0)
+                dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
+                        snd_hdac_chip_readw(bus, CORBRP));
+
+        snd_hdac_chip_writew(bus, CORBRP, 0);
+        for (timeout = 1000; timeout > 0; timeout--) {
+                if (snd_hdac_chip_readw(bus, CORBRP) == 0)
+                        break;
+                udelay(1);
+        }
+        if (timeout <= 0)
+                dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
+                        snd_hdac_chip_readw(bus, CORBRP));
+}
+
+/**
+ * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
+ * @bus: HD-audio core bus
+ */
+void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
+{
+        spin_lock_irq(&bus->reg_lock);
+        /* CORB set up */
+        bus->corb.addr = bus->rb.addr;
+        bus->corb.buf = (__le32 *)bus->rb.area;
+        snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
+        snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
+
+        /* set the corb size to 256 entries (ULI requires explicitly) */
+        snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
+        /* set the corb write pointer to 0 */
+        snd_hdac_chip_writew(bus, CORBWP, 0);
+
+        /* reset the corb hw read pointer */
+        snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
+        if (!bus->corbrp_self_clear)
+                azx_clear_corbrp(bus);
+
+        /* enable corb dma */
+        snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
+
+        /* RIRB set up */
+        bus->rirb.addr = bus->rb.addr + 2048;
+        bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
+        bus->rirb.wp = bus->rirb.rp = 0;
+        memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
+        snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
+        snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
+
+        /* set the rirb size to 256 entries (ULI requires explicitly) */
+        snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
+        /* reset the rirb hw write pointer */
+        snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
+        /* set N=1, get RIRB response interrupt for new entry */
+        snd_hdac_chip_writew(bus, RINTCNT, 1);
+        /* enable rirb dma and response irq */
+        snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
+        spin_unlock_irq(&bus->reg_lock);
+}
+EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
+
+/**
+ * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
+ * @bus: HD-audio core bus
+ */
+void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
+{
+        spin_lock_irq(&bus->reg_lock);
+        /* disable ringbuffer DMAs */
+        snd_hdac_chip_writeb(bus, RIRBCTL, 0);
+        snd_hdac_chip_writeb(bus, CORBCTL, 0);
+        /* disable unsolicited responses */
+        snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
+        spin_unlock_irq(&bus->reg_lock);
+}
+EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
+
+static unsigned int azx_command_addr(u32 cmd)
+{
+        unsigned int addr = cmd >> 28;
+
+        if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
+                addr = 0;
+        return addr;
+}
+
+/**
+ * snd_hdac_bus_send_cmd - send a command verb via CORB
+ * @bus: HD-audio core bus
+ * @val: encoded verb value to send
+ *
+ * Returns zero for success or a negative error code.
+ */
+int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
+{
+        unsigned int addr = azx_command_addr(val);
+        unsigned int wp, rp;
+
+        spin_lock_irq(&bus->reg_lock);
+
+        bus->last_cmd[azx_command_addr(val)] = val;
+
+        /* add command to corb */
+        wp = snd_hdac_chip_readw(bus, CORBWP);
+        if (wp == 0xffff) {
+                /* something wrong, controller likely turned to D3 */
+                spin_unlock_irq(&bus->reg_lock);
+                return -EIO;
+        }
+        wp++;
+        wp %= AZX_MAX_CORB_ENTRIES;
+
+        rp = snd_hdac_chip_readw(bus, CORBRP);
+        if (wp == rp) {
+                /* oops, it's full */
+                spin_unlock_irq(&bus->reg_lock);
+                return -EAGAIN;
+        }
+
+        bus->rirb.cmds[addr]++;
+        bus->corb.buf[wp] = cpu_to_le32(val);
+        snd_hdac_chip_writew(bus, CORBWP, wp);
+
+        spin_unlock_irq(&bus->reg_lock);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
+
+#define AZX_RIRB_EX_UNSOL_EV    (1<<4)
+
+/**
+ * snd_hdac_bus_update_rirb - retrieve RIRB entries
+ * @bus: HD-audio core bus
+ *
+ * Usually called from interrupt handler.
+ */
+void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
+{
+        unsigned int rp, wp;
+        unsigned int addr;
+        u32 res, res_ex;
+
+        wp = snd_hdac_chip_readw(bus, RIRBWP);
+        if (wp == 0xffff) {
+                /* something wrong, controller likely turned to D3 */
+                return;
+        }
+
+        if (wp == bus->rirb.wp)
+                return;
+        bus->rirb.wp = wp;
+
+        while (bus->rirb.rp != wp) {
+                bus->rirb.rp++;
+                bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
+
+                rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
+                res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
+                res = le32_to_cpu(bus->rirb.buf[rp]);
+                addr = res_ex & 0xf;
+                if (addr >= HDA_MAX_CODECS) {
+                        dev_err(bus->dev,
+                                "spurious response %#x:%#x, rp = %d, wp = %d",
+                                res, res_ex, bus->rirb.rp, wp);
+                        snd_BUG();
+                } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
+                        snd_hdac_bus_queue_event(bus, res, res_ex);
+                else if (bus->rirb.cmds[addr]) {
+                        bus->rirb.res[addr] = res;
+                        bus->rirb.cmds[addr]--;
+                } else {
+                        dev_err_ratelimited(bus->dev,
+                                "spurious response %#x:%#x, last cmd=%#08x\n",
+                                res, res_ex, bus->last_cmd[addr]);
+                }
+        }
+}
+EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
+
+/**
+ * snd_hdac_bus_get_response - receive a response via RIRB
+ * @bus: HD-audio core bus
+ * @addr: codec address
+ * @res: pointer to store the value, NULL when not needed
+ *
+ * Returns zero if a value is read, or a negative error code.
+ */
+int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
+                              unsigned int *res)
+{
+        unsigned long timeout;
+        unsigned long loopcounter;
+
+        timeout = jiffies + msecs_to_jiffies(1000);
+
+        for (loopcounter = 0;; loopcounter++) {
+                spin_lock_irq(&bus->reg_lock);
+                if (!bus->rirb.cmds[addr]) {
+                        if (res)
+                                *res = bus->rirb.res[addr]; /* the last value */
+                        spin_unlock_irq(&bus->reg_lock);
+                        return 0;
+                }
+                spin_unlock_irq(&bus->reg_lock);
+                if (time_after(jiffies, timeout))
+                        break;
+                if (loopcounter > 3000)
+                        msleep(2); /* temporary workaround */
+                else {
+                        udelay(10);
+                        cond_resched();
+                }
+        }
+
+        return -EIO;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
+
+/*
+ * Lowlevel interface
+ */
+
+/**
+ * snd_hdac_bus_enter_link_reset - enter link reset
+ * @bus: HD-audio core bus
+ *
+ * Enter to the link reset state.
+ */
+void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
+{
+        unsigned long timeout;
+
+        /* reset controller */
+        snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
+
+        timeout = jiffies + msecs_to_jiffies(100);
+        while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
+               time_before(jiffies, timeout))
+                usleep_range(500, 1000);
+}
+EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
+
+/**
+ * snd_hdac_bus_exit_link_reset - exit link reset
+ * @bus: HD-audio core bus
+ *
+ * Exit from the link reset state.
+ */
+void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
+{
+        unsigned long timeout;
+
+        snd_hdac_chip_updateb(bus, GCTL, 0, AZX_GCTL_RESET);
+
+        timeout = jiffies + msecs_to_jiffies(100);
+        while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
+                usleep_range(500, 1000);
+}
+EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
+
+/* reset codec link */
+static int azx_reset(struct hdac_bus *bus, bool full_reset)
+{
+        if (!full_reset)
+                goto skip_reset;
+
+        /* clear STATESTS */
+        snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
+
+        /* reset controller */
+        snd_hdac_bus_enter_link_reset(bus);
+
+        /* delay for >= 100us for codec PLL to settle per spec
+         * Rev 0.9 section 5.5.1
+         */
+        usleep_range(500, 1000);
+
+        /* Bring controller out of reset */
+        snd_hdac_bus_exit_link_reset(bus);
+
+        /* Brent Chartrand said to wait >= 540us for codecs to initialize */
+        usleep_range(1000, 1200);
+
+ skip_reset:
+        /* check to see if controller is ready */
+        if (!snd_hdac_chip_readb(bus, GCTL)) {
+                dev_dbg(bus->dev, "azx_reset: controller not ready!\n");
+                return -EBUSY;
+        }
+
+        /* Accept unsolicited responses */
+        snd_hdac_chip_updatel(bus, GCTL, 0, AZX_GCTL_UNSOL);
+
+        /* detect codecs */
+        if (!bus->codec_mask) {
+                bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
+                dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
+        }
+
+        return 0;
+}
+
+/* enable interrupts */
+static void azx_int_enable(struct hdac_bus *bus)
+{
+        /* enable controller CIE and GIE */
+        snd_hdac_chip_updatel(bus, INTCTL, 0, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
+}
+
+/* disable interrupts */
+static void azx_int_disable(struct hdac_bus *bus)
+{
+        struct hdac_stream *azx_dev;
+
+        /* disable interrupts in stream descriptor */
+        list_for_each_entry(azx_dev, &bus->stream_list, list)
+                snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
+
+        /* disable SIE for all streams */
+        snd_hdac_chip_writeb(bus, INTCTL, 0);
+
+        /* disable controller CIE and GIE */
+        snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0);
+}
+
+/* clear interrupts */
+static void azx_int_clear(struct hdac_bus *bus)
+{
+        struct hdac_stream *azx_dev;
+
+        /* clear stream status */
+        list_for_each_entry(azx_dev, &bus->stream_list, list)
+                snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
+
+        /* clear STATESTS */
+        snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
+
+        /* clear rirb status */
+        snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
+
+        /* clear int status */
+        snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
+}
+
+/**
+ * snd_hdac_bus_init_chip - reset and start the controller registers
+ * @bus: HD-audio core bus
+ * @full_reset: Do full reset
+ */
+bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
+{
+        if (bus->chip_init)
+                return false;
+
+        /* reset controller */
+        azx_reset(bus, full_reset);
+
+        /* initialize interrupts */
+        azx_int_clear(bus);
+        azx_int_enable(bus);
+
+        /* initialize the codec command I/O */
+        snd_hdac_bus_init_cmd_io(bus);
+
+        /* program the position buffer */
+        if (bus->use_posbuf && bus->posbuf.addr) {
+                snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
+                snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
+        }
+
+        bus->chip_init = true;
+        return true;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
+
+/**
+ * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
+ * @bus: HD-audio core bus
+ */
+void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
+{
+        if (!bus->chip_init)
+                return;
+
+        /* disable interrupts */
+        azx_int_disable(bus);
+        azx_int_clear(bus);
+
+        /* disable CORB/RIRB */
+        snd_hdac_bus_stop_cmd_io(bus);
+
+        /* disable position buffer */
+        if (bus->posbuf.addr) {
+                snd_hdac_chip_writel(bus, DPLBASE, 0);
+                snd_hdac_chip_writel(bus, DPUBASE, 0);
+        }
+
+        bus->chip_init = false;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
+
+/**
+ * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
+ * @bus: HD-audio core bus
+ * @status: INTSTS register value
+ * @ask: callback to be called for woken streams
+ */
+void snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
+                                    void (*ack)(struct hdac_bus *,
+                                                struct hdac_stream *))
+{
+        struct hdac_stream *azx_dev;
+        u8 sd_status;
+
+        list_for_each_entry(azx_dev, &bus->stream_list, list) {
+                if (status & azx_dev->sd_int_sta_mask) {
+                        sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
+                        snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
+                        if (!azx_dev->substream || !azx_dev->running ||
+                            !(sd_status & SD_INT_COMPLETE))
+                                continue;
+                        if (ack)
+                                ack(bus, azx_dev);
+                }
+        }
+}
+EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
diff --git a/sound/hda/hdac_stream.c b/sound/hda/hdac_stream.c
new file mode 100644
index 000000000000..b513a15c777f
--- /dev/null
+++ b/sound/hda/hdac_stream.c
@@ -0,0 +1,536 @@
+/*
+ * HD-audio stream operations
+ */
+
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/export.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/hdaudio.h>
+#include <sound/hda_register.h>
+
+/**
+ * snd_hdac_stream_init - initialize each stream (aka device)
+ * @bus: HD-audio core bus
+ * @azx_dev: HD-audio core stream object to initialize
+ * @idx: stream index number
+ * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
+ * @tag: the tag id to assign
+ *
+ * Assign the starting bdl address to each stream (device) and initialize.
+ */
+void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
+                          int idx, int direction, int tag)
+{
+        azx_dev->bus = bus;
+        if (bus->posbuf.area)
+                azx_dev->posbuf = (__le32 *)(bus->posbuf.area + idx * 8);
+        /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
+        azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
+        /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
+        azx_dev->sd_int_sta_mask = 1 << idx;
+        azx_dev->index = idx;
+        azx_dev->direction = direction;
+        azx_dev->stream_tag = tag;
+        list_add_tail(&azx_dev->list, &bus->stream_list);
+}
+EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
+
+/**
+ * snd_hdac_stream_start - start a stream
+ * @azx_dev: HD-audio core stream to start
+ * @fresh_start: false = wallclock timestamp relative to period wallclock
+ *
+ * Start a stream, set start_wallclk and set the running flag.
+ */
+void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
+{
+        struct hdac_bus *bus = azx_dev->bus;
+
+        azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
+        if (!fresh_start)
+                azx_dev->start_wallclk -= azx_dev->period_wallclk;
+
+        /* enable SIE */
+        snd_hdac_chip_updatel(bus, INTCTL, 0, 1 << azx_dev->index);
+        /* set DMA start and interrupt mask */
+        snd_hdac_stream_updateb(azx_dev, SD_CTL,
+                                0, SD_CTL_DMA_START | SD_INT_MASK);
+        azx_dev->running = true;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
+
+/**
+ * snd_hdac_stream_clear - stop a stream DMA
+ * @azx_dev: HD-audio core stream to stop
+ */
+void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
+{
+        snd_hdac_stream_updateb(azx_dev, SD_CTL,
+                                SD_CTL_DMA_START | SD_INT_MASK, 0);
+        snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
+        azx_dev->running = false;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
+
+/**
+ * snd_hdac_stream_stop - stop a stream
+ * @azx_dev: HD-audio core stream to stop
+ *
+ * Stop a stream DMA and disable stream interrupt
+ */
+void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
+{
+        snd_hdac_stream_clear(azx_dev);
+        /* disable SIE */
+        snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
+}
+EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
+
+/**
+ * snd_hdac_stream_reset - reset a stream
+ * @azx_dev: HD-audio core stream to reset
+ */
+void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
+{
+        unsigned char val;
+        int timeout;
+
+        snd_hdac_stream_clear(azx_dev);
+
+        snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
+        udelay(3);
+        timeout = 300;
+        do {
+                val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
+                        SD_CTL_STREAM_RESET;
+                if (val)
+                        break;
+        } while (--timeout);
+        val &= ~SD_CTL_STREAM_RESET;
+        snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
+        udelay(3);
+
+        timeout = 300;
+        /* waiting for hardware to report that the stream is out of reset */
+        do {
+                val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
+                        SD_CTL_STREAM_RESET;
+                if (!val)
+                        break;
+        } while (--timeout);
+
+        /* reset first position - may not be synced with hw at this time */
+        if (azx_dev->posbuf)
+                *azx_dev->posbuf = 0;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
+
+/**
+ * snd_hdac_stream_setup -  set up the SD for streaming
+ * @azx_dev: HD-audio core stream to set up
+ */
+int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
+{
+        struct hdac_bus *bus = azx_dev->bus;
+        struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
+        unsigned int val;
+
+        /* make sure the run bit is zero for SD */
+        snd_hdac_stream_clear(azx_dev);
+        /* program the stream_tag */
+        val = snd_hdac_stream_readl(azx_dev, SD_CTL);
+        val = (val & ~SD_CTL_STREAM_TAG_MASK) |
+                (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
+        if (!bus->snoop)
+                val |= SD_CTL_TRAFFIC_PRIO;
+        snd_hdac_stream_writel(azx_dev, SD_CTL, val);
+
+        /* program the length of samples in cyclic buffer */
+        snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
+
+        /* program the stream format */
+        /* this value needs to be the same as the one programmed */
+        snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
+
+        /* program the stream LVI (last valid index) of the BDL */
+        snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
+
+        /* program the BDL address */
+        /* lower BDL address */
+        snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
+        /* upper BDL address */
+        snd_hdac_stream_writel(azx_dev, SD_BDLPU,
+                               upper_32_bits(azx_dev->bdl.addr));
+
+        /* enable the position buffer */
+        if (bus->use_posbuf && bus->posbuf.addr) {
+                if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
+                        snd_hdac_chip_writel(bus, DPLBASE,
+                                (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
+        }
+
+        /* set the interrupt enable bits in the descriptor control register */
+        snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
+
+        if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK)
+                azx_dev->fifo_size =
+                        snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
+        else
+                azx_dev->fifo_size = 0;
+
+        /* when LPIB delay correction gives a small negative value,
+         * we ignore it; currently set the threshold statically to
+         * 64 frames
+         */
+        if (runtime->period_size > 64)
+                azx_dev->delay_negative_threshold =
+                        -frames_to_bytes(runtime, 64);
+        else
+                azx_dev->delay_negative_threshold = 0;
+
+        /* wallclk has 24Mhz clock source */
+        azx_dev->period_wallclk = (((runtime->period_size * 24000) /
+                                    runtime->rate) * 1000);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
+
+/**
+ * snd_hdac_stream_cleanup - cleanup a stream
+ * @azx_dev: HD-audio core stream to clean up
+ */
+void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
+{
+        snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
+        snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
+        snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
+        azx_dev->bufsize = 0;
+        azx_dev->period_bytes = 0;
+        azx_dev->format_val = 0;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
+
+/**
+ * snd_hdac_stream_assign - assign a stream for the PCM
+ * @bus: HD-audio core bus
+ * @substream: PCM substream to assign
+ *
+ * Look for an unused stream for the given PCM substream, assign it
+ * and return the stream object.  If no stream is free, returns NULL.
+ * The function tries to keep using the same stream object when it's used
+ * beforehand.  Also, when bus->reverse_assign flag is set, the last free
+ * or matching entry is returned.  This is needed for some strange codecs.
+ */
+struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
+                                           struct snd_pcm_substream *substream)
+{
+        struct hdac_stream *azx_dev;
+        struct hdac_stream *res = NULL;
+
+        /* make a non-zero unique key for the substream */
+        int key = (substream->pcm->device << 16) | (substream->number << 2) |
+                (substream->stream + 1);
+
+        list_for_each_entry(azx_dev, &bus->stream_list, list) {
+                if (azx_dev->direction != substream->stream)
+                        continue;
+                if (azx_dev->opened)
+                        continue;
+                if (azx_dev->assigned_key == key) {
+                        res = azx_dev;
+                        break;
+                }
+                if (!res || bus->reverse_assign)
+                        res = azx_dev;
+        }
+        if (res) {
+                spin_lock_irq(&bus->reg_lock);
+                res->opened = 1;
+                res->running = 0;
+                res->assigned_key = key;
+                res->substream = substream;
+                spin_unlock_irq(&bus->reg_lock);
+        }
+        return res;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
+
+/**
+ * snd_hdac_stream_release - release the assigned stream
+ * @azx_dev: HD-audio core stream to release
+ *
+ * Release the stream that has been assigned by snd_hdac_stream_assign().
+ */
+void snd_hdac_stream_release(struct hdac_stream *azx_dev)
+{
+        struct hdac_bus *bus = azx_dev->bus;
+
+        spin_lock_irq(&bus->reg_lock);
+        azx_dev->opened = 0;
+        azx_dev->running = 0;
+        azx_dev->substream = NULL;
+        spin_unlock_irq(&bus->reg_lock);
+}
+EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
+
+/*
+ * set up a BDL entry
+ */
+static int setup_bdle(struct hdac_bus *bus,
+                      struct snd_dma_buffer *dmab,
+                      struct hdac_stream *azx_dev, __le32 **bdlp,
+                      int ofs, int size, int with_ioc)
+{
+        __le32 *bdl = *bdlp;
+
+        while (size > 0) {
+                dma_addr_t addr;
+                int chunk;
+
+                if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
+                        return -EINVAL;
+
+                addr = snd_sgbuf_get_addr(dmab, ofs);
+                /* program the address field of the BDL entry */
+                bdl[0] = cpu_to_le32((u32)addr);
+                bdl[1] = cpu_to_le32(upper_32_bits(addr));
+                /* program the size field of the BDL entry */
+                chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
+                /* one BDLE cannot cross 4K boundary on CTHDA chips */
+                if (bus->align_bdle_4k) {
+                        u32 remain = 0x1000 - (ofs & 0xfff);
+
+                        if (chunk > remain)
+                                chunk = remain;
+                }
+                bdl[2] = cpu_to_le32(chunk);
+                /* program the IOC to enable interrupt
+                 * only when the whole fragment is processed
+                 */
+                size -= chunk;
+                bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
+                bdl += 4;
+                azx_dev->frags++;
+                ofs += chunk;
+        }
+        *bdlp = bdl;
+        return ofs;
+}
+
+/**
+ * snd_hdac_stream_setup_periods - set up BDL entries
+ * @azx_dev: HD-audio core stream to set up
+ *
+ * Set up the buffer descriptor table of the given stream based on the
+ * period and buffer sizes of the assigned PCM substream.
+ */
+int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
+{
+        struct hdac_bus *bus = azx_dev->bus;
+        struct snd_pcm_substream *substream = azx_dev->substream;
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        __le32 *bdl;
+        int i, ofs, periods, period_bytes;
+        int pos_adj, pos_align;
+
+        /* reset BDL address */
+        snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
+        snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
+
+        period_bytes = azx_dev->period_bytes;
+        periods = azx_dev->bufsize / period_bytes;
+
+        /* program the initial BDL entries */
+        bdl = (__le32 *)azx_dev->bdl.area;
+        ofs = 0;
+        azx_dev->frags = 0;
+
+        pos_adj = bus->bdl_pos_adj;
+        if (!azx_dev->no_period_wakeup && pos_adj > 0) {
+                pos_align = pos_adj;
+                pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
+                if (!pos_adj)
+                        pos_adj = pos_align;
+                else
+                        pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
+                                pos_align;
+                pos_adj = frames_to_bytes(runtime, pos_adj);
+                if (pos_adj >= period_bytes) {
+                        dev_warn(bus->dev, "Too big adjustment %d\n",
+                                 pos_adj);
+                        pos_adj = 0;
+                } else {
+                        ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
+                                         azx_dev,
+                                         &bdl, ofs, pos_adj, true);
+                        if (ofs < 0)
+                                goto error;
+                }
+        } else
+                pos_adj = 0;
+
+        for (i = 0; i < periods; i++) {
+                if (i == periods - 1 && pos_adj)
+                        ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
+                                         azx_dev, &bdl, ofs,
+                                         period_bytes - pos_adj, 0);
+                else
+                        ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
+                                         azx_dev, &bdl, ofs,
+                                         period_bytes,
+                                         !azx_dev->no_period_wakeup);
+                if (ofs < 0)
+                        goto error;
+        }
+        return 0;
+
+ error:
+        dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
+                azx_dev->bufsize, period_bytes);
+        return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
+
+static cycle_t azx_cc_read(const struct cyclecounter *cc)
+{
+        struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
+
+        return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
+}
+
+static void azx_timecounter_init(struct hdac_stream *azx_dev,
+                                 bool force, cycle_t last)
+{
+        struct timecounter *tc = &azx_dev->tc;
+        struct cyclecounter *cc = &azx_dev->cc;
+        u64 nsec;
+
+        cc->read = azx_cc_read;
+        cc->mask = CLOCKSOURCE_MASK(32);
+
+        /*
+         * Converting from 24 MHz to ns means applying a 125/3 factor.
+         * To avoid any saturation issues in intermediate operations,
+         * the 125 factor is applied first. The division is applied
+         * last after reading the timecounter value.
+         * Applying the 1/3 factor as part of the multiplication
+         * requires at least 20 bits for a decent precision, however
+         * overflows occur after about 4 hours or less, not a option.
+         */
+
+        cc->mult = 125; /* saturation after 195 years */
+        cc->shift = 0;
+
+        nsec = 0; /* audio time is elapsed time since trigger */
+        timecounter_init(tc, cc, nsec);
+        if (force) {
+                /*
+                 * force timecounter to use predefined value,
+                 * used for synchronized starts
+                 */
+                tc->cycle_last = last;
+        }
+}
+
+/**
+ * snd_hdac_stream_timecounter_init - initialize time counter
+ * @azx_dev: HD-audio core stream (master stream)
+ * @streams: bit flags of streams to set up
+ *
+ * Initializes the time counter of streams marked by the bit flags (each
+ * bit corresponds to the stream index).
+ * The trigger timestamp of PCM substream assigned to the given stream is
+ * updated accordingly, too.
+ */
+void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
+                                      unsigned int streams)
+{
+        struct hdac_bus *bus = azx_dev->bus;
+        struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
+        struct hdac_stream *s;
+        bool inited = false;
+        cycle_t cycle_last = 0;
+        int i = 0;
+
+        list_for_each_entry(s, &bus->stream_list, list) {
+                if (streams & (1 << i)) {
+                        azx_timecounter_init(s, inited, cycle_last);
+                        if (!inited) {
+                                inited = true;
+                                cycle_last = s->tc.cycle_last;
+                        }
+                }
+                i++;
+        }
+
+        snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
+        runtime->trigger_tstamp_latched = true;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
+
+/**
+ * snd_hdac_stream_sync_trigger - turn on/off stream sync register
+ * @azx_dev: HD-audio core stream (master stream)
+ * @streams: bit flags of streams to sync
+ */
+void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
+                                  unsigned int streams, unsigned int reg)
+{
+        struct hdac_bus *bus = azx_dev->bus;
+        unsigned int val;
+
+        if (!reg)
+                reg = AZX_REG_SSYNC;
+        val = _snd_hdac_chip_read(l, bus, reg);
+        if (set)
+                val |= streams;
+        else
+                val &= ~streams;
+        _snd_hdac_chip_write(l, bus, reg, val);
+}
+EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
+
+/**
+ * snd_hdac_stream_sync - sync with start/strop trigger operation
+ * @azx_dev: HD-audio core stream (master stream)
+ * @start: true = start, false = stop
+ * @streams: bit flags of streams to sync
+ *
+ * For @start = true, wait until all FIFOs get ready.
+ * For @start = false, wait until all RUN bits are cleared.
+ */
+void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
+                          unsigned int streams)
+{
+        struct hdac_bus *bus = azx_dev->bus;
+        int i, nwait, timeout;
+        struct hdac_stream *s;
+
+        for (timeout = 5000; timeout; timeout--) {
+                nwait = 0;
+                i = 0;
+                list_for_each_entry(s, &bus->stream_list, list) {
+                        if (streams & (1 << i)) {
+                                if (start) {
+                                        /* check FIFO gets ready */
+                                        if (!(snd_hdac_stream_readb(s, SD_STS) &
+                                              SD_STS_FIFO_READY))
+                                                nwait++;
+                                } else {
+                                        /* check RUN bit is cleared */
+                                        if (snd_hdac_stream_readb(s, SD_CTL) &
+                                            SD_CTL_DMA_START)
+                                                nwait++;
+                                }
+                        }
+                        i++;
+                }
+                if (!nwait)
+                        break;
+                cpu_relax();
+        }
+}
+EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
diff --git a/sound/pci/hda/hda_codec.c b/sound/pci/hda/hda_codec.c
index c13d5c3e1d03..b86e2f449e56 100644
--- a/sound/pci/hda/hda_codec.c
+++ b/sound/pci/hda/hda_codec.c
@@ -550,7 +550,7 @@ int snd_hda_bus_new(struct snd_card *card,
         if (!bus)
                 return -ENOMEM;
 
-        err = snd_hdac_bus_init(&bus->core, card->dev, &bus_ops);
+        err = snd_hdac_bus_init(&bus->core, card->dev, &bus_ops, NULL);
         if (err < 0) {
                 kfree(bus);
                 return err;
diff --git a/sound/pci/hda/hda_controller.h b/sound/pci/hda/hda_controller.h
index be1b7ded8d82..15a796c21b9d 100644
--- a/sound/pci/hda/hda_controller.h
+++ b/sound/pci/hda/hda_controller.h
@@ -21,135 +21,10 @@
 #include <sound/pcm.h>
 #include <sound/initval.h>
 #include "hda_codec.h"
+#include <sound/hda_register.h>
 
-/*
- * registers
- */
-#define AZX_REG_GCAP                    0x00
-#define   AZX_GCAP_64OK         (1 << 0)   /* 64bit address support */
-#define   AZX_GCAP_NSDO         (3 << 1)   /* # of serial data out signals */
-#define   AZX_GCAP_BSS          (31 << 3)  /* # of bidirectional streams */
-#define   AZX_GCAP_ISS          (15 << 8)  /* # of input streams */
-#define   AZX_GCAP_OSS          (15 << 12) /* # of output streams */
-#define AZX_REG_VMIN                    0x02
-#define AZX_REG_VMAJ                    0x03
-#define AZX_REG_OUTPAY                  0x04
-#define AZX_REG_INPAY                   0x06
-#define AZX_REG_GCTL                    0x08
-#define   AZX_GCTL_RESET        (1 << 0)   /* controller reset */
-#define   AZX_GCTL_FCNTRL       (1 << 1)   /* flush control */
-#define   AZX_GCTL_UNSOL        (1 << 8)   /* accept unsol. response enable */
-#define AZX_REG_WAKEEN                  0x0c
-#define AZX_REG_STATESTS                0x0e
-#define AZX_REG_GSTS                    0x10
-#define   AZX_GSTS_FSTS         (1 << 1)   /* flush status */
-#define AZX_REG_INTCTL                  0x20
-#define AZX_REG_INTSTS                  0x24
-#define AZX_REG_WALLCLK                 0x30    /* 24Mhz source */
-#define AZX_REG_OLD_SSYNC               0x34    /* SSYNC for old ICH */
-#define AZX_REG_SSYNC                   0x38
-#define AZX_REG_CORBLBASE               0x40
-#define AZX_REG_CORBUBASE               0x44
-#define AZX_REG_CORBWP                  0x48
-#define AZX_REG_CORBRP                  0x4a
-#define   AZX_CORBRP_RST        (1 << 15)  /* read pointer reset */
-#define AZX_REG_CORBCTL                 0x4c
-#define   AZX_CORBCTL_RUN       (1 << 1)   /* enable DMA */
-#define   AZX_CORBCTL_CMEIE     (1 << 0)   /* enable memory error irq */
-#define AZX_REG_CORBSTS                 0x4d
-#define   AZX_CORBSTS_CMEI      (1 << 0)   /* memory error indication */
-#define AZX_REG_CORBSIZE                0x4e
-
-#define AZX_REG_RIRBLBASE               0x50
-#define AZX_REG_RIRBUBASE               0x54
-#define AZX_REG_RIRBWP                  0x58
-#define   AZX_RIRBWP_RST        (1 << 15)  /* write pointer reset */
-#define AZX_REG_RINTCNT                 0x5a
-#define AZX_REG_RIRBCTL                 0x5c
-#define   AZX_RBCTL_IRQ_EN      (1 << 0)   /* enable IRQ */
-#define   AZX_RBCTL_DMA_EN      (1 << 1)   /* enable DMA */
-#define   AZX_RBCTL_OVERRUN_EN  (1 << 2)   /* enable overrun irq */
-#define AZX_REG_RIRBSTS                 0x5d
-#define   AZX_RBSTS_IRQ         (1 << 0)   /* response irq */
-#define   AZX_RBSTS_OVERRUN     (1 << 2)   /* overrun irq */
-#define AZX_REG_RIRBSIZE                0x5e
-
-#define AZX_REG_IC                      0x60
-#define AZX_REG_IR                      0x64
-#define AZX_REG_IRS                     0x68
-#define   AZX_IRS_VALID         (1<<1)
-#define   AZX_IRS_BUSY          (1<<0)
-
-#define AZX_REG_DPLBASE                 0x70
-#define AZX_REG_DPUBASE                 0x74
-#define   AZX_DPLBASE_ENABLE    0x1     /* Enable position buffer */
-
-/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
-enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
-
-/* stream register offsets from stream base */
-#define AZX_REG_SD_CTL                  0x00
-#define AZX_REG_SD_STS                  0x03
-#define AZX_REG_SD_LPIB                 0x04
-#define AZX_REG_SD_CBL                  0x08
-#define AZX_REG_SD_LVI                  0x0c
-#define AZX_REG_SD_FIFOW                0x0e
-#define AZX_REG_SD_FIFOSIZE             0x10
-#define AZX_REG_SD_FORMAT               0x12
-#define AZX_REG_SD_BDLPL                0x18
-#define AZX_REG_SD_BDLPU                0x1c
-
-/* PCI space */
-#define AZX_PCIREG_TCSEL                0x44
-
-/*
- * other constants
- */
-
-/* max number of fragments - we may use more if allocating more pages for BDL */
-#define BDL_SIZE                4096
-#define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
-#define AZX_MAX_FRAG            32
-/* max buffer size - no h/w limit, you can increase as you like */
-#define AZX_MAX_BUF_SIZE        (1024*1024*1024)
-
-/* RIRB int mask: overrun[2], response[0] */
-#define RIRB_INT_RESPONSE       0x01
-#define RIRB_INT_OVERRUN        0x04
-#define RIRB_INT_MASK           0x05
-
-/* STATESTS int mask: S3,SD2,SD1,SD0 */
-#define AZX_MAX_CODECS          8
+#define AZX_MAX_CODECS          HDA_MAX_CODECS
 #define AZX_DEFAULT_CODECS      4
-#define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
-
-/* SD_CTL bits */
-#define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
-#define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
-#define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
-#define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
-#define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
-#define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
-#define SD_CTL_STREAM_TAG_SHIFT 20
-
-/* SD_CTL and SD_STS */
-#define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
-#define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
-#define SD_INT_COMPLETE         0x04    /* completion interrupt */
-#define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
-                                 SD_INT_COMPLETE)
-
-/* SD_STS */
-#define SD_STS_FIFO_READY       0x20    /* FIFO ready */
-
-/* INTCTL and INTSTS */
-#define AZX_INT_ALL_STREAM      0xff       /* all stream interrupts */
-#define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
-#define AZX_INT_GLOBAL_EN       0x80000000 /* global interrupt enable bit */
-
-/* below are so far hardcoded - should read registers in future */
-#define AZX_MAX_CORB_ENTRIES    256
-#define AZX_MAX_RIRB_ENTRIES    256
 
 /* driver quirks (capabilities) */
 /* bits 0-7 are used for indicating driver type */
@@ -183,9 +58,6 @@ enum {
         AZX_SNOOP_TYPE_NVIDIA,
 };
 
-/* HD Audio class code */
-#define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
-
 struct azx_dev {
         struct snd_dma_buffer bdl; /* BDL buffer */
         u32 *posbuf;            /* position buffer pointer */