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authorStephen Warren <swarren@nvidia.com>2013-03-21 15:56:42 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2013-03-25 11:56:36 -0400
commita7fc5d256be9fda27bb69e872e6a212542a84230 (patch)
treefdb60a4ae066005a92656830dee9cb5a9a4257ed /sound/soc/tegra
parent95d36075694b0431da22c3aef3d0dccdcc781344 (diff)
ASoC: tegra: add Tegra114 support to tegra_asoc_utils.c
Tegra114 requires different PLL rates. Modify the code to know about this. On Tegra114 only for now, use regular clk_get() rather than clk_get_sys() to retrieve clocks. This assumes that the clocks will be represented in device tree. We can assure that from the start of any Tegra114 audio support. For older chips, I'll add the required clocks properties to the device trees this kernel cycle, and switch this code to only support the "new_clocks" path next cycle. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/tegra')
-rw-r--r--sound/soc/tegra/tegra_asoc_utils.c30
-rw-r--r--sound/soc/tegra/tegra_asoc_utils.h1
2 files changed, 25 insertions, 6 deletions
diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c
index 49861c6ed874..24fb001be7f4 100644
--- a/sound/soc/tegra/tegra_asoc_utils.c
+++ b/sound/soc/tegra/tegra_asoc_utils.c
@@ -43,8 +43,10 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
43 case 88200: 43 case 88200:
44 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20) 44 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
45 new_baseclock = 56448000; 45 new_baseclock = 56448000;
46 else 46 else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30)
47 new_baseclock = 564480000; 47 new_baseclock = 564480000;
48 else
49 new_baseclock = 282240000;
48 break; 50 break;
49 case 8000: 51 case 8000:
50 case 16000: 52 case 16000:
@@ -54,8 +56,10 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
54 case 96000: 56 case 96000:
55 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20) 57 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
56 new_baseclock = 73728000; 58 new_baseclock = 73728000;
57 else 59 else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30)
58 new_baseclock = 552960000; 60 new_baseclock = 552960000;
61 else
62 new_baseclock = 368640000;
59 break; 63 break;
60 default: 64 default:
61 return -EINVAL; 65 return -EINVAL;
@@ -169,6 +173,7 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
169 struct device *dev) 173 struct device *dev)
170{ 174{
171 int ret; 175 int ret;
176 bool new_clocks = false;
172 177
173 data->dev = dev; 178 data->dev = dev;
174 179
@@ -176,24 +181,37 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
176 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA20; 181 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA20;
177 else if (of_machine_is_compatible("nvidia,tegra30")) 182 else if (of_machine_is_compatible("nvidia,tegra30"))
178 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA30; 183 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA30;
179 else 184 else if (of_machine_is_compatible("nvidia,tegra114")) {
185 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA114;
186 new_clocks = true;
187 } else {
188 dev_err(data->dev, "SoC unknown to Tegra ASoC utils\n");
180 return -EINVAL; 189 return -EINVAL;
190 }
181 191
182 data->clk_pll_a = clk_get_sys(NULL, "pll_a"); 192 if (new_clocks)
193 data->clk_pll_a = clk_get(dev, "pll_a");
194 else
195 data->clk_pll_a = clk_get_sys(NULL, "pll_a");
183 if (IS_ERR(data->clk_pll_a)) { 196 if (IS_ERR(data->clk_pll_a)) {
184 dev_err(data->dev, "Can't retrieve clk pll_a\n"); 197 dev_err(data->dev, "Can't retrieve clk pll_a\n");
185 ret = PTR_ERR(data->clk_pll_a); 198 ret = PTR_ERR(data->clk_pll_a);
186 goto err; 199 goto err;
187 } 200 }
188 201
189 data->clk_pll_a_out0 = clk_get_sys(NULL, "pll_a_out0"); 202 if (new_clocks)
203 data->clk_pll_a_out0 = clk_get(dev, "pll_a_out0");
204 else
205 data->clk_pll_a_out0 = clk_get_sys(NULL, "pll_a_out0");
190 if (IS_ERR(data->clk_pll_a_out0)) { 206 if (IS_ERR(data->clk_pll_a_out0)) {
191 dev_err(data->dev, "Can't retrieve clk pll_a_out0\n"); 207 dev_err(data->dev, "Can't retrieve clk pll_a_out0\n");
192 ret = PTR_ERR(data->clk_pll_a_out0); 208 ret = PTR_ERR(data->clk_pll_a_out0);
193 goto err_put_pll_a; 209 goto err_put_pll_a;
194 } 210 }
195 211
196 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20) 212 if (new_clocks)
213 data->clk_cdev1 = clk_get(dev, "mclk");
214 else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
197 data->clk_cdev1 = clk_get_sys(NULL, "cdev1"); 215 data->clk_cdev1 = clk_get_sys(NULL, "cdev1");
198 else 216 else
199 data->clk_cdev1 = clk_get_sys("extern1", NULL); 217 data->clk_cdev1 = clk_get_sys("extern1", NULL);
diff --git a/sound/soc/tegra/tegra_asoc_utils.h b/sound/soc/tegra/tegra_asoc_utils.h
index 974c9f8830f9..19fdcafed32f 100644
--- a/sound/soc/tegra/tegra_asoc_utils.h
+++ b/sound/soc/tegra/tegra_asoc_utils.h
@@ -29,6 +29,7 @@ struct device;
29enum tegra_asoc_utils_soc { 29enum tegra_asoc_utils_soc {
30 TEGRA_ASOC_UTILS_SOC_TEGRA20, 30 TEGRA_ASOC_UTILS_SOC_TEGRA20,
31 TEGRA_ASOC_UTILS_SOC_TEGRA30, 31 TEGRA_ASOC_UTILS_SOC_TEGRA30,
32 TEGRA_ASOC_UTILS_SOC_TEGRA114,
32}; 33};
33 34
34struct tegra_asoc_utils_data { 35struct tegra_asoc_utils_data {